MAX3946 [MAXIM]
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance; 1.0625Gbps至11.3Gbps ，激光阻抗不匹配公差SFP +激光驱动器
| 型号： | MAX3946 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.0625Gbps to 11.3Gbps, SFP+ Laser Driver with Laser Impedance Mismatch Tolerance |
| 文件： | 总28页 (文件大小：2198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5182; Rev 0; 3/10
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
General Description
Features
S 225mW Power Dissipation Enables < 1W SFP+
The MAX3946 is a +3.3V, multirate, low-power laser
diode driver designed for Ethernet and Fibre Channel
transmission systems at data rates up to 11.3Gbps.
This device is optimized to drive a differential transmit-
ter optical subassembly (TOSA) with a 25I flex circuit.
The unique design of the output stage enables use of
unmatched TOSAs, greatly reducing headroom limita-
tions and lowering power consumption.
Modules
S Up to 100mW Power Consumption Reduction by
Enabling the Use of Unmatched FP/DFB TOSAs
S Supports SFF-8431 SFP+ MSA and SFF-8472
Digital Diagnostic
S 225mW Power Dissipation at 3.3V (I
MOD
= 40mA,
I
= 60mA Assuming 25I TOSA)
BIAS
The device receives differential CML-compatible signals
with on-chip line termination. It can deliver laser modula-
tion current of up to 80mA, at an edge speed of 20ps
(20% to 80%), into a 5Ito 25Iexternal differential load.
The device is designed to have a symmetrical output
stage with on-chip back terminations integrated into
its outputs. A high-bandwidth, fully differential signal
path is implemented to minimize deterministic jitter. An
equalization block can be activated to compensate for
the SFP+ connector. The integrated bias circuit provides
programmable laser bias current up to 80mA. Both the
laser bias generator and the laser modulator can be dis-
abled from a single pin, DISABLE.
S Single +3.3V Power Supply
S Up to 11.3Gbps (NRZ) Operation
S Programmable Modulation Current from 10mA to
100mA (5I Load)
S Programmable Bias Current from 5mA to 80mA
S Programmable Input Equalization
S Programmable Output Deemphasis
S 25I Output Back Termination at TOUT+ and
TOUT-
S DJ Performance 7ps
P-P
with Mismatched
Differential Load (5I)
A 3-wire digital interface reduces the pin count and
permits adjustment of input equalization, pulse-width
adjustment, Tx polarity, Tx deemphasis, modulation cur-
rent, and bias current without the need for external com-
ponents. The MAX3946 is available in a 4mm x 4mm,
24-pin TQFN package.
S DJ Performance 5ps
with Mismatched
P-P
Differential Load (25I)
S DJ Performance 5ps
with 50I Differential Load
P-P
S Programmable Pulse Width
S Edge Transition Times of 20ps
S Bias Current Monitor
Applications
4x/8x FC SFP+ Optical Transceivers
10GFC SFP+ Optical Transceivers
S Integrated Eye Safety Features
S 3-Wire Digital Interface
10GBASE-LR SFP+ Optical Transceivers
10GBASE-LRM SFP+ Optical Transceivers
OC192-SR XFP/SFP+ Transceivers
S -40°C to +95°C Operation
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX3946ETG+
-40°C to +85°C
24 TQFN-EP*
Note: Parts are guaranteed by design and characterization to
operate over the -40°C to +95°C ambient temperature range
(T ) and are tested up to +85°C.
A
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
ABSOLUTE MAXIMUM RATINGS
CC CCT CCD
V
, V
, V
................................................-0.3V to +4.0V
Current into BIAS.........................................................................+130mA
Current Into TOUT+ and TOUT-.................................... +100mA
Current Into TIN+ and TIN- ............................. -20mA to +20mA
Voltage Range at TIN+, TIN-,
Continuous Power Dissipation (T = +70NC)
A
24-Pin TQFN (derate 27.8mW/NC above +70NC).......2222mW
Storage Temperature Range .......................... -55NC to +150NC
Die Attach Temperature .................................................+400NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
DISABLE, SDA, SCL, CSEL, FAULT,
BMAX, BMON, and BIAS...................... -0.3V to (V
+ 0.3V)
CC
Voltage Range at BIAS........................................................-0.3V to V
CC
Voltage Range at TOUT+ and TOUT-....(V - 1.3V) to (V + 1.3V)
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +2.85V to +3.63V, T = -40°C to +85°C, and Figure 1. Guaranteed by design and characterization from T = -40°C to +95°C.
A
A
Typical values are at V
noted.) (Note 1)
= +3.3V, I
= 60mA, I
= 40mA, 25I differential output load, and T = +25°C, unless otherwise
MOD A
CC
BIAS
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Excludes output current through the exter-
nal pullup inductors (Note 2)
Power-Supply Current
Power-Supply Voltage
Power-Supply Noise
POWER-ON RESET
I
68
90
mA
V
CC
V
2.85
3.63
100
10
CC
DC to 10MHz
mV
P-P
10MHz to 20MHz
V
V
for Enable High
for Enable Low
2.55
2.45
2.75
V
CC
CC
2.3
V
DATA INPUT SPECIFICATION
Input Data Rate
1
10
11.3
0.7
Gbps
TXEQ_EN = high, launch amplitude into
FR4 transmission line P 5.5in
0.19
Differential Input Voltage
V
IN
V
P-P
TXEQ_EN = low
0.15
75
1.0
Differential Input Resistance
Differential Input Return Loss
R
100
12
125
I
IN
SDD11
Part powered on, f P 10GHz
dB
Common-Mode Input Return
Loss
SCC11
Part powered on, 1GHz P f P 10GHz
10
dB
BIAS GENERATOR
Current into BIAS pin, DISABLE = low, and
TX_EN = high
Maximum Bias Current
I
80
mA
mA
BIASMAX
Current into BIAS pin, DISABLE = low, and
TX_EN = high
Minimum Bias Current
Bias-Off Current
I
5
BIASMIN
Current into BIAS pin, DISABLE = high or
TX_EN = low or SET_BIAS = H0x00; BIAS
I
100
FA
BIAS-OFF
pin voltage at V
CC
2
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.85V to +3.63V, T = -40°C to +85°C, and Figure 1. Guaranteed by design and characterization from T = -40°C to +95°C.
A
A
Typical values are at V
noted.) (Note 1)
= +3.3V, I
= 60mA, I
= 40mA, 25I differential output load, and T = +25°C, unless otherwise
MOD A
CC
BIAS
PARAMETER
SYMBOL
CONDITIONS
P 80mA, V = V - 1.5V
CC
MIN
TYP
MAX
UNITS
5mA P I
(Notes 1, 3)
BIAS
BIAS
Bias Current DAC Stability
1
3
%
Instantaneous Compliance
Voltage at BIAS
V
0.9
1.5
10
2.1
11
V
BIAS
G
= I
/I
, external resistor to
BMON
BMON BIAS
BMON Current Gain
G
9
0
mA/A
BMON
ground defines voltage
Compliance Voltage at BMON
BMON Current Gain Stability
LASER MODULATOR
1.8
4
V
5mA P I P 80mA (Notes 1, 3)
1.2
%
BIAS
TOUT+ and TOUT-
Instantaneous Output
Compliance Voltage
V
CC
1.0
-
V
+
CC
1.0
V
Current into external 25I differential termi-
nation, output common-mode
80
60
voltage = V
CC
Maximum Modulation Current
I
mA
mA
MODMAX
P-P
Current into external 50I differential termi-
nation, output common-mode
voltage = V
CC
Minimum Modulation Current
Differential Output Resistance
I
10
MODMIN
P-P
2 x R
50
I
OUT
Current between TOUT+ and TOUT- when
DISABLE = high or TX_EN = low or
SET_IMOD = H0x00
Modulation-Off Maximum Current
Modulation Current DAC Stability
I
100
FA
%
MOD-OFF
10mA P I
P 80mA (Notes 1, 3)
1.5
22
3
MOD
20% to 80%, 20mA P I
P 80mA
P 80mA,
30
MOD
Modulation Current Edge Speed
(Note 1)
t
t
ps
R, F
20% to 80%, 10mA P I
MOD
22
5
30
12
12
TXDE_MD[1:0] = 3d
10mA P I
P 60mA, 11.3Gbps, output
MOD
differential load = 50I
10mA P I P 80mA, 11.3Gbps, output
MOD
5
differential load = 25I
Deterministic Jitter (Notes 1, 4)
DJ
RJ
ps
P-P
10mA P I P 80mA, 11.3Gbps, output
MOD
7
differential load = 5I
10mA P I P 60mA, 10.7Gbps, output
MOD
5
10.5
0.55
differential load = 50I (K28.5 pattern)
10mA P I P 80mA, output differential
MOD
Random Jitter
0.19
ps
RMS
load = 25I (Note 1)
Part powered on, f P 5GHz
Part powered on, f P 10GHz
8
6
Differential Output Return Loss
SDD22
dB
_______________________________________________________________________________________
3
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.85V to +3.63V, T = -40°C to +85°C, and Figure 1. Guaranteed by design and characterization from T = -40°C to +95°C.
A
A
Typical values are at V
noted.) (Note 1)
= +3.3V, I
= 60mA, I
= 40mA, 25I differential output load, and T = +25°C, unless otherwise
MOD A
CC
BIAS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SAFETY FEATURES
FAULT always occurs for V
R 1.3,
BMAX
Threshold Voltage at BMAX
Threshold Voltage at BIAS
V
FAULT never occurs for V
(Note 1, Figure 1)
< 1.1
BMAX
1.1
1.2
1.3
V
V
V
BMAX
FAULT never occurs for V
R 0.57,
BIAS
V
0.44
0.48
0.57
BIAS
FAULT always occurs for V
< 0.44
BIAS
Warning always occurs for V
R
BMON
V
CC
0.7
-
V
CC
0.6
-
V
CC
-
Threshold Voltage at BMON
SFP TIMING REQUIREMENTS
DISABLE Assert Time
V
V
V
- 0.5V, warning never occurs for
CC
BMON
0.5
< V
- 0.7V
BMON
CC
Time from rising edge of DISABLE input
signal to I < I and I
t
<
MOD
0.05
1
Fs
_OFF
BIAS
BIAS-OFF
I
MOD-OFF
Time from falling edge of DISABLE to I
BIAS
DISABLE Negate Time
t
0.5
50
5
200
2
Fs
Fs
Fs
Fs
_ON
and I
at 90% of steady state
MOD
FAULT Reset Time of Power-On
Time
Time from power-on or negation of FAULT
using DISABLE
t
_INIT
Time from fault to FAULT on, C
P
FAULT
FAULT Reset Time
DISABLE to Reset
t
0.5
_FAULT
20pF, R
= 4.7kI
FAULT
Time DISABLE must be held high to reset
FAULT
0.5
80
BIAS CURRENT DAC
Full-Scale Current
LSB Size
I
SET_IBIAS[8:1] = HxFF
100
190
±0.5
mA
FA
BIAS-FS
Integral Nonlinearity
INL
5mA P I
5mA P I
P 80mA
%FS
BIAS
P 80mA, guaranteed mono-
BIAS
Differential Nonlinearity
DNL
LSB
±0.5
tonic at 8-bit resolution SET_IBIAS[8:1]
MODULATION CURRENT DAC (25I DIFFERENTIAL LOAD)
Full-Scale Current
LSB Size
I
SET_IMOD[8:1] = HxFF
80
105
200
Q1
mA
FA
MOD-FS
Integral Nonlinearity
INL
10mA P I
10mA P I
P 80mA
%FS
MOD
P 80mA, guaranteed mono-
MOD
Differential Nonlinearity
DNL
Q0.5
LSB
tonic at 9-bit resolution SET_IMOD[8:0]
CONTROL I/O SPECIFICATIONS
I
12
IH
DISABLE Input Current
FA
I
Depends on pullup resistance
500
800
IL
DISABLE Input High Voltage
DISABLE Input Low Voltage
V
1.8
0
V
V
V
IH
CC
V
0.8
IL
4
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.85V to +3.63V, T = -40°C to +85°C, and Figure 1. Guaranteed by design and characterization from T = -40°C to +95°C.
A
A
Typical values are at V
noted.) (Note 1)
= +3.3V, I
= 60mA, I
= 40mA, 25I differential output load, and T = +25°C, unless otherwise
MOD A
CC
BIAS
PARAMETER
DISABLE Input Resistance
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, SCL, CSEL)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
R
Internal pullup resistor
4.7
7.5
10
kI
PULL
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.0
V
V
V
IH
CC
V
0.8
IL
V
80
mV
HYST
V
= 0V or V , internal pullup or pull-
CC
IN
Input Leakage Current
I , I
IL IH
150
FA
down is 75kI typical
Output High Voltage
Output Low Voltage
V
External pullup is (4.7kI to 10kI) to V
External pullup is (4.7kI to 10kI) to V
V - 0.5
CC
V
V
OH
CC
V
0.4
OL
CC
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (Figure 5)
SCL Clock Frequency
SCL Pulse-Width High
SCL Pulse-Width Low
SDA Setup Time
f
400
1000
kHz
Fs
SCL
t
0.5
CH
t
0.5
Fs
CL
DS
DH
t
100
100
ns
SDA Hold Time
t
ns
SCL Rise to SDA Propagation
Time
t
5
ns
ns
ns
D
CSEL Pulse-Width Low
t
500
CSW
CSEL Leading Time Before the
First SCL Edge
t
t
500
500
L
T
CSEL Trailing Time After the Last
SCL Edge
ns
Total bus capacitance on one line with
4.7kI pullup to V
SDA, SCL Load
C
B
20
pF
CC
Note 1: Guaranteed by design and characterization (T = -40NC to +95NC).
A
Note 2: BIAS is connected to 2.0V. TOUT+/TOUT- are connected through pullup inductors to a separate supply that is equal to V
.
CCT
I
= 4.92 + 0.0383 x I + 0.3692 x I
BIAS MOD
CC
Note 3: Stability is defined as [(I_measured) - (I_reference)]/(I_reference) over the listed current range, temperature, and V
=
CC
V
Q5%. V
= 3.0V to 3.45V. Reference current measured at V
, T = +25NC.
CCREF
CCREF
CCREF
A
7
7
Note 4: Measured with K28.5 data pattern at 10.7Gbps and with a (2 - 1 PRBS + 72 zeros + 2 - 1 PRBS (inverted) + 72 ones)
pattern at 11.3Gbps.
_______________________________________________________________________________________
5
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
V
CCD
0.01µF
V
CC
V
+
-
CCT
2.0V
4.7kI
0.01µF
0.1µF
V
CC
V
V
CCT
EET
V
CC
V
CC
0.01µF
SAMPLING
OSCILLOSCOPE
0.1µF
0.1µF
0.01µF
35I
Z = 50I
25I
50I
50I
TIN+
TIN-
TOUT+
0
MAX3946
75I
0.01µF
Z = 50I
0
25I
TOUT-
EP
35I
50I
50I
V
V
CC
CC
0.01µF
V
V
CCT
EET
V
CCT
V
CC
0.01µF
0.01µF
0.1µF
1kI
1kI
4.7kI
Figure 1. AC Test Setup
6
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Typical Operating Characteristics
7
7
(V
CC
= +3.3V, T = +25°C, data pattern = 2 - 1 PRBS + 72 zeros + 2 - 1 PRBS (inverted) +72 ones, unless otherwise noted.)
A
10.3Gbps OPTICAL EYE DIAGRAM
10.3Gbps ELECTRICAL EYE DIAGRAM
MAX3946 toc01
MAX3946 toc02
23
2
- 1 PRBS
50Ω LOAD
20ps/div
INPUT DIFFERENTIAL RETURN LOSS
vs. FREQUENCY
INPUT COMMON-MODE RETURN LOSS
vs. FREQUENCY
INPUT DIFFERENTIAL TO COMMON-MODE
RETURN LOSS vs. FREQUENCY
0
0
-5
0
-10
-20
-30
-40
-50
-5
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
100
1000
10,000
100,000
1000
10,000
100,000
100
1000
10,000
100,000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT DIFFERENTIAL RETURN LOSS
vs. FREQUENCY
OUTPUT COMMON-MODE RETURN LOSS
vs. FREQUENCY
RANDOM JITTER vs. MODULATION
CURRENT (AT LOAD)
0
-5
0
-5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
11.3Gbps, 25Ω DIFFERENTIAL LOAD
1111 0000 PATTERN
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
-35
100
1000
10,000
100,000
100
1000
10,000
100,000
0
10 20 30 40 50 60 70 80
FREQUENCY (MHz)
FREQUENCY (MHz)
MODULATION CURRENT (mA
)
P-P
_______________________________________________________________________________________
7
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Typical Operating Characteristics (continued)
7
7
(V
CC
= +3.3V, T = +25°C, data pattern = 2 - 1 PRBS + 72 zeros + 2 - 1 PRBS (inverted) +72 ones, unless otherwise noted.)
A
SUPPLY CURRENT vs. TEMPERATURE
(I = 40mA , I = 60mA)
TOTAL CURRENT vs. TEMPERATURE
AT LOAD = 40mA , I = 60mA)
EYE CROSSING PERCENT
vs. SET_PWCTRL
(I
MOD
P-P BIAS
MOD
P-P BIAS
100
220
210
200
190
180
170
160
150
140
75
70
65
60
55
50
45
40
35
30
25
CURRENT INTO V , V , AND V
PLUS MODULATION AND BIAS CURRENT
PINS
CCD
CURRENT INTO V , V , AND V
PINS
CC CCT
CC CCT
CCD
90
80
70
60
50
25Ω LOAD
(25Ω LOAD) = 45.8 + 1.038 x I
I
+
TOTAL
BIAS
2.08 x I
MOD
5Ω LOAD
(5Ω LOAD) = 45.8 + 1.038 x I
I
+
TOTAL
BIAS
1.57 x I
MOD
-40 -25 -10
5
20 35 50 65 80 95
-40 -25 -10
5
20 35 50 65 80 95
TEMPERATURE (°C)
TEMPERATURE (°C)
SET_PWCTRL[3:0]
BIAS CURRENT
vs. DAC SETTING
MODULATION CURRENT (AT LOAD)
vs. DAC SETTING
MODULATION CURRENT DEEMPHASIS
vs. MANUAL DEEMPHASIS SETTING
120
100
80
60
40
20
0
90
80
70
60
50
40
30
20
10
0
10
9
8
7
6
5
4
3
2
1
0
SET_IMOD[8:0] = 230d
TXDE_MD[1:0] = 2d
R
= 25Ω
LOAD
DIFFERENTIAL
R
= 50Ω
LOAD
DIFFERENTIAL
0
200
400
600
0
200
400
600
10
20
30
40
SET_IBIAS[8:0]
SET_IMOD[8:0]
SET_TXDE[5:0]
BIAS MONITOR CURRENT
vs. TEMPERATURE
TRANSITION TIME
vs. MODULATION CURRENT
TRANSITION TIME
vs. DEEMPHASIS SETTING
700
600
500
400
300
200
100
0
40
35
30
25
20
15
10
40
35
30
25
20
15
10
25Ω LOAD, 20% TO 80%
10Gbps, 11111 00000 PATTERN
SET_IMOD[8:0] = 230d
25Ω LOAD, 20% TO 80%
10Gbps, 1111 0000 PATTERN
I
= 60mA
BIAS
I
= 30mA
BIAS
FALL TIME
RISE TIME
FALL TIME
RISE TIME
I
= 10mA
BIAS
-40 -25 -10
5
20 35 50 65 80 95
0
20
40
I
60
(mA)
80
100
10
20
30
40
TEMPERATURE (°C)
SET_TXDE[5:0]
MOD
8
______________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Typical Operating Characteristics (continued)
7
7
(V
CC
= +3.3V, T = +25°C, data pattern = 2 - 1 PRBS + 72 zeros + 2 - 1 PRBS (inverted) +72 ones, unless otherwise noted.)
A
TRANSMITTER DISABLE
TRANSMITTER ENABLE
RESPONSE TO FAULT
MAX3946 toc20
MAX3946 toc18
MAX3946 toc19
V
V
CC
CC
EXTERNAL FAULT
V
BIAS
3.3V
3.3V
t_ = 600ns
ON
HIGH
FAULT
LOW
LOW
FAULT
FAULT
HIGH
HIGH
DISABLE
DISABLE
LOW
LOW
LOW
DISABLE
OUTPUT
OUTPUT
OUTPUT
100ns/div
1µs/div
1µs/div
FAULT RECOVERY
FREQUENT ASSERTION OF DISABLE
MAX3946 toc21
MAX3946 toc22
EXTERNAL FAULT
V
V
BIAS
BIAS
EXTERNAL FAULT
REMOVED
HIGH
LOW
FAULT
FAULT
LOW
HIGH
LOW
HIGH
DISABLE
OUTPUT
DISABLE
OUTPUT
LOW
4µs/div
4µs/div
_______________________________________________________________________________________
9
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Pin Configuration
TOP VIEW
18
17
16
15
14
13
12
11
10
9
V
19
20
V
CCT
EET
TOUT+
TOUT+
V
CC
TIN+ 21
TIN- 22
MAX3946
TOUT-
TOUT-
V
8
23
24
CC
*EP
+
7
V
V
CCT
EET
1
2
3
4
5
6
THIN QFN
(4mm × 4mm)
*EXPOSED PAD CONNECTED TO GROUND.
Pin Description
PIN
NAME
FUNCTION
Power Supply. Provides supply voltage to the digital block.
Disable Input, CMOS Input. Set to logic-low for normal operation. Logic-high or open disables both
the modulation current and the bias current. Internally pulled up by a 7.5kI resistor to V
1, 15
V
CCD
2
3
DISABLE
FAULT
.
CC
Fault Output, Open Drain. Logic-high indicates a fault condition. FAULT remains high even after the
fault condition has been removed. A logic-low occurs when the fault condition has been removed and
the fault latch has been cleared by toggling the DISABLE pin. FAULT should be pulled up to V
by
CC
a 4.7kI to 10kI resistor.
Analog Laser Bias-Current Limit. A resistive voltage-divider connected among BMON, BMAX, and
ground sets the maximum allowed laser bias current limit. The voltage at BMAX is internally com-
pared to 1.2V bandgap reference voltage.
4
5
BMAX
BMON
Bias Current-Monitor Output. Current out of this pin develops a ground-referenced voltage across
external resistor(s) that is proportional to the laser bias current. The current sourced by this pin is
typically 1/100th the BIAS pin current.
6, 7, 12, 13
8, 9
V
Power Supply. Provides supply voltage to the output block.
CCT
TOUT-
TOUT+
BIAS
Inverted Modulation Current Output. Internally pulled up by a 25I resistor to V
.
CCT
10, 11
14
Noninverted Modulation Current Output. Internally pulled up by a 25I resistor to V
.
CCT
Laser Bias Current Connection
Chip-Select Input, CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low ends
the cycle and resets the control state machine. Internally pulled down by a 75kI resistor to ground.
16
17
CSEL
SDA
Serial-Data Bidirectional Input, CMOS. Open-drain output. This pin has a 75kI internal pullup, but it
requires an external 4.7kI to 10kI pullup resistor. (Data line-collision protection is implemented.)
10 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Pin Description (continued)
PIN
18
NAME
FUNCTION
Serial-Clock Input, CMOS. This pin has 75kI internal pulldown.
Ground
SCL
19, 24
20, 23
21
V
EET
V
CC
Power-Supply Connections. Provides supply voltage to the core circuitry.
Noninverted Data Input
TIN+
TIN-
22
Inverted Data Input
Exposed Pad. Ground. Must be soldered to circuit board ground for proper thermal and electrical
performance (see the Exposed-Pad Package and Thermal Considerations section).
—
EP
V
CCD
7.5kI
TOUT+
DISABLE
EYE SAFETY AND
OUTPUT CONTROL
TX_EN
25I
25I
FAULT
BMAX
V
CCT
LASER BIAS
CURRENT LIMITER
V
CM
POWER-ON RESET
TOUT-
BIAS
50I
50I
TX_POL
TIN+
TIN-
1
0
I
I
BIAS
PW
CONTROL
EQ
BIAS
100
V
CC
I
+ I
MOD_DAC DE_DAC
BMON
V
CCD
CONTROL
LOGIC
75kI
SDA
3-WIRE
INTERFACE
SCL
REGISTER
CSEL
MAX3946
75kI
75kI
SET_TXEQ
SET_PWCTRL
9b DAC SET_IMOD
6b DAC SET_TXDE
9b DAC SET_IBIAS
Figure 2. Functional Diagram
______________________________________________________________________________________ 11
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
the initialization procedure after POR. The LSB (bit 0)
of SET_IBIAS is initialized to zero after POR and can
be updated using the BIASINC register. The IBIASMAX
register should be programmed to a desired maximum
Detailed Description
The MAX3946 SFP+ laser driver is designed to drive
5I to 50I lasers from 1Gbps to 11.3Gbps. The device
contains an input buffer with programmable equaliza-
bias current value (up to 96mA) to protect the laser. The
tion, pulse-width adjustment, bias current and modula-
IBIASMAX register limits the maximum SET_IBIAS[8:1]
tion current DACs, output driver with programmable
DAC code.
deemphasis, power-on reset circuitry, bias monitor, laser
After initialization the value of the SET_IBIAS DAC reg-
current limiter, and eye-safety circuitry. A 3-wire digital
ister should be updated using the BIASINC register
interface is used to control the transmitter functions.
to optimize cycle time and enhance laser safety. The
The registers that control the device’s functionality are
BIASINC register is an 8-bit register where the first 5
TXCTRL, SET_IMOD, SET_IBIAS, IMODMAX, IBIASMAX,
bits contain the increment information in two’s comple-
MODINC, BIASINC, SET_TXEQ, SET_PWCTRL, and
ment notation. Increment values range from -8 to +7
SET_TXDE.
LSBs. If the updated value of SET_IBIAS[8:1] exceeds
Input Buffer with Programmable
Equalization
IBIASMAX[7:0], the IBIASERR warning flag is set and
SET_IBIAS[8:0] remains unchanged.
The input is internally biased and terminated with 50Ito
a common-mode voltage. The first amplifier stage fea-
tures a programmable equalizer for high-frequency loss-
es including SFP connector. Equalization is controlled
by the SET_TXEQ register and TXEQ_EN bit, TXCTRL[3]
(Table 1). The TX_POL bit in the TXCTRL register con-
trols the polarity of TOUT+ and TOUT- vs. TIN+ and TIN-.
The SET_PWCTRL register controls the output eye cross-
ing (Table 5). A status indicator bit (TXED) monitors the
presence of an AC input signal.
Modulation Current DAC
The modulation current from the device is optimized to
provide up to 80mA of modulation current into a 5I to
25I differential laser load (60mA for 50I laser load)
with 300FA to 200FA resolution. The modulation current
is controlled through the 3-wire digital interface using
the SET_IMOD, IMODMAX, MODINC, and SET_TXDE
registers.
For laser operation, the laser modulation current can be
set using the 9-bit SET_IMOD DAC. The upper 8 bits
are set by the SET_IMOD[8:1] register, commonly used
during the initialization procedure after POR. The LSB (bit 0)
of SET_IMOD is initialized to zero after POR and can
be updated using the MODINC register. The IMODMAX
register should be programmed to a desired maximum
modulation current value (up to 96mA) to protect the
laser. The IMODMAX register limits the maximum
SET_IMOD[8:1] DAC code.
Bias Current DAC
The device’s bias current is optimized to provide up
to 80mA of bias current into a 5I to 50I laser load
with 200FA resolution. The bias current is controlled
through the 3-wire digital interface using the SET_IBIAS,
IBIASMAX, and BIASINC registers.
For laser operation, the laser bias current can be set
using the 9-bit SET_IBIAS DAC. The upper 8 bits are set
by the SET_IBIAS[8:1] register, commonly used during
Table 1. Input Equalization Control Register Settings
TXCTRL[3]
SET_TXEQ[2:1]
DESCRIPTION
TXEQ_EN
0
1
1
1
1
X
0
0
1
1
X
0
1
0
1
150mV
to 1000mV
differential input amplitude (default setting)
P-P P-P
Optimized for 1in to 4in FR4, 190mV
Optimized for 4in to 6in FR4, 190mV
Optimized for 1in to 4in FR4, 450mV
Optimized for 4in to 6in FR4, 450mV
to 450mV
to 450mV
to 700mV
to 700mV
differential launch amplitude from source
differential launch amplitude from source
differential launch amplitude from source
differential launch amplitude from source
P-P
P-P
P-P
P-P
P-P
P-P
P-P
P-P
12 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
BIAS
V
CC
MAX3946
I
BIAS
+
-
0.6V
100
IF BMAX AND
BMON ARE
NOT USED
IF BMAX IS
NOT USED
IF BMON IS
NOT USED
OR
OR
OR
WARNING
BMON
BMAX
R1
R2
R1
100kI
1kI
FAULT
1.2V
1kI
R2
Figure 3. BMON and BMAX Circuitry
After initialization the value of the SET_IMOD DAC reg-
ister should be updated using the MODINC register
to optimize cycle time and enhance laser safety. The
MODINC register is an 8-bit register where the first 5 bits
contain the increment information in two’s comple-
ment notation. Increment values range from -8 to +7
LSBs. If the updated value of SET_IMOD[8:1] exceeds
IMODMAX[7:0], the IMODERR warning flag is set and
SET_IMOD[8:0] remains unchanged.
BMON and BMAX Functions
Current out of the BMON pin is typically 1/100th the
value of the current at the BIAS pin. The total resistance
to ground at BMON sets the voltage gain. An internal
comparator at the BMAX pin latches a fault if the voltage
on BMAX exceeds the value of 1.2V. The BMAX voltage-
sense pin is connected by means of a voltage-divider to
the BMON pin and ground. The full-scale range of the
BMON voltage is 1.2V x (R1/R2 + 1) (Figure 3). The ana-
log bias-current limit is determined by (1.2V/R2) x 100.
Modulation current sent to the laser is actually the com-
bination of the current generated by the SET_IMOD reg-
ister and current subtracted from this by the SET_TXDE
register.
Eye Safety and Output Control Circuitry
The safety and output control circuitry includes the dis-
able pin (DISABLE) and disable bit (TX_EN), along with a
fault indicator and fault detectors (Figure 4). The device
has two types of faults, HARD FAULT and SOFT FAULT.
A HARD FAULT triggers the FAULT pin, and the output
to the laser is disabled. A SOFT FAULT operates as a
warning, and the outputs are not disabled. Both types of
faults are stored in the TXSTAT1 and TXSTAT2 registers.
Output Driver
The output driver is optimized for a 5I to 50I differen-
tial load. The output stage also features programmable
deemphasis that can be set as a percentage of the mod-
ulation current. The deemphasis function is controlled by
the TXDE_MD[1] and TXDE_MD[0] bits (TXCTRL[5:4])
and SET_TXDE[5:0].
The FAULT pin is a latched output that can be cleared
by toggling the DISABLE pin. Toggling the DISABLE
pin also clears the TXSTAT1 and TXSTAT2 registers.
Power-On Reset (POR)
POR ensures that the laser is off until supply voltage has
reached a specified threshold (2.75V). After POR, bias
current and modulation current ramps are controlled to
avoid overshoot. In the case of a POR, all registers are
reset to their default values.
A single-point fault can be a short to V
or ground.
CC
Table 2 shows the circuit response to various single-
point failures.
______________________________________________________________________________________ 13
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
FAULT REGISTERS
V
CC
TOUT-
TOUT+
<0> FAULT
I
MOD
0.44V
<1>
<2>
BIAS
V
- 2V
CC
FAULT REGISTER
TXSTAT1
<3>
V
- 1.3V
1.3V
CC
I
BIAS
BMAX
ADDR = H0x06
<4>
<5>
<6>
I
BIAS
UNUSED
100
BMON
V
CC
- 0.5V
2.3V
POR
<7>
V
RESET
CC
7.5kI
DISABLE
WARNING REGISTER
TXSTAT2
UNUSED
<0>
LOSS-OF-SIGNAL
CIRCUIT
ADDR = H0x07
<1>
SET_IBIAS
IBIASMAX
SET_IMOD
IMODMAX
<2>
<3>
Figure 4. Eye Safety Circuitry
14 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Table 2. Circuit Response to Single-Point Faults
PIN
NAME
SHORT TO V
SHORT TO GROUND
OPEN
CC
1
V
CCD
Normal
Disabled—HARD FAULT
Normal (Note 3)—Redundant path
Normal (Note 1). Can only be dis-
abled by other means.
2
DISABLE
Disabled
Disabled
3
4
5
FAULT
BMAX
BMON
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Disabled—HARD FAULT
Disabled—HARD FAULT
Disabled—HARD FAULT
Disabled—HARD FAULT
Disabled—Fault (external supply
shorted) (Note 2)
6
7
V
Normal
Normal
Normal (Note 3)—Redundant path
Normal (Note 3)—Redundant path
CCT
CCT
Disabled—Fault (external supply
shorted) (Note 2)
V
8
9
TOUT-
TOUT-
TOUT+
TOUT+
I
I
I
I
is reduced
is reduced
is reduced
is reduced
Disabled—HARD FAULT
Disabled—HARD FAULT
Disabled—HARD FAULT
Disabled—HARD FAULT
I
I
I
I
is reduced
is reduced
is reduced
is reduced
MOD
MOD
MOD
MOD
MOD
MOD
MOD
MOD
10
11
Disabled—Fault (external supply
shorted) (Note 2)
12
V
Normal
Normal
Normal (Note 3)—Redundant path
CCT
CCT
Disabled—Fault (external supply
shorted) (Note 2)
13
14
15
V
Normal (Note 3)—Redundant path
Disabled—HARD FAULT
BIAS
I
is on—No fault
Disabled—HARD FAULT
BIAS
Disabled—Fault (external supply
shorted) (Note 2)
V
CCD
Normal
Normal (Note 3)—Redundant path
16
17
18
CSEL
SDA
SCL
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Normal (Note 1)
Disabled—Fault (external
supply shorted) (Note 2)
19
20
V
Normal
Normal (Note 3)—Redundant path
Normal (Note 3)—Redundant path
EET
Disabled—HARD FAULT (external
supply shorted) (Note 2)
V
Normal
CC
21
22
TIN+
TIN-
SOFT FAULT
SOFT FAULT
SOFT FAULT
SOFT FAULT
Normal (Note 1)
Normal (Note 1)
Disabled—HARD FAULT (external
supply shorted) (Note 2)
23
24
V
Normal
Normal (Note 3)—Redundant path
Normal (Note 3)—Redundant path
CC
Disabled—Fault (external
supply shorted) (Note 2)
V
Normal
EET
Note 1: Normal—Does not affect laser power.
Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device), and the main supply is col-
lapsed by the short.
Note 3: Normal in functionality, but performance could be affected.
Warning: Shorted to V
or shorted to ground on some pins can violate the Absolute Maximum Ratings.
CC
______________________________________________________________________________________ 15
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Read Mode (RWN = 1)
3-Wire Interface
The device implements a proprietary 3-wire digital inter-
face. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL pin has been set
to a logic-high. All data transfers are most significant bit
(MSB) first.
The master generates 16 total clock cycles at SCL. The
master outputs a total of 8 bits (MSB first) to the SDA line
at the falling edge of the clock. The SDA line is released
after the RWN bit has been transmitted. The slave out-
puts 8 bits of data (MSB first) at the rising edge of the
clock. The master closes the transmission by setting
CSEL to 0. Figure 5 shows the interface timing.
Mode Control
Normal mode allows read-only instruction for all regis-
ters except MODINC and BIASINC. The MODINC and
BIASINC registers can be updated during normal mode.
Doing so speeds up the laser control update through the
3-wire interface by a factor of two. The normal mode is
the default mode.
Protocol
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates 16
clock cycles to SCL. All operations transfer 8 bits to the
device. The RWN bit determines if the cycle is read or
write. See Table 3.
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2)
registers. To enter the setup mode, the MODECTRL
register (address = H0x0E) must be set to H0x12. After
the MODECTRL register has been set to H0x12, the
next operation is unrestricted. The setup mode is auto-
matically exited after the next operation is finished. This
sequence must be repeated if further unrestricted set-
tings are necessary.
Register Addresses
The device contains 13 registers available for program-
ming. Table 4 shows the registers and addresses.
Write Mode (RWN = 0)
The master generates 16 total clock cycles at SCL. The
master outputs a total of 16 bits (MSB first) to the SDA
line at the falling edge of the clock. The master closes
the transmission by setting CSEL to 0. Figure 5 shows
the interface timing.
Table 3. Digital Communication Word Structure
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Register Address
RWN
Data that is written or read
Table 4. Register Descriptions and Addresses
ADDRESS
H0x05
H0x06
H0x07
H0x08
H0x09
H0x0A
H0x0B
H0x0C
H0x0D
H0x0E
H0x0F
H0x10
H0x11
NAME
TXCTRL
FUNCTION
Transmitter Control Register
Transmitter Status Register 1
Transmitter Status Register 2
Bias Current Setting Register
TXSTAT1
TXSTAT2
SET_IBIAS
SET_IMOD
IMODMAX
IBIASMAX
MODINC
Modulation Current Setting Register
Maximum Modulation Current Setting Register
Maximum Bias Current Setting Register
Modulation Current Increment Setting Register
Bias Current Increment Setting Register
Mode Control Register
BIASINC
MODECTRL
SET_PWCTRL
SET_TXDE
SET_TXEQ
Pulse-Width Control Register
Deemphasis Control Register
Equalization Control Register
16 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
WRITE MODE
CSEL
SCL
t
t
T
L
t
CH
0
t
CL
1
2
3
4
5
6
7
8
9
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
t
DS
SDA
A6
A5
A4
A3
A2
A1
A0
RWN
D7
D6
t
DH
READ MODE
CSEL
SCL
t
t
T
L
t
CH
0
t
CL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
t
D
DS
SDA
A6
A5
A4
A3
A2
A1
A0
RWN
D7
D6
D5
D4
D3
D2
D1
D0
t
DH
Figure 5. Timing for 3-Wire Digital Interface
Transmitter Control Register (TXCTRL)
Bit #
7
X
X
6
X
X
5
4
3
2
1
TX_POL
1
0
TX_EN
1
ADDRESS
Name
TXDE_MD[1] TXDE_MD[0] TXEQ_EN SOFTRES
H0x05
Default Value
0
0
0
0
Bits 5 and 4: TXDE_MD[1:0]. Controls the mode of the transmit output deemphasis circuitry.
00 = deemphasis is fixed at 6.25% of the modulation amplitude
01 = deemphasis is fixed at 3.125% of the modulation amplitude
10 = deemphasis is programmed by the SET_TXDE register setting
11 = deemphasis is at its maximum of approximately 9%
Bit 3: TXEQ_EN. Enables or disables the input equalization circuitry.
0 = disabled
1 = enabled
Bit 2: SOFTRES. Resets all registers to their default values.
0 = normal
1 = reset
Bit 1: TX_POL. Controls the polarity of the signal path.
0 = inverse
1 = normal
Bit 0: TX_EN. Enables or disables the output circuitry.
0 = disabled
1 = enabled
______________________________________________________________________________________ 17
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Transmitter Status Register 1 (TXSTAT1)
7
6
5
4
3
2
1
0
Bit #
ADDRESS
(STICKY) (STICKY) (STICKY) (STICKY) (STICKY) (STICKY) (STICKY) (STICKY)
Name
FST[7]
X
FST[6]
X
X
X
FST[4]
X
FST[3]
X
FST[2]
X
FST[1]
X
TX_FAULT
X
H0x06
Default Value
Bit 7: FST[7]. When the V
supply voltage is below 2.3V, the POR circuitry reports a fault. Once the V
supply
CCT
CCT
voltage is above 2.75V, the POR resets all registers to their default values and the fault is cleared.
Bit 6: FST[6]. When the voltage at BMON is above V - 0.5V, a SOFT FAULT is reported.
CC
Bit 4: FST[4]. When the voltage at BMAX goes above 1.3V, a HARD FAULT is reported.
Bit 3: FST[3]. When the common-mode voltage at V goes below V - 1.3V, a SOFT FAULT is reported.
TOUTQ
CC
Bit 2: FST[2]. When the voltage at V
goes below V
- 0.8V, a HARD FAULT is reported.
TOUTQ
CC
Bit 1: FST[1]. When the BIAS voltage goes below 0.44V, a HARD FAULT is reported.
Bit 0: TX_FAULT. Copy of a FAULT signal in FST[7:6] and FST[4:1]. A POR resets the FST bits to 0.
Transmitter Status Register 2 (TXSTAT2)
3
2
1
0
Bit #
7
6
5
4
ADDRESS
(STICKY) (STICKY) (STICKY) (STICKY)
Name
X
X
X
X
X
X
X
X
IMODERR IBIASERR
TXED
X
X
X
H0x07
Default Value
X
X
Bit 3: IMODERR. Any attempt to modify SET_IMOD[8:1] above IMODMAX[7:0] flags a warning at IMODERR. (See the
Programming Modulation Current section.)
Bit 2: IBIASERR. Any attempt to modify SET_IBIAS[8:1] above IBIASMAX[7:0] flags a warning at IBIASERR. (See the
Programming Bias Current section.)
Bit 1: TXED. This indicates the absence of an AC signal at the transmit input.
Bias Current Setting Register (SET_IBIAS)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS SET_IBIAS
Name
[8] (MSB)
[7]
[6]
[5]
[4]
[3]
[2]
[1]
H0x08
Default Value
0
0
0
0
0
0
0
1
Bits 7 to 0: SET_IBIAS[8:1]. The bias current DAC is controlled by a total of 9 bits. The SET_IBIAS[8:1] bits are used
to set the bias current with even denominations from 0 to 510 bits. The LSB (SET_IBIAS[0]) is controlled by the BIASINC
register and is used to set the odd denominations in the SET_IBIAS[8:0]. Any direct write to SET_IBIAS[8:1] resets the
LSB.
18 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Modulation Current Setting Register (SET_IMOD)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD SET_IMOD
Name
[8] (MSB)
[7]
[6]
[5]
[4]
[3]
[2]
[1]
H0x09
Default Value
0
0
0
0
0
1
0
0
Bits 7 to 0: SET_IMOD[8:1]. The modulation current DAC is controlled by a total of 9 bits. The SET_IMOD[8:1] bits
are used to set the modulation current with even denominations from 0 to 510 bits. The LSB (SET_IMOD[0]) is con-
trolled by the MODINC register and is used to set the odd denominations in the SET_IMOD[8:0]. Any direct write to
SET_IMOD[8:1] resets the LSB.
Maximum Modulation Current Setting Register (IMODMAX)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX IMODMAX
Name
[7] (MSB)
[6]
[5]
[4]
[3]
[2]
[1]
[0] (LSB)
H0x0A
Default Value
0
0
1
0
0
0
0
0
Bits 7 to 0: IMODMAX[7:0]. The IMODMAX register is an 8-bit register that can be used to limit the maximum modula-
tion current. IMODMAX[7:0] is continuously compared to SET_IMOD[8:1]. Any attempt to modify SET_IMOD[8:1] above
IMODMAX[7:0] is ignored and flags a warning at IMODERR.
Maximum Bias Current Setting Register (IBIASMAX)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
IBIASMAX IBIASMAX IBIASMAX IBIASMAX IBIASMAX IBIASMAX IBIASMAX IBIASMAX
Name
[7] (MSB)
[6]
[5]
[4]
[3]
[2]
[1]
[0] (LSB)
H0x0B
Default Value
0
0
1
0
0
0
0
0
Bits 7 to 0: IBIASMAX[7:0]. The IBIASMAX register is an 8-bit register that can be used to limit the maximum bias
current. IBIASMAX[7:0] is continuously compared to SET_IBIAS[8:1]. Any attempt to modify SET_IBIAS[8:1] above
IBIASMAX[7:0] is ignored and flags a warning at IBIASERR.
Modulation Current Increment Setting Register (MODINC)
Bit #
7
6
X
0
5
X
0
4
3
2
1
0
ADDRESS
SET_IMOD
[0] (LSB)
MODINC
[4] (MSB)
MODINC
[3]
MODINC
[2]
MODINC
[1]
MODINC
[0] (LSB)
Name
H0x0C
Default Value
0
0
0
0
0
0
Bit 7: SET_IMOD[0]. This is the LSB of the SET_IMOD[8:0] bits. This bit can only be updated by the use of MODINC[4:0].
Bits 4 to 0: MODINC[4:0]. This string of bits is used to increment or decrement the modulation current. When written
to, the SET_IMOD[8:0] bits are updated. MODINC[4:0] are a two’s complement string.
______________________________________________________________________________________ 19
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Bias Current Increment Setting Register (BIASINC)
Bit #
7
6
X
0
5
X
0
4
3
2
1
0
ADDRESS
SET_IBIAS
[0] (LSB)
BIASINC
[4] (MSB)
BIASINC
[3]
BIASINC
[2]
BIASINC
[1]
BIASINC
[0] (LSB)
Name
H0x0D
Default Value
0
0
0
0
0
0
Bit 7: SET_IBIAS[0]. This is the LSB of the SET_IBIAS[8:0] bits. This bit can only be updated by the use of BIASINC[4:0].
Bits 4 to 0: BIASINC[4:0]. This string of bits is used to increment or decrement the bias current. When written to, the
SET_IBIAS[8:0] bits are updated. BIASINC[4:0] are a two’s complement string.
Mode Control Register (MODECTRL)
Bit #
7
6
5
4
3
2
1
0
ADDRESS
MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL MODECTRL
Name
[7] (MSB)
0
[6]
0
[5]
0
[4]
0
[3]
0
[2]
0
[1]
0
[0](LSB)
0
H0x0E
Default Value
Bits 7 to 0: MODECTRL[7:0]. The MODECTRL register enables the user to switch between normal and setup modes.
The setup mode is achieved by setting this register to H0x12. MODECTRL must be updated before each write opera-
tion. Exceptions are MODINC and BIASINC, which can be updated in normal mode.
Pulse-Width Control Register (SET_PWCTRL)
Bit #
7
X
X
6
X
X
5
X
X
4
X
X
3
2
1
0
ADDRESS
SET_PWCTRL SET_PWCTRL SET_PWCTRL SET_PWCTRL
Name
[3] (MSB)
0
[2]
0
[1]
0
[0] (LSB)
0
H0x0F
Default Value
Bits 3 to 0: SET_PWCTRL[3:0]. This is a 4-bit register used to control the eye crossing by adjusting the pulse width.
Deemphasis Control Register (SET_TXDE)
Bit #
7
X
X
6
X
X
5
4
3
2
1
0
ADDRESS
SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE SET_TXDE
[5] (MSB)
Name
[4]
[3]
[2]
[1]
[0] (LSB)
H0x10
Default Value
0
0
0
0
0
1
Bits 5 to 0: SET_TXDE[5:0]. This is a 6-bit register used to control the amount of deemphasis on the transmitter output.
When calculating the total modulation current, the amount of deemphasis must be taken into account. The deemphasis
is set as a percentage of modulation current.
Equalization Control Register (SET_TXEQ)
Bit #
7
X
X
6
X
X
5
X
X
4
X
X
3
X
X
2
1
0
X
X
ADDRESS
SET_TXEQ SET_TXEQ
Name
[2]
[1]
H0x11
Default Value
0
0
Bits 2 to 1: SET_TXEQ[2:1]. These 2 bits are used to control the amount of equalization on the transmitter input. See
Table 1 for more information.
20 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
6b) TXDE_MD[1:0] = 01, then
Design Procedure
Programming Bias Current
0.3mA SET_IMOD 8:0 +16
[
]
(
)
50Ω
50Ω + R
LD
I
=
×
1) IBIASMAX[7:0] = Maximum_Bias_Current_Value
MOD
−0.15mA SET_IMOD 8:4 +1
[
]
(
)
2) SET_IBIAS [8:1] = Initial_Bias_Current_Value
i
Note: The total bias current is calculated using the
SET_IBIAS[8:0] DAC value. SET_IBIAS[8:1] are the bits
that can be manually written. SET_IBIAS[0] can only be
updated using the BIASINC register.
6c) TXDE_MD[1:0] = 10, then set SET_TXDE[5:0] can be
set to any value ≥ SET_IMOD[8:4] and
0.3mA SET_IMOD 8:0 +16
[
]
(
)
)
50Ω
50Ω + R
LD
I
=
×
MOD
When implementing an APC loop it is recommended to
use the BIASINC register, which guarantees the fastest
bias current update.
−0.15mA SET_TXDE 5:0 +1
[
]
(
When SET_TXDE[5:0] is increased, the deemphasis
current increases and the overall peak-to-peak modu-
lation current decreases. This effect saturates when
SET_TXDE[5:0] = 0.2 x (SET_IMOD[8:0] + 16) - 1, and
further increases to SET_TXDE[5:0] do not increase the
deemphasis current.
3) BIASINC [4:0] = New_Increment_Value
i
4) If (SET_IBIAS [8:1] P IBIASMAX[7:0]), then (SET_
i
IBIAS [8:0] = SET_IBIAS [8:0] + BIASINC [4:0])
i
i-1
i
5) Else (SET_IBIAS [8:0] = SET_IBIAS - [8:0])
i
i 1
The total bias current can be calculated as follows:
6d) TXDE_MD[1:0] = 11, then
6) I
= [SET_IBIAS [8:0] + 16] x 200FA
BIAS
i
50Ω
50Ω + R
×
I
= 0.9 × 0.3mA SET_IMOD 8:0 +16
[
]
(
)
Programming Modulation Current
1) IMODMAX[7:0] = Maximum_Modulation_Current_Value
MOD
LD
Note: When TXDE_MD[1:0] = 10 and the SET_TXDE
register is set by the user, the minimum allowed deem-
phasis is 3% and the maximum is 10%. These limits are
internally set by the MAX3946.
2) SET_IMOD[8:1] = Initial_Modulation_Current_Value x 1.06
i
Note: The total modulation laser current is calculated
using the SET_IMOD[8:0] DAC value, and the SET_TXDE
register value. SET_IMOD[8:1] are the bits that can be
manually written. SET_IMOD[0] can only be updated
using the MODINC register.
Programming Transmit Output Deemphasis
1) TXDE_MD[1:0] = Transmit_Deemphasis_Mode
When implementing modulation compensation, it is rec-
ommended to use the MODINC register, which guaran-
tees the fastest modulation current update.
2) SET_TXDE[5:0] = Transmit_Deemphasis_Value. If
TXDE_MD[1:0] = 00, 01, or 11, the value of SET_TXDE
is automatically set by the device and there is no
need to enter data to SET_TXDE.
3) MODINC [4:0] = New_Increment_Value
i
For Transmit_Deemphasis_Mode:
4) If (SET_IMOD [8:1] P IMODMAX[7:0]), then (SET_
i
IMOD [8:0] = SET_IMOD - [8:0] + MODINCi[4:0])
i
i 1
00 = deemphasis is fixed at 6% of the modulation ampli-
tude (the device controls the SET_TXDE value), default
setting
5) Else (SET_IMOD [8:0] = SET_IMOD - [8:0])
i
i 1
The following equations give the modulation current
(peak-to-peak) seen at the laser when driven differen-
01 = deemphasis is fixed at 3% of the modulation ampli-
tude (the device controls the SET_TXDE value)
tially. R
is the differential load impedance of the
EXTD
laser plus any added series resistance.
10 = deemphasis is programmed by the SET_TXDE
register setting
6a) TXDE_MD[1:0] = 00, then
11 = deemphasis is at its maximum of approximately 9%
(the device controls the SET_TXDE value)
0.3mA SET_IMOD 8:0 +16
[
]
(
)
50Ω
50Ω + R
LD
I
=
×
MOD
−0.15mA SET_IMOD 8:3 + 2
[
]
(
)
______________________________________________________________________________________ 21
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
pulse-width distortion. The code of 1111 corresponds to
a balanced state for differential output. The pulse-width
distortion is bidirectional around the balanced state (see
the Typical Operating Characteristics section).
Programming Pulse-Width Control
The eye crossing at the Tx output can be adjusted using
the SET_PWCTRL register. Table 5 shows these set-
tings. The sign of the number specifies the direction of
Applications Information
Table 5. Eye-Crossing Settings for
SET_PWCTRL
Laser Safety and IEC 825
Using the MAX3946 laser driver alone does not ensure
that a transmitter design is compliant with IEC 825. The
entire transmitter circuit and component selections must
be considered. Each user must determine the level of
fault tolerance required by the application, recognizing
that Maxim products are neither designed nor authorized
for use as components in systems intended for surgical
implant into the body, for applications intended to sup-
port or sustain life, or for any other application in which
the failure of a Maxim product could create a situation
where personal injury or death could occur.
SET_PWCTRL[3:0] PWD SET_PWCTRL[3:0] PWD
1000
1001
1010
1011
1100
1101
1110
1111
-7
-6
-5
-4
-3
-2
-1
0
0111
0110
0101
0100
0011
0010
0001
0000
8
7
6
5
4
3
2
1
Table 6. Register Summary
REGISTER
FUNCTION/
ADDRESS
BIT
NUMBER/
TYPE
REGISTER NORMAL SETUP
DEFAULT
VALUE
BIT NAME
NOTES
NAME
MODE
MODE
R
R
RW
RW
5
4
TXDE_MD[1]
TXDE_MD[0]
0
0
MSB deemphasis mode
LSB deemphasis mode
Input equalization
0: disabled, 1: enabled
R
R
R
RW
RW
RW
3
2
1
TXEQ_EN
SOFTRES
TX_POL
0
0
1
Transmitter
Control Register
Address =
H0x05
TXCTRL
Global digital reset
Tx polarity
0: inverse, 1: normal
Tx control
0: disabled, 1: enabled
R
R
R
R
RW
R
0
TX_EN
FST[7]
FST[6]
FST[4]
1
X
X
X
TX_PORàTX_VCC low-
limit violation
7 (sticky)
6 (sticky)
4 (sticky)
BMON open/shorted to
R
V
CC
BMAX current exceeded
or open/short to ground
R
Transmitter
Status Register 1
Address =
H0x06
V
common-mode
TOUT+/-
TXSTAT1
R
R
R
R
R
R
3 (sticky)
2 (sticky)
1 (sticky)
FST[3]
FST[2]
FST[1]
X
X
X
low-limit
V
low-limit violation
TOUT+/-
BIAS open or shorted to
ground
Copy of FAULT signal
in case POR bits 6 to 1
reset to 0
R
R
0 (sticky)
TX_FAULT
X
22 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Table 6. Register Summary (continued)
REGISTER
FUNCTION/
ADDRESS
BIT
NUMBER/
TYPE
REGISTER NORMAL SETUP
DEFAULT
VALUE
BIT NAME
NOTES
NAME
MODE
MODE
Warning increment result
> IMODMAX
R
R
R
R
3 (sticky)
2 (sticky)
IMODERR
IBIASERR
X
X
Transmitter
Status Register 2
Address =
H0x07
TXSTAT2
Warning increment result
> IBIASMAX
R
R
R
R
R
R
R
R
R
R
1 (sticky)
TXED
X
0
0
0
0
0
0
0
1
Tx edge detection
MSB bias DAC
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
SET_IBIAS[8]
SET_IBIAS[7]
SET_IBIAS[6]
SET_IBIAS[5]
SET_IBIAS[4]
SET_IBIAS[3]
SET_IBIAS[2]
SET_IBIAS[1]
Bias Current
Setting Register
Address =
H0x08
SET_IBIAS
Accessible through
REG_ADDR = H0x0D
7
SET_IBIAS[0]
0
LSB bias DAC
R
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
SET_IMOD[8]
SET_IMOD[7]
SET_IMOD[6]
SET_IMOD[5]
SET_IMOD[4]
SET_IMOD[3]
SET_IMOD[2]
SET_IMOD[1]
0
0
0
0
0
1
0
0
MSB modulation DAC
Modulation
Current Setting
Register
Address =
H0x09
SET_IMOD
Accessible through
REG_ADDR = H0x0C
7
SET_IMOD[0]
0
LSB modulation DAC
MSB modulation limit
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
IMODMAX[7]
IMODMAX[6]
IMODMAX[5]
IMODMAX[4]
IMODMAX[3]
IMODMAX[2]
IMODMAX[1]
IMODMAX[0]
IBIASMAX[7]
IBIASMAX[6]
IBIASMAX[5]
IBIASMAX[4]
IBIASMAX[3]
IBIASMAX[2]
IBIASMAX[1]
IBIASMAX[0]
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
Maximum
Modulation
Current Setting
Register
IMODMAX
Address =
H0x0A
LSB modulation limit
MSB bias limit
Maximum Bias
Current Setting
Register
IBIASMAX
Address =
H0x0B
LSB bias limit
______________________________________________________________________________________ 23
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Table 6. Register Summary (continued)
REGISTER
FUNCTION/
ADDRESS
BIT
NUMBER/
TYPE
REGISTER NORMAL SETUP
DEFAULT
VALUE
BIT NAME
NOTES
NAME
MODE
MODE
LSB of SET_IMOD DAC
register address = H0x09
R
R
7
4
SET_IMOD[0]
MODINC[4]
0
0
Modulation
Current
MSB MOD DAC two’s
complement
RW
RW
Increment
Setting Register
Address =
H0x0C
MODINC
RW
RW
RW
RW
RW
RW
3
2
1
MODINC[3]
MODINC[2]
MODINC[1]
0
0
0
LSB MOD DAC two’s
complement
RW
R
RW
R
0
7
4
MODINC[0]
SET_IBIAS[0]
BIASINC[4]
0
0
0
LSB of SET_IBIAS DAC
register address = H0x08
MSB bias DAC two’s
complement
Bias Current
Increment
RW
RW
Setting Register
Address =
H0x0D
BIASINC
RW
RW
RW
RW
RW
RW
3
2
1
BIASINC[3]
BIASINC[2]
BIASINC[1]
0
0
0
LSB bias DAC two’s
complement
RW
RW
0
BIASINC[0]
0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
7
6
5
4
3
2
1
0
MODECTRL[7]
MODECTRL[6]
MODECTRL[5]
MODECTRL[4]
MODECTRL[3]
MODECTRL[2]
MODECTRL[1]
MODECTRL[0]
0
0
0
0
0
0
0
0
MSB mode control
Mode Control
Register
Address =
H0x0E
MODECTRL
LSB mode control
MSB Tx pulse-width
control
R
RW
3
SET_PWCTRL[3]
0
Pulse-Width
Control Register
Address =
H0x0F
R
R
RW
RW
2
1
SET_PWCTRL[2]
SET_PWCTRL[1]
0
0
SET_
PWCTRL
LSB Tx pulse-width con-
trol
R
RW
0
SET_PWCTRL[0]
0
R
R
R
R
R
R
RW
RW
RW
RW
RW
RW
5
4
3
2
1
0
SET_TXDE[5]
SET_TXDE[4]
SET_TXDE[3]
SET_TXDE[2]
SET_TXDE[1]
SET_TXDE[0]
0
0
0
0
0
1
MSB Tx deemphasis
Deemphasis
Control Register
Address = H0x10
SET_TXDE
SET_TXEQ
LSB Tx deemphasis
Tx equalization
Equalization
Control Register
Address = H0x11
R
R
RW
RW
2
1
SET_TXEQ[2]
SET_TXEQ[1]
0
0
24 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
V
V
CCT
CCT
DEEMPHASIS
CONTROL
25I
25I
TOUT+
TOUT-
TIN+
50I
50I
CONTROL
LOOP
TIN-
V
V
EET
EET
V
CCT
V
V
CCD
CCD
FAULT
7.5kI
75kI
CLAMP
DISABLE
SDA
SCL, CSEL
75kI
V
EET
V
V
EER
EET
V
EER
Figure 6. Simplified I/O Structures
• Maintain 100I differential transmission line imped-
Layout Considerations
The data inputs and outputs are the most critical paths
for the device and great care should be taken to mini-
mize discontinuities on these transmission lines between
the connector and the IC. Here are some suggestions for
maximizing the performance of the IC:
ance into the IC.
• Use good high-frequency layout techniques and mul-
tilayer boards with an uninterrupted ground plane to
minimize EMI and crosstalk.
Refer to the schematic and board layers of the MAX3946
Evaluation Kit (MAX3946EVKIT) for more information.
• The data inputs should be wired directly between the
cable connector and IC without stubs.
Exposed-Pad Package and
Thermal Considerations
• The data transmission lines to the laser should be kept
as short as possible and be designed for 50I differ-
ential or 25I single-ended characteristic impedance.
The exposed pad on the 24-pin TQFN provides a very
low-thermal resistance path for heat removal from the IC.
The pad is also electrical ground on the IC and must be
soldered to the circuit board ground for proper thermal
and electrical performance. Refer to Application Note 862:
HFAN-08.1: Thermal Considerations of QFN and Other
Exposed-Paddle Packages for additional information.
• An uninterrupted ground plane should be positioned
beneath the high-speed I/Os.
• Ground path vias should be placed close to the IC and
the input/output interfaces to allow a return current
path to the IC and the laser.
______________________________________________________________________________________ 25
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Typical Application Circuit for 10GBASE-LRM
HOST BOARD
SFP CONNECTOR
SFP+ OPTICAL TRANSCEIVER
V
(3.3V)
CC
HOST FILTER
SUPPLY FILTER
V
CC
V
V
CCT
CCD
0.1µF
0.1µF
Z
= 100I
DIFF
TOUT-
TOUT+
TIN+
TIN-
FR4 MICROSTRIP UP
TO 5.5in
10G FP-TOSA
BIAS
BMAX
BMON
MAX3946
R
2
3-WIRE
INTERFACE
R
1
FAULT
DISABLE
SCL
SDA
CSEL
V
EET
V
CC
4.7kI TO 10kI
SOFTWARE
3-WIRE
INTERFACE
TX_FAULT
DS1878
SFP CONTROLLER
TX_DISABLE
RATE SELECT
MODE_DEF1 (SCL)
MODE_DEF2 (SDA)
ADC
2
I C
R
PD
V
CC
10G LINEAR PIN ROSA
V
(3.3V)
CC
HOST FILTER
= 100I
SUPPLY FILTER
Z
0.1µF
0.1µF
DIFF
FR4 MICROSTRIP UP
TO 12in
R
MON
26 _____________________________________________________________________________________
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Typical Application Circuit for 10GBASE-LR
HOST BOARD
SFP CONNECTOR
SFP+ OPTICAL TRANSCEIVER
V
CC
(3.3V)
HOST FILTER
SUPPLY FILTER
V
CC
V
V
CCT
CCD
0.1µF
0.1µF
Z
= 100I
DIFF
TOUT-
TOUT+
TIN+
TIN-
FR4 MICROSTRIP UP
TO 5.5in
10G DFB-
TOSA
BIAS
BMAX
BMON
MAX3946
11.3G FP/DFB
LDD
R
2
3-WIRE
INTERFACE
R
1
FAULT
DISABLE
SCL
SDA
CSEL
V
EET
V
CC
4.7kI TO 10kI
SOFTWARE
3-WIRE
INTERFACE
TX_FAULT
DS1878
SFP CONTROLLER
RATE SELECT
TX_DISABLE
MODE_DEF1 (SCL)
MODE_DEF2 (SDA)
ADC
2
I C
R
PD
V
CC
V
CC
(3.3V)
CAZ
HOST FILTER
SUPPLY FILTER
V
CCR
V
CC
SCL
SDA
CSEL
3-WIRE
INTERFACE
4.7kI TO 10kI
RPMIN
LOS
LOS
MAX3945
0.1µF
0.1µF
11.3G LAM
R
MON
Z
= 100I
DIFF
0.1µF
0.1µF
RIN+
RIN-
ROUT+
ROUT-
V
EE
FR4 MICROSTRIP UP
TO 12in
10G PIN ROSA
______________________________________________________________________________________ 27
1.0625Gbps to 11.3Gbps, SFP+ Laser Driver
with Laser Impedance Mismatch Tolerance
Chip Information
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PROCESS: SiGe BiPOLAR
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
24 TQFN-EP
T2444+3
21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
28
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
©2020 ICPDF网 联系我们和版权申明