MAX3952 [MAXIM]
10Gbps 16:1 Serializer ; 10Gbps的16 ： 1串行器\n
| 型号： | MAX3952 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10Gbps 16:1 Serializer
|
| 文件： | 总10页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2405; Rev 0; 4/02
10Gbps 16:1 Serializer
General Description
Features
ꢀ Operates at 9.953Gbps and 10.3125Gbps
ꢀ 16-Bit LVDS Interface
The MAX3952 16:1 serializer is optimized for 10.3Gbps
and 9.95Gbps Ethernet applications. A serial clock out-
put is provided for retiming the data at the latch input of
the laser driver. Both the high-speed data and clock are
CML outputs. The serializer operates from a single
+3.3V supply, consuming only 1.15W typical power.
ꢀ Single +3.3V Supply
ꢀ 1.15W Power Dissipation
ꢀ LVDS Source Clock Output
The clock multiplier reference clock frequency can be
either 1/16 or 1/64 the serial output clock rate. A FIFO
aligns the phase between the parallel clock input and
the internally synthesized clock. In addition, a 1/16
counterdirectional clock output (LVDS) is provided for
use as the clock signal of the XAUI codec IC or framer.
ꢀ Built-In 27 - 1 PRBS Pattern Generator
ꢀ Deterministic Jitter: 9ps (max) at 0°C to +85°C
ꢀ Operating Temperature Range: -40°C to +85°C
✕
ꢀ 68-Pin QFN Package (10mm 10mm)
The operating temperature range is from -40°C to
+85°C. The MAX3952 is available in a 10mm ✕ 10mm
68-pin QFN package.
Applications
Ordering Information
10Gbps Ethernet LAN
10Gbps Ethernet WAN
PART
TEMP RANGE
PIN-PACKAGE
MAX3952EGK
-40°C to +85°C
68 QFN
Pin Configuration appears at end of data sheet.
Typical Application Circuit
3.3V
644.53MHz
REFCLK INPUT
0.1µF
5V
100Ω
REFCLK+ REFCLK- CKSET
V
CC
PDIO+
PDIO-
V _VCO
CC
FIL
SDO+
SDO-
PDI15+
PDI15-
MAC
MAX3930
MAX3952
PCLKI+
PCLKI-
SCLKO+
SCLKO-
PCLKO+
PCLKO-
PRBSEN LOCK
TTL
FIFOERR RESET
GND
SCLKEN
THIS SYMBOL REPRESENTS A TRANSMISSION LINE
OF CHARACTERISTIC IMPEDANCE (Z = 50Ω).
0
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10Gbps 16:1 Serializer
ABSOLUTE MAXIMUM RATINGS
Power Supply (V )....................................................-0.5 to +5V
Continuous Power Dissipation (T = +85°C)
CC
A
CML Output Current (SDO , SCLKO )..............................22mA
LVDS Input Voltage Levels
QFN (derate 30.3mW/°C above 70°C).......................2424mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +160°C
(PDI_ , PCLKI ).....................................-0.5V to (V
LVDS Output Voltage (PCLKO )................-0.5V to (V
+ 0.5V)
+ 0.5V)
CC
CC
Voltage Levels at FIL, RESET, CKSET........-0.5V to (V
+ 0.5V)
CC
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V
= +3V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS load = 100Ω, T = +25°C, unless
CC A
CC
A
otherwise noted.)
PARAMETER
Supply Current
LVDS INPUT SPECIFICATIONS (PDI [15…0], PCLKI )
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
(Note 1)
350
500
mA
CC
Input Voltage Range
V
0
2400
mV
mV
µA
mV
Ω
I
Differential Input Voltage
Input Common-Mode Current
Threshold Hysteresis
|V
ID
|
100
Input, V = 1.2V
100
70
OS
Differential Input Impedance
R
85
100
115
1.475
400
25
IN
LVDS OUTPUT SPECIFICATIONS (PCLKO )
Output High Voltage
Output Low Voltage
V
V
V
OH
V
0.925
250
OL
Differential Output Voltage
|V
OD
|
mV
Change in Magnitude
of Differential Outputs
for Complementary Inputs
∆|V
|
|
mV
V
OD
Offset Output Voltage
1.125
80
1.275
25
Change in Magnitude
of Output Offset Voltage
for Complementary States
∆|V
mV
OS
Differential Output Impedance
Output Current
140
12
Ω
Short together
Short to ground
mA
40
2
_______________________________________________________________________________________
10Gbps 16:1 Serializer
DC ELECTRICAL CHARACTERISTICS (continued)
(V
= +3V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS load = 100Ω, T = +25°C, unless
CC A
CC
A
otherwise noted.)
PARAMETER
CML OUTPUT SPECIFICATIONS (SDO , SCLKO )
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Output
R = 50Ω to V
640
85
800
100
1000
115
mV
P-P
L
CC
Differential Output Impedance
Ω
V
0.2
-
CC
Output Common-Mode Voltage
R = 50Ω to V
V
L
CC
LVTTL SPECIFICATIONS (RESET, FIFO_ERROR, LOCK, PRBSEN)
LVTTL Input High Voltage
LVTTL Input Low Voltage
LVTTL Input High Current
LVTTL Input Low Current
LVTTL Output High Voltage
LVTTL Output Low Voltage
V
2.0
V
V
IH
V
0.8
10
10
IL
I
-28
-50
2.4
µA
µA
V
IH
I
IL
V
I
I
= 20µA
= 1mA
V
CC
OH
OH
OL
V
0.4
V
OL
LVPECL INPUT SPECIFICATIONS (REFCLK )
V
1.16
-
V
0.88
-
CC
CC
LVPECL Input High Voltage
LVPECL Input Low Voltage
V
V
V
IH
V
1.81
-
V
1.48
-
CC
CC
V
IL
V
1.3
-
CC
LVPECL Input Bias Voltage
V
LVPECL Single-Ended Impedance
1.4
kΩ
LVPECL Differential Input
Voltage Swing
300
1900
mV
P-P
Note 1: CML outputs AC-coupled to 100Ω differential load, PRBSEN = GND, and SCLKEN = GND.
_______________________________________________________________________________________
3
10Gbps 16:1 Serializer
AC ELECTRICAL CHARACTERISTICS
(V
= +3V to +3.6V, T = -40°C to +85°C. Typical values are at V
= +3.3V, differential LVDS and CML load = 100Ω, T = +25°C,
CC A
CC
A
unless otherwise noted.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tx DATA INPUT SPECIFICATIONS (PDI [15…0], PCLKI )
Parallel Input Setup Time
Parallel Input Hold Time
t
(Figure 1)
(Figure 1)
200
200
ps
ps
SU
t
H
Tx SOURCE CLOCK OUTPUT SPECIFICATIONS (PCLKO )
Parallel Clock Output
Rise/Fall Time
t , t
r
20% to 80%
100
250
55
ps
%
f
Parallel Clock Output Duty Cycle
45
SERIAL DATA OUTPUT SPECIFICATIONS (SDO , SCLKO )
Bit-Error Rate
1 ✕ 10-12
Serial Data Output Rise/Fall Time
Serial Output Clock-to-Data Delay
t , t
20% to 80%
(Note 3)
28
ps
ps
r
f
t
-15
+15
CK-Q
Serial Data or Clock Output
Random Jitter
t
0.9
ps
RMS
RJ
0°C to +85°C (Note 4)
-40°C to +85°C (Note 4)
100kHz to 10GHz
9
Serial Data Output
Deterministic Jitter
t
ps
P-P
DJ
15
17
10
7
Serial Clock or Data Output
Return Loss
RL =
-20log|S
dB
10GHz to 13GHz
|
22
13GHz to 15GHz
Tx REFERENCE CLOCK INPUT SPECIFICATIONS (REFCLK )
Reference Clock Frequency
Tolerance
-100
30
+100
70
ppm
%
Reference Clock Input Duty Cycle
RESET INPUT (RESET)
Minimum Pulse Width of FIFO
UI is PCLKO period
Reset
4
UI
UI
Tolerated Drift Between PCLKI
and PCLKO After Reset
UI is PCLKO period; drift is PCLKO crossing -
PCLKI crossing
-1
+1
Note 2: See Table 1 for valid operating clock frequencies. AC characteristics are guaranteed by design and characterization.
Note 3: Relative to the falling edge of the SCLKO.
Note 4: Deterministic jitter includes pattern-dependent jitter and pulse-width distortion. Measured with a pattern equivalent to 223 - 1
PRBS.
4
_______________________________________________________________________________________
10Gbps 16:1 Serializer
Typical Operating Characteristics
(T = +25°C, V
A
= +3.3V, unless otherwise noted.)
CC
RCLKI TO SCLKO JITTER TRANSFER
SERIAL CLOCK OUTPUT RANDOM JITTER
5
0
-5
-10
-15
-20
-25
10
100
1k
10k
f
= 155.52MHz, RANDOM JITTER = 513fs
RMS
REFCLK
JITTER FREQUENCY (Hz)
SUPPLY CURRENT vs. TEMPERATURE
SERIAL CLOCK AND DATA OUTPUTS
450
430
410
390
370
350
330
310
290
SCLKO
SDO
20ps/div
-40
10
60
110
TEMPERATURE (°C)
_______________________________________________________________________________________
5
10Gbps 16:1 Serializer
Pin Description
PIN
NAME
FUNCTION
1, 4, 5, 13,
17, 18, 26,
34, 35, 51,
52, 68
GND
Ground
2
3
REFCLK+
REFCLK-
Positive Reference Clock Input, LVPECL
Negative Reference Clock Input, LVPECL
6, 9, 12, 25,
43, 60
V
Positive Power Supply
CC
7
8
SCLKO-
SCLKO+
SDO-
Negative Serial Clock Output, CML. 9.95328GHz or 10.3125GHz
Positive Serial Clock Output, CML. 9.95328GHz or 10.3125GHz
10
11
Negative Serial Data Output, CML. 9.95328Gbps or 10.3125Gbps
Positive Serial Data Output, CML. 9.95328Gbps or 10.3125Gbps
SDO+
Control Input for Disabling SCLKO Output:
SCLKEN = GND ⇒ SCLKO Off
14
SCLKEN
SCLKEN = V
⇒ SCLKO Active
CC
15
16
PCLKO+
PCLKO-
Positive Source Clock Output. LVDS, 622MHz or 644MHz. Clocks the MAC.
Negative Source Clock Output. LVDS, 622MHz or 644MHz. Clocks the MAC.
19, 21, 23,
27, 29, 31,
36, 38, 40,
44, 46, 48,
54, 56, 58, 61
PDI15+ to PDI0+
PDI15- to PDI0-
Positive Parallel Data Inputs, LVDS. PDI15+ is MSB
Negative Parallel Data Inputs, LVDS. PDI15- is MSB
20, 22, 24,
28, 30, 32,
37, 39, 41,
45, 47, 49,
55, 57, 59, 62
33
42
50
53
63
64
65
66
67
RESET
PRBSEN
FIFO_ERROR
LOCK
16 x 4-Bit FIFO Reset Input, TTL, Active High
PRBS Pattern Generator Enable Input, TTL, Active High
FIFO Error, TTL, Active High
PLL Lock Indicator, TTL, Active High
PCLKI+
PCLKI-
Positive Parallel Clock Input, LVDS
Negative Parallel Clock Input, LVDS
CKSET
Reference Clock Programming Pin. Programming instructions in Table 1.
Filter Capacitor Input Pin
FIL
V
VCO
Loop Filter and VCO Positive Power Supply
CC_
6
_______________________________________________________________________________________
10Gbps 16:1 Serializer
this condition, assert RESET high for at least 4UI.
FIFO_ERROR can be connected directly to the RESET
input to clear timing errors. After reset, the full elastic
range of the FIFO is available again.
Detailed Description
The MAX3952 converts 16-bit-wide, 622Mbps/644Mbps
data to 9.95Gbps/10.3Gbps serial data (Figures 3 and
4). Data is loaded into the 16:1 mux through a 16 x 4
FIFO buffer for wide tolerance to clock skew. Clock and
data inputs are LVDS levels, and high-speed serial out-
puts are current-mode logic (CML). An internal PLL fre-
quency synthesizer generates a serial clock from a
low-speed reference clock.
Frequency Synthesizer
The PLL synthesizes a 9.95GHz/10.31GHz clock from
an external reference clock. The PLL reference clock
(REFCLK ) can be programmed as 622MHz/644MHz
or 155MHz/161MHz using the CKSET pin. See Table 1
for CKSET settings. The parallel output clock (PCLKO )
is derived from the synthesizer and is SCLKO ÷ 16.
A TTL-compatible loss-of-lock indicator (LOCK),
asserts low when the VCO is unable to lock to the refer-
ence frequency. This pin can be used to directly drive
an LED. If jitter on the REFCLK input is present, an
error with respect to the divided down SCLKO frequen-
cy of 500ppm will be indicated by a low state on LOCK.
Low-Voltage Differential-Signal
Inputs and Outputs
The MAX3952 has LVDS inputs for interfacing with
high-speed digital circuitry. This technology uses
250mV to 400mV differential low-voltage swings to
achieve fast transition times, minimal power dissipation,
and noise immunity. For proper operation, the parallel
clock LVDS outputs (PCLKO ) require 100Ω differential
DC terminations between the positive and negative out-
puts. Do not terminate these outputs to ground. The
parallel data and parallel clock LVDS inputs (PDI_+,
PDI_-, PCLKI+, PCLKI-) are internally terminated with a
100Ω differential input resistance and therefore do not
require external termination.
Table 1. Setting REFCLK Frequency
REFERENCE CLOCK
FREQUENCY (MHz)
CKSET PIN
SETTING
SERIAL CLOCK
FREQUENCY (GHz)
622.08
644.53
155.52
161.13
OPEN
9.95
10.3
9.95
10.3
V
CC
LVPECL Inputs
The reference clock (REFCLK ) has LVPECL inputs for
interfacing to a crystal oscillator using AC- or
DC-coupling. The REFCLK inputs are self-biasing to
- 1.3V for AC-coupled inputs. Only a 100Ω differ-
ential termination resistance must be added when
inputs are AC-coupled.
GND
30kΩ to GND
Internal Pattern Generator
V
CC
The MAX3952 includes a SONET-compliant internal pat-
tern generator capable of a 27 - 1 PRBS pattern.
Connecting the PRBSEN pin to V
generator.
enables the pattern
CC
Current-Mode Logic Outputs
The high-speed data and clock outputs (SDO ,
SCLKO ) of the MAX3952 are designed using CML.
The CML outputs include internal 50Ω back termination
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Use controlled impedance transmission lines to inter-
face with the MAX3952 clock and data inputs and out-
puts. Give special consideration to filtering the
to V . These outputs are intended to drive a 50Ω
CC
transmission line terminated with a matched load
impedance. For detailed instructions on how to inter-
face with LVDS, PECL, and CML, refer to HFAN-01.0:
Introduction to LVDS, PECL, and CML.
V
_VCO pin; all other power supplies can be con-
CC
FIFO Buffer
Data is latched into the MAX3952 by the parallel input
clock (PCLKI ). The parallel input clock is the FIFO
write clock. The parallel output clock (PCLKO ) is the
FIFO read clock that loads the 16:1 mux. The FIFO
allows the read and write clock to vary by up to 1UI
(unit interval). This specification makes the MAX3952
noncompliant with the IEEE802.3ae standard, as this
standard requires a tolerance of 14UI. Conditions that
result in the read and write clock accessing the same
FIFO address are indicated by FIFO_ERROR. To clear
nected through a common filter.
Exposed Pad (EP) Package
The EP 68-pin QFN incorporates features that provide a
very low thermal resistance path for heat removal from
the IC to a PC board. The MAX3952’s exposed paddle
must be soldered directly to a ground plane with good
thermal conductance. Refer to HFAN-08.1: Thermal
Considerations of QFN and Other Exposed-Paddle
Packages.
_______________________________________________________________________________________
7
10Gbps 16:1 Serializer
Chip Information
TRANSISTOR COUNT:8400
PROCESS: SiGe bipolar
100.47ps
1.608ns
622MHz CLOCK
(PCLKI)
9.953GHz CLOCK
(SCLKO)
622Mbps DATA
(PDI)
9.953Gbps DATA
(SDO)
t
SU
t
H
t
CLK-Q
Figure 1. Setup and Hold Time
Figure 2. Definition of Clock to Q
RESET FIFO-ERROR
PCLKI+
WRITE
LVDS
CLK
PCLKI-
PDI+[15...0]
PDI-[15...0]
SDO+
SDO-
16 16 x 4-BIT
FIFO
16
16:1
MUX
16-BIT
REG
CML
16
LVDS
0
1
16
DATA
16
READ
PRBS
GENERATOR
PRBSEN
SIS
MAX3952
PCLKO+
SCLKO+
SCLKO-
LVDS
CML
PCLKO-
REFCLK+
LVPECL
FREQUENCY
GENERATOR
REFCLK-
CKSET
LOCK
SCLKEN
FIL
VCC_VCO
Figure 3. Functional Diagram
_______________________________________________________________________________________
8
10Gbps 16:1 Serializer
PCLKO
PCLKI
t
t
H
SU
PARALLEL
INPUT DATA
(PDI_)
VALID PARALLEL DATA*
SERIAL
OUTPUT DATA
(SDO)
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, PCLKO = (PCLKO+) - (PCLKO-).
*PDI15 = D15; PDI14 = D14 ... PDIO = DO.
THIS FIGURE IS NOT INTENDED TO SHOW A SPECIFIC TIMING RELATIONSHIP BETWEEN PARALLEL
INPUT DATA AND SERIAL OUTPUT DATA.
Figure 4. Parallel and Serial Data Timing
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
GND
REFCLK+
REFCLK-
GND
1
2
3
4
5
6
7
8
9
51 GND
50 FIFO_ERROR
49 PDI4-
48 PDI4+
47 PDI5-
GND
46 PDI5+
45 PDI6-
V
CC
SCLKO-
SCLKO+
44 PDI6+
MAX3951
V
CC
43
42
V
CC
SDO- 10
SDO+ 11
VCC 12
PRBSEN
41 PDI7-
40 PDI7+
GND 13
39
38 PDI8+
PDI8-
SCLKEN 14
PCLKO+ 15
37
36
PDI9-
PDI9+
16
PCLKO-
GND 17
35 GND
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
QFN*
*EXPOSED PAD IS CONNECTED TO GND.
_______________________________________________________________________________________
9
10Gbps 16:1 Serializer
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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