MAX395EWG-T [MAXIM]
SPST, 8 Func, 1 Channel, CMOS, PDSO24, 0.300 INCH, MS-013AD, SOIC-24;
| 型号： | MAX395EWG-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | SPST, 8 Func, 1 Channel, CMOS, PDSO24, 0.300 INCH, MS-013AD, SOIC-24 光电二极管 |
| 文件： | 总24页 (文件大小：426K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0448; Rev 0; 11/95
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX395 8-channel, serially controlled, single-pole/sin-
gle-throw (SPST) analog switch offers eight separately
controlled switches. The switches conduct equally well in
either direction. On-resistance (100Ω max) is matched
between switches to 5Ω max and is flat (10Ω max) over
the specified signal range.
♦ SPI™/QSPI™, Microwire™-Compatible Serial
Interface
♦ 8 Separately Controlled SPST Switches
♦ 100Ω Signal Paths with ±5V Supplies
♦ Rail-to-Rail Signal Handling
These CMOS devices can operate continuously with
dual power supplies ranging from ±2.7V to ±8V or a
single supply between +2.7V and +16V. Each switch
can handle rail-to-rail analog signals. The off leakage
current is only 0.1nA at +25°C or 5nA at +85°C.
♦ Asynchronous RESET Input
♦ Pin Compatible with Industry-Standard MAX335
♦ ±2.7V to ±8V Dual Supplies
+2.7V to +16V Single Supply
Upon power-up, all switches are off, and the internal shift
registers are reset to zero. The MAX395 is electrically
equivalent to two MAX391 quad switches controlled by a
serial interface, and is pin compatible with the MAX335.
♦ >2kV ESD Protection per Method 3015.7
♦ TTL/CMOS-Compatible Inputs (with +5V or
±5V Supplies)
The serial interface is compatible with SPI™/QSPI™ and
Microwire™. Functioning as a shift register, it allows data
(at DIN) to be clocked in synchronously with the rising
edge of clock (SCLK). The shift register’s output (DOUT)
enables several MAX395s to be daisy chained.
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
24 Narrow Plastic DIP
24 Wide SO
MAX395CNG
MAX395CWG
MAX395C/D
MAX395ENG
MAX395EWG
MAX395MRG
All digital inputs have 0.8V to 2.4V logic thresholds, ensur-
ing both TTL- and CMOS-logic compatibility when using
±5V supplies or a single +5V supply.
0°C to +70°C
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
24 Narrow Plastic DIP
24 Wide SO
________________________Ap p lic a t io n s
Serial Data-Acquisition
Systems
Industrial and Process-
Control Systems
24 Narrow CERDIP**
*
Contact factory for dice specifications.
Avionics
ATE Equipment
Networking
** Contact factory for availability.
Audio Signal Routing
________________Fu n c t io n a l Dia g ra m
__________________P in Co n fig u ra t io n
NO0
NO7
TOP VIEW
SCLK
V+
1
2
3
4
5
6
7
8
9
24 CS
MAX395
23 RESET
22 DOUT
21 V-
COM0
COM7
DIN
LOGIC
GND
NO0
PARALLEL REGISTER AND TRANSLATOR
8-BIT SHIFT REGISTER
20 NO7
19 COM7
18 NO6
17 COM6
16 NO5
15 COM5
14 NO4
13 COM4
COM0
NO1
DOUT
DIN
COM1
NO2
RESET
MAX395
COM2 10
NO3 11
SCLK
CS
CLOCK TRANSLATOR
LATCH
COM3 12
CS TRANSLATOR
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
Continuous Power Dissipation (T = +70°C)
A
V+ ...........................................................................-0.3V, +17V
V- ............................................................................-17V, +0.3V
V+ to V-...................................................................-0.3V, +17V
SCLK, CS, DIN, DOUT, RESET .................-0.3V to (V+ + 0.3V)
NO, COM.................................................(V- - 2V) to (V+ + 2V)
Continuous Current into Any Terminal..............................±30mA
Peak Current, NO_ or COM_
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)...1067mW
Wide SO (derate 11.76mW/°C above +70°C)...............941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C)....1000mW
Operating Temperature Ranges
MAX395C_ G .......................................................0°C to +70°C
MAX395E_ G ....................................................-40°C to +85°C
MAX395MRG ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
MAX395
(pulsed at 1ms,10% duty cycle)..................................±100mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Dual Supplies
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 1)
MAX
PARAMETER
ANALOG SWITCH
SYMBOL
CONDITIONS
UNITS
Analog Signal Range
V
, V
C, E, M
= +25°C
V-
V+
100
125
5
V
COM NO
T
A
60
V+ = 5V, V- = -5V,
= ±3V, I
COM, NO On-Resistance
R
Ω
ON
V
COM
= 1mA
= 1mA
NO
C, E, M
= +25°C
T
A
COM, NO On-Resistance Match
Between Channels (Note 2)
V+ = 5V, V- = -5V,
= ±3V, I
∆R
Ω
Ω
ON
V
COM
NO
C, E, M
= +25°C
10
T
10
A
COM, NO On-Resistance
Flatness (Note 2)
V+ = 5V, V- = -5V, I = 1mA,
NO
R
FLAT(ON)
V
COM
= -3V, 0V, 3V
C, E, M
= +25°C
15
T
-0.1
-10
-0.1
-10
-0.1
-10
0.1
0.002
0.002
0.002
0.002
0.01
0.1
10
A
V+ = 5.5V, V- = -5.5V,
= -4.5V, V = 4.5V
V
COM
NO
C, E, M
= +25°C
NO Off Leakage Current
(Note 3)
I
nA
NO(OFF)
T
0.1
10
A
V+ = 5.5V, V- = -5.5V,
= 4.5V, V = -4.5V
V
COM
NO
C, E, M
= +25°C
T
0.1
10
A
V+ = 5.5V, V- = -5.5V,
= -4.5V, V = 4.5V
V
COM
NO
C, E, M
= +25°C
COM Off Leakage Current
(Note 3)
I
nA
nA
COM(OFF)
T
0.1
10
A
V+ = 5.5V, V- = -5.5V,
= 4.5V, V = -4.5V
V
COM
NO
C, E, M
= +25°C
-10
-0.2
-20
T
0.2
20
A
COM On Leakage Current
(Note 3)
V+ = 5.5V, V- = -5.5V,
= V = ±4.5V
I
COM(ON)
V
COM
NO
C, E, M
DIGITAL I/O
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold High
V
C, E, M
C, E, M
C, E, M
2.4
V
V
IH
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold Low
V
IL
0.8
1
DIN, SCLK, CS, RESET Input
Current Logic High or Low
V
, V
,
DIN SCLK
I
I
-1
0.03
100
µA
IH, IL
V
CS
= 0.8V or 2.4V
DOUT Output Voltage Logic High
DOUT Output Voltage Logic Low
SCLK Input Hysteresis
V
I
= 0.8mA
= -1.6mA
DOUT
C, E, M
C, E, M
C, E, M
2.8
0
V+
V
V
DOUT
DOUT
V
I
0.4
DOUT
SCLK
mV
HYST
2
_______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 1)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
SWITCH DYNAMIC CHARACTERISTICS
T
= +25°C
200
90
400
500
400
500
A
Turn-On Time
Turn-Off Time
t
From rising edge of CS
ns
ns
ON
C, E, M
= +25°C
T
A
t
From rising edge of CS
From rising edge of CS
OFF
C, E, M
Break-Before-Make Delay
Charge Injection (Note 4)
NO Off Capacitance
t
T
A
= +25°C
= +25°C
= +25°C
= +25°C
5
15
2
ns
pC
pF
pF
BBM
V
CTE
C
= 1nF, V = 0V, R = 0Ω
T
A
10
L
NO
S
C
V
NO
= GND, f = 1MHz
T
A
2
NO(OFF)
COM Off Capacitance
C
V
COM
= GND, f = 1MHz
T
A
2
COM(OFF)
V
= V = GND,
NO
COM
Switch On Capacitance
Off Isolation
C
T
= +25°C
= +25°C
= +25°C
8
pF
dB
dB
(ON)
A
f = 1MHz
R
= 50Ω, C = 15pF,
L
L
V
T
A
-90
ISO
V
NO
= 1V
, f = 100kHz
RMS
R
= 50Ω, C = 15pF,
L
L
Channel-to-Channel Crosstalk
V
T
A
<-90
CT
V
NO
= 1V
, f = 100kHz
RMS
POWER SUPPLY
Power-Supply Range
V+, V-
I+
C, E, M
= +25°C
±3
±8
20
30
1
V
T
A
7
DIN = CS = SCLK = 0V or V+,
RESET = 0V or V+
V+ Supply Current
V- Supply Current
µA
C, E, M
= +25°C
T
-1
-2
0.1
DIN = CS = SCLK = 0V or V+,
RESET = 0V or V+
A
I-
µA
C, E, M
2
_______________________________________________________________________________________
3
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
TIMING CHARACTERISTICS—Dual Supplies (Figure 1)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 1)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
SERIAL DIGITAL INTERFACE
SCLK Frequency
Cycle Time
f
C, E, M
C, E, M
C, E, M
0
2.1
MHz
ns
SCLK
t
+ t
CL
480
240
CH
MAX395
CS Lead Time
t
ns
CSS
CS Lag Time
t
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
240
190
190
200
0
ns
ns
ns
ns
ns
CSH2
SCLK High Time
SCLK Low Time
Data Setup Time
Data Hold Time
t
CH
t
CL
DS
DH
t
17
-17
85
t
T
A
= +25°C
DIN Data Valid after Falling SCLK
(Note 4)
50% of SCLK to 10% of DOUT,
= 10pF
t
ns
ns
µs
ns
DO
C
C, E, M
400
100
L
20% of V+ to 70% of V+,
= 10pF
Rise Time of DOUT (Note 4)
t
DR
C, E, M
C
L
Allowable Rise Time at DIN, SCLK
(Note 4)
20% of V+ to 70% of V+,
= 10pF
t
C, E, M
C, E, M
C, E, M
2
100
2
SCR
C
L
20% of V+ to 70% of V+,
= 10pF
Fall Time of DOUT (Note 4)
t
DF
C
L
Allowable Fall Time at DIN, SCLK
(Note 4)
20% of V+ to 70% of V+,
= 10pF
t
µs
ns
SCF
C
L
RESET Minimum Pulse Width
t
T
A
= +25°C
70
RW
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R = R - R . On-resistance match between channels and on-resistance flatness are guaranteed only with
ON
ON(max)
ON(min)
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
V
/V , V
= output. NO = input to off switch.
10 COM NO COM
Note 7: Between any two switches. See Figure 3.
4
_______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.5V to +5.5V, V- = 0V, T = T
A
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
ANALOG SWITCH
Analog Signal Range
V
, V
C, E, M
= +25°C
V-
V+
175
225
0.1
10
V
COM NO
T
A
125
V+ = 5V, V
= 3.5V,
COM
COM, NO On-Resistance
R
Ω
ON
I
NO
= 1mA
C, E, M
= +25°C
T
-0.1
-10
0.002
0.002
0.002
0.002
0.002
A
V+ = 5.5V, V
= 4.5V,
COM
V
NO
= 0V
C, E, M
= +25°C
NO Off Leakage Current
(Notes 4, 5)
I
nA
NO(OFF)
T
-0.1
-10
0.1
10
A
V+ = 5.5V, V
= 0V,
COM
V
NO
= 4.5V
C, E, M
= +25°C
T
-0.1
-10
0.1
10
A
V+ = 5.5V, V
= 4.5V,
= 0V,
COM
V
NO
= 0V
C, E, M
= +25°C
COM Off Leakage Current
(Notes 4, 5)
I
nA
nA
COM(OFF)
T
-0.1
-10
0.1
10
A
V+ = 5.5V, V
COM
V
NO
= 4.5V
C, E, M
= +25°C
T
-0.2
-20
0.2
20
A
COM On Leakage Current
(Notes 4, 5)
V+ = 5.5V,
= V = 4.5V
I
COM(ON)
V
COM
NO
C, E, M
DIGITAL I/O
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold High
V
C, E, M
C, E, M
C, E, M
2.4
V
V
IH
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold Low
V
IL
0.8
1
DIN, SCLK, CS, RESET Input
Current Logic High or Low
V
, V
,
DIN SCLK
I
, I
IH IL
-1
0.03
µA
V
CS
= 0.8V or 2.4V
DOUT Output Voltage Logic High
DOUT Output Voltage Logic Low
SCLK Input Hysteresis
V
I
= -0.8mA
= 1.6mA
DOUT
C, E, M
C, E, M
C, E, M
2.8
0
V+
V
V
DOUT
DOUT
V
DOUT
I
0.4
SCLK
100
200
90
mV
HYST
SWITCH DYNAMIC CHARACTERISTICS
T
A
= +25°C
400
500
400
500
Turn-On Time
Turn-Off Time
t
From rising edge of CS
ns
ns
ON
C, E, M
= +25°C
T
A
t
From rising edge of CS
From rising edge of CS
OFF
C, E, M
Break-Before-Make Delay
Charge Injection (Note 4)
t
T
= +25°C
T = +25°C
A
15
2
ns
BBM
A
V
C
= 1nF, V = 0V, R = 0Ω
10
pC
CTE
L
NO
S
R
V
NO
= 50Ω, C = 15pF,
L
L
Off Isolation (Note 6)
V
T
= +25°C
= +25°C
-90
dB
dB
ISO
A
= 1V
, f = 100kHz
RMS
Channel-to-Channel Crosstalk
(Note 7)
R = 50Ω, C = 15pF,
L L
V
NO
V
T
A
<-90
CT
= 1V
, f = 100kHz
RMS
POWER SUPPLY
T
= +25°C
7
20
30
A
DIN = CS = SCLK = 0V or
V+, RESET = 0V or V+
V+, V- Supply Current
I+
µA
C, E, M
_______________________________________________________________________________________
5
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
TIMING CHARACTERISTICS—Single +5V Supply (Figure 1)
(V+ = +4.5V to +5.5V, V- = 0V, T = T
A
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
SERIAL DIGITAL INTERFACE
SCLK Frequency
f
C, E, M
C, E, M
C, E, M
0
2.1
MHz
ns
SCLK
Cycle Time (Note 4)
t
+ t
CL
480
240
CH
MAX395
CS Lead Time (Note 4)
t
ns
CSS
CS Lag Time (Note 4)
t
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
240
190
190
200
0
ns
ns
ns
ns
ns
CSH2
SCLK High Time (Note 4)
SCLK Low Time (Note 4)
Data Setup Time (Note 4)
Data Hold Time (Note 4)
t
CH
t
CL
DS
DH
t
17
-17
85
t
T = +25°C
A
DIN Data Valid after Falling SCLK
(Note 4)
50% of SCLK to 10% of
DOUT, C = 10pF
L
t
ns
ns
µs
ns
DO
C, E, M
400
100
20% of V+ to 70% of V+,
Rise Time of DOUT (Note 4)
t
DR
C, E, M
C
= 10pF
L
Allowable Rise Time at DIN,
SCLK (Note 4)
20% of V+ to 70% of V+,
= 10pF
t
C, E, M
C, E, M
C, E, M
2
100
2
SCR
C
L
20% of V+ to 70% of V+,
= 10pF
Fall Time of DOUT (Note 4)
t
DF
C
L
Allowable Fall Time at DIN,
SCLK (Note 4)
20% of V+ to 70% of V+,
= 10pF
t
µs
ns
SCF
C
L
RESET Minimum Pulse Width
t
T
A
= +25°C
70
RW
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R = R - R . On-resistance match between channels and on-resistance flatness are guaranteed only with
ON
ON(max)
ON(min)
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
V
/V , V
= output. NO = input to off switch.
10 COM NO COM
Note 7: Between any two switches. See Figure 3.
6
_______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +3.0V to +3.6V, V- = 0V, T = T
A
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
ANALOG SWITCH
Analog Signal Range
V
, V
C, E, M
= +25°C
V-
V+
500
600
0.1
5
V
COM NO
T
A
270
V+ = 3.0V, V
= 1.5V,
= 3V,
= 0V,
= 3V,
= 0V,
= 3V,
= 0V,
COM
COM, NO On-Resistance
R
Ω
ON
I
NO
= 1mA
C, E, M
= +25°C
T
-0.1
-5
0.002
0.002
0.002
0.002
0.002
0.002
A
V+ = 3.0V, V
COM
V
NO
= 0V
C, E, M
= +25°C
NO Off Leakage Current
(Notes 4, 5)
I
nA
nA
nA
NO(OFF)
T
-0.1
-5
0.1
5
A
V+ = 3.6V, V
COM
V
NO
= 3V
C, E, M
= +25°C
T
-0.1
-5
0.1
5
A
V+ = 3.6V, V
COM
V
NO
= 0V
C, E, M
= +25°C
COM Off Leakage Current
(Notes 4, 5)
I
COM(OFF)
T
0.1
-5
0.1
5
A
V+ = 3.6V, V
COM
V
NO
= 3V
C, E, M
= +25°C
T
-0.1
-10
-0.1
-10
0.1
10
0.1
10
A
V+ = 3.6V, V
COM
V
NO
= 0V
C, E, M
= +25°C
COM On Leakage Current
(Notes 4, 5)
I
COM(ON)
T
A
V+ = 3.6V, V
COM
V
NO
= 3V
C, E, M
DIGITAL I/O
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold High
V
C, E
C, E
C, E
2.4
V
V
IH
DIN, SCLK, CS, RESET Input
Voltage Logic Threshold Low
V
IL
0.8
1
DIN, SCLK, CS, Input
Current Logic High or Low
V
, V
,
DIN SCLK
I
I
-1
0.03
µA
IH, IL
V
CS
= 0.8V or 2.4V
DOUT Output Voltage Logic High
DOUT Output Voltage Logic Low
SCLK Input Hysteresis
V
I
= 0.1mA
= -1.6mA
DOUT
C, E, M
C, E, M
C, E, M
2.8
0
V+
V
V
DOUT
DOUT
V
DOUT
I
0.4
SCLK
100
260
90
mV
HYST
SWITCH DYNAMIC CHARACTERISTICS
T
A
= +25°C
600
800
300
400
Turn-On Time
Turn-Off Time
t
From rising edge of CS
ns
ns
ON
C, E, M
= +25°C
T
A
t
From rising edge of CS
From rising edge of CS
OFF
C, E, M
Break-Before-Make Delay
Charge Injection (Note 4)
t
T
= +25°C
T = +25°C
A
15
2
ns
BBM
A
V
C
= 1nF, V = 0V, R = 0Ω
10
pC
CTE
L
NO
S
R
V
NO
= 50Ω, C = 15pF,
L
L
Off Isolation (Note 6)
V
T
= +25°C
= +25°C
-90
dB
dB
ISO
A
= 1V
, f = 100kHz
RMS
Channel-to-Channel Crosstalk
(Note 7)
R = 50Ω, C = 15pF,
L L
V
NO
V
T
A
<-90
CT
= 1V
, f = 100kHz
RMS
POWER SUPPLY
T
= +25°C
6
20
30
A
DIN = CS = SCLK = 0V or V+,
RESET = 0V or 5V
V+ Supply Current
I+
µA
C, E, M
_______________________________________________________________________________________
7
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
TIMING CHARACTERISTICS—Single +3V Supply (Figure 1)
(V+ = +3.0V to +3.6V, V- = 0V, T = T
A
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
SERIAL DIGITAL INTERFACE
SCLK Frequency
f
C, E, M
C, E, M
C, E, M
0
2.1
MHz
ns
SCLK
Cycle Time (Note 4)
t
+ t
CL
480
240
CH
MAX395
CS Lead Time (Note 4)
t
ns
CSS
CS Lag Time (Note 4)
t
C, E, M
C, E, M
C, E, M
C, E, M
C, E, M
240
190
190
200
0
ns
ns
ns
ns
ns
CSH2
SCLK High Time (Note 4)
SCLK Low Time (Note 4)
Data Setup Time (Note 4)
Data Hold Time (Note 4)
t
CH
t
CL
DS
DH
t
38
-38
150
t
T = +25°C
A
DIN Data Valid after Falling SCLK
(Note 4)
50% of SCLK to 10% of
DOUT, C = 10pF
L
t
ns
ns
µs
ns
DO
C, E, M
400
300
20% of V+ to 70% of V+,
Rise Time of DOUT (Note 4)
t
DR
C, E, M
C
= 10pF
L
Allowable Rise Time at DIN,
SCLK (Note 4)
20% of V+ to 70% of V+,
= 10pF
t
C, E, M
C, E, M
C, E, M
2
300
2
SCR
C
L
20% of V+ to 70% of V+,
= 10pF
Fall Time of DOUT (Note 4)
t
DF
C
L
Allowable Fall Time at DIN,
SCLK (Note 4)
20% of V+ to 70% of V+,
= 10pF
t
µs
ns
SCF
C
L
RESET Minimum Pulse Width
t
T
A
= +25°C
105
RW
Note 1: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 2: ∆R = R - R . On-resistance match between channels and on-resistance flatness are guaranteed only with
ON
ON(max)
ON(min)
specified voltages. Flatness is defined as the difference between the maximum and minimum value of on-resistance as
measured over the specified analog signal range.
Note 3: Leakage parameters are 100% tested at maximum rated hot temperature and guaranteed by correlation at room temp.
Note 4: Guaranteed by design.
Note 5: Leakage testing at single supply is guaranteed by testing with dual supplies.
Note 6: See Figure 6. Off isolation = 20log
V
/V , V
= output. NO = input to off switch.
10 COM NO COM
Note 7: Between any two switches. See Figure 3.
8
_______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V+ = +5V, V- = -5V, GND = 0V, T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
COM
ON-RESISTANCE vs. V
COM
ON-RESISTANCE vs. V
COM
AND TEMPERATURE
(DUAL SUPPLIES)
(DUAL SUPPLIES)
(SINGLE SUPPLY)
140
120
100
110
100
90
400
350
300
250
V+ = 2.5V
V- = 0V
V± = ±5.5V
V± = ±2.5V
V± = ±3V
T
= +125°C
= +85°C
A
80
80
60
40
T
A
200
70
V+ = 3V
V+ = 5V
60
150
100
V± = ±5V
T
A
= +25°C
= -55°C
50
V+ = 9V
V+ = 12V
8 10 12
T
A
20
0
50
0
40
30
-5 -4 -3 -2 -1
0
1
2
3
4
5
0
2
4
6
-5 -4 -3 -2 -1
0
1
2
3
4
5
V
COM
(V)
V
COM
(V)
V
COM
(V)
ON-RESISTANCE vs. V
COM
AND TEMPERATURE
(SINGLE SUPPLY)
OFF-LEAKAGE vs.
TEMPERATURE
ON-LEAKAGE vs.
TEMPERATURE
1000
100
180
160
10,000
1000
100
V+ = 5V
V- = 0V
V± = ±5.5V
V± = ±5.5V
T
= +125°C
A
140
120
100
80
T
= +85°C
A
10
1
T
A
= +25°C
10
1
T
= -55°C
A
60
40
0.1
0.1
-50 -25
0
25 50
75 100 125
0
1
2
3
(V)
4
5
-50 -25
0
25 50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
V
COM
DATA HOLD TIME vs.
POWER-SUPPLY VOLTAGE
CHARGE INJECTION vs. V
TURN-ON/OFF TIMES vs. V
COM
COM
50
40
30
20
5
4
3
250
200
150
100
A: V+ = 5V, V- = 5V
B: V+ = 5V, V- = 0V
2
1
10
0
0
B = t
ON
A = t
ON
-10
-1
-20
-30
-40
-50
-2
-3
-4
-5
B = t
OFF
A = t
OFF
50
0
0
2
4
6
8
-5 -4 -3 -2 -1
0
1
2
3
4
5
-5 -4 -3 -2 -1
0
1
2
3
4
5
SUPPLY VOLTAGE (V)
V
COM
(V)
V
COM
(V)
_______________________________________________________________________________________
9
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V+ = +5V, V- = -5V, GND = 0V, T = +25°C, unless otherwise noted.)
A
DATA SETUP TIME vs.
POSITIVE SUPPLY VOLTAGE
POWER-SUPPLY CURRENT
vs. TEMPERATURE
MINIMUM SCLK PULSE WIDTH vs.
POSITIVE SUPPLY VOLTAGE
100
90
35
30
25
20
100
10
V± = ±5.5V
80
I+
MAX395
70
60
50
40
1
0.1
0.01
30
20
10
0
I-
15
10
0.001
0
2
4
6
8
-50 -25
0
25 50
75 100 125
0
2
4
6
8
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
FREQUENCY RESPONSE
20
0
100
10
INSERTION LOSS
V± = ±5V
600Ω IN AND OUT
0
-20
-20
-40
PHASE
-40
-60
1
ISOLATION OF
A BARE SOCKET
-60
OFF ISOLATION
-80
0.1
0.01
-80
-100
V± = ±5V
50Ω IN AND OUT
-120
-100
10k
100k
1M
10M 100M
1G
10
100
1k
10k
FREQUENCY (Hz)
FREQUENCY (Hz)
______________________________________________________________P in De s c rip t io n
PIN
1
NAME
SCLK
V+
FUNCTION
Serial Clock Digital Input
2
Positive Analog Supply Voltage Input
Serial Data Digital Input
3
DIN
Ground. Connect to digital ground. (Analog signals have no ground reference;
they are limited to V+ and V-.)
4
GND
5, 7, 9, 11, 14, 16, 18, 20
NO0–NO7
COM0–COM7
V-
Normally Open Analog Switches 0–7
6, 8, 10, 12, 13, 15, 17, 19
Common Analog Switches 0–7
21
22
Negative Analog Supply Voltage Input. Connect to GND for single-supply operation
Serial Data Digital Output. (High is sourced from V+.)
DOUT
Reset Input. Connect to digital (logic) supply (or V+). Drive low to set all switch-
es off and set internal shift registers to 0.
23
24
RESET
CS
Chip-Select Digital Input (Figure 1)
Note: NO_ and COM_ pins are identical and interchangeable. Either may be considered as an input or an output; signals pass
equally well in either direction.
10 ______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
register will contain only the last eight serial data bits,
_______________De t a ile d De s c rip t io n
regardless of when they were entered. On the rising
edge of CS, all the switches will be set to the corre-
sponding states.
Ba s ic Op e ra t io n
The MAX395’s interface can be thought of as an 8-bit
shift register controlled by CS (Figure 2). While CS is
low, input data appearing at DIN is clocked into the
shift register synchronously with SCLK’s rising edge.
The data is an 8-bit word, each bit controlling one of
eight switches in the MAX395 (Table 1). DOUT is the
shift register’s output, with data appearing synchro-
nously with SCLK’s falling edge. Data at DOUT is sim-
ply the input data delayed by eight clock cycles.
The MAX395’s three-wire serial interface is compatible
with SPI™, QSPI™, and Microwire™ standards. If inter-
facing with a Motorola processor serial interface, set
CPOL = 0. The MAX395 is considered a slave device
(Figures 2 and 3). Upon power-up, the shift register
contains all zeros, and all switches are off.
The latch that drives the analog switch is updated on
the rising edge of CS, regardless of SCLK’s state. This
meets all the SPI and QSPI requirements.
When shifting the input data, D7 is the first bit in and
out of the shift register. While shifting data, the switches
remain in their previous configuration. When the eight
bits of data have been shifted in, CS is driven high. This
updates the new switch configuration and inhibits fur-
ther data from entering the shift register. Transitions at
DIN and SCLK have no effect when CS is high, and
DOUT holds the first input bit (D7) at its output.
Da is y Ch a in in g
For a simple interface using several MAX395s, “daisy
chain” the shift registers as shown in Figure 5. The CS
p ins of a ll d e vic e s a re c onne c te d tog e the r, a nd a
stream of data is shifted through the MAX395s in series.
When CS is brought high, all switches are updated
simultaneously. Additional shift registers may be includ-
ed anywhere in series with the MAX395 data chain.
More or less than eight clock cycles can be entered
during the CS low period. When this happens, the shift
t
CLL
t
CSH2
CS
• • •
t
t
CH
CSS
t
OFF
t
CSH0
• • •
SCLK
DIN
t
CL
t
DS
t
CSH1
t
DH
• • •
t
DO
• • •
DOUT
COM OUT
• • •
Figure 1. Timing Diagram
______________________________________________________________________________________ 11
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
Ad d re s s a b le S e ria l In t e rfa c e
When several serial devices are configured as slaves,
a d d re s s a b le b y the p roc e s s or, DIN p ins of e a c h
d e c ode log ic ind ivid ua lly c ontrol CS of e a c h sla ve
device. When a slave is selected, its CS pin is driven
low, data is shifted in, and CS is driven high to latch the
data. Typically, only one slave is addressed at a time.
DOUT is not used.
CS
SCLK
DIN
SWITCHES
UPDATED
MAX395
__________Ap p lic a t io n s In fo rm a t io n
Mu lt ip le x e rs
The MAX395 c a n b e us e d a s a multip le xe r, b ut to
obtain the same electrical performance with slightly
improved programming speed, use the MAX349 8-
channel mux or the MAX350 dual 4-channel mux, both
in 18-pin packages.
D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS
DOUT
D0 D7 D6 D5 D4 D3 D2 D1 D0
DATA BITS FROM PREVIOUS DATA INPUT
Figure 2. Three-Wire Interface Timing
Table 1. Serial-Interface Switch Programming
DATA BITS
RESET
FUNCTION
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
X
X
X
0
X
X
X
X
X
0
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
All switches open, D7–D0 = 0
Switch 7 open (off)
Switch 7 closed (on)
Switch 6 open (off)
Switch 6 closed (on)
Switch 5 open (off)
Switch 5 closed (on)
Switch 4 open (off)
Switch 4 closed (on)
Switch 3 open (off)
Switch 3 closed (on)
Switch 2 open (off)
Switch 2 closed (on)
Switch 1 open (off)
Switch 1 closed (on)
Switch 0 open (off)
Switch 0 closed (on)
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
X
X
1
X
X
X
X
X
X
1
X
X
X
X
1
X
X
1
12 ______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
8 x 1 Mu lt ip le x e r
To use the MAX395 as an 8x1 multiplexer, connect all
common pins together (COM0–COM7) to form the mux
output; the mux inputs are NO0–NO7.
Du a l, Diffe re n t ia l 4 -Ch a n n e l Mu lt ip le x e r
To us e the MAX395 a s a d ua l (4x2) mux, c onne c t
COM0–COM3 tog e the r a nd c onne c t COM4–COM7
together, forming the two outputs. The mux input pairs
become NO0/NO4, NO1/NO5, NO2/NO6, and NO3/NO7.
The mux can be programmed normally, with only one
channel selected for every eight clock pulses, or it can
be programmed in a fast mode, where channel chang-
ing occurs on each clock pulse. In this mode, the chan-
ne ls a re s e le c te d b y s e nd ing a s ing le hig h p uls e
(corresponding to the selected channel) at DIN, and a
corresponding CS low pulse for every eight clock puls-
es. As this is clocked through the register by SCLK,
each switch sequences one channel at a time, starting
with Channel 7.
The mux can be programmed normally, with only one
differential channel selected for every eight clock puls-
es, or it can be programmed in a fast mode, where
channel changing occurs on each clock pulse.
In fast mode, the channels are selected by sending two
high pulses spaced four clock pulses apart (corre-
sponding to the two selected channels) at DIN, and a
corresponding CS low pulse for each of the first eight
clock pulses. As this is clocked through the register by
SCLK
DIN
SK
SO
DOUT
DIN
MISO
MOSI
MAX395
MAX395
SPI
PORT
MICROWIRE
PORT
DOUT
CS
SI
SCLK
CS
SCK
I/O
I/O
CPOL = 0, CPHA = 0
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX395, BUT MAY BE USED FOR DATA-ECHO PURPOSES.
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
MAX395, BUT MAY BE USED FOR DATA-ECHO PURPOSES.
Figure 3. Connections for Microwire
Figure 4. Connections for SPI and QSPI
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
SCLK
DIN
CS
MAX395
MAX395
MAX395
DOUT
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 5. Daisy-Chained Connection
______________________________________________________________________________________ 13
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
DIN
SCLK
CS1
CS2
CS3
MAX395
TO OTHER
SERIAL
DEVICES
CS
CS
CS
MAX395
MAX395
MAX395
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 6. Addressable Serial Interface
Re s e t Fu n c t io n
RESET is the internal reset pin. It is usually connected
to a logic signal or V+. Drive RESET low to open all
switches and set the contents of the internal shift regis-
ter to zero simultaneously. When RESET is high, the
part functions normally and DOUT is sourced from V+.
RESET must not be driven beyond V+ or GND.
D4
D0
SCLK
SW4
SW0
DIN
P o w e r-S u p p ly Co n s id e ra t io n s
FOUR CLOCK
Overview
The MAX395 construction is typical of most CMOS ana-
log switches. It has three supply pins: V+, V-, and
GND. V+ and V- are used to drive the internal CMOS
switches and to set the limits of the analog voltage on
any switch. Reverse ESD-protection diodes are inter-
nally connected between each analog signal pin and
both V+ and V-. If any analog signal exceeds V+ or V-,
one of these diodes will conduct. During normal opera-
tion, these (and other) reverse-biased ESD diodes leak,
forming the only current drawn from V+ or V-.
PULSES
Figure 7. Differential Multiplexer Input Control
SCLK, each switch sequences one differential channel
at a time, starting with channel 7/0. After the first eight
bits have been sent, subsequent channel sequencing
can occur by repeating this sequence or, even faster,
by sending only one DIN high pulse and one CS low
pulse for each four clock pulses.
Virtually all the analog leakage current is through the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages vary as the signal varies. The difference in the
two diode leakages to the V+ and V- pins constitutes
the analog signal-path leakage current. All analog leak-
S P DT S w it c h e s
To use the MAX395 as a quad, single-pole/double-
throw (SPDT) switch, connect COM0 to NO1, COM2 to
NO3, COM4 to NO5, and COM6 to NO7, forming the
four “common” pins. Program these four switches with
pairs of instructions, as shown in Table 2.
14 ______________________________________________________________________________________
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
MAX395
Table 2. SPDT Switch Programming
DATA BITS
D4 D3
RESET
FUNCTION
D7
D6
D5
D2
D1
D0
0
1
1
1
1
1
1
1
1
X
0
X
1
X
X
X
0
X
X
X
1
X
X
X
X
X
0
X
X
X
X
X
1
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
1
All switches open, D7–D0 = 0
Switch 7 off and 6 on
Switch 6 off and 7 on
Switch 5 off and 4 on
Switch 4 off and 5 on
Switch 3 off and 2 on
Switch 2 off and 3 on
Switch 1 off and 0 on
Switch 0 off and 1 on
1
0
X
X
X
X
X
X
X
X
X
X
X
X
1
0
X
X
X
X
X
X
X
X
1
0
X
X
X
X
1
0
age current flows to the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of either the same or
opposite polarity.
Single Supply
The MAX395 operates from a single supply between
+3V and +16V when V- is connected to GND. All of the
bipolar precautions must be observed.
The re is no c onne c tion b e twe e n the a na log s ig na l
paths and GND.
Hig h -Fre q u e n c y P e rfo rm a n c e
In 50Ω systems, signal response is reasonably flat up
to 50MHz (s e e Typ ic a l Op e ra ting Cha ra c te ris tic s ).
Ab ove 20MHz, the on-re s p ons e ha s s e ve ra l minor
peaks that are highly layout dependent. The problem is
not turning the switch on, but turning it off. The off-state
switch acts like a capacitor and passes higher frequen-
cies with less attenuation. At 10MHz, off isolation is
about -45dB in 50Ω systems, becoming worse (approx-
imately 20dB per decade) as frequency increases.
Hig he r c irc uit imp e d a nc e s a ls o ma ke off is ola tion
wors e . Ad ja c e nt c ha nne l a tte nua tion is a b out 3d B
above that of a bare IC socket, and is due entirely to
capacitive coupling.
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic lim-
its. The logic-level translators convert the logic levels to
switched V+ and V- signals to drive the analog signal
gates. This drive signal is the only connection between
the logic supplies (and signals) and the analog sup-
plies. V+, and V- have ESD-protection diodes to GND.
The logic-level inputs and output have ESD protection
to V+ and to GND.
The logic-level thresholds are CMOS and TTL compati-
ble when V+ is +5V. As V+ is raised, the threshold
inc re a s e s s lig htly. So whe n V+ re a c he s +12V, the
threshold is about 3.1V; slightly above the TTL guaran-
teed high-level minimum of 2.8V, but still compatible
with CMOS outputs.
Bipolar Supplies
The MAX395 operates with bipolar supplies between
±3.0V and ±8V. The V+ and V- supplies need not be
symmetrical, but their sum cannot exceed the absolute
maximum rating of 17V. Do not connect the MAX395
V+ to +3V and connect the logic-level pins to TTL
logic-level signals. This exceeds the absolute maxi-
mum ratings and can damage the part and/or exter-
nal circuits.
______________________________________________________________________________________ 15
S e ria lly Co n t ro lle d , Lo w -Vo lt a g e ,
8 -Ch a n n e l S P S T S w it c h
___________________Ch ip To p o g ra p h y
NO3
COM3
NO2
COM2
COM5
COM4
NO4
NO5
MAX395
COM1
COM6
NO6
NO1
0. 120"
(3. 05mm)
COM0
COM7
NO7
NO0
GND
V-
DOUT
CS
V+
RESET
SCLK
DIN
0. 100"
(2. 54mm)
TRANSISTOR COUNT: 500
SUBSTRATE CONNECTED TO V+.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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Example: MAX358CPD
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P = Package Type
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D = Number of Pins
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When a part has a four-letter suffix, the first letter of the suffix denotes
product grade. For example, the first "A" in MAX631ACPA indicates 5%
output accuracy; the remaining three letters denote temperature range,
package type, and number of pins. Therefore, the MAX631ACPA has 5%
accuracy, operates over the 0°C to 70°C range, comes in a plastic DIP
package, and has eight pins.
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Mil-Std-883B
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-T
Part number is furnished on tape-and-reel
Indicates a lead-free (RoHS) qualified version. See our lead-free
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+
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Indicates a lead-free (RoHS) part on tape and reel.
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Indicates that the device has a Moisture Sensitivity Level (MSL)
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Indicates an RoHS-compliant part which has an exemption for
#
Information
(EMMI)
lead.
Lookup Lead-Free
Products and
Temperature Ranges
C
I
0°C to +70°C
Content Data
-20°C to +85°C
-40°C to +85°C
-40°C to +125°C
-55°C to +125°C
E
A
M
Package Type
A SSOP (Shrink Small-Outline Package)
B UCSP (Chip Scale Package), CERQUAD
C TO-220, TQFP (Thin Quad Flat Pack)
D Ceramic Sidebraze
E
F
QSOP (Quarter Small-Outline Package)
Ceramic Flat Pack
H Module, SBGA (Super Ball Grid Array, 5x5 TQFP)
CERDIP Dual-In-Line
K SOT (8 Leads)
LCC (Leadless Ceramic Chip Carrier)
J
L
M MQFP (Metric Quad Flat Pack)
N Narrow Plastic Dual-In-Line
P
Plastic Dual-In-Line
Q PLCC (Plastic Leaded Chip Carrier)
R Narrow CERDIP (300 mil)
S
T
Small Outline (150 mil), TO-52 (2 or 3 leads)
TO-5 Type (also TO-99, TO-100, Thin QFN)
U TSSOP, µMAX, SOT
V TO-39
W Wide SOIC (300 mil)
X SC-70 (3, 5, 6 leads)
Y Narrow Sidebraze (300 mil)
Z
TO-92, MQUAD, Thin SOT
/D Dice
/PR Rugged Plastic
/W Wafer
Number of Pins
A 8
B 10, 64
C 12, 192
D 14
E
F
16
22, 256
G 24
H 44
I
J
28
32
K 5, 68
40
L
M 7, 48
N 18
O 42
P
20
Q 2, 100
R 3, 84
S
T
4, 80
6, 160
U 60
V 8 (0.200" pin circle, isolated case)
W 10 (0.230" pin circle, isolated case)
X 36
Y 8 (0.200" pin circle, case to pin 4)
Z
10 (0.230" pin circle, case to pin 5)
Second-Source Numbering System
In most cases, Maxim's part number for a second-source productfollows the
industry's most widely accepted numbering systemfor that particular part,
rather than our own convention. Thisincludes the original designators for
product grade, temperaturerange, package type, and number of pins.
Maxim frequently supplies second-sourceproducts in packages or
temperature ranges that are not suppliedby other manufacturers. Whenever
possible, these devices are givenpart numbers that follow the original
numbering convention.
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