MAX3969ETP+T [MAXIM]
Support Circuit, 1-Func, Bipolar, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD-1, TQFN-20;
| 型号： | MAX3969ETP+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Support Circuit, 1-Func, Bipolar, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD-1, TQFN-20 放大器 |
| 文件： | 总11页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3251; Rev 0; 4/04
200Mbps SFP Limiting Amplifier
General Description
Features
The MAX3969 limiting amplifier with PECL data outputs is
ideal for low-cost ATM, Fast Ethernet, FDDI and ESCON
fiber optic receivers.
♦ 1mV
Input Sensitivity
P-P
♦ Loss-of-Signal Detector with Programmable
Threshold
The MAX3969 features 1mV
input sensitivity and an
P-P
♦ TTL LOS and PECL Signal Detect
♦ Analog Received-Signal-Strength Indicator
♦ Output Squelch Function
integrated power detector that senses the input signal
power. It provides a received-signal-strength indicator
(RSSI), which is an analog indication of the power level.
Signal strength is also indicated by the complementary
TTL loss-of-signal (LOS) outputs and the PECL signal-
detect (SD) output, both of which indicate the power
level relative to a programmable threshold.
♦ Compatible with 4B/5B Data Coding
The threshold can be adjusted to detect signal ampli-
tudes as low as 2.7mV . An optional squelch function
P-P
disables switching of the data outputs by holding them
at a known state when the signal is below the pro-
grammed threshold.
Ordering Information
PIN-
The MAX3969 is available in die form and a 4mm x
4mm, 20-pin thin QFN package.
PART
TEMP RANGE
PKG CODE
PACKAGE
-40°C to +85°C 20 Thin QFN
Dice*
MAX3969ETP
T2044-2
—
Applications
MAX3969E/D**
—
SFP/SFF Transceivers
*Dice are designed to operate over a -40°C to +100°C junction
temperature (T ) range, but are tested and guaranteed only at
Fast Ethernet/FDDI Transceivers
155Mbps LAN ATM Transceivers
ESCON Receivers
J
T
A
= +25°C.
**Future product—contact factory for availability.
FTTx Transceivers
Typical Application Circuits
SFP OPTICAL RECEIVER WITH DIAGNOSTICS
HOST BOARD
V
CC
C
AZ
0.027µF
+2.97V TO +3.63V
C
FILTER
0.01µF
DIAGNOSTIC
MONITOR
0.01µF
R
LOS
4.7kΩ
CZP
RSSI
CZN FILTER
V
V
CC
CCO
TO
LOS
10kΩ
V
V
CC
LOS
SD
SQUELCH
IN-
C
IN
0.01µF
CC
MAX3969
0.1µF
0.1µF
FILT
IN
OUT-
OUT+
OUT-
OUT+
MAX3657
IN+
INV
C
IN
0.01µF
V
GND
TH
GND
150Ω
150Ω
R1
100kΩ
R2
Typical Application Circuits continued at end of data sheet.
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
200Mbps SFP Limiting Amplifier
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage Range (V , V
) ..........-0.5V to +7.0V
Continuous Power Dissipation (T = +85°C)
A
CC CCO
Voltage at FILTER, RSSI, IN+, IN-, CZP, CZN, SQUELCH,
INV, V ..................................................-0.5V to (V + 0.5V)
TTL Output Current (LOS, LOS) ......................................... 9mA
PECL Output Current (OUT+, OUT-, SD) ......................... 50mA
Differential Voltage Between CZP and CZN..........-1.5V to +1.5V
Differential Voltage Between IN+ and IN- .............-1.5V to +1.5V
20-Pin Thin QFN (derate 16.9mW/°C above +85°C) ....1099mW
Operating Junction Temperature Range (die).....-40°C to +150°C
Die Attach Temperature...................................................+400°C
Storage Temperature Range.............................-50°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
TH
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +2.97V to +5.5V, PECL outputs terminated with 50Ω to V
- 2V, R1 = 100kΩ, T = -40°C to +85°C, unless otherwise noted.
CC A
CC
Typical values are at V
= +3.3V, T = +25°C.) (Note 1)
A
CC
PARAMETER
CONDITIONS
PECL outputs open
MIN
TYP
22
5
MAX
45
UNITS
mA
dB
Supply Current
LOS Hysteresis
Input = 4.0mV
(Note 2)
3.0
8.0
P-P
Squelch Input Current
27
100
µA
PECL Output-Voltage High
PECL Output-Voltage Low
(Note 3)
(Note 3)
-1085
-1830
-3.0
-880
-1550
+3.0
+3.6
2.7
mV
mV
dB
Input = 7mV
Input = 7mV
or 90mV , 0°C to +85°C
P-P
P-P
LOS Assert Accuracy
or 90mV , -40°C to +85°C
-3.6
dB
P-P
P-P
Minimum LOS Assert Input
Maximum LOS Deassert Input
Input Sensitivity
mV
mV
mV
mV
P-P
P-P
P-P
P-P
143
(Note 4)
(Note 4)
1
4
Input Overload
1500
2.4
TTL Output High
R
LOS
= 4.7kΩ to 10kΩ
3.0
1
V
TTL Output Leakage
TTL Output Low
(Note 5)
= 800µA
20
0.5
µA
V
I
0.2
0.8
50
10
OL
Data Output Transition Time
Pulse-Width Distortion
LOS, SD Assert/Deassert Time
20% to 80%, Input > 4mV
(Note 4)
0.35
1.20
250
ns
ps
µs
P-P
Input > 4mV
(Notes 4, 6)
P-P
C
= 0.01µF
FILTER
Note 1: Dice are tested and guaranteed only at T = +25°C.
A
Note 2: LOS hysteresis = 20log(V
/ V
).
LOS-DEASSERT
LOS-ASSERT
Note 3: Relative to supply voltage (V
).
CCO
Note 4: AC characteristics are guaranteed by design and characterization.
Note 5: Input < LOS threshold (LOS = HIGH), V = 2.4V.
LOS
Note 6: Pulse-width distortion = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 100Mbps 1-0 pattern.
2
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier
Typical Operating Characteristics
(V
= +3.3V, PECL outputs terminated with 50Ω to V
- 2V, R1 = 100kΩ, T = +25°C, unless otherwise noted.)
CC A
CC
OUTPUT EYE DIAGRAM
23
OUTPUT EYE DIAGRAM
SUPPLY CURRENT vs. TEMPERATURE
(PECL OUTPUTS OPEN)
23
(V = 2mV , 155Mbps, 2 - 1 PRBS)
(V = 1500mV , 155Mbps, 2 - 1 PRBS)
IN
P-P
IN
P-P
MAX3969 toc02
MAX3969 toc03
60
55
50
45
40
35
30
25
20
15
10
5
200mV/div
200mV/div
0
1ns/div
1ns/div
-40
-15
10
35
60
85
AMBIENT TEMPERATURE (°C)
BIT ERROR RATIO vs. DIFFERENTIAL
INPUT VOLTAGE
RSSI VOLTAGE vs. DIFFERENTIAL
INPUT VOLTAGE
TRANSFER FUNCTION
10-03
1800
1600
1400
1200
1000
800
3.00
2.80
2.60
2.40
2.20
2.00
1.80
1.60
1.40
1.20
1.00
RSSI LOAD > 10kΩ
155Mbps
23
155Mbps
- 1 PRBS
23
10-04
10-05
10-06
10-07
10-08
10-09
10-10
2
- 1 PRBS
2
LOS LOW
LOS HIGH
10-11
10-12
600
0.1 0.2 0.3 0.4
DIFFERENTIAL INPUT VOLTAGE (mV
0.8
0
0.6 0.7
0.5
0.01
0.1
1
10
100 1000 10,000
1
10
100
1000
)
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
P-P
LOSS-OF-SIGNAL HYSTERESIS
vs. TEMPERATURE
POWER-DETECT THRESHOLD vs. R2
RSSI VOLTAGE vs. TEMPERATURE
(LOS LOW, RSSI LOAD > 10kΩ)
(R1 = 100kΩ)
10
9
8
7
6
5
4
3
2
1
0
1000
100
10
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
1.4
155Mbps
23
2
-1 PRBS
INPUT = 100mV
P-P
SD HIGH/
LOS LOW
R2 = 50kΩ
INPUT = 50mV
P-P
SD LOW/
LOS HIGH
R2 = 10kΩ
INPUT = 10mV
P-P
P-P
155Mbps
23
INPUT = 5mV
2
- 1 PRBS
1
-40
-15
10
35
60
85
10 20 30 40 50 60 70 80 90 100 110 120
-40 -20
0
20
40
60
80 100
AMBIENT TEMPERATURE (°C)
R2 (kΩ)
AMBIENT TEMPERATURE (°C)
_______________________________________________________________________________________
3
200Mbps SFP Limiting Amplifier
Typical Operating Characteristics (continued)
(V
= +3.3V, PECL outputs terminated with 50Ω to V
- 2V, R1 = 100kΩ, T = +25°C, unless otherwise noted.)
CC A
CC
POWER-DETECT TIMING WITH SQUELCH
(INPUT = 12mV , C
DATA OUTPUT TRANSITION TIME
vs. TEMPERATURE
PULSE-WIDTH DISTORTION
vs. DIFFERENTIAL INPUT VOLTAGE
= 0.01µF,
P-P FILTER
23
R2 = 15kΩ, 155Mbps, 2 - 1 PRBS)
MAX3969 toc10
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100
90
80
70
60
50
40
30
20
10
0
100Mbps
1-0 PATTERN
IN
OUT
INPUT DATA THROUGH
117MHz FILTER
LOS
SD
UNFILTERED
INPUT DATA
-40
-15
10
35
60
85
1
10
100
1000
10,000
10µs/div
AMBIENT TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (mV
)
P-P
Pin Description
PIN
NAME
FUNCTION
Inverting Input of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a
1
INV
resistor from V to INV (R2), and from INV to ground (R1 = 100kΩ), to program the desired threshold
TH
voltage.
Filter Output of Logarithmic Full-Wave Detectors (FWDs). The FWD outputs are summed together at
2
3
FILTER
RSSI
FILTER to generate the RSSI output. Connect a capacitor from FILTER to V
for proper operation.
CC
Received-Signal-Strength Indicator Output. The voltage at RSSI indicates the input-signal power. The
RSSI output is reduced approximately 120mV when LOS is asserted.
4
5
IN-
IN+
Inverting Data Input
Noninverting Data Input
6 , 7, 8
9
GND
CZP
CZN
Ground
Autozero Capacitor Input. Connect a 0.027µF capacitor between CZP and CZN.
Autozero Capacitor Input. Connect a 0.027µF capacitor between CZP and CZN.
10
11
V
Output-Buffer Supply Voltage. Connect to the same potential as V
.
CC
CCO
12
OUT+
OUT-
Noninverting PECL Data Output. Terminate with 50Ω to (V
- 2V).
CC
13
Inverting PECL Data Output. Terminate with 50Ω to (V
- 2V).
CC
Signal Detect, PECL Output. The SD output is high when input power is above the power-detect
threshold, and low when input power is below the power-detect threshold. This pin is PECL-
14
15
16
SD
compatible and should be terminated with 50Ω to (V
- 2V) or equivalent.
CC
Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is high when input
power is below the power-detect threshold, and low when input power is above the power-detect
threshold.
LOS
LOS
Inverted Loss-of-Signal Output, TTL Open Collector (with ESD Protection). The LOS output is low
when input power is below the power-detect threshold, and high when input power is above the
power-detect threshold.
4
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier
Pin Description
PIN
NAME
FUNCTION
17, 18
V
Supply Voltage
Squelch Input. The squelch function disables the data outputs by forcing OUT- low and OUT+ high
SQUELCH when the signal is below the power-detect threshold. Connect to GND or leave unconnected to
disable squelch. Connect to V to enable squelch.
CC
19
CC
Output of Internal Op Amp that Sets Power-Detect Threshold Voltage (Figure 1). Connect a resistor
20
EP
V
TH
from V to INV (R2) and from INV to ground (R1 = 100kΩ), to program the desired threshold voltage.
TH
Exposed
Pad
Ground. The exposed pad must be soldered to the circuit board ground for proper thermal and
electrical performance.
C
AZ
V
V
CCO
CC
CZP
CZN
OFFSET
CORRECTION
MAX3969
1
1
OUT-
C
C
IN
IN
PECL
IN-
IN+
O
OUT+
SQUELCH
FWD
FWD
FWD
RSSI
LOS
FILTER
V
CC
TTL
C
FILTER
LOS
1.2V
REFERENCE
SD
PECL
INV
V
TH
R1
GND
100kΩ
R2
Figure 1. Functional Diagram
circuit. By correcting the DC offsets, the limiting amplifi-
er sensitivity and power-detector accuracy are
improved.
Detailed Description
The MAX3969 contains a series of limiting amplifiers
and power detectors, offset correction, data-squelch
circuitry, TTL buffers for LOS outputs, and PECL output
buffers for signal detect (SD) and data outputs. See
Figure 1 for the functional diagram.
The offset correction is optimized for data streams with
a 50% duty cycle. A different average duty cycle results
in increased pulse-width distortion and loss of sensitivi-
ty. The offset-correction circuitry is less sensitive to vari-
ations of input duty cycle (for example, the 40% to 60%
duty cycle encountered in 4B/5B coding) when the
Gain Stages and Offset Correction
A cascade of limiting amplifiers provides approximately
65dB of combined small-signal gain. The large gain
makes the amplifier susceptible to small DC offsets in
the signal path. To correct DC offsets, the amplifier has
an internal feedback loop that acts as a DC autozero
input is less than 30mV
.
P-P
The data inputs must be AC-coupled for the offset cor-
rection loop to function properly. Differential input
impedance is >5kΩ.
_______________________________________________________________________________________
5
200Mbps SFP Limiting Amplifier
Power Detector
PECL Outputs
Each amplifier stage contains a logarithmic FWD, which
indicates the RMS input signal power. The FWD outputs
are summed together at the FILTER pin where the sig-
The data outputs (OUT+, OUT-) and signal-detect out-
put (SD) are supply-referenced PECL outputs. See
Figure 2 for the equivalent output circuit.
nal is filtered by an external capacitor (C
) con-
FILTER
Both data outputs must be terminated for proper opera-
tion, but the SD output can be left open if not required
in the application. The proper termination for a PECL
nected between FILTER and V . The FILTER signal
CC
generates the RSSI output voltage (V
), which is
RSSI
proportional to the input power in decibels. When LOS
is low, V is approximated by the following equation:
output is 50Ω to (V
- 2V), but other standard termina-
CC
RSSI
tion techniques can be used. For more information on
PECL terminations and how to interface with other logic
families, refer to Maxim Application Note HFAN-01.0:
Introduction to LVDS, PECL, and CML.
V
(V) = 1.2V + 0.5log (V )
IN
RSSI
where, V is the data input voltage measured in mV
.
IN
P-P
This relation translates to a 25mV increase in V
for
RSSI
every 1dB increase in V . The RSSI output is reduced
TTL Outputs
The LOS outputs (LOS, LOS) are implemented with
open-collector, Schottky-clamped, ESD-protected, TTL-
compatible outputs. See Figure 3 for the equivalent out-
put circuit. The LOS outputs require external pullup
resistors for proper operation. Resistor values between
4.7kΩ and 10kΩ are recommended.
IN
approximately 120mV when LOS is high.
Typically the RSSI output is connected to an A/D con-
verter for diagnostic monitoring. This output can be left
open if not required in the application. The RSSI output
is designed to drive a minimum load resistance of 10kΩ
to ground, and a maximum capacitance of 10pF. A
10kΩ series resistor is required to buffer loads greater
than 10pF.
If the LOS outputs are not required for the application,
they can be left open.
Signal-Strength Comparator
A comparator is used to indicate the input signal
strength relative to a user-programmable threshold.
One of the comparator inputs is connected to the RSSI
output signal, and the other is connected to the thresh-
Design Procedure
Program the Power-Detect Threshold
The suggested procedure for setting the power-detect
threshold is given below and is illustrated in Figure 4.
old voltage (V ), which is set externally and provides
TH
1) Determine the maximum receiver sensitivity
(RX_MAX) in dBm and the PIN-TIA responsivity (G)
in V/W.
a trip point for signal-strength indication. When the sig-
nal strength is above the threshold, the SD output
asserts high and the LOS output deasserts low.
Likewise, when the signal strength falls below the
threshold, SD deasserts low and LOS asserts high. To
ensure chatter-free operation, the comparator is
designed with approximately 5dB of hysteresis.
2) Calculate the differential voltage swing (VIN_SEN) at
the MAX3969 inputs while operating at sensitivity.
(RX_MAX / 10)
V
= 10
x 2 x G
IN_SEN
3) Calculate the threshold voltage (V
) at which
IN_TH
LOS must be low (SD must be high) by allowing
3.6dB (1.8dB optical) margin for power-detector
accuracy.
Squelch
The squelch function disables the data outputs by forc-
ing OUT- low and OUT+ high when the input signal is
below the programmed threshold. This function
ensures that when there is a loss of signal, the limiting
amplifier and all downstream devices do not respond to
input noise. Connect SQUELCH to GND or leave it
unconnected to disable squelch. Connect SQUELCH to
V
= V
x 0.66
IN_TH
IN_SEN
4) Use V
and the line labeled (SD HIGH / LOS
IN_TH
LOW) in the Power-Detect Threshold vs. R2 graph
in the Typical Operating Characteristics to deter-
mine the value of R2. Select R1=100kΩ.
V
to enable squelch.
CC
6
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier
10 log(OPTICAL POWER)
V
CCO
PIN-TIA RESPONSIVITY = G
RX_MAX (SENSITIVITY)
1.8dB
SD HIGH / LOS LOW
2.5dB
SD LOW / LOS HIGH
OUT-
5dB
3.6dB
OUT+
20 log(V
)
IN
ESD
STRUCTURES
V
IN_TH
V
IN_SEN
Figure 4. Signal Levels for Power-Detect Threshold
Select C
FILTER
For SFP/SFF, FDDI, 155Mbps ATM LAN, Fast Ethernet,
and ESCON receivers, Maxim recommends C
=
FILTER
0.01µF. This capacitor value ensures chatter-free
LOS/SD and provides a typical assert/deassert time of
Figure 2. Equivalent PECL Output Circuit
10µs. For other applications, the value of C
be calculated using the following equation:
can
FILTER
C
FILTER
= τ / 825Ω
where τ is the desired time constant of the power detector.
V
CCO
Select C
and C
IN
AZ
External-coupling capacitors (C ) are required on the
IN
data inputs for the offset correction loop to function
properly. The offset correction loop bandwidth is deter-
mined by the external capacitor (C ) connected
AZ
between CZP and CZN. The poles associated with C
IN
LOS/LOS
and C must work together to provide a flat response
AZ
at the lower -3dB corner frequency. For SFP/SFF, FDDI,
155Mbps ATM LAN, Fast Ethernet, and ESCON
receivers, Maxim recommends the following:
ESD
STRUCTURES
C
= 0.01µF
IN
C
= 0.027µF
AZ
Figure 3. Equivalent TTL Output Circuit
_______________________________________________________________________________________
7
200Mbps SFP Limiting Amplifier
Applications Information
Table 1. Bond Pad Coordinates
Wire Bonding
For high-current density and reliable operation, the
MAX3969 uses gold metalization. For best results, use
gold-wire ball-bonding techniques. Use caution if
attempting wedge bonding. Die pad size is 4 mils x 4
mils. Die thickness is 16 mils.
COORDINATES (µm)
PAD
NAME
X
Y
1
2
INV
FILTER
RSSI
IN-
46.6
659.5
505.6
351.7
197.8
46.6
46.6
3
46.6
4
46.6
Table 1 lists the bond pad coordinates for the MAX3969.
The origin for pad coordinates is defined as the bottom
left corner of the bottom left pad. All pad locations are
referenced from the origin and indicate the center of the
pad where the bond wire should be connected. Refer to
Maxim Application Note HFAN-08.0.1: Understanding
Bonding-Coordinates and Physical Die Size for detailed
information.
5
IN+
46.6
6
GND
GND
GND
CZP
195.1
432.7
589.3
743.2
945.7
1204.9
1204.9
1204.9
1204.9
1204.9
1053.7
808.0
586.6
432.7
195.1
-99.1
-99.1
-99.1
-99.1
-99.1
-96.4
81.7
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CZN
V
CCO
OUT+
OUT-
SD
262.6
492.1
697.3
818.8
818.8
818.8
818.8
818.8
Pin Configuration
LOS
LOS
TOP VIEW
V
V
CC
CC
20 19 18 17 16
SQUELCH
INV
FILTER
RSSI
IN-
1
2
3
4
5
15 LOS
14 SD
V
TH
13 OUT-
12 OUT+
MAX3969
Chip Information
11
V
CCO
IN+
TRANSISTOR COUNT: 915
6
7
8
9
10
SUBSTRATE CONNECTED TO GND
PROCESS: Silicon Bipolar
DIE THICKNESS: 16 mils
THIN QFN
8
_______________________________________________________________________________________
200Mbps SFP Limiting Amplifier
Chip Topography
V
V
SQUELCH
19
V
LOS
16
CC
TH
CC
18
17
20
LOS
SD
15
14
INV
1
2
FILTER
47mil
(1.19mm)
RSSI
IN-
3
4
5
13
12
11
OUT-
OUT+
IN+
ORIGIN
9
8
10
7
6
V
CCO
GND
GND
CZP
CZN
GND
57mil
(1.45mm)
_______________________________________________________________________________________
9
200Mbps SFP Limiting Amplifier
Typical Application Circuits (continued)
C
AZ
V
CC
CC
0.027µF
C
FILTER
0.01µF
SFF OR 1 x 9 MSA RECEIVER
0.01µF
CZP
RSSI
CZN FILTER
V
V
CCO
LOS
V
V
CC
LOS
SD
SQUELCH
IN-
C
IN
CC
0.01µF
MAX3969
FILT
IN
OUT-
OUT+
OUT-
OUT+
MAX3657
IN+
INV
C
IN
V
GND
TH
GND
0.01µF
50Ω
50Ω
50Ω
R1
100kΩ
R2
V
CC
- 2V
10 ______________________________________________________________________________________
200Mbps SFP Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
1
C
21-0139
2
PACKAGE OUTLINE
12, 16, 20, 24L THIN QFN, 4x4x0.8mm
2
C
21-0139
2
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX3969ETP-T
Support Circuit, 1-Func, Bipolar, 4 X 4 MM, 0.80 MM HEIGHT, MO-220WGGD-1, TQFN-20
MAXIM
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