MAX3992 [MAXIM]
10Gbps Clock and Data Recovery with Equalizer;
| 型号： | MAX3992 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10Gbps Clock and Data Recovery with Equalizer |
| 文件： | 总12页 (文件大小：271K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3496; Rev 2; 11/06
10Gbps Clock and Data Recovery
with Equalizer
General Description
Features
♦ Multirate Operation from 9.95Gbps to 11.1Gbps
♦ Span Up to 300mm (12in) FR4 with One Connector
♦ Low-Output Jitter Generation: 4mUIRMS
♦ Low-Output Deterministic Jitter: 4.6psP-P
♦ XFI-Compliant Input Interface
The MAX3992 is a 10Gbps clock and data recovery
(CDR) with equalizer IC for XFP optical transmitters. The
MAX3992 and the MAX3991 (CDR with limiting amplifier)
form a signal conditioner chipset for use in XFP trans-
ceiver modules. The chipset is XFI compliant and offers
multirate operation for data rates from 9.95Gbps to
11.1Gbps.
The MAX3992 recovers the data for up to 12 inches of
FR-4 and one connector without the need for a stand-
alone equalizer. The phase-locked loop is optimized for
jitter tolerance in SONET, Ethernet, and Fibre-Channel
♦ LOS Indicator
♦ LOL Indicator
♦ Power Dissipation: 356mW
applications. Low jitter generation of 4mUI
leaves
RMS
adequate margin for meeting SONET jitter requirements
at the optical output.
An AC-based power detector asserts the loss-of-signal
(LOS) output when the input signal is removed. An exter-
nal reference clock, with frequency equal to 1/64 or 1/16
of the serial data rate, is used to aid in frequency acqui-
sition. A loss-of-lock (LOL) indicator is provided to indi-
cate the lock status of the receiver PLL.
Ordering Information
PIN-
PACKAGE
PKG
CODE
PART
TEMP RANGE
MAX3992UTG
0°C to +85°C
0°C to +85°C
24 QFN
24 QFN
T2444-4
T2444-4
MAX3992UTG+*
The MAX3992 is available in a 4mm x 4mm, 24-pin QFN
package. It consumes 356mW from a single +3.3V sup-
ply and operates over a 0°C to +85°C temperature range.
*Future product—contact factory for availability.
+Denotes lead-free package.
Pin Configuration
Applications
9.95Gbps to 11.1Gbps Optical XFP Modules
SONET OC-192/SDH STM-64 XFP Transceivers
10.3Gbps/11.1Gbps Ethernet XFP Transceivers
10.5Gbps Fibre-Channel XFP Transceivers
10Gbps DWDM Transceivers
TOP VIEW
24
23
22
21
20
19
V
CC
V
1
2
3
4
5
6
18
17
16
15
14
13
CC
10Gbps XFP Copper Modules
GND
SDI-
SDI+
GND
GND
SDO-
SDO+
GND
High-Speed Backplane Interconnects
MAX3992
V
CC
V
CC
Typical Application Circuit appears at end of data sheet.
7
8
9
10
11
12
4mm x 4mm QFN*
*THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR
PROPER THERMAL AND ELECTRICAL PERFORMANCE.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10Gbps Clock and Data Recovery
with Equalizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V ..............................................-0.5V to +4.0V
Input Voltage Levels
Voltage at (CFIL, LOL, VTH, POL,
LOS, FCTL1, FCTL2) ..............................-0.5V to (V
CC
+ 0.5V)
CC
(SDI+, SDI-, REFCLK+,
REFCLK-) ....................................(V
CML Output Voltage
(SDO+, SDO-, SCLKO+,
SLCKO-)......................................(V
Continuous Power Dissipation (T = +85°C)
A
- 1.0V) to (V
- 1.0V) to (V
+ 0.5V)
+ 0.5V)
24-Pin QFN (derate 20.8mW/°C above +85°C) .........1355mW
Junction Temperature Range.............................-40°C to+150°C
Storage Temperature Range.............…………..-55°C to +150°C
Lead Temperature (soldering, 10s) ..……………………..+300°C
CC
CC
CC
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(See Table 1 for operating conditions. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.)
A
CC
PARAMETER
Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
108
145
mA
CC
DATA INPUT SPECIFICATION (SDI± ±
Single-Ended Input Resistance
Differential Input Resistance
R
42
84
50
58
Ω
Ω
SE
R
100
116
D
Single-Ended Input Resistance
Matching
5
%
0.1GHz to 5.5GHz (Note 1)
5.5GHz to 12GHz (Note 1)
15
6
Differential-Input Return Loss
SDD11
SCD11
SCC11
dB
dB
dB
Differential to Common-Mode
Conversion
0.1GHz to 15GHz
0.1GHz to 15GHz
17
7
Common-Mode Input Return
Loss
REFERENCE CLOCK SPECIFICATION (REFCLK± ±
Single-Ended Input Resisitance
84
100
200
116
232
Ω
Ω
Differential Input Resistance
168
CML OUTPUT SPECIFICATION (SDO± ±
SDO Differential Output Swing
(Note 2)
RL = 50Ω to V
575
650
725
mV
P-P
SDO Output Common-Mode
Voltage
V
-
CC
V
CC
0.16
SCLKO Differential Output
Single-Ended Output Resistance
Differential Output Resistance
380
50
mV
P-P
42
84
58
Ω
R
O
100
116
Ω
Single-Ended Output Resistance
Matching
5
%
0.1GHz to 5.5GHz (Note 1)
5.5GHz to 12GHz (Note 1)
(20% to 80%) (Note 2)
(Note 3)
13
8
Differential-Output Return Loss
SDD22
dB
Rise/Fall Time
18
23
30
50
ps
µs
Power-Down Assert Time
2
_______________________________________________________________________________________
10Gbps Clock and Data Recovery
with Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.25
8.0
UNITS
JITTER SPECIFICATION
120kHz < f ≤ 8MHz (Notes 2, 4)
f ≤ 120kHz (Note 5)
(Notes 2, 4)
0.05
0.03
5.6
Jitter Peaking
J
dB
P
Jitter Transfer Bandwidth
J
MHz
BW
>2.8
(Note 6)
f = 400kHz
2.8
Sinusoidal Jitter Tolerance
Jitter Generation
(Notes 2, 4, 7)
UI
P-P
f = 4MHz
0.4
0.4
0.55
0.45
4
f = 80MHz
(Notes 2, 4, 8)
5.5
13
mUI
ps
RMS
Serial-Data Output Deterministic
Jitter
DJ
PRBS 27 - 1 (Note 2)
4.6
P-P
PLL ACQUISITION/LOCK SPECIFICATION
Acquisition Time
Figures 1, 2 (Note 2)
Figure 1 (Note 2)
(Note 9)
200
90
µs
LOL Assert Time
µs
Maximum Frequency Pullin Time
2
ms
Frequency Difference at which
LOL Is Asserted
∆f = f
N = 16 or 64
/ N - f
,
,
VCO
REFCLK
|
|
∆f/f
∆f/f
651
ppm
ppm
REFCLK
REFCLK
Frequency Difference at which
LOL Is Deasserted
∆f = f / N - f
VCO
N = 16 or 64
REFCLK
|
|
500
LOSS-OF-SIGNAL (LOS± SPECIFICATION
VTH Control Voltage Range
LOS Gain Factor
VTH
150
500
mV
V/V
VTH/
10
V
V
V
LOS_ASSERT
Minimum LOS Assert Voltage
Maximum LOS Assert Voltage
LOS Gain-Factor Accuracy
LOS Hysteresis
15
50
mV
mV
dB
dB
%
LOS_ASSERT
LOS_ASSERT
(Notes 2, 10)
(Notes 2, 11)
-1.5
3.5
-10
3
+1.5
3.9
+10
90
3.7
LOS Gain-Factor Stability
LOS Assert Time
(Note 2) Overtemperature and supply
Figure 2 (Note 2)
µs
LOS Deassert Time
Figure 2 (Note 2)
90
µs
VTH Input Current
-5
+5
µA
LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2±
Input High Voltage
V
2.0
-30
V
IH
Input Low Voltage
Input Current
V
0.8
V
IL
+30
µA
V
0.5
-
CC
Output High Voltage
Output Low Voltage
V
Sourcing 30µA
Sinking 1mA
V
V
OH
V
0.4
OL
_______________________________________________________________________________________
3
10Gbps Clock and Data Recovery
with Equalizer
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at V
= +3.3V, T = +25°C, unless otherwise noted.)
CC
A
Note 1: Measured with 100mV
differential amplitude.
P-P
Note 2: Guaranteed by design and characterization.
Note 3: Measured from the time that the FCTL1 input goes high with FCTL2 = 0, to the time when the supply current drops to less
than 40% of the nominal value.
31
Note 4: Measured with PRBS = 2 - 1.
Note 5: Larger C
can be used to reduce jitter peaking at ≤ 120kHz. A larger C
will increase acquisition time. C
should
FILT
FILT
FILT
not exceed 200nF.
Note 6: Measurement limited by test equipment.
-12
Note 7: Jitter tolerance is for BER ≤ 10 , measured with additional 0.1VI deterministic jitter through 15 inches of FR4. (See Typical
Operating Characteristics 1.)
Note 8: Measured with 50kHz to 80MHz SONET filter.
Note 9: Applies on power-up or after standby.
Note 10: Over process, temperature and supply.
Note 11: Hysteresis is defined as 20Log(V
/V
).
LOS-DEASSERT LOS-ASSERT
Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.)
PARAMETER
Supply Voltage
SYMBOL
CONDITIONS
MIN
3.0
0
TYP
(See Table 2)
50
MAX
3.6
UNITS
V
V
CC
Ambient Temperature
Input Data Rate
T
A
+85
°C
Rb
Gbps
Differential Input Voltage to
Transmission Line
V
0 to 12 inches FR-4
400
1000
mV
D
P-P
P-P
Output Load Resistance
RL
RL is AC-coupled
Ω
REFCLK Differential Input Voltage
Swing
300
30
1600
70
mV
REFCLK Duty Cycle
REFCLK Frequency
REFCLK Accuracy
%
Rb / 16
Rb / 64
f
GHz
ppm
ps
REFCLK
Relative to Rb / 16 or Rb / 64
-100
+100
1200
300
10
F
= Rb / 64
= Rb / 16
REFCLK
REFCLK
REFCLK Rise/Fall Times (20% to
80%)
f
REFCLK Random Jitter
Noise bandwidth < 100MHz
ps
RMS
Table 2. Serial Data Rate and Reference Clock Frequency
DATA RATE (Rb±
(Gbps±
/16 REFERENCE CLOCK
/64 REFERENCE CLOCK
FREQUENCY (MHz±
APPLICATION
FREQUENCY (MHz±
OC-192 SONET – SDH64
OC-192 SONET over FEC
ITU G.709
9.95328
10.664
622.08
666.5
155.52
166.625
10.709
669.3125
644.53125
693.483125
657.421875
167.328125
161.1328125
173.3707813
164.355469
10Gbps Ethernet, IEEE 802.3ae
10Gbps Ethernet over ITU G.709
10Gbps Fibre Channel
10.3125
11.09573
10.51875
Note: The part should be in standby mode when data rates are being switched.
4
_______________________________________________________________________________________
10Gbps Clock and Data Recovery
with Equalizer
∆f/f
REFCLK
651ppm
500ppm
LOL
ASSERT TIME
ACQUISITION
TIME
LOL
*ASSERT AND ACQUISITION TIME ARE DEFINED
WITH A VALID REFERENCE CLOCK APPLIED.
Figure 1. TX LOL Assert and PLL Acquisition Time
DATA INPUT
POWER
LOS ASSERT TIME
LOS DEASSERT TIME
LOS
ACQUISITION TIME
LOL
Figure 2. LOS Assert/Deassert Time
_______________________________________________________________________________________
5
10Gbps Clock and Data Recovery
with Equalizer
Typical Operating Characteristics
(V
= 3.3V, T = +25°C, unless otherwise noted.)
CC
A
RECOVERED REFERENCE SIGNAL
MAX3992 INPUT
(15in FR-4)
JITTER GENERATION vs. POWER-SUPPLY
WHITE NOISE AMPLITUDE (BW < 100kHz)
31
PRBS 2 -1 15in FR-4
MAX3992 toc02
MAX3992 toc01
16
PRBS 231-1
500
14
12
10
50
8
6
-50
4
2
-500
0
0
1
1
0
0.35
0.65
0
10
20
30
40
)
50
NORMALIZED BIT TIME (UI)
NORMALIZED BIT TIME (UI)
NOISE AMPLITUDE (mV
RMS
POWER-SUPPLY INDUCED OUTPUT
JITTER vs. RIPPLE FREQUENCY
SINUSOIDAL JITTER TOLERANCE
12in FR-4 231-1 PRBS DATA
JITTER TRANSFER
3
0
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
100
10
TOLERANCE EXCEEDS
MODULATION
CAPABILITIES OF TEST
EQUIPMENT
-3
-6
-9
1
XFI TELECOM
MASK
-12
-15
-18
-21
0.1
0.01
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
MAX3992
SUPPLY CURRENT vs. TEMPERATURE
DIFFERENTIAL S11
SDD11
140
130
120
110
100
90
10
5
0
-5
XFI MASK
-10
-15
-20
-25
-30
-35
-40
80
-10
0
10 20 30 40 50 60 70 80 90
TEMPERATURE (°C)
10M
100M
1G
10G
100G
FREQUENCY (Hz)
6
_______________________________________________________________________________________
10Gbps Clock and Data Recovery
with Equalizer
Typical Operating Characteristics (continued)
(V
= 3.3V, T = +25°C, unless otherwise noted.)
A
CC
DIFFERENTIAL TO COMMON MODE S11
SCD11
COMMON MODE S11
SCC11
0
-10
-20
-30
-40
-50
-60
0
-5
XFI MASK
XFI MASK
-10
-15
-20
-25
-30
-35
-40
10M
100M
1G
10G
100G
10M
100M
1G
10G
100G
FREQUENCY (Hz)
FREQUENCY (Hz)
Pin Description
PIN
NAME
FUNCTION
1, 6, 11, 13, 18
V
+3.3V Power Supply
Supply Ground
CC
2, 5, 14, 17
GND
SDI-
3
4
Negative Serial Input, CML
Positive Serial Input, CML
SDI+
Positive Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use
in device testing).
7
SCLKO+
Negative Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use
in device testing).
8
9
SCLKO-
FCTL2
POL
Function Control Input 2, TTL. See Table 3 for more information.
Data Polarity Control Input, TTL. Connect to V
or leave open to maintain the same polarity as the
CC
10
input. Connect to GND to invert the polarity of the data.
Loop-Filter Capacitor Connection. Connect a 0.047µF capacitor between CFIL and V
Positive Serial Data Output, CML
12
15
16
19
20
CFIL
SDO+
SDO-
LOL
.
CC
Negative Serial Data Output, CML
Lock Status Indicator, TTL. This output goes high to indicate the receiver is out of lock.
LOS
Receiver Loss-of-Signal Indicator, TTL . This output goes high when the input signal is removed.
Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the
reference clock source. REFCLK have a 200Ω differential impedance. See the Detailed Description
section for more information. See Table 2.
21
REFCLK+
_______________________________________________________________________________________
7
10Gbps Clock and Data Recovery
with Equalizer
Pin Description (continued)
PIN
NAME
FUNCTION
Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the
reference clock source. REFCLK have a 200Ω differential impedance. See the Detailed Description
section for more information. See Table 2.
22
REFCLK-
23
24
FCTL1
VTH
Function Control Input 1, TTL. See Table 3 for more information.
LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS
power detector can be disabled if VTH is connected to V , which forces LOS low.
CC
Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal
and electrical performance. The MAX3992 uses exposed-pad variation T2444-4 in the package
outline drawing. See the exposed-pad package.
Exposed
Pad
EP
Functional Diagram
VTH
LOS
MAX3992
DFF
SDI+
SDI-
SDO+
SDO-
EQUALIZER
CML
CML
CML
D
Q
PLL
PHASE/
FREQUENCY
DETECTOR
SCLKO+
SCLKO-
VCO
REFCLK+
REFCLK-
LOL
DETECTOR
200Ω
FUNCTIONAL
CONTROL
FCTL1
FCTL2
CFIL
LOL
POL
Figure 3. Functional Diagram
most of the deterministic jitter caused by frequency
dependent skin effect and dielectric losses, as well as
connector loss.
Detailed Description
The MAX3992 clock and data recovery with equalizer
recovers data from the XFI interface. It consists of an
equalizer with LOS power detector and a data retimer
with LOL indicator. An optional recovered clock may
also be enabled for performance testing.
PLL Retimer
The integrated PLL recovers a synchronous clock that
is used to retime the input data. Connect a 0.047µF
capacitor between CFIL and V
to provide PLL damp-
CC
Equalizer
The SDI inputs of the MAX3992 accept serial NRZ data
from XFI standard interfaces. When signals from
ening. The external reference connected to REFCLK
aids in frequency acquisition. Because the reference
clock is only used for frequency acquisition, an
extremely low jitter generation can be achieved from a
low-quality reference clock. The reference clock should
be within 100ppm of the bit rate divided by 16 or 64.
400mV
to 1000mV
are applied to a transmission
P-P
P-P
line from 0 to 12 inches of FR-4, the equalizer restores
them for recovery by the CDR. The equalizer removes
8
_______________________________________________________________________________________
10Gbps Clock and Data Recovery
with Equalizer
Loss-of-Lock Monitor
The LOL output indicates that the frequency difference
Design Procedure
Modes of Operation
The MAX3992 has a standby mode and jitter test mode
in addition to its normal operating mode. Standby is
used to conserve power. In the standby mode, the
power consumption of the MAX3992 falls below 40% of
the normal-operation power consumption. The jitter test
mode enables the SCLK outputs to clock a BERT when
testing jitter generation, jitter transfer, and jitter toler-
ance. The FCTL1 and FCTL2 TTL inputs are used to
select the mode of operation as shown in Table 3.
between the recovered clock and the reference clock is
excessive. LOL may assert due to excessive jitter at the
data input, incorrect frequency, or loss of input data.
The LOL detector monitors the frequency difference
between the recovered clock and the reference clock.
The LOL output is asserted high when the frequency
difference exceeds 650ppm.
Loss-of-Signal Monitor
The LOS output indicates a loss of input data. Set VTH
>500mV. When the input signal is removed (<50mV),
LOS will be asserted high.
Serial Data Rate and
Reference Clock Frequency
Reference Clock Input
The REFCLK inputs are internally terminated and self-
biased to allow AC-coupling. The input impedance is
100Ω single-ended (200Ω differential). The REFCLK
inputs of the MAX3991 and MAX3992 should be con-
nected close together in parallel. The impedance look-
ing into the parallel combination is 100Ω differential.
This allows both the MAX3991 and MAX3992 to easily
interface with one reference clock without using addi-
tional components. See Figure 4.
Input Configuration
The SDI± inputs of the MAX3992 are current-mode
logic (CML) compatible. The inputs have internal 50Ω
terminations for minimum external components. See
Figure 5 for the input structure. For additional informa-
tion on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
Output Configuration
The MAX3992 uses CML for its high-speed digital out-
puts (SDO± and SCLKO±). The configuration of the out-
put circuit includes internal 50Ω back terminations to
V
. See Figure 6 for the output structure. CML outputs
CC
may be terminated by 50Ω to V , or by 100Ω differen-
CC
tial impedance. The relation of the output polarity to input
can be reversed using the POL pin. For additional infor-
mation on logic interfacing, refer to Maxim Application
Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
50W
MAX3991
50W
MAX3992
REFERENCE
REFERENCE
CLOCK
200Ω
200Ω
200Ω
CLOCK
50W
50W
TRANSMITTER-ONLY TERMINATION
MAX3992
200Ω
TRANSCEIVER TERMINATION
Figure 4. Reference Clock Termination
_______________________________________________________________________________________
9
10Gbps Clock and Data Recovery
with Equalizer
Applications Information
V
CC
Exposed Pad (EP) Package
The exposed pad, 24-pin QFN incorporates features
that provide a very low thermal-resistance path for heat
removal from the IC. The pad is electrical ground on the
MAX3992 and must be soldered to the circuit board for
proper thermal and electrical performance.
50Ω
50Ω
SDI+
SDI-
Layout Considerations
For best performance, use good high-frequency layout
techniques. Filter voltage supplies, keep ground con-
nections short, and use multiple vias where possible.
Use controlled-impedance transmission lines to inter-
face with the MAX3992 high-speed inputs and outputs.
Power-supply decoupling should be placed as close to
V
as possible. To reduce feedthrough, take care to
CC
Figure 5. CML Input Model
isolate the input signals from the output signals.
VCC
(SDI+) - (SDI-)
50Ω
50Ω
(SDO+) - (SDO-)
POL = VCC
SDO+
SDO-
(SDO+) - (SDO-)
POL = GND
Figure 7. Polarity (POL) Function
Table 3. Functional Control
GND
FCTL1
FCTL2
DESCRIPTION
Figure 6. CML Output Model
Normal operation, serial clock output
disabled.
0
1
0
0
0
1
Standby power-down mode.
Normal operation, serial clock output
disabled.
Serial clock output enabled for jitter
testing.
1
1
10 ______________________________________________________________________________________
10Gbps Clock and Data Recovery
with Equalizer
Typical Application Circuit
V
CC
0.047µF
TOSA
V
CFIL
CC GND
SDI+
SDI-
SDO+
SDO-
MAX3975
MAX3992
DRIVER
REFCLK+
REFCLK-
LOL LOS
FCTL VTH POL
2
GND
30-PIN
CONNECTOR
DS1862*
CONTROLLER
2-WIRE INTERFACE
2
N.C.
LOL LOS
SDI+
SDI-
FCTL VTH POL
REFCLK+
REFCLK-
ROSA
SDO+
SDO-
MAX3991
V
CFIL
CC GND
XFI
REFERENCE
0.047µF
50Ω TRANSMISSION LINE
*FUTURE PRODUCT.
V
CC
______________________________________________________________________________________ 11
10Gbps Clock and Data Recovery
with Equalizer
Chip Information
Package Information
TRANSISTOR COUNT: 10,300
PROCESS: SiGe bipolar
SUBSTRATE: SOI
(The package drawing(s) in this data sheet may not
reflect the most current specifications. For the latest
package outline information, go to www.maxim-
ic.com/packages.) (QFN 4mm x 4mm x 0.8mm, pack-
age code: T2444-4)
Revision History
Rev 0; 11/04: Initial data sheet release.
Rev 1; 11/05: Changed Jitter Peaking max to typ (page 3); added new Note 5 (page 4); updated Typical
Application Circuit (page 11).
Rev 2: 11/06: Changed Jitter Tolerance min from 2.2UI
to 2.8UI ; changed Jitter Generation max from
P-P
P-P
6.9mUI
, to 5.5mUI
(page 3).
RMS
RMS
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相关型号：
MAX3992UTG+
ATM/SONET/SDH Clock Recovery Circuit, 1-Func, Bipolar, 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, QFN-24
MAXIM
MAX3992UTG+T
Clock Recovery Circuit, 1-Func, Bipolar, 4 X 4 MM, 0.80 MM HEIGHT, LEAD FREE, QFN-24
MAXIM
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