MAX4051AEEE-T [MAXIM]
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19-0463; Rev 0; 1/96
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX4051/MAX4052/MAX4053 a nd MAX4051A/
MAX4052A/MAX4053A are low-voltage, CMOS analog
ICs configured as an 8-channel multiplexer (MAX4051/A),
two 4-channel multiplexers (MAX4052/A), and three sin-
gle-pole/double-throw (SPDT) switches (MAX4053/A).
The A-suffix parts are fully characterized for on-resistance
match, on-resistance flatness, and low leakage.
♦ Pin Compatible with Industry-Standard
74HC4051/74HC4052/74HC4053
♦ Guaranteed On-Resistance:
100Ω with ±5V Supplies
♦ Guaranteed Match Between Channels:
6Ω (MAX4051A–MAX4053A)
12Ω (MAX4051–MAX4053)
These CMOS devices can operate continuously with
dual power supplies ranging from ±2.7V to ±8V or a
single supply between +2.7V and +16V. Each switch
can handle rail-to-rail analog signals. The off leakage
c urre nt is only 0.1nA a t + 25°C or 5nA a t + 85°C
(MAX4051A/MAX4052A/4053A).
♦ Guaranteed Low Off Leakage Currents:
0.1nA at +25°C (MAX4051A–MAX4053A)
1nA at +25°C (MAX4051–MAX4053)
♦ Guaranteed Low On Leakage Currents:
0.1nA at +25°C (MAX4051A–MAX4053A)
1nA at +25°C (MAX4051–MAX4053)
All digital inputs have 0.8V to 2.4V logic thresholds,
ensuring TTL/CMOS-logic compatibility when using
±5V or a single +5V supply.
♦ Single-Supply Operation from +2.0V to +16V
Dual-Supply Operation from ±2.7V to ±8V
♦ TTL/CMOS-Logic Compatible
♦ Low Distortion: < 0.04% (600Ω)
♦ Low Crosstalk: < -90dB (50Ω)
♦ High Off Isolation: < -90dB (50Ω)
________________________Ap p lic a t io n s
Battery-Operated Equipment
Audio and Video Signal Routing
Low-Voltage Data-Acquisition Systems
Communications Circuits
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 QSOP
MAX4051ACPE
MAX4051ACSE
MAX4051ACEE
Ordering Information continued at end of data sheet.
___________________________________P in Co n fig u ra t io n s /Fu n c t io n a l Dia g ra m s
TOP VIEW
MAX4052
MAX4053
MAX4051
NO0B
NO1B
COMB
NO3B
NO2B
INH
NOB
NCB
NOA
COMA
NCA
INH
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
NO1
NO3
COM
NO7
NO5
INH
V-
V+
V+
1
2
3
4
5
6
7
8
16
15
14
13
12
16
15
14
13
12
V+
16
15
14
NO1A
NO2A
COMA
NO0A
COMB
COMC
NOC
NCC
NO2
NO4
13 NO0
12 NO6
11 ADDC
11 NO3A
10 ADDB
11 ADDC
10 ADDB
V-
V-
LOGIC
10
9
ADDB
ADDA
LOGIC
GND
GND
9
9
ADDA
GND
ADDA
DIP/SO/QSOP
DIP/SO/QSOP
DIP/SO/QSOP
________________________________________________________________ Maxim Integrated Products
1
Call toll free 1-800-998-8800, or visit our WWW site at http://www.maxim-ic.com
for free samples or the latest literature.
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
Continuous Power Dissipation (T = +70°C)
A
V+ ........................................................................-0.3V to +17V
V-..........................................................................+0.3V to -17V
V+ to V-................................................................-0.3V to +17V
Voltage into Any Terminal (Note 1) ..........(V- - 2V) to (V+ + 2V)
or 30mA (whichever occurs first)
Plastic DIP (derate 10.53mW/°C above +70°C)............842mW
Narrow SO (derate 8.70mW/°C above +70°C)..............696mW
QSOP (derate 8.00mW/°C above +70°C) .....................640mW
CERDIP (derate 10.00mW/°C above +70°C) ................800mW
Operating Temperature Ranges
Continuous Current into Any Terminal..............................±30mA
Peak Current, NO or COM
(pulsed at 1ms, 10% duty cycle) .................................±100mA
MAX405_C_ E/MAX405_AC_E .............................0°C to +70°C
MAX405_E_ E/MAX405_AE_E...........................-40°C to +85°C
MAX405_MJE/MAX405_AMJE ........................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Note 1: Signals on any terminal exceeding V+ or V- are clamped by internal diodes. Limit forward-diode current to maximum
current rating.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Dual Supplies
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
ANALOG SWITCH
Analog Signal Range
V
, V
C, E, M
= +25°C
V-
V+
V
COM NO
T
60
100
125
A
V+ = 5V, V- = -5V, I
= 1mA,
NO
COM–NO On-Resistance
R
Ω
ON
V
= ±3V
COM
C, E, M
MAX4051A,
T
A
= +25°C
6
MAX4052A,
MAX4053A
COM–NO On-Resistance
Match Between Channels
(Note 3)
V+ = 5V, V- = -5V,
C, E, M
= +25°C
12
12
18
10
15
∆R
I
V
= 1mA,
= ±3V
Ω
Ω
ON
NO
MAX4051,
MAX4052,
MAX4053
T
A
COM
5
C, E, M
V+ = 5V, V- = -5V,
I = 1mA,
NO
MAX4051A,
MAX4052A,
MAX4053A
T
A
= +25°C
COM–NO On-Resistance
Flatness (Note 4)
R
FLAT(ON)
C, E, M
= +25°C
V
COM
= -3V, 0V, 3V
T
-1
0.002
0.002
1
A
V+ = 5.5V, V- = -5.5V,
= 4.5V,
MAX4051,
MAX4052,
MAX4053
V
C, E
M
-10
10
NO
V
COM
= -4.5V
-100
100
0.1
5
NO Off Leakage Current
(Note 5)
I
nA
NO(OFF)
T
A
= +25°C -0.1
V+ = 5.5V, V- = -5.5V,
= -4.5V,
MAX4051A,
MAX4052A, C, E
V
-5
NO
V
COM
= 4.5V
MAX4053A
M
-100
100
2
_______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
T
= +25°C -0.1
0.002
0.002
0.002
0.002
0.002
0.002
0.002
0.002
0.002
0.002
0.002
0.002
0.1
5
A
MAX4051A C, E
M
-5
-100
-1
100
1
T
A
= +25°C
MAX4051
C, E
M
-10
-100
10
100
0.1
2.5
100
1
V+ = 5.5V, V- = -5.5V,
= 4.5V,
V
NO
T
A
= +25°C -0.1
V
COM
= -4.5V
MAX4052A,
MAX4053A
C, E
M
-2.5
-100
-1
T
A
= +25°C
MAX4052,
MAX4053
C, E
M
-5
5
-50
50
0.1
5
COM Off Leakage
Current (Note 5)
I
nA
COM(OFF)
T
A
= +25°C -0.1
MAX4051A C, E
M
-5
-100
-1
100
1
T
A
= +25°C
MAX4051
C, E
M
-10
-100
10
100
0.1
2.5
50
1
V+ = 5.5V, V- = -5.5V,
= -4.5V,
V
NO
T
A
= +25°C -0.1
V
COM
= 4.5V
MAX4052A,
MAX4053A
C, E
M
-2.5
-50
-1
T
A
= +25°C
MAX4052,
MAX4053
C, E
M
-5
5
-50
50
0.1
5
T
A
= +25°C -0.1
MAX4051A C, E
M
-5
-100
-1
100
1
T
A
= +25°C
MAX4051
C, E
M
-10
-100
10
100
0.1
2.5
50
1
COM On Leakage
Current (Note 5)
V+ = 5.5V, V- = -5.5V,
= V = ±4.5V
I
nA
COM(ON)
V
COM
NO
T
A
= +25°C -0.1
MAX4052A,
MAX4053A
C, E
M
-2.5
-50
-1
T
A
= +25°C
MAX4052,
MAX4053
C, E
M
-5
5
-50
50
_______________________________________________________________________________________
3
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
A
MIN
MAX
A
MIN
TYP
(Note 2)
MAX
PARAMETER
DIGITAL I/O
SYMBOL
CONDITIONS
UNITS
ADD, INH Input Logic
Threshold High
V
C, E, M
C, E, M
C, E, M
2.4
V
V
IH
ADD, INH Input Logic
Threshold Low
V
IL
0.8
1
ADD, INH Input Current
Logic High or Low
I
, I
IH IL
V
, V
= V+, 0V
-1
0.03
µA
ADD INH
SWITCH DYNAMIC CHARACTERISTICS
T
= +25°C
50
40
175
225
150
200
250
A
Turn-On Time (Note 6)
Turn-Off Time (Note 6)
t
Figure 3
Figure 3
ns
ns
ON
C, E, M
= +25°C
T
A
t
OFF
C, E, M
Transition Time
t
Figure 2
Figure 4
T
= +25°C
= +25°C
A
75
10
ns
ns
TRANS
A
Break-Before-Make Delay
t
T
2
OPEN
C
= 1nF, R = 0Ω, V = 0V,
S NO
L
Charge Injection (Note 6)
Q
T
A
= +25°C
2
10
pC
Figure 5
NO Off Capacitance
COM Off Capacitance
C
V
= GND, f = 1MHz, Figure 7
T
= +25°C
T = +25°C
A
2
2
pF
pF
NO(OFF)
NO
A
C
V
COM
= GND, f = 1MHz, Figure 7
COM(OFF)
V
= V = GND, f = 1MHz,
NO
COM
Switch On Capacitance
Off Isolation
C
T
= +25°C
= +25°C
= +25°C
8
pF
dB
dB
(ON)
A
Figure 7
C
V
NO
= 15pF, R = 50Ω, f = 100kHz,
L
L
V
T
A
<-90
<-90
ISO
= 1V
, Figure 6
RMS
Channel-to-Channel
Crosstalk
C = 15pF, R = 50Ω, f = 100kHz,
L L
V
NO
V
T
A
CT
= 1V
, Figure 6
RMS
POWER SUPPLY
12,MX4053/A
Power-Supply Range
V+, V-
I+
C, E, M
= +25°C
±2.7
-1
±8
1
V
T
A
0.1
0.1
V+ Supply Current
V- Supply Current
INH = ADD = 0V or V+
INH = ADD = 0V or V+
µA
C, E, M
= +25°C
10
1
T
-1
A
I-
µA
C, E, M
-10
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: ∆R = R - R
.
ON(MIN)
ON
ON(MAX)
Note 4: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges; i.e., V = 3V to 0V and 0V to -3V.
NO
Note 5: Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation at
T
A
= +25°C.
Note 6: Guaranteed by design, not production tested.
4
_______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.5V to +5.5V, V- = 0V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
ANALOG SWITCH
Analog Signal Range
V
, V
C, E, M
= +25°C
V-
V+
225
280
1
V
COM NO
T
A
125
V+ = 5V, I
= 1mA,
NO
COM–NO On-Resistance
R
Ω
ON
V
COM
= 3.5V
C, E, M
= +25°C
T
-1
-10
-100
-1
0.002
A
V+ = 5.5V, V = 4.5V,
NO
C, E
M
10
100
1
V
COM
= 0V
NO Off Leakage Current
(Note 5)
I
nA
nA
nA
NO(OFF)
T
A
= +25°C
0.002
0.002
0.002
0.002
0.002
0.002
0.002
V+ = 5.5V, V = 0V,
NO
C, E
M
-10
-100
-1
10
100
1
V
COM
= 4.5V
T
A
= +25°C
MAX4051/A C, E
M
-10
-100
-1
10
100
1
V+ = 5.5V, V = 4.5V,
NO
V
COM
= 0V
T
A
= +25°C
MAX4052/A,
MAX4053/A
C, E
M
-5
5
-50
-1
50
1
COM Off Leakage
Current (Note 5)
I
COM(OFF)
T
A
= +25°C
MAX4051/A C, E
M
-10
-100
-1
10
100
1
V+ = 5.5V, V = 0V,
NO
V
COM
= 4.5V or 0V
T
A
= +25°C
MAX4052/A,
MAX4053/A
C, E
M
-5
5
-50
-1
50
1
T
A
= +25°C
MAX4051/A C, E
M
-10
-100
-1
10
100
1
COM On Leakage
Current (Note 5)
V+ = 5.5V,
= V = 4.5V
I
COM(ON)
V
COM
NO
T
A
= +25°C
MAX4052/A,
MAX4053/A
C, E
M
-10
-100
10
100
DIGITAL I/O
ADD, INH Input Logic
Threshold High
V
C, E, M
C, E, M
C, E, M
2.4
V
V
IH
ADD, INH Input Logic
Threshold Low
V
IL
0.8
1
ADD, INH Input Current
Logic High or Low
I
I
V
V = V+, 0V
-1
-1
0.03
µA
IH, IL
ADD, INH
POWER SUPPLY
T
A
= +25°C
1
V+ Supply Current
I+
INH = ADD = 0V or V+
µA
C, E, M
10
_______________________________________________________________________________________
5
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.5V to +5.5V, V- = 0V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
SWITCHDYNAMIC CHARACTERISTICS
T
= +25°C
90
60
200
275
125
175
A
Turn-On Time (Note 6)
t
Figure 3
ns
ON
C, E, M
= +25°C
T
A
Turn-Off Time (Note 6)
Break-Before-Make Delay
Charge Injection (Note 6)
t
Figure 3
Figure 4
ns
ns
OFF
C, E, M
t
T
A
= +25°C
30
2
OPEN
C
= 1nF, R = 0Ω, V = 0V,
S NO
L
Q
T
A
= +25°C
10
pC
Figure 5
C
V
NO
= 15pF, R = 50Ω, f = 100kHz,
L
L
Off Isolation
V
T
= +25°C
= +25°C
<-90
<-90
dB
dB
ISO
A
= 1V
, Figure 6
RMS
Channel-to-Channel
Crosstalk
C = 15pF, R = 50Ω, f = 100kHz,
L L
V
NO
V
T
A
CT
= 1V
, Figure 6
RMS
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: ∆R = R - R
.
ON(MIN)
ON
ON(MAX)
Note 4: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges; i.e., V = 3V to 0V and 0V to -3V.
NO
Note 5: Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation at
T
A
= +25°C.
Note 6: Guaranteed by design, not production tested.
12,MX4053/A
6
_______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +3.0V to +3.6V, V- = 0V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
ANALOG SWITCH
Analog Signal Range
V
, V
C, E, M
= +25°C
V-
V+
525
700
1
V
COM NO
T
A
250
I
V
= 1mA, V+ = 3V,
NO
COM–NO On-Resistance
R
Ω
ON
= 1.5V
COM
C, E, M
= +25°C
T
-1
-10
-100
-1
0.002
A
V+ = 3.6V, V = 3V,
V
NO
C, E
M
10
100
1
= 0V
COM
NO Off Leakage Current
(Note 5)
I
nA
nA
nA
NO(OFF)
T
A
= +25°C
0.002
0.002
0.002
0.002
0.002
0.002
0.002
V+ = 3.6V, V = 0V,
V
NO
C, E
M
-10
-100
-1
10
100
1
= 3V
COM
T
A
= +25°C
MAX4051/A C, E
M
-10
-100
-1
10
100
1
V+ = 3.6V, V = 3V,
V
NO
= 0V
COM
T
A
= +25°C
MAX4052/A,
MAX4053/A
C, E
M
-5
5
-50
-1
50
1
COM Off Leakage
Current (Note 5)
I
COM(OFF)
T
A
= +25°C
MAX4051/A C, E
M
-10
-100
-1
10
100
1
V+ = 3.6V, V = 0V,
V
NO
= 3V
COM
T
A
= +25°C
MAX4052/A,
MAX4053/A
C, E
M
-5
5
-50
-1
50
1
T
A
= +25°C
MAX4051/A C, E
M
-10
-100
-1
10
100
1
COM On Leakage
Current (Note 5)
V+ = 3.6V,
= V = 3V
I
COM(ON)
V
COM
NO
T
A
= +25°C
MAX4052/A,
MAX4053/A
C, E
M
-10
-100
10
100
V
DIGITAL I/O
ADD, INH Input Logic
Threshold High
V
C, E, M
C, E, M
C, E, M
2.4
IH
ADD, INH Input Logic
Threshold Low
V
IL
0.8
1
V
ADD, INH Input Current
Logic High or Low
I
I
V
V = V+, 0V
-1
-1
0.03
µA
µA
IH, IL
ADD, INH
POWER SUPPLY
T
A
= +25°C
1
V+ Supply Current
I+
INH = ADD = 0V or V+
C, E, M
10
_______________________________________________________________________________________
7
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +3.0V to +3.6V, V- = 0V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 2)
MAX
PARAMETER
SYMBOL
CONDITIONS
UNITS
SWITCHDYNAMIC CHARACTERISTICS
T
= +25°C
180
100
600
700
300
400
A
Turn-On Time (Note 6)
t
Figure 3
ns
ON
C, E, M
= +25°C
T
A
Turn-Off Time (Note 6)
Break-Before-Make Delay
Charge Injection (Note 6)
t
Figure 3
Figure 4
ns
ns
OFF
C, E, M
t
T
A
= +25°C
90
1
OPEN
C
= 1nF, R = 0Ω, V = 0V,
S NO
L
Q
T
A
= +25°C
10
pC
Figure 5
C
V
NO
= 15pF, R = 50Ω, f = 100kHz,
L
L
Off Isolation
V
T
= +25°C
= +25°C
<-90
<-90
dB
dB
ISO
A
= 1V
, Figure 6
RMS
Channel-to-Channel
Crosstalk
C = 15pF, R = 50Ω, f = 100kHz,
L L
V
NO
V
T
A
CT
= 1V
, Figure 6
RMS
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: ∆R = R - R
.
ON(MIN)
ON
ON(MAX)
Note 4: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges; i.e., V = 3V to 0V and 0V to -3V.
NO
Note 5: Leakage parameters are 100% tested at maximum-rated hot operating temperature, and guaranteed by correlation at
T
A
= +25°C.
Note 6: Guaranteed by design, not production tested.
12,MX4053/A
8
_______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V+ = +5V, V- = -5V, GND = 0V, T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
COM
AND TEMPERATURE
(DUAL SUPPLIES)
ON-RESISTANCE vs. V
COM
ON-RESISTANCE vs. V
COM
(SINGLE SUPPLY)
(DUAL SUPPLIES)
300
275
110
110
V+ = 5V
V- = -5V
V- = 0V
100
90
100
90
250
225
V± = ±3V
T
= +125°C
= +85°C
A
80
70
80
70
200
175
150
125
T
A
V+ = 3V
60
50
60
50
T
A
= +25°C
= -55°C
V± = ±5V
100
75
V+ = 5V
T
A
40
30
40
30
50
-5 -4 -3 -2 -1
0
1
2
3
4
5
0
1
2
3
4
5
-5 -4 -3 -2 -1
0
1
2
3
4
5
V
COM
(V)
V
COM
(V)
V
COM
(V)
ON-RESISTANCE vs. V
COM
AND TEMPERATURE
(SINGLE SUPPLY)
ON-LEAKAGE vs.
TEMPERATURE
OFF-LEAKAGE vs.
TEMPERATURE
1000
100
180
160
10,000
1000
100
V+ = 5.5V
V- = -5.5V
V+ = 5.5V
V- = -5.5V
V+ = 5V
V- = 0V
T
= +125°C
A
140
120
100
80
T
= +85°C
A
T
= +25°C
A
10
1
10
1
T
= -55°C
A
60
40
0.1
0.1
-50 -25
0
25 50
75 100 125
0
1
2
3
(V)
4
5
-50 -25
0
25 50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
V
COM
SUPPLY CURRENT vs.
TEMPERATURE
CHARGE INJECTION vs. V
COM
5
0
10
V+ = 5V
V- = -5V
= V = 0V, 5V
V
EN
A
I+
I-
V+ = 5V
V- = 0V
1
V+ = 5V
V- = -5V
-5
0.1
-5 -4 -3 -2 -1
0
1
2
3
4
5
-50 -25
0
25 50
75 100 125
V
COM
(V)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V+ = +5V, V- = -5V, GND = 0V, T = +25°C, unless otherwise noted.)
A
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
FREQUENCY RESPONSE
5
0
-10
-20
100
10
V± = ±5V
600Ω IN AND OUT
0
-5
INSERTION LOSS
-30
-40
-50
-60
-70
-80
-90
-10
-15
-20
-25
-30
-35
-40
OFF ISOLATION
1
0.1
0.01
ON PHASE
50Ω IN/OUT
0.01
0.1
1
10
100 300
10
100
1k
10k
FREQUENCY (MHz)
FREQUENCY (Hz)
_____________________________________________________________P in De s c rip t io n s
PIN
NAME
FUNCTION
MAX4051/
MAX4051A
MAX4052/
MAX4052A
MAX4053/
MAX4053A
13, 1, 15, 2,
14, 5, 12, 4
—
—
NO0–NO7
Analog Switch Inputs 0–7
Analog Switch Common
3
—
—
—
15
1
COM
NO0B–NO3B
COMB
NOB
—
—
—
—
—
—
1, 2, 5, 4
Analog Switch “B” Inputs 0–3
3
Analog Switch “B” Common
—
—
—
—
Analog Switch “B” Normally Open Input
Analog Switch “B” Normally Closed Input
Analog Switch “A” Normally Open Input
Analog Switch “A” Normally Closed Input
2
NCB
3
NOA
5
NCA
Digital Inhibit Input. Normally connect to GND. Can be driven
to logic high to set all switches off.
6
7
8
6
7
8
6
7
8
INH
V-
12,MX4053/A
Negative Analog Supply Voltage Input. Connect to GND for
single-supply operation.
Ground. Connect to digital ground. (Analog signals have no
ground reference; they are limited to V+ and V-.)
GND
9
9
9
ADDA
ADDB
ADDC
NO0A–NO3A
COMA
NCC
Digital Address “A” Input
10
11
—
—
—
—
—
16
10
10
11
—
4
Digital Address “B” Input
—
Digital Address “C” Input
12, 15, 14, 11
Analog Switch “A” Inputs 0–3
13
—
—
—
16
Analog Switch “A” Common
12
13
14
16
Analog Switch “C” Normally Closed Input
Analog Switch “C” Normally Open Input
Analog Switch “C” Common
NOC
COMC
V+
Positive Analog and Digital Supply Voltage Input
Note: NO, NC, and COM pins are identical and interchangeable. Any may be considered an input or output; signals pass equally
well in both directions.
10 ______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
Table 1. Truth Table/Switch Programming
ADDRESS BITS
ON SWITCHES
INH
1
MAX4051/
MAX4051A
MAX4052/
MAX4052A
MAX4053/
MAX4053A
ADDC*
ADDB
ADDA
X
X
X
All switches open
All switches open
All switches open
COMA–NCA,
COMB–NCB,
COMC–NCC
COMB–NO0B,
COMC–NO0C
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
COM–NO0
COMA–NOA,
COMB–NCB,
COMC–NCC
COMB–NO1B,
COMC–NO1C
0
0
0
0
0
0
COM–NO1
COM–NO2
COM–NO3
COM–NO4
COM–NO5
COM–NO6
COM–NO7
COMA–NCA,
COMB–NOB,
COMC–NCC
COMB–NO2B,
COMC–NO2C
COMA–NOA,
COMB–NOB,
COMC–NCC
COMB–NO3B,
COMC–NO3C
COMA–NCA,
COMB–NCB,
COMC–NOC
COMB–NO0B,
COMC–NO0C
COMA–NOA,
COMB–NCB,
COMC–NOC
COMB–NO1B,
COMC–NO1C
COMA–NCA,
COMB–NOB,
COMC–NOC
COMB–NO2B,
COMC–NO2C
COMA–NOA,
COMB–NOB,
COMC–NOC
COMB–NO3B,
COMC–NO3C
0
X = Don’t care
* ADDC not present on MAX4052.
Note: NO and COM pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well
in either direction.
Virtually all the analog leakage current comes from the
ESD diodes. Although the ESD diodes on a given signal
__________Ap p lic a t io n s In fo rm a t io n
P o w e r-S u p p ly Co n s id e ra t io n s
pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages will vary as the signal varies. The difference in
the two diode leakages to the V+ and V- pins consti-
tutes the analog signal path leakage current. All analog
leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This is
why both sides of a given switch can show leakage cur-
rents of either the same or opposite polarity.
Overview
The MAX4051/MAX4052/MAX4053 a nd MAX4051A/
MAX4052A/MAX4053A construction is typical of most
CMOS analog switches. They have three supply pins:
V+, V-, and GND. V+ and V- are used to drive the inter-
nal CMOS switches and set the limits of the analog volt-
age on any switch. Reverse ESD-protection diodes are
internally connected between each analog signal pin
and both V+ and V-. If any analog signal exceeds V+ or
V-, one of these diodes will conduct. During normal
operation, these (and other) reverse-biased ESD diodes
leak, forming the only current drawn from V+ or V-.
The re is no c onne c tion b e twe e n the a na log s ig na l
paths and GND.
______________________________________________________________________________________ 11
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic lim-
its. The logic-level translators convert the logic levels
into switched V+ and V- signals to drive the gates of
V+
EXTERNAL BLOCKING DIODE
D1
the analog signals. This drive signal is the only connec-
tion between the logic supplies (and signals) and the
a na log s up p lie s . V+ a nd V- ha ve ESD-p rote c tion
diodes to GND.
MAX4051/A
MAX4052/A
MAX4053/A
V+
The logic-level thresholds are TTL/CMOS compatible
when V+ is +5V. As V+ rises, the threshold increases
slightly, so when V+ reaches +12V, the threshold is
about 3.1V; above the TTL-guaranteed high-level mini-
mum of 2.8V, but still compatible with CMOS outputs.
*
*
*
*
COM
NO
V-
Bipolar Supplies
These devices operate with bipolar supplies between
±3.0V and ±8V. The V+ and V- supplies need not be
symmetrical, but their sum cannot exceed the absolute
maximum rating of +17V.
EXTERNAL BLOCKING DIODE
D2
V-
Single Supply
These devices operate from a single supply between
+3V and +16V when V- is connected to GND. All of the
bipolar precautions must be observed. At room temper-
ature, they actually “work” with a single supply at near
or below +1.7V, although as supply voltage decreases,
switch on-resistance and switching times become very
high.
* INTERNAL PROTECTION DIODES
Figure 1. Overvoltage Protection Using External Blocking
Diodes
Hig h -Fre q u e n c y P e rfo rm a n c e
In 50Ω systems, signal response is reasonably flat up
to 50MHz (s e e Typ ic a l Op e ra ting Cha ra c te ris tic s ).
Ab ove 20MHz, the on re s p ons e ha s s e ve ra l minor
peaks which are highly layout dependent. The problem
is not turning the switch on, but turning it off. The off-
state switch acts like a capacitor, and passes higher
frequencies with less attenuation. At 10MHz, off isola-
tion is about -45dB in 50Ω systems, becoming worse
(a p p roxima te ly 20d B p e r d e c a d e ) a s fre q ue nc y
increases. Higher circuit impedances also make off iso-
lation worse. Adjacent channel attenuation is about 3dB
above that of a bare IC socket, and is entirely due to
capacitive coupling.
Ove rvo lt a g e P ro t e c t io n
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
Always sequence V+ on first, then V-, followed by the
log ic inp uts (NO) a nd b y COM. If p owe r-s up p ly
sequencing is not possible, add two small signal diodes
(D1, D2) in series with the supply pins for overvoltage
protection (Figure 1).
12,MX4053/A
Adding diodes reduces the analog signal range to one
diode drop below V+ and one diode drop above V-, but
does not affect the devices’ low switch resistance and
low le a ka g e c ha ra c te ris tic s . De vic e op e ra tion is
unchanged, and the difference between V+ and V-
should not exceed 17V. These protection diodes are
not recommended when using a single supply if signal
levels must extend to ground.
12 ______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
______________________________________________Te s t Circ u it s /Tim in g Dia g ra m s
V+
V+
V+
0V
V
V
ADD
50%
ADD
NO0
ADDC
ADDB
ADDA
V+
V-
NO1–NO6
V
NO0
90%
NO7
MAX4051/A
50Ω
V
OUT
INH
COM
0V
V
GND
90%
V-
V-
OUT
35pF
35pF
35pF
V
NO7
300Ω
t
t
TRANS
TRANS
V+
V+
V+
V
ADD
50%
V
ADD
NO0
NO1–NO2
ADDC
ADDB
V+
V-
0V
V
NO0
90%
MAX4052/A
NO3
50Ω
INH
COM
0V
V
OUT
GND
V
OUT
V-
V-
90%
V
NO3
300Ω
t
t
TRANS
TRANS
V+
V+
V+
V
ADD
V
ADD
50%
NO
ADD
INH
V-
0V
V
NC
MAX4053/A
90%
NC
V+
50Ω
COM
0V
V
OUT
GND
V-
90%
V
OUT
300Ω
V
NO
V-
t
t
TRANS
TRANS
V- = 0V FOR SINGLE-SUPPLY OPERATION.
REPEAT TEST FOR EACH SECTION.
Figure 2. Address Transition Time
______________________________________________________________________________________ 13
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
V+
V+
V+
0V
V
INH
50%
NO0
ADDC
ADDB
ADDA
V+
NO1–NO7
V
NO0
90%
MAX4051/A
V
INH
V
OUT
V
OUT
INH
COM
90%
GND
V-
V-
35pF
0V
300Ω
50Ω
t
t
ON
OFF
V+
V+
V+
0V
50%
V
INH
NO0
NO1–NO3
ADDC
ADDB
V+
V
NO0
90%
MAX4052/A
V
INH
INH
COM
V
OUT
V
OUT
GND
90%
V-
V-
35pF
0V
300Ω
50Ω
t
ON
t
OFF
V+
V+
V+
0V
V
INH
50%
NO
ADD
INH
V+
V-
V
NO_
MAX4053/A
5
NC
90%
V
INH
COM
V
OUT
GND
V-
V-
V
OUT
90%
35pF
300Ω
0V
50Ω
t
t
ON
OFF
V- = 0V FOR SINGLE-SUPPLY OPERATION.
REPEAT TEST FOR EACH SECTION.
Figure 3. Enable Switching Time
14 ______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
V+
V+
V+
V+
V
V
ADD
ADD
NO0–N07
NO0–NO3
ADDC
ADDB
ADDA
ADDC
ADDB
V+
V+
MAX4052/A
MAX4051/A
50Ω
50Ω
V
INH
INH
COM
COM
OUT
V
OUT
GND
GND
V-
V-
V-
V-
35pF
35pF
300Ω
300Ω
V+
V+
t
< 20ns
R
V
V+
0V
ADD
t < 20ns
F
V
50%
ADD
NO, NC
ADD
INH
V+
V
NO_
MAX4053/A
80%
50Ω
COM
V
OUT
GND
V-
V-
35pF
V
OUT
300Ω
0V
V- = 0V FOR SINGLE-SUPPLY OPERATION.
REPEAT TEST FOR EACH SECTION.
t
OPEN
Figure 4. Break-Before-Make Interval
V+
V+
0V
V
INH
V+
NO
ADDC
V
= 0V
CHANNEL
SELECT
NO
ADDB
MAX4051/A
MAX4052/A
MAX4053/A
ADDA
INH
∆ V
OUT
V
OUT
V
INH
V
COM
OUT
GND
V-
V-
C = 1000pF
L
50Ω
∆ V
IS THE MEASURED VOLTAGE DUE TO CHARGE
TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF.
OUT
V- = 0V FOR SINGLE-SUPPLY OPERATION.
REPEAT TEST FOR EACH SECTION.
Q = ∆ V
OUT
X C
L
Figure 5. Charge Injection
______________________________________________________________________________________ 15
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
V+
10nF
NETWORK
ANALYZER
50Ω 50Ω
V
IN
V
OUT
V+
OFF ISOLATION = 20log
V
NO
ADDC
ADDB
ADDA
IN
CHANNEL
SELECT
MAX4051/A
MAX4052/A
MAX4053/A
V
OUT
ON LOSS = 20log
V
IN
V
OUT
MEAS.
REF.
INH
COM
V
OUT
CROSSTALK = 20log
GND
V-
V
IN
50Ω
50Ω
10nF
V-
MEASUREMENTS ARE STANDARDIZED AGAINST SHORT AT SOCKET TERMINALS.
OFF ISOLATION IS MEASURED BETWEEN COM AND "OFF" NO TERMINAL ON EACH SWITCH.
ON LOSS IS MEASURED BETWEEN COM AND "ON" NO TERMINAL ON EACH SWITCH.
CROSSTALK (MAX4052 AND MAX4053) IS MEASURED FROM ONE CHANNEL (A, B, C) TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 6. Off Isolation, On Loss, and Crosstalk
V+
V+
12,MX4053/A
NO
NO
ADDC
CHANNEL
SELECT
ADDB
ADDA
MAX4051/A
MAX4052/A
MAX4053/A
1MHz
INH
COM
CAPACITANCE
ANALYZER
GND
V-
V-
Figure 7. NO/COM Capacitance
16 ______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
___________________________________________Ord e rin g In fo rm a t io n (c o n t in u e d )
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 QSOP
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 Narrow SO
16 QSOP
MAX4051AEPE
MAX4051AESE
MAX4051AEEE
MAX4051AMJE
MAX4051CPE
MAX4051CSE
MAX4051CEE
MAX4051C/D
MAX4051EPE
MAX4051ESE
MAX4051EEE
MAX4051MJE
MAX4052ACPE
MAX4052ACSE
MAX4052ACEE
MAX4052AEPE
MAX4052AESE
MAX4052AEEE
MAX4052AMJE
MAX4052CPE
MAX4052CSE
MAX4052CEE
MAX4052C/D
MAX4052EPE
MAX4052ESE
MAX4052EEE
MAX4052MJE
MAX4053ACPE
MAX4053ACSE
MAX4053ACEE
MAX4053AEPE
MAX4053AESE
MAX4053AEEE
MAX4053AMJE
MAX4053CPE
MAX4053CSE
MAX4053CEE
MAX4053C/D
MAX4053EPE
MAX4053ESE
MAX4053EEE
MAX4053MJE
0°C to +70°C
0°C to +70°C
16 CERDIP**
16 Plastic DIP
16 Narrow SO
16 QSOP
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
16 Plastic DIP
16 Narrow SO
16 QSOP
0°C to +70°C
16 CERDIP**
16 Plastic DIP
16 Narrow SO
16 QSOP
0°C to +70°C
0°C to +70°C
Dice*
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
16 Plastic DIP
16 Narrow SO
16 QSOP
0°C to +70°C
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 Narrow SO
16 QSOP
16 CERDIP**
16 Plastic DIP
16 Narrow SO
16 QSOP
0°C to +70°C
16 CERDIP**
0°C to +70°C
* Contact factory for dice specifications.
** Contact factory for availability.
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
0°C to +70°C
16 Plastic DIP
16 Narrow SO
16 QSOP
16 CERDIP**
16 Plastic DIP
16 Narrow SO
16 QSOP
___________________Ch ip To p o g ra p h y
MAX4051/A
0°C to +70°C
0°C to +70°C
NO6
NO4 V+
0°C to +70°C
Dice*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 Narrow SO
16 QSOP
NO2
16 CERDIP**
COM
NO7
NO1
N. C.
NO0
N. C.
0. 108"
(2. 74mm)
NO5
INH
NO3
ADDA
V-
ADDC
GND
ADDB
0. 080"
(2. 03mm)
N. C. = NO CONNECT
TRANSISTOR COUNT: 161
SUBSTRATE CONNECTED TO V+.
______________________________________________________________________________________ 17
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
_____________________________________________Ch ip To p o g ra p h ie s (c o n t in u e d )
MAX4052/A
MAX4053/A
NO2C
NO0C V+
NCB
NOB V+
NO2B
COMB
COMC
NO3C
N. C.
NOC
NO1B
COMB
NO0B
N. C.
COMA
NOA
N. C.
COMC
0. 108"
(2. 74mm)
0. 108"
(2. 74mm)
NO1C
INH
NCC
INH
NO3B
NCA
ADDB
ADDA
V-
N. C.
V-
ADDC
GND ADDB
GND
ADDC
0. 080"
0. 080"
(2. 03mm)
(2. 03mm)
N. C. = NO CONNECT
N. C. = NO CONNECT
TRANSISTOR COUNT: 161
SUBSTRATE CONNECTED TO V+.
TRANSISTOR COUNT: 161
SUBSTRATE CONNECTED TO V+.
12,MX4053/A
18 ______________________________________________________________________________________
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
12,MX4053/A
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
E
MIN
MAX
0.200
–
MIN
–
MAX
5.08
–
A
–
E1
D
A1 0.015
A2 0.125
A3 0.055
0.38
3.18
1.40
0.41
1.14
0.20
0.13
7.62
6.10
2.54
7.62
–
0.175
0.080
0.022
0.065
0.012
0.080
0.325
0.310
–
4.45
2.03
0.56
1.65
0.30
2.03
8.26
7.87
–
A3
A2
A1
A
L
B
0.016
B1 0.045
0.008
D1 0.005
0.300
E1 0.240
0.100
eA 0.300
C
0° - 15°
E
C
e
e
B1
eA
eB
–
–
B
eB
L
–
0.400
0.150
10.16
3.81
0.115
2.92
D1
INCHES
MILLIMETERS
PKG. DIM
PINS
Plastic DIP
PLASTIC
DUAL-IN-LINE
PACKAGE
(0.300 in.)
MIN
MAX MIN
MAX
8
P
P
P
P
P
N
D
D
D
D
D
D
0.348 0.390 8.84
9.91
14
16
18
20
24
0.735 0.765 18.67 19.43
0.745 0.765 18.92 19.43
0.885 0.915 22.48 23.24
1.015 1.045 25.78 26.54
1.14 1.265 28.96 32.13
21-0043A
INCHES
MILLIMETERS
DIM
MIN
0.053
MAX
0.069
0.010
0.019
0.010
0.157
MIN
1.35
0.10
0.35
0.19
3.80
MAX
1.75
0.25
0.49
0.25
4.00
A
D
A1 0.004
B
C
E
e
0.014
0.007
0.150
0°-8°
A
0.101mm
0.004in.
0.050
1.27
e
H
L
0.228
0.016
0.244
0.050
5.80
0.40
6.20
1.27
A1
C
B
L
INCHES
MILLIMETERS
DIM PINS
Narrow SO
SMALL-OUTLINE
PACKAGE
MIN MAX
MIN
MAX
5.00
8.75
8
0.189 0.197 4.80
D
D
D
E
H
14 0.337 0.344 8.55
16 0.386 0.394 9.80 10.00
21-0041A
(0.150 in.)
______________________________________________________________________________________ 19
Lo w -Vo lt a g e , CMOS An a lo g
Mu lt ip le x e rs /S w it c h e s
_________________________________________P a c k a g in g In fo rm a t io n (c o n t in u e d )
INCHES
MILLIMETERS
INCHES
MILLIMETERS
DIM
DIM PINS
MIN
0.061
MAX
MIN
MAX
1.73
0.25
1.55
0.31
0.25
MIN MAX MIN
MAX
4.98
0.18
8.74
1.40
8.74
0.76
9.98
A
0.068
1.55
16 0.189 0.196 4.80
16 0.0020 0.0070 0.05
20 0.337 0.344 8.56
20 0.0500 0.0550 1.27
24 0.337 0.344 8.56
24 0.0250 0.0300 0.64
28 0.386 0.393 9.80
28 0.0250 0.0300 0.64
D
S
D
S
D
S
D
S
D
A1 0.004 0.0098 0.127
A2 0.055
0.061
0.012
1.40
0.20
0.19
B
C
D
E
e
0.008
A
0.0075 0.0098
SEE VARIATIONS
e
0.150
0.157
3.81
3.99
A1
B
0.25 BSC
0.635 BSC
0.76
21-0055A
H
h
0.230
0.010
0.016
0.244
0.016
0.035
5.84
0.25
0.41
6.20
0.41
0.89
S
L
N
S
α
SEE VARIATIONS
SEE VARIATIONS
0°
8°
0°
8°
E
H
QSOP
QUARTER
SMALL-OUTLINE
PACKAGE
h x 45°
α
A2
N
E
L
C
12,MX4053/A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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