MAX41464 [MAXIM]
300MHzâ960MHz ASK Transmitter with I2C Interface;
| 型号： | MAX41464 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 300MHzâ960MHz ASK Transmitter with I2C Interface |
| 文件： | 总39页 (文件大小：614K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
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MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
General Description
Benefits and Features
The MAX41461/MAX41462 is a UHF sub-GHz ISM/SRD
transmitter is designed to transmit On-Off Keying (OOK)
or Amplitude-Shift Keying (ASK) data in the 286MHz to
960MHz frequency range. It integrates a fractional phase-
locked-loop (PLL), so a single, low-cost crystal can be
used to generate commonly used world-wide sub-GHz
frequencies. The fast response time of the PLL allows
for frequency-hopping spread spectrum protocols for in-
creased range and security. The chip also features pre-
set modes with pin-selectable frequencies so that only
one wire is required for external microcontroller interface.
The only frequency-dependent components required are
for the external antenna matching network. Optionally,
the device can be put into programmable mode and
● Low Implementation Cost
• Bits-to-RF Single Wire Operation
• Low Bill-of-Materials (BOM)
• Uses Single, Low-Cost, 16MHz Crystal
• Small 3mm x 3mm µMAX-10 Package
● Increased Range, Data Rates, and Security
• Up to +16dBm PA Output Power
• Fast Frequency Switching for FHSS/DSSS
• Fast-On Oscillator: < 250μs Startup Time
• Up to 200kbps NRZ Data Rate
● Extend Battery Life with Low Supply Current
• < 8mA ASK Manchester Coded
• Selectable Standby and Shutdown Modes
• Auto Shutdown at < 20nA (typ) Current
2
programmed using an I C interface. The crystal-based
● Ease of Use
architecture
of
the MAX41461/MAX41462 elimi-
• Pin Selectable 300MHz–928MHz Frequencies
• Pin Compatible ASK and FSK Versions
• +1.8V to +3.6V Single-Supply Operation
• Fully Programmable with 400kHz/1MHz
nates many of the common problems with SAW-
based transmitters by providing greater modulation
depth, faster frequency settling, higher tolerance of the
transmit frequency, and reduced temperature depen-
dence. A clock-out signal at 800kHz is also provided.
2
I C Interface
The MAX41461/MAX41462 provides output power up to
+13dBm into a 50Ω load while drawing < 8mA (Manches-
ter coded). The output load can be adjusted to increase
power up to +16dBm, and a PA boost mode can be en-
abled at frequencies above 850MHz to compensate for
losses. The PA output power can also be controlled us-
Ordering Information appears at end of data sheet.
Simplified Block Diagram
DATA
/SDA
PA
VDD
GND
CONTROL
2
ing programmable register settings in I C mode.
DATA
ACTIVITY
DETECTOR
The MAX41461/MAX41462 also features single-supply
operation from +1.8V to +3.6V. The device has an auto-
shutdown feature to extend battery life and a fast oscillator
wake-up with data activity detection.
PAOUT
PAGND
SEL[1:0]
PA
LOCK DETECT
FRAC-N
PLL
The MAX41461/MAX41462 is available in a 10-pin
µMAX package and is specified over the -40°C to +105°C
extended temperature range. The MAX41461/MAX41462
has an ESD rating of 2.5kV HBM.
XTAL1
XTAL2
CRYSTAL
OSCILLATOR
CLKOUT
/SCL
/16
Applications
● Building Automation and Security
● Wireless Sensors and Alarms
● Remote and Passive Keyless Entry (RKE/PKE)
● Tire Pressure Monitoring Systems (TPMS)
● Automatic Meter Reading (AMR)
● Garage Door Openers (GDO)
● Radio Control Toys
● Internet of Things (IoT)
19-100419; Rev 1; 3/19
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Absolute Maximum Ratings
V
DD
to GND.............................................................. -0.3V to +4V
Junction Temperature.......................................................+150°C
All Others Pins to GND...............................-0.3V to (V
+ 0.3)V
Storage Temperature Range ..............................-60°C to +150°C
Lead Temperature (reflow) ...............................................+300°C
Soldering Temperature (reflow) ........................................+260°C
DD
Continuous Power Dissipation (T = +70°C, derate 5.6mW/°C
A
above +70°C) ................................................................ 444.4mW
Operating Temperature Range .......................... -40°C to +105°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.
Package Information
10 µMAX (similar to 10 TSSOP)
Package Code
U10+2
Outline Number
21-0061
90-0330
Land Pattern Number
Thermal Resistance, Single-Layer Board:
Junction-to-Ambient (θ
)
180°C/W
36°C/W
JA
Junction-to-Case Thermal Resistance (θ
)
JC
Thermal Resistance, Four-Layer Board:
Junction-to-Ambient (θ
)
JA
113.1°C/W
36°C/W
Junction-to-Case Thermal Resistance (θ
)
JC
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different
suffix character, but the drawing pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a
four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/
thermal-tutorial.
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Maxim Integrated | 2
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Electrical Characteristics
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V
= +1.8V to +3.6V, T = -40°C to +105°C, P
OUT
=
DD
A
+13dBm for 300MHz–450MHz or +11dBm for 863MHz–928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V
DD
= +3V, T = +25°C, unless otherwise noted. (Note 1))
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC CHARACTERISTICS
V
DATA
at 50% duty
cycle (ASK) (Note
f
= 315MHz
7
12
RF
3, Note 4)
f
f
= 434MHz
8
12
19
RF
RF
= 863MHz–
10
928MHz
f
= 315MHz,
RF
P
= 16dBm
24
26
OUT
(Note 5)
V
DATA
at 50% duty
f
= 434MHz,
=
cycle (ASK) (Note
3, Note 4)
RF
P
OUT
16dBm (Note 5)
f
= 863MHz–
RF
928MHz, P
16dBm,
PA_BOOST =
1 (Note 5)
=
OUT
45
Operating Current
I
mA
DD
f
f
f
= 315MHz
= 434MHz
=
9.5
RF
RF
RF
V
at 50% duty
DATA
cycle (ASK), Low
Phase Noise mode
(Note 3, Note 4)
10.5
12.8
863MHz–928MHz
f
f
f
= 315MHz
= 434MHz
=
2
2
3
3
RF
RF
RF
PA off (Note 2)
3
4
863MHz–928MHz
f
f
f
= 315MHz
= 434MHz
=
4
4
RF
RF
RF
PA off, Low Phase
Noise mode (Note
2)
5
863MHz–928MHz
PA_BOOST = 0
PA_BOOST = 1
1.8
1.8
3
3.6
3.0
Supply Voltage
V
V
DD
2.7
200
250
19
T
A
T
A
T
A
= 25°C
= 105°C
= 25°C
500
Crystal oscillator
on, everything off.
Standby Current
I
μA
nA
STDBY
Shutdown Current
I
Everything off
100
SHDN
MODULATION PARAMETERS
Supply current and output power are
greatly dependent on board layout and
PAOUT match
ASK Modulation Depth
70
dB
Maximum NRZ Data
Rate
200
kbps
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Maxim Integrated | 3
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Electrical Characteristics (continued)
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V
= +1.8V to +3.6V, T = -40°C to +105°C, P
OUT
=
DD
A
+13dBm for 300MHz–450MHz or +11dBm for 863MHz–928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V
DD
= +3V, T = +25°C, unless otherwise noted. (Note 1))
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER AMPLIFIER
f
f
f
f
= 300MHz–450MHz (Note 4)
13
17
11
RF
RF
RF
RF
= 300MHz–450MHz (Note 4, Note 5)
= 863MHz–928MHz (Note 4)
Output Power
P
OUT
dBm
dBc
= 863MHz–928MHz (Note 4, Note 5),
16
PA_BOOST = 1
PA_BOOST = 0. Supply current, output
power, and harmonics are dependent on
board layout and PAOUT match.
Maximum Carrier
Harmonics
-24
PLL
Low Current mode (default)
286
286.7
425
960
320
480
960
Low Phase Noise mode, LODIV = DIV12
Low Phase Noise mode, LODIV = DIV8
Low Phase Noise mode, LODIV = DIV4
Frequency Range
MHz
860
f
= 315MHz, Low
f
f
f
f
= 200kHz
= 1MHz
-82
-90
-80
-90
RF
OFFSET
OFFSET
OFFSET
OFFSET
Current mode
(default)
f
= 434MHz,
= 200kHz
= 1MHz
RF
PLL Phase Noise
dBc/Hz
Low Current mode
(default)
f
= 915MHz, Low OFFSET
= 200KHz
= 1MHz
-82
-104
4
f
RF
Phase Noise mode
f
OFFSET
LO Divider Settings
8
12
f
/
Minimum Synthesizer
Frequency Step
XTAL
Hz
16
2
f
f
f
f
= 315MHz
= 434MHz
= 868MHz
= 915MHz
f
f
f
f
± f
± f
± f
± f
-67
-60
-57
-56
RF
RF
RF
RF
RF
RF
RF
RF
XTAL
XTAL
XTAL
XTAL
Reference Spur
dBc
Reference Frequency
Input Level
500
mV
P-P
26MHz frequency step, 902MHz to
928MHz band, time from end of register
write to frequency settled to within 5kHz
of desired carrier
Frequency Switching
Time
50
μs
Loop Bandwidth
LBW
300
kHz
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Maxim Integrated | 4
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Electrical Characteristics (continued)
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V
= +1.8V to +3.6V, T = -40°C to +105°C, P
OUT
=
DD
A
+13dBm for 300MHz–450MHz or +11dBm for 863MHz–928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V
DD
= +3V, T = +25°C, unless otherwise noted. (Note 1))
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LO Frequency Divider
Range
N
11
72
f
f
= 315MHz
= 915MHz
30
90
RF
Turn-On Time of PLL
t
μs
PLL
RF
CRYSTAL OSCILLATOR
Crystal Frequency
f
Recommended value (Note 3)
12.8
16
19.2
MHz
μs
XTAL
Crystal Oscillator
Startup Time
t
See Preset Mode Transmission section
243
XO
Frequency Pulling by
3
ppm/V
pF
V
DD
Crystal Input
Capacitance
Internal capacitance of XTAL1 and
XTAL2 pins to ground
C
12
X
CMOS INPUT/OUTPUT
V
SCL/SDA
1.8V compatible
1.8V compatible
0.36
V
V
IL
Input Low Voltage
0.1 x
V
SEL0/SEL1
SCL/SDA
IL_SEL
V
DD3
V
IH
1.44
Input High Voltage
0.9 x
V
SEL0/SEL1
IH_SEL
V
DD3
Input Current
I /I
±10
μA
V
IL IH
Output Low Voltage
V
OL
I
I
= 650μA
0.25
SINK
V
DD
-
Output High Voltage
V
OH
= 350μA
V
SOURCE
0.25
Maximum Capacitance
at SEL0/SEL1 Pins
C
10
10
pF
L_SEL
Maximum Load
Capacitance at
CLKOUT/SDO Pin
C
pF
LOAD
SERIAL INTERFACE (FIGURE 1)
SCL Clock Frequency
f
400
500
1000
kHz
ns
SCL
Bus Free Time Between
STOP and START
Conditions
t
BUF
Hold Time (Repeated)
START Condition
t
260
ns
HD:STA
Low Period of SCL
High Period of SCL
t
500
260
0
ns
ns
LOW
t
HIGH
Receive
Transmit
150
Data Hold Time
Data Setup Time
t
ns
ns
HD:DAT
0
t
50
SU:DAT
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Maxim Integrated | 5
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Electrical Characteristics (continued)
(Typical Application Circuit, all RF inputs and outputs are referenced to 50Ω, V
= +1.8V to +3.6V, T = -40°C to +105°C, P
OUT
=
DD
A
+13dBm for 300MHz–450MHz or +11dBm for 863MHz–928MHz, PA_BOOST = 0, unless otherwise noted. Typical values are at V
DD
= +3V, T = +25°C, unless otherwise noted. (Note 1))
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Start Setup Time
t
260
ns
ns
SU:STA
SDA and SCL Rise
Time
t
R
120
120
20 x
SDA and SCL Fall Time
t
ns
F
V
/5.5
IO
Stop Setup Time
t
260
ns
ns
SU:STO
Noise Spike Reject
t
25
SP
Note 1: Supply current, output power and efficiency are greatly dependent on board layout and PA output match.
Note 2: 100% tested at T = +25°C. Limits over operating temperature and relevant supply voltage are guaranteed by design and
A
characterization over temperature.
Note 3: Guaranteed by design and characterization. Not production tested.
Note 4: Typical values are average, peak power is 3dB higher.
Note 5: Using high output power match, see Table 3.
SDA
t
BUF
t
HD:STA
t
t
F
SP
t
LOW
SCL
t
SU:STA
t
t
HD:STA
HIGH
t
R
t
SU:STO
t
t
HD:DAT
SU:DAT
REPEATED
START
STOP
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH (MIN)
IL (MAX)
Figure 1. Serial Interface Timing Diagram
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Maxim Integrated | 6
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Typical Operating Characteristics
(Typical Application Circuit, RF output terminated to 50Ω. Typical values are at V
= +3V, T = +25°C, unless otherwise noted.)
A
DD
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Maxim Integrated | 7
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Typical Operating Characteristics (continued)
(Typical Application Circuit, RF output terminated to 50Ω. Typical values are at V
= +3V, T = +25°C, unless otherwise noted.)
A
DD
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Maxim Integrated | 8
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Pin Configurations
10 µMAX
TOP VIEW
MAX41460
XTAL2
GND
1
2
3
4
5
10 XTAL1
CSB/
9
PDNB
8
7
6
SCLK
V
DD
DATA
/SDI
GND_PA
PA
CLKOUT
/SDO
10 µMAX
TOP VIEW
MAX41461–MAX41464
XTAL2
GND
1
2
3
4
5
10 XTAL1
9
8
7
6
SEL1
SEL0
V
DD
DATA
/SDA
GND_PA
PA
CLKOUT
/SCL
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Maxim Integrated | 9
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Pin Description
PIN
MAX4146
1–MAX41
464
NAME
FUNCTION
MAX4146
0
XTAL2
GND
XTAL2
GND
1
2
3
4
Second Crystal Input. See Crystal Oscillator section.
Ground. Connect to system ground.
V
V
Supply Voltage. Bypass to GND with a 100nF capacitor as close to the pin as possible.
Ground for the Power Amplifier (PA). Connect to system ground.
DD
DD
GND_PA
GND_PA
Power-Amplifier Output. The PA output requires a pullup inductor to the supply voltage,
which can be part of the output-matching network to an antenna.
PA
PA
5
MAX41460: Buffered Clock Output or SPI Data Output.
CLKOUT/
SDO
CLKOUT/
SCL
2
6
MAX41461–MAX41464: Buffered Clock Output. I C clock input for register programming
when in Serial Interface Mode (SEL0 and SEL1 are unconnected or HIZ). The frequency of
CLKOUT is 800kHz when not in Program mode.
MAX41460: Data Input. SPI bus serial data input for register programming when CSB is at
logic-low.
DATA/
SDA
2
DATA/SDI
7
8
MAX41461–MAX41464: Data Input. I C serial data input for register programming when in
Serial Interface mode (SEL0 and SEL1 are unconnected or HIZ). When not in Program
mode, DATA also controls the power-up state (see the Auto-Shutdown in Preset Mode
section in the appropriate data sheet).
MAX41460: SPI Bus Serial Clock Input.
SCLK
SEL0
MAX41461–MAX41464: Three-state Mode Input. See Preset Modes section in the
appropriate data sheet for details. For three-state input open, the impedance on the pin
must be greater than 1MΩ.
MAX41460: SPI Bus Chip Enable. Active Low.
CSB
SEL1
9
MAX41461–MAX41464: Three-state Mode Input. See Preset Modes section in the
appropriate data sheet for details. For three-state input open, the impedance on the pin
must be greater than 1MΩ.
XTAL1
XTAL1
10
First Crystal Input. See Crystal Oscillator section.
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Maxim Integrated | 10
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Detailed Description
The MAX41461/MAX41462 is part of the MAX4146x family of UHF sub-GHz ISM/SRD transmitters designed to
transmit ASK data in the 286MHz to 960MHz frequency range. The MAX4146x family is available in the following
versions.
Table 1. MAX4146x Versions
VERSION
MODULATION AND INTERFACE
PRESET FREQUENCIES (MHz)
No presets, programmable through SPI
MAX41460
MAX41461
MAX41462
MAX41463
MAX41464
ASK/FSK with SPI
2
ASK (optional I C)
315/318/319.51/345/433.42/433.92/908/915
315/433/433.92/434/868/868.3/868.35/868.5
315/433.42/433.92/908/908.42/908.8/915/916
315/433.92/868.3/868.35/868.42/868.5/868.95/869.85
2
ASK (optional I C)
2
FSK (optional I C)
2
FSK (optional I C)
2
The MAX41460 uses an SPI programming interface. The MAX41461–MAX41464 feature an I C interface, as well
as preset modes (pin-selectable output frequencies using only one crystal frequency). No programming is required
in preset modes and only a single-input data interface to an external microcontroller is needed. The MAX41461/
2
MAX41462 parts are identical when put in I C programming mode. All MAX4146x versions are fully programmable for
all output frequencies, as described in the Electrical Characteristics table. The only frequency-dependent components
required are for the the external antenna match.
The crystal-based architecture of the MAX41461/MAX41462 provides greater modulation depth, faster frequency
settling, higher tolerance of the transmit frequency, and reduced temperature dependence. It integrates a fractional
phase-locked-loop (PLL); so a single, low-cost crystal can be used to generate commonly used world-wide sub-GHz
frequencies. A buffered clock-out signal make the device compatible with almost any microcontroller or code-hopping
generator.
The MAX41461/MAX41462 provides +13dBm output power into a 50Ω load at 315MHz using an integrated high
efficiency power amplifier (PA). The output load can be adjusted to increase power up to +16dBm and a PA boost
mode can be enabled at frequencies above 850MHz to compensate for losses. The PA output power can also be
controlled using programmable register settings. The MAX41461/MAX41462 feature fast oscillator wake-up upon data
activity detection and has an auto-shutdown feature to extend battery life.
The MAX41461/MAX41462 operates at a supply voltage of +1.8V to +3.6V and is available in a 10-pin µMAX
package that is specified over the -40°C to +105°C extended temperature range.
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Maxim Integrated | 11
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Preset Modes
The MAX41461/MAX41462 contain preset settings depending on the state of pins SEL1 and SEL0. All presets must use
a 16MHz crystal. The frequency of the CLKOUT pin is always 800kHz.
Table 2. Programming and Preset Modes
SEL1 STATE
Ground
Ground
Ground
Open
SEL0 STATE
Ground
MAX41461
MAX41462
2
2
I C Mode
I C Mode
Open
315
318
315
433.92
433
V
DD
Ground
Open
319.51
345
Open
434
Open
V
908
868.3
868
DD
V
DD
V
DD
V
DD
Ground
Open
915
433.92
433.42
868.5
868.35
V
DD
Preset Mode Transmission
The wake-up of the device is as follows:
1) The microcontroller sends a wake-up pulse on DATA. The duration of the wake-up pulse should be longer than
+ t
t
.
PLL
XO
2) After the falling edge of wake-up pulse, the microcontroller should wait for at least t time and start data transmission.
TX
In preset mode, t = 10μs.
TX
3) CLKOUT is generated 80μs after internal 3.2MHz clock is available.
> (t + t
XO PLL
)
> t
TX
WAKEUP PULSE
TRANSMITTING
DATA
t
XO
OSCILLATING
3.2 MHz
CLOCK
80µs
OSCILLATING
CLKOUT
Figure 2. Wake-Up Timing Diagram for Preset Mode
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Maxim Integrated | 12
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Auto-Shutdown in Preset Mode
The MAX41461/MAX41462 in preset mode has an automatic shutdown feature that places the device in low-power
14
shutdown mode if the DATA input stays at logic 0 for a wait time equal to 2 cycles of the internal 3.2MHz clock. This
equates to a wait time of approximately 5.1ms.
When the device is in automatic shutdown, a pulse on DATA initiates the warm up of the crystal and PLL. See
Startup section for requirements on the wake-up pulse.
When the device is operating, each occurrence of logic 1 on the data line resets an internal counter to zero and it begins
to count again. If the counter reaches the end-of-count, the device enters shutdown mode.
Power Amplifier
The MAX41461/MAX41462 PA is a high-efficiency, open-drain switching-mode amplifier. In a switching-mode amplifier,
the gate of the final-stage FET is driven with a 25% duty-cycle square wave at the transmit frequency. The PA also has
an internal set of capacitors that can be switched in and out to present different capacitance values at the PA output using
the PACAP[4:0] register values. This allows extra flexibility for tuning the output matching network. When the matching
network is tuned correctly, the output FET resonates the attached tank circuit (pullup inductor from PA to V ) with
DD
a minimum amount of power dissipated in the FET. With a proper output-matching network, the PA can drive a wide
range of antenna impedances, which include a PCB trace antenna or a 50Ω antenna. The output-matching π-network
suppresses the carrier harmonics and transforms the antenna impedance to an optimal impedance at the PA pin. The
Typical Application Circuit can deliver an output power of +13dBm with a +3.0V supply. Table 3 has approximate PA load
impedances for desired output powers.
The PAPWR bits in the PA1 register control the output power of the PA. This setting adjust the number of parallel drivers
used, which determine the final output power (see Figure 3).
PA
LODRV[7]
5
PACAP[4:0]
LODRV[2]
FREQUENCY
SYNTHESIZER
DUTY CYCLE
GENERATOR
+
PA_BOOST
PAPWR[2:0]
3
LODRV[1]
LODRV[0]
PAPWR[2:0] IS ON REGISTER PA1 (ADDRESS 0x06).
PACAP[4:0] IS ON REGISTER PA2 (ADDRESS 0x07).
Figure 3. Power Amplifier
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Maxim Integrated | 13
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Boost Mode
The PA can deliver up to 16dBm of output power.
High output power can be achieved in two ways:
● Lower the load impedance for the PA by adjusting the output matching network,
● For frequencies over 850MHz, change the duty cycle of the square wave driving the PA from 25% to 50% by setting
PA_BOOST = 1 in register SHDN (0x05) and adjusting the output matching network.
Note that, when using PA_BOOST = 1, the maximum supply voltage should not exceed 3V. For frequencies under
850MHz, the PA_BOOST bit should remain at 0, the output match can be adjusted to provide higher output power.
Table 3. PA Load Impedance for Desired Output Power
FREQUENCY (MHz)
OUTPUT POWER (dBm)
PA LOAD IMPEDANCE (Ω)
315
13
165
16
315
45
(PA_BOOST = 0)
434
434
13
180
57
16
(PA_BOOST = 0)
863–928
863–928
11
190
34
16
(PA_BOOST = 1)
Refer to the MAX4146x EV Kit User's Guide for details.
Programmable Output Capacitance
The MAX41461/MAX41462 has an internal set of capacitors that can be switched in and out to present different capacitor
values at the PA output. The capacitors are connected from the PA output to ground. This allows changing the tuning
network along with the synthesizer divide ratio each time the transmitted frequency changes, making it possible to
maintain maximum transmitter power while moving rapidly from one frequency to another.
The variable capacitor is programmed through register PA2 (0x07) bits 4:0 (PACAP). The tuning capacitor has a nominal
resolution of 0.18pF, from 0pF to 5.4pF. In preset mode, the variable capacitor is set to 0pF.
Transmitter Power Control
The transmitter power of the MAX41461/MAX41462 can be set in approximately 2.5dB steps by setting PAPWR[2:0]
2
register bits using the I C interface. The transmitted power (and the transmitter current) can be lowered by increasing the
load impedance on the PA. Conversely, the transmitted power can be increased by lowering the load impedance.
Preset Mode Output Power
The output power of the PA in Preset mode (where both SEL0 and SEL1 pins are not connected to GND) is always set for
maximum power level (PAPWR[2:0] = 0x7) for a given load impedance. In order to adjust output power levels in preset
mode, the load impedance must be adjusted accordingly.
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Maxim Integrated | 14
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Crystal (XTAL) Oscillator
The XTAL oscillator in the MAX41461/MAX41462 is designed to present a capacitance of approximately 12pF from the
XTAL1 and XTAL2 pins to ground. In most cases, this corresponds to a 6pF load capacitance applied to the external
crystal when typical PCB parasitics are included. It is very important to use a crystal with a load capacitance equal to the
capacitance of the MAX41461/MAX41462 crystal oscillator plus PCB parasitics. If a crystal designed to oscillate with a
different load capacitance is used, the crystal is pulled away from its stated operating frequency introducing an error in
the reference frequency. The crystal’s natural frequency is typically below its specified frequency. However, when loaded
with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already
accounted for in the specification of the load capacitance. Accounting for typical board parasitics, a 16MHz, 12pF crystal
is recommended. Please note that adding discrete capacitance on the crystal also increases the startup time and adding
too much capacitance could prevent oscillation altogether.
Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given
by:
C
M
1
+ C
1
+ C
6
f
=
−
× 10
P
2
C
C
(
)
CASE
LOAD
CASE
SPEC
where:
f is the amount the crystal frequency pulled in ppm.
P
C
C
C
C
is the motional capacitance of the crystal.
M
is the case capacitance.
CASE
SPEC
LOAD
is the specified load capacitance.
is the load capacitance.
When the crystal is loaded as specified (i.e., C
= C
), the frequency pulling equals zero. For additional details
SPEC
LOAD
on crystal pulling and load capacitance affects, refer to Maxim Tutorial 5422 – Crystal Calculations for ISM RF Products.
Turn-On Time of Crystal Oscillator
The turn-on time of crystal oscillator (XO), t , is defined as elapsed time from the instant of turning on XO circuit to the
XO
first rising edge of XO divider clock output. The external microcontroller turns on the XO by,
1. Sending a wakeup pulse for MAX41461–MAX41464 in the preset mode, or
2
2
2. Writing to device I C address for MAX41461–MAX41464 in the I C mode, or
3. Pulling CSB pin low on the MAX41460.
Crystal Divider
The recommended crystal frequencies are 13.0MHz, 16.0MHz, and 19.2MHz. An internal clock of
3.2MHz±0.1MHz frequency is required. To maintain the internal 3.2MHz time base, XOCLKDIV[1:0] (register CFG1,
0x00, bit 4) must be programmed, based on the crystal frequency, as shown in Table 4.
Table 4. Required Crystal Divider Programming
CRYSTAL FREQUENCY (MHz)
Crystal Divider Ratio
XOCLKDIV[1:0]
13.0
16.0
19.2
4
5
6
00
01
10
Crystal Frequency in Preset Mode
For MAX41461/MAX41462 in preset mode (where both SEL0 and SEL1 pins are not connected to GND), crystal
frequency must be 16MHz to ensure accurate output frequency.
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Maxim Integrated | 15
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Phase-Locked Loop (PLL)
The MAX41461/MAX41462 utilizes a fully integrated fractional-N PLL for its frequency synthesizer. All PLL components,
including loop filter, are included on-chip. The synthesizer has a 16-bit fractional-N topology with a divide ratio that can
be set from 11 to 72, allowing the transmit frequency to be adjusted in increments of f
/65536. The fractional-N
XTAL
architecture also allows exact FSK frequency deviations to be programmed. FSK deviations as low as ±1kHz and as high
as ±100kHz can be set by programming the appropriate registers.
The internal VCO can be tuned continuously from 286MHz to 960MHz in normal mode, and from 286MHz–320MHz,
425MHz–480MHz, and 860MHz–960MHz in low phase noise mode.
Frequency Programming
The desired frequency can be programmed by setting bits FREQ in registers PLL3, PLL4, and PLL5 (0x0B, 0x0C, 0x0D).
To calculate the FREQ bits, use:
65536 x f
C
FREQ[23 : 0] = ROUND
f
(
)
XTAL
See Table 5 to program the LODIV bits in register PLL1 (0x08) when choosing a LO frequency. It is recommended to
leave bits CPVAL and CPLIN at factory defaults. If integer-N synthesis is desired, set bit FRACMODE = 0 in register
PLL1.
Table 5. LODIV Setting
FREQUENCY RANGE (MHz)
286–960, Low Current Mode
LODIV SETTING
0x0
0x3
0x2
0x1
286–320, Low Phase Noise Mode
425–480, Low Phase Noise Mode
860–960, Low Phase Noise Mode
Fractional-N Spurs
The 16-bit fractional-N, delta-sigma modulator can produce spurious that can show up on the power amplifier output
spectrum. If slight frequency offsets can be tolerated, set the LSB of FREQ (register PLL5, bit 0) to logic-high. Using an
odd value (logic 1 at bit 0) of the 24-bit FREQ register will produce lower PLL spurious compared to even values (logic 0
at bit 0).
Turn-On Time of PLL
The turn-on time of PLL, t
, is defined as the elapsed time from the instant when the XO output is available to the
PLL
instant when PLL frequency acquisition is complete.
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Maxim Integrated | 16
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
2
Two-Wire I C Serial Interface
2
When pins SEL0 and SEL1 are grounded, the MAX41461/MAX41462 features a 2-wire I C-compatible serial interface
consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate bidirectional communication
between the MAX41461/MAX41462 and the master at clock frequencies up to 1MHz. The master device initiates a data
transfer on the bus and generates the SCL signal to permit data transfer. The MAX41461/MAX41462 functions as an
2
I C slave device that transfers and receives data to and from the master. Pull SDA and SCL high with external pullup
2
resistors of 1kΩ or greater, referenced to V
for proper I C operation.
DD
One bit transfers during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte into or out
of the MAX41461/MAX41462 (8 bits and an ACK/NACK). The data on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and
STOP Conditions section). Both SDA and SCL remain high when the bus is not busy.
2
2
Figure 4 and Figure 5 show I C Write transaction and I C Read transaction protocols, respectively.
SCLK
S6 S5 S4 S3 S2 S1 S0 0
DEVICE ADD
A
A7 A6 A5 A4 A3 A2 A1 A0 A
D7 D6 D5 D4 D3 D2 D1 D0 A
WR DATA
SDI
START
REG ADD
STOP
0
ACK FROM SLAVE
r/w = 0
A
2
Figure 4. I C Write
SCLK
S S S S S S S
A A A A A A A A
S S S S S S S
6 5 4 3 2 1 0
D D D D D D D D
A
0
A
A
1 A
6 5
4 3 2 1 0
7
6
5
4
3
2
1
0
7
6 5 4 3 2 1 0
SDI
START
DEVICE ADD
r/w = 0
REG ADD
ACK FROM SLAVE
START
DEVICE ADD
r/w = 1
RD DATA
STOP
ACK FROM MASTER
0
1
A
A
2
Figure 5. I C Read
START and STOP Conditions
The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is
high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while
SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the
MAX41461/MAX41462 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull
SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high
period of the clock pulse.
To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the
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Maxim Integrated | 17
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the
acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master
must reattempt communication at a later time.
Slave Address
2
The MAX41461/MAX41462 has a 7-bit I C slave address that must be sent to the device following a START condition
to initiate communication. The slave address is internally programmed to 0xD2 for WRITE and 0xD3 for READ. The
MAX41461/MAX41462 continuously awaits a START condition followed by its slave address. When the device
recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period, then it is ready to accept
or send data, depending on the R/W bit.
Write Cycle
When addressed with a write command, the MAX41461/MAX41462 allows the master to write to either a single register
or to multiple successive registers.
A write cycle begins with the bus master issuing a START condition, followed by the 7 slave address bits and a write bit
(R/W = 0). The MAX41461/MAX41462 issues an ACK if the slave address byte is successfully received. The bus master
must then send the address of the first register it wishes to write to (see Register Map). The slave acknowledges the
address and the master can then write one byte to the register at the specified address. Data is written beginning with
the most significant bit (MSB). The MAX41461/MAX41462 again issues an ACK if the data is successfully written to the
register.
The master can continue to write data to the successive internal registers with the MAX41461/MAX41462 acknowledging
each successful transfer, or the master can terminate transmission by issuing a STOP condition. The write cycle does
not terminate until the master issues a STOP condition.
2
Figure 6 illustrates I C Burst Write transaction protocol.
SCLK
…..
S S S S S S S
6 5 4 3 2 1 0
A A A A A A A A
7 6 5 4 3 2 1 0
D D D D D D D D
7 6 5 4 3 2 1 0
D D D D D D D D
7 6 5 4 3 2 1 0
D D D D D D D D
7 6 5 4 3 2 1 0
D D D D D D D D
7 6 5 4 3 2 1 0
0 A
A
A
A
A
…..
A
SDI
START
DEVICE ADDR
r/w = 0
REG ADDR
WR DATA TO ADDR
WR DATA TO ADDR+1
WR DATA TO ADDR+2
STOP
….
WR DATA TO ADDR+N
0
ACK FROM SLAVE
A
NOTE: ADDRESS AUTO-INCREMENT
2
Figure 6. I C Burst Write
Read Cycle
When addressed with a read command, the MAX41461/MAX41462 allows the master to read back a single register or
multiple successive registers.
A read cycle begins with the bus master issuing a START condition, followed by the 7 slave address bits and a write
bit (R/W = 0). The device issues an ACK if the slave address byte is successfully received. The bus master must then
send the address of the first register it wishes to read. The slave acknowledges the address. A START condition is then
issued by the master, followed by the 7 slave address bits and a read bit (R/W = 1). The device issues an ACK if the
slave address byte is successfully received. The device starts sending data MSB first with each SCL clock cycle. At the
9th clock cycle, the master can issue an ACK and continue to read successive registers, or the master can terminate the
transmission by issuing a NACK. The read cycle does not terminate until the master issues a STOP condition.
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Maxim Integrated | 18
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Buffered Clock Output
MAX41461/MAX41462 provides a buffered clock output (CLKOUT) on pin 6 of the chip in the preset mode, and the
2
2
frequency of CLKOUT is 800 kHz. In I C mode, MAX41461/MAX41462 uses pin 6 as the SCL line of the I C interface.
CLKOUT_DELAY[1:0] (register CFG2, address 0x01, bits 7:6) is only used in the preset modes, with a preset value of
0x02. These two register bits are not used in programming mode.
State Diagrams
2
In the I C programming mode, the device has four major states: shutdown, standby, programming, and transmitter-
enabled. These states describe the power-on or power-off status of the transmitter's three primary internal circuit blocks:
the crystal oscillator (XO), the PLL synthesizer, and the power amplifier (PA).
Table 6. State Descriptions
State
XO
Off
On
On
On
PLL
Off
Off
On
On
PA
Shutdown
Off
Standby
Off
Off
Programming
Transmitter-Enabled
On with Ramp-up
Configuration register values are retained in all states unless changed by programming, or if the device is powered
off or undergoes a SOFTRESET.
2
A wake-up byte with 7-bit device address from the I C bus initiates the warm-up of the XO and PLL.
2
The device can support two types of I C transactions: register access only, and register access followed by data
transmission. The event trigger of data transmission is a rising edge on I2C_TXEN, which is a special signal
with two register-bit aliases I2C_TXEN1 (register CFG6, 0x0A, bit 2) and I2C_TXEN2 (register CFG7, 0x10, bit
2). A rising edge on I2C_TXEN can be generated by clearing I2C_TXEN1 and setting I2C_TXEN2 in a single
2
I C transaction.
I2C_TXEN is automatically cleared in two cases: 1) wake-up from shutdown, 2) return to programming state
from the transmitter-enabled state. In those two cases, a rising edge on I2C_TXEN can be generated by setting
I2C_TXEN2 in CFG7, without explicit clearing of I2C_TXEN1.
Data to be transmitted are written into a special register, byte I2C_TX_DATA[7:0] (register I2C3, 0x13, bits 7:0).
2
Automatic incrementing of addresses in I C burst write are disabled for this special register. Each data byte written
into I2C_TX_DATA will be transferred into a FIFO buffer. The device has an internal 1-bit signal FIFO_STOP.
At the end of data transmission, FIFO_STOP is set, and the device references the PWDN_MODE[1:0] (register
CFG4, 0x03, bits 1:0) to enter shutdown, standby, or programming state. The shutdown and standby states can
only be entered after the transmitter-enabled state.
2
In both the shutdown and standby states, programming through the I C interface is not allowed. The device will
2
exit the shutdown or standby state once its 7-bit I C address is received.
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Maxim Integrated | 19
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
PLL
PROGRAMMING
XO + PLL
WARM-UP
ENABLED
(PLL ON)
FIFO STOP,
7-bit
RISING
I2C_TXEN
7-bit
ADDRESS
RECOGNIZED
PWDN_MODE
ADDRESS
== 2
RECOGNIZED
FIFO STOP,
PWDN_MODE
== 0
FIFO STOP,
PWDN_MODE
== 1
POWER-ON-RESET
SHUTDOWN
PA RAMP
DOWN
TX
ENABLED
STANDBY
(PLL OFF)
PA RAMP
DOWN
Figure 7. Simplified State Diagram in Programming Mode
In the preset mode, the MAX41461/MAX41462 device has two major states: shutdown, and transmitter-enabled.
After power is applied, the device enters the shutdown state, refer to Initial Programming. A rising edge on DATA (pin 7)
initiates the warm-up of the XO and PLL. After PLL is locked, a falling edge on DATA enables the transmitter. The device
returns to shutdown state when there is no DATA activity, (i.e., DATA stays at 0 for 16384 cycles of the internal 3.2MHz
clock).
FALLING
DATA
XO CLOCK
AVAILABLE
XO + PLL
WARM-UP
TX
ENABLED
WAIT FOR PLL
SETTLING
SHUT-DOWN TIMER
TIMEOUT
RISING DATA
POWER-ON-RESET
PA RAMP
DOWN
SHUTDOWN
Figure 8. State Diagram in Preset Mode
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Maxim Integrated | 20
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Initial Programming
2
After turning on power supply (or a soft reset), two I C transactions are required to initialize the PLL frequency
synthesizer. The first transaction ensures register ADDL2 at address 0x1A is written to its default of 0x80. The
second transaction burst-writes 20 consecutive registers from address 0x00 to 0x13.
The device needs to transmit an 8-bit dummy packet for initial programming. The initial programming must clear
MODMODE (register CFG1, address 0x00, bit 0), clear I2C_TXEN1 (register CFG6, address 0x0A, bit 2), configure
FREQ[23:0] (register PLL3, PLL4 and PLL5) to desired frequency, set I2C_TXEN2 (register CFG7, address 0x10,
bit 2), and configure I2C_TX_DATA[7:0] (register I2C3, address 0x13) to 0x00. In addition, BCLK_POSTDIV[2:0],
BCLK_PREDIV[7:0], and PKTLEN_MODE should be configured to default values in the register map.
Initial programming cannot be completed by a single burst-write transaction because the I2C_TX_DATA register at
2
address 0x13 is a special register that disables automatic address increment. However, two I C transactions may be
merged to a combined transaction, where each write begins with a START mark and the slave address.
After initial programming, the device will enter the shutdown, standby, or programming state according to the setting of
PWDN_MODE[1:0] (register CFG4, address 0x03, bit[1:0] ).
Startup
Programming Mode
This section assumes that initial programming is done after power on (or soft reset). Configuration register values are
retained in all states unless changed by programming, or if the device is powered off or undergoes a SOFTRESET.
2
Case 1: Using Two I C Transactions for Startup from Shutdown
2
The startup of MAX41461/MAX41462 in programming mode, from shutdown state, uses two I C transactions: one for
configuration update, and the other for data transmission.
2
In the first I C transaction, the master device burst-writes consecutive registers that are a portion or all of the 16 registers
from address 0x00 to 0x0F. Those consecutive registers may or may not include CFG6. If CFG6 is included, the
I2C_TXEN1 bit should be cleared; otherwise, I2C_TXEN1 is automatically cleared in the wake-up from shutdown.
2
In the second I C transaction, the master device can set I2C_TXEN2 (register CFG7, address 0x10, bit 2), configure
PKTLEN_MODE (register I2C1, address 0x11, bit 7) and PKTLEN[14:0], and write the data to be transmitted into
I2C_TX_DATA (register I2C3, address 0x13). Automatic increment of register address during burst write is disabled at
address 0x13.
2
The event-trigger for wake-up is the recognition of I C address of the MAX41461/MAX41462 device. The event trigger
for data transmission is the rising edge I2C_TXEN that has two aliases of I2C_TXEN1 and I2C_TXEN2. The time lag
between those two triggers must be longer than t +t
waiting time between two I C transactions.
. To meet this requirement, the master device can adjust the
XO PLL
2
shutdown
device
1st data
set
device
addr
TXEN
byte
addr
SDA
Byte
Byte Byte Byte Byte Byte Byte
+ACK +ACK +ACK +ACK +ACK +ACK
...
programming
+ACK
CFG7 I2C1
I2C2
I2C3
> (tXO+tPLL)
2
Figure 9. Using Two I C Transactions to Start Data Transmission From the Shutdown State
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Maxim Integrated | 21
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
2
2
Case 2: Using a Single I C Transactions for Startup from Shutdown (recommended for use with I C Fast
Mode)
2
From shutdown state, the start-up of device in programming mode may use a single I C transaction to burst-write
consecutive registers starting from address 0x00. Data to be transmitted are written into I2C_TX_DATA (register I2C3,
address 0x13). Automatic increment of register address during burst write is disabled at address 0x13. The programming
should clear I2C_TXEN1 and set I2C_TXEN2.
2
The event-trigger for wake-up is the recognition of I C address of the device. The event-trigger for data transmission is
the rising edge of I2C_TXEN that two aliases of I2C_TXEN1 and I2C_TXEN2. The time lag between those two triggers,
2
here 162 cycles of SCL, must be longer than t
is recommended.
+ t
. To meet this requirement, the fast-mode I C with 400kHz SCL
PLL
XO
shutdown
device
1st data
set
clear
TXEN
TXEN
byte
addr
SDA
Byte Byte Byte
Byte
+ACK
CFG6
Byte Byte Byte Byte
+ACK +ACK +ACK +ACK
...
...
PLL3~7
...
+ACK +ACK +ACK
CFG1
CFG7 I2C1
I2C2
I2C3
> (tXO+tPLL)
2
Figure 10. Using a Single I C Transaction to Start Data Transmission From the Shutdown State
2
Case 3: Using a Combined I C Transaction for Startup from Shutdown (recommended for use with most
2
I C clock rates)
2
From shutdown state, the startup of MAX41461/MAX41462 in programming mode can use a combined I C transaction
with repeated START marks. In a combined transaction, the master device can do multiple read/write operations without
2
losing control to other master devices on the I C bus. For example, the combined transaction can have a burst-read
operation followed by a burst-write operation.
In the burst-write operation, the master device should write consecutive registers starting from CFG7 (address 0x10)
or any register preceding CFG7. Data to be transmitted are written into I2C_TX_DATA (register I2C3, address
0x13). Automatic incrementing of register addresses during burst-write is disabled at address 0x13. The programming
should set I2C_TXEN2 (and clear I2C_TXEN1 if CFG6 is included in the registers to write).
The event-trigger for wake-up is the recognition of device address in the burst-read operation. The event-trigger for data
transmission is the rising edge of I2C_TXEN that has two aliases of I2C_TXEN1 and I2C_TXEN2. The time lag between
those two triggers must be longer than t
+ t
. To meet this requirement, the master device can adjust the number of
PLL
XO
registers to read in the burst-read operation.
shutdown
device
1st data
set
device
addr
TXEN
byte
addr
SDA
Byte
Byte Byte
+ACK +ACK
Byte Byte Byte Byte
+ACK +ACK +ACK +ACK
...
reg read
+ACK
optional
CFG7 I2C1
I2C2
I2C3
> (tXO+tPLL)
2
Figure 11. Using a Combined I C Transaction to Start Data Transmission From the Shutdown State
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Maxim Integrated | 22
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
2
2
Case 4: Using a Single I C Transactions for Startup from Standby (recommended for use with I C Fast-
2
mode and I C Fast-mode Plus)
2
From standby state, the startup of MAX41461/MAX41462 in programming mode can use a single I C transaction
to burst-write consecutive registers starting from CFG6 (address 0x0A) or any register preceding CFG6. Data
to be transmitted are written into I2C_TX_DATA (register I2C3, address 0x13). Automatic incrementing of
register addresses during burst-write is disabled at address 0x13. The programming should clear I2C_TXEN1 and
set I2C_TXEN2.
2
The event-trigger for wake-up is the recognition of I C address of the device. The event-trigger for data
transmission is the rising edge of I2C_TXEN that two aliases of I2C_TXEN1 and I2C_TXEN2. The time lag
between those two triggers, here ≥72 cycles of SCL, must be longer than t
requirement is met for the fast-mode I C with 400kHz SCL. In the case of Fast-mode Plus I C with 1MHz SCL, the
master device can burst-write registers starting from PLL1.
for startup from standby. This
PLL
2
2
standby
1st data
byte
clear
TXEN
set
TXEN
device
addr
SDA
Byte Byte
+ACK +ACK
Byte
+ACK
CFG6
Byte Byte Byte Byte
+ACK +ACK +ACK +ACK
...
PLL3~7
...
optional
CFG7 I2C1
I2C2
I2C3
> tPLL
2
Figure 12. Using a Single I C Transaction to Start Data Transmission From the Standby State
2
Case 5: Using a Single I C Transactions for Startup from Programming
The MAX41461/MAX41462 device can transmit a data packet each time in the transmitter-enabled state. After data
transmission, the device refers to the setting of PWDN_MODE[1:0] to enter the shutdown, standby, or programming
state. If the next data packet requires fast start-up, PWDN_MODE[1:0] can be configured to 0x10 so that the device
returns to the programming state.
2
Then, the master device can use a single I C transaction to burst-write consecutive registers starting from CFG7
(address 0x10) or any register preceding CFG7. Data to be transmitted are written into I2C_TX_DATA (register I2C3,
address 0x13). Automatic incrementing of register addresses during burst-write is disabled at address 0x13. The
programming should set I2C_TXEN2 (and clear I2C_TXEN1 if CFG6 is included in the registers to write). There is no
restrictions arising from t
and t
.
PLL
XO
programming state
1st data
byte
set
TXEN
device
addr
SDA
Byte Byte
+ACK +ACK
Byte Byte Byte Byte
+ACK +ACK +ACK +ACK
...
optional
CFG7 I2C1
I2C2
I2C3
2
Figure 13. Using a Single I C Transaction to Start Data Transmission From the Programming State
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Maxim Integrated | 23
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
FIFO Buffer
2
The I C interface is a bus connected to multiple master or slave devices. The microcontroller is a master device and
2
the MAX41461/MAX41462 is a slave device. The microcontroller can initiate communication with the slave device by I C
addressing (e.g., sending a START mark followed by 7-bit device address). The slave device is required to acknowledge
2
every byte transferred through I C.
For data transmission, the microcontroller can burst-write consecutive registers, including CFG7 and I2C3. The purpose
of writing CFG7 is to set I2C_TXEN2 and, therefore, generate a trigger to enable the transmitter. Automatic increment
2
of register address in I C burst-write is disabled for the I2C3 register, which is also named I2C_TX_DATA. Once the
transmitter is enabled, all bytes written to I2C_TX_DATA are moved into a FIFO buffer. The buffer size is 4 bytes. The
FIFO buffer is enabled only in the transmitter-enabled state.
A programmable baud-rate clock is used for retrieving and transmitting bits from the FIFO buffer. The baud rate is
programmable by BCLK_PREDIV[7:0] (register CFG3, 0x02, bits 7:0) and BCLK_POSTDIV[2:0] (register CFG2, 0x01,
bits 2:0) as the following expression:
f
CLK
BaudRate =
BCLK_POSTDIV
2 × (1 + BCLK_PREDIV) × 2
where f
is the crystal-divider output clock rate (nominally, 3.2 MHz). Valid values of BCLK_PREDIV are from 3 to
CLK
255. Valid values of BCLK_POSTDIV are from 1 to 5.
To avoid underflow of the FIFO buffer, the baud-rate must be lower than 8/9 of the SCL clock rate. The device can
support three modes of SCL clock frequencies: 100kHz, 400kHz, and 1MHz. In the 100kHz mode, it is recommended
to limit baud-rate to no more than 50kbps.
2
A FIFO overflow is avoided by utilizing the I C clock stretching mechanism. Clock stretching is done before the ACK
bit. There is no clock-stretching timeout.
Each time before data transmission, the I2C1 and I2C2 registers are configured to specify PKTLEN_MODE and
PKTLEN[14:0]. Data transmission stops when PKTLEN_MODE is set and the number of bauds transmitted is equal to
PKTLEN[14:0]. Data transmission also stops at FIFO underflow or overflow. An internal 1-bit flag FIFO_STOP is set
at the end of data transmission. The rising edge of FIFO_STOP serves as the event trigger to disable the transmitter.
See State Diagrams section.
When the number of bauds to be transmitted is known before data transmission and less than 32768, it is
recommended to set PKTLEN_MODE and configure PKTLEN[14:0] as the number of bauds to be transmitted.
Otherwise, clear PKTLEN_MODE and utilize FIFO underflow to stop data transmission. Once the microcontroller
stops writing I2C_TX_DATA, FIFO underflow will occur after the data stored in FIFO buffer are transmitted.
Read-only register I2C4, I2C5, and I2C6 are provided to report diagnostic information for the FIFO buffer.
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Maxim Integrated | 24
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Frequency-Hopping
In programming mode, the frequency synthesizer is initialized to a frequency in a selected ISM band by initial
programming. After that, for the purpose of frequency dithering or frequency hopping, the FREQ[23:0] registers can be
updated to a new frequency in the same selected band for each data packet to be transmitted.
Because programming is not allowed in the transmitted-enabled state (see State Diagrams section), frequency
configuration cannot be changed when PA is enabled. See Startup section for details on how to program the device for
data transmission.
After transmitting a data packet, the device enters the shutdown, standby, or programming state according to the setting
of PWDN_MODE[1:0] register. The three options have different startup time for transmitting the the next data packet.
The startup time from shutdown is at least (t
+ t
+ t ), where t
is the turn-on time of crystal oscillator, t
is
PLL
XO
PLL
TX
XO
the turn-on time of PLL, t is the turn-on time of transmitter.
TX
The startup time from standby is at least (t
+ t ).
TX
PLL
The t time is 27 cycles of the SCL clock plus 2 cycles of the baud-rate clock. For example, the SCL clock rate is 1MHz,
TX
the baud rate is 100kb/s, the value of t is 47μs. See Electrical Characteristics table for typical values of t
and t
.
PLL
TX
XO
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Maxim Integrated | 25
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Register Map
Register Map
ADDRESS
TX
NAME
MSB
LSB
FSKSHA
PE
MODMO
DE
0x00
0x01
CFG1[7:0]
XOCLKDELAY[1:0]
XOCLKDIV[1:0]
–
–
SYNC
CLKOUT_DELAY[1:
0]
CFG2[7:0]
–
–
–
–
–
BCLK_POSTDIV[2:0]
0x02
0x03
0x04
CFG3[7:0]
CFG4[7:0]
CFG5[7:0]
BCLK_PREDIV[7:0]
–
–
–
–
–
–
– PWDN_MODE[1:0]
RESERVED[5:0]
RESERV RESERV PA_BOO
0x05
SHDN[7:0]
–
–
–
–
–
–
ED
ED
ST
0x06
0x07
PA1[7:0]
PA2[7:0]
RESERVED[2:0]
–
PAPWR[2:0]
–
PACAP[4:0]
LODIV[1:0]
FRACM
ODE
LOMOD
E
0x08
0x09
0x0A
PLL1[7:0]
PLL2[7:0]
CFG6[7:0]
CPLIN[1:0]
RESERV RESERV
RESERVED[1:0]
–
–
–
–
–
–
–
CPVAL[1:0]
ED
ED
I2C_TXE RESERV RESERV
N1 ED ED
–
–
0x0B
0x0C
0x0D
0x0E
0x0F
PLL3[7:0]
PLL4[7:0]
PLL5[7:0]
PLL6[7:0]
PLL7[7:0]
FREQ[23:16]
FREQ[15:8]
FREQ[7:0]
–
–
DELTAF[6:0]
–
–
–
–
–
–
DELTAF_SHAPE[3:0]
I2C_TXE RESERV RESERV
0x10
0x11
CFG7[7:0]
I2C1[7:0]
–
–
N2
ED
ED
PKTLEN
_MODE
PKTLEN[14:8]
0x12
0x13
I2C2[7:0]
I2C3[7:0]
PKTLEN[7:0]
I2C_TX_DATA[7:0]
PKTCO
MPLETE
0x14
0x15
0x16
I2C4[7:0]
I2C5[7:0]
I2C6[7:0]
TX_PKTLEN[14:8]
TX_PKTLEN[7:0]
FIFO_E FIFO_FU
UFLOW
–
OFLOW
–
–
–
FIFO_WORDS[2:0]
MPTY
LL
SOFTRE
SET
0x17
CFG8[7:0]
–
–
–
–
RESERV RESERV RESERV
ED ED ED
0x18
0x19
0x1A
CFG9[7:0]
ADDL1[7:0]
ADDL2[7:0]
RESERVED[4:0]
RESERVED[1:0]
RESERVED[1:0]
RESERVED[1:0]
RESERVED[6:0]
RESERVED[1:0]
RESERV
ED
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Maxim Integrated | 26
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Register Details
CFG1 (0x00)
BIT
Field
7
6
5
4
3
–
–
2
1
0
XOCLKDELAY[1:0]
0x2
XOCLKDIV[1:0]
0x1
FSKSHAPE
0b0
SYNC
0b0
MODMODE
0b0
Reset
Access
Type
Write, Read
Write, Read
–
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: No delay. XO clock is immediately enabled to
rest of digital block
0x1: XO clock is enabled after 16 cycles to rest of
XOCLKDELA
Y
Start delay before enabling XO clock to digital digital block
7:6
block
0x2: XO clock is enabled after 32 cycles to rest of
digital block
0x3: XO clock is enabled after 64 cycles to rest of
digital block
0x0: Divide XO clock by 4 for digital clock
0x1: Divide XO clock by 5 for digital clock. High
time is 2 cycles, low time is 3 cycles
0x2: Divide XO clock by 6 for digital clock
0x3: Divide XO clock by 7 for digital clock. High
time is 3 cycles, and low time is 4 cycles
XOCLKDIV
5:4
XO clock division ratio for digital block
Sets the state of FSK Gaussain Shaping
0x0: FSK Shaping disabled
0x1: FSK Shaping enabled
FSKSHAPE
SYNC
2
1
0
Controls if clock output acts as an input.
When an input, it will sample the DATA pin.
0x0
0x1
0x0: ASK Mode
0x1: FSK Mode
MODMODE
Configures modulator mode
CFG2 (0x01)
BIT
Field
7
6
5
–
–
4
–
–
3
–
–
2
1
BCLK_POSTDIV[2:0]
0x1
0
CLKOUT_DELAY[1:0]
0x2
Reset
Access
Type
Write, Read
–
–
–
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: CLKOUT will start toggling after 64 cycles
whenever moving into normal mode from shutdown
mode
Selects the delay when CLKOUT starts
toggling upon exiting SHUTDOWN mode, in
divided XO clock cycles
0x1: CLKOUT will start toggling after 128 cycles
whenever moving into normal mode from shutdown
mode
CLKOUT_DE
LAY
7:6
0x2: CLKOUT will start toggling after 256 cycles
whenever moving into normal mode from shutdown
mode
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Maxim Integrated | 27
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
BITFIELD
BITS
DESCRIPTION
DECODE
0x3: CLKOUT will start toggling after 512 cycles
whenever moving into normal mode from shutdown
mode
0x0: RESERVED
0x1: Divide by 1
0x2: Divide by 2
0x3: Divide by 3
0x4: Divide by 4
0x5: Divide by 5
0x6: RESERVED
0x7: RESERVED
BCLK_POST
DIV
2:0
Baud clock post-divider setting.
CFG3 (0x02)
BIT
Field
7
6
5
4
3
2
1
0
BCLK_PREDIV[7:0]
0x3
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x00: RESERVED
0x01: RESERVED
BCLK_PRED
IV
Baud clock predivision ratio. Valid values are 0x02: RESERVED
7:0
from 3 to 255.
0x03: Divide by 3
...
0xFF: Divide by 255
CFG4 (0x03)
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
–
–
1
0
PWDN_MODE[1:0]
0x0
Reset
Access
Type
–
–
–
–
–
–
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: SHUTDOWN low power state is enabled.
While entering low power state, XO, PLL, and PA
are shutdown.
0x1: STANDBY low power state is enabled. While
entering low power state, XO is enabled. PLL and
PA are shutdown
PWDN_MOD
E
1:0
Power Down Mode Select
0x2: FAST WAKEUP low power state is enabled.
While entering low power state, XO and PLL are
enabled. PA is shutdown.
0x3: Will revert to 0x2
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Maxim Integrated | 28
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
CFG5 (0x04)
BIT
Field
7
–
–
6
–
–
5
4
3
2
1
0
RESERVED[5:0]
0x00
Reset
Access
Type
–
–
Write, Read
BITFIELD
BITS
DESCRIPTION
RESERVED
5:0
Write to 00 hex.
SHDN (0x05)
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
1
RESERVED RESERVED PA_BOOST
0x1 0x0 0x0
0
Reset
Access
Type
–
–
–
–
–
Write, Read Write, Read Write, Read
BITFIELD
RESERVED
RESERVED
BITS
DESCRIPTION
DECODE
2
1
Write to 1 binary.
Write to 0 binary.
1
0
Enables a boost in PA output power for
frequencies above 850MHz. This requires a
different PA match compared to normal
operation.
0x0: PA Output power in normal operation.
0x1: PA Output power in boost mode for more
output power.
PA_BOOST
0
PA1 (0x06)
BIT
Field
7
6
RESERVED[2:0]
0x4
5
4
–
–
3
–
–
2
1
0
PAPWR[2:0]
0x0
Reset
Access
Type
Write, Read
–
–
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
RESERVED
7:5
Write to 100 binary.
100
0x0: Minimum, 1 driver
0x1: 2 Drivers
0x2: 3 Drivers
0x3: 4 Drivers
0x4: 5 Drivers
0x5: 6 Drivers
0x6: 7 Drivers
0x7: 8 Drivers
Controls the PA output power by enabling
parallel drivers.
PAPWR
2:0
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Maxim Integrated | 29
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
PA2 (0x07)
BIT
Field
7
–
–
6
–
–
5
–
–
4
3
2
1
0
PACAP[4:0]
0x0
Reset
Access
Type
–
–
–
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x00: 0
0x01: 175
0x02: 350
0x03: 525
0x04: 700
0x05: 875
0x06: 1050
0x07: 1225
0x08: 1400
0x09: 1575
0x0A: 1750
0x0B: 1925
0x0C: 2100
0x0D: 2275
0x0E: 2450
0x0F: 2625
0x10: 2800
0x11: 2975
0x12: 3150
0x13: 3325
0x14: 3500
0x15: 3675
0x16: 3850
0x17: 4025
0x18: 4200
0x19: 4375
0x1A: 4550
0x1B: 4725
0x1C: 4900
0x1D: 5075
0x1E: 5250
0x1F: 5425
Controls shunt capacitance on PA output in
fF.
PACAP
4:0
PLL1 (0x08)
BIT
7
6
5
4
3
2
1
0
FRACMOD
E
Field
CPLIN[1:0]
RESERVED[1:0]
0x00
LODIV[1:0]
0x0
LOMODE
0b0
Reset
0x1
0x1
Access
Type
Write, Read
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Sets the level of charge pump offset current
for fractional N mode to improve close in
0x0: No extra current
0x1: 5% of charge pump current
CPLIN
7:6
phase noise. Set to 'DISABLED' for integer N 0x2: 10% of charge pump current
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Maxim Integrated | 30
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
BITFIELD
BITS
DESCRIPTION
DECODE
mode.
0x3: 15% of charge pump current
Sets PLL between fractional-N and integer-N 0x0: Integer N Mode
FRACMODE
RESERVED
5
mode.
0x1: Fractional N Mode
4:3
Write to 00 binary.
00
0x0: Disabled
0x1: LC VCO divided by 4
0x2: LC VCO divided by 8
0x3: LC VCO divided by 12
LODIV
2:1
0
Sets LO generation. For lower power,
choose LOWCURRENT. For higher
performance, choose LOWNOISE.
0x0: Ring Oscillator Mode
0x1: LC VCO Mode
LOMODE
PLL2 (0x09)
BIT
Field
7
6
5
–
–
4
–
–
3
–
–
2
–
–
1
0
RESERVED RESERVED
0x0 0b0
CPVAL[1:0]
0x0
Reset
Access
Type
Write, Read Write, Read
–
–
–
–
Write, Read
BITFIELD
RESERVED
RESERVED
BITS
DESCRIPTION
DECODE
7
6
Write to 0 binary.
Write to 0 binary.
0
0
0x0: 5µA
0x1: 10µA
0x2: 15µA
0x3: 20µA
CPVAL
1:0
Sets Charge Pump Current
CFG6 (0x0A)
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
2
1
0
–
–
I2C_TXEN1 RESERVED RESERVED
0x0 0x0 0x0
Reset
Access
Type
–
–
–
–
–
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
2
2
Enables DATA transmission in I C mode.
Aliased address for I2C_TXEN1.
0x0: Data transmission not enabled in I C mode.
I2C_TXEN1
2
2
0x1: Data transmission enabled in I C mode.
RESERVED
RESERVED
1
0
Write to 0 binary.
Write to 0 binary.
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Maxim Integrated | 31
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
PLL3 (0x0B)
BIT
Field
7
7
7
6
5
5
5
5
4
3
2
1
0
0
0
0
FREQ[23:16]
0x13
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
FREQ
7:0
FREQ value to PLL. LO frequency= FREQ<23:0>/2^16*fXTAL
PLL4 (0x0C)
BIT
Field
6
4
3
3
3
2
1
1
1
FREQ[15:8]
0xB0
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
FREQ
7:0
FREQ value to PLL
PLL5 (0x0D)
BIT
Field
6
4
2
FREQ[7:0]
Reset
0x00
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
FREQ
7:0
FREQ value to PLL
PLL6 (0x0E)
BIT
Field
7
–
–
6
4
2
DELTAF[6:0]
0x28
Reset
Access
Type
–
Write, Read
BITFIELD
BITS
DESCRIPTION
For FSK mode, MODMODE=1 and FSKSHAPE=0, sets the frequency
deviation from the space frequency for the mark frequency. fDELTA =
DELTAF[6:0] * fXTAL/ 8192
DELTAF
6:0
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Maxim Integrated | 32
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
PLL7 (0x0F)
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
2
1
0
DELTAF_SHAPE[3:0]
0x4
Reset
Access
Type
–
–
–
–
Write, Read
BITFIELD
BITS
3:0
DESCRIPTION
For FSK mode, MODMODE = 1 and FSKSHAPE = 1, sets the frequency
deviation from the space frequency for the mark frequency. fDELTA =
DELTAF_SHAPE[3:0] * fXTAL / 81920
DELTAF_SHAPE
CFG7 (0x10)
BIT
Field
7
–
–
6
–
–
5
–
–
4
–
–
3
–
–
2
1
0
I2C_TXEN2 RESERVED RESERVED
0x0 0x0 0x0
Reset
Access
Type
–
–
–
–
–
Write, Read Write, Read Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
Enables DATA transmission in I2C
mode. Aliased address for I2C_TXEN1
2
0x0: Data transmission not enabled in I C mode.
I2C_TXEN2
2
2
0x1: Data transmission enabled in I C mode.
RESERVED
RESERVED
1
0
Write to 0 binary.
I2C1 (0x11)
BIT
7
6
5
4
3
2
1
0
PKTLEN_M
ODE
Field
PKTLEN[14:8]
0x0
Reset
0x0
Access
Type
Write, Read
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: PKTLEN[14:0] need not be
programmed. FIFO underflow event will be treated
as end of packet event. For cases where actual
packet length is greater than 32767 bits, it is
expected that the µC will pad such a packet to
make it an integral multiple of 8-bits
0x1: PKTLEN[14:0] will provide the length of
packet. Once FIFO is read for PKTLEN[14:0] bits,
or if FIFO underflow, MAX4146x will consider that
as an end of packet event.
PKTLEN_MO
DE
7
Packet Length Mode
Packet Length
PKTLEN
6:0
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Maxim Integrated | 33
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
I2C2 (0x12)
BIT
Field
7
6
5
4
3
2
1
0
PKTLEN[7:0]
0xFF
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
PKTLEN
7:0
Packet Length
I2C3 (0x13)
BIT
Field
7
6
5
4
3
2
1
0
I2C_TX_DATA[7:0]
0x0
Reset
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
2
Transmit data to be written into FIFO for I C mode of operation. At this
2
2
I2C_TX_DATA
7:0
address, I C register address will not auto increment within an I C transaction
burst, and subsequent writes will keep going to FIFO
I2C4 (0x14)
BIT
7
6
5
4
3
TX_PKTLEN[14:8]
0x0
2
1
0
PKTCOMPL
ETE
Field
Reset
0x0
Access
Type
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
DECODE
PKTCOMPL
ETE
0x0: Packet transmission is not completed
0x1: Packet transmission is completed
7
Indicates if Packet tranmission is completed
Provides status information of bits transmitted
for the current packet
TX_PKTLEN
6:0
I2C5 (0x15)
BIT
Field
7
6
5
4
3
2
1
0
TX_PKTLEN[7:0]
0x0
Reset
Access
Type
Read Only
BITFIELD
TX_PKTLEN
BITS
DESCRIPTION
7:0
Provides status information of bits transmitted for the current packet
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Maxim Integrated | 34
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
I2C6 (0x16)
BIT
Field
7
6
5
4
3
–
–
–
2
1
FIFO_WORDS[2:0]
0x0
0
FIFO_EMP
TY
UFLOW
0x0
OFLOW
0x0
FIFO_FULL
0x0
Reset
0x1
Access
Type
Read Only
Read Only
Read Only
Read Only
Read Only
BITFIELD
BITS
DESCRIPTION
UFLOW
7
6
5
4
FIFO Underflow status
FIFO Overflow status
FIFO Empty Status
FIFO Full Status
OFLOW
FIFO_EMPTY
FIFO_FULL
This field captures the number of locations currently filled in FIFO. Each
location corresponds to 8-bit data word
FIFO_WORDS
2:0
CFG8 (0x17)
BIT
7
–
–
–
6
–
–
–
5
–
–
–
4
–
–
–
3
–
–
–
2
–
–
–
1
–
–
–
0
SOFTRESE
T
Field
Reset
0b0
Access
Type
Write, Read
BITFIELD
BITS
DESCRIPTION
DECODE
0x0: Deassert the reset
SOFTRESET
0
Places DUT into software reset.
0x1: Resets the entire digital, until this bit is set to
0
CFG9 (0x18)
BIT
Field
7
6
5
RESERVED[4:0]
0x0
4
3
2
1
0
RESERVED RESERVED RESERVED
0x0 0x0 0x0
Reset
Access
Type
Write, Read
Write, Read Write, Read Write, Read
BITFIELD
RESERVED
RESERVED
RESERVED
RESERVED
BITS
7:3
2
DESCRIPTION
DECODE
Write to 0_0000 binary.
Write to 0 binary.
Write to 0 binary.
Write to 0 binary.
00000
0
0
0
1
0
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Maxim Integrated | 35
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
ADDL1 (0x19)
BIT
Field
7
6
5
4
3
2
1
0
RESERVED[1:0]
0x0
RESERVED[1:0]
0x0
RESERVED[1:0]
0x0
RESERVED[1:0]
0x0
Reset
Access
Type
Write, Read
Write, Read
Write, Read
Write, Read
BITFIELD
RESERVED
RESERVED
RESERVED
RESERVED
BITS
DESCRIPTION
DECODE
7:6
5:4
3:2
1:0
Write to 00 binary.
Write to 00 binary.
00
00
00
00
Write to 00 binary.
Write to 00 binary.
ADDL2 (0x1A)
BIT
Field
7
6
5
4
3
RESERVED[6:0]
0x0
2
1
0
RESERVED
0x1
Reset
Access
Type
Write, Read
Write, Read
BITFIELD
RESERVED
RESERVED
BITS
7
DESCRIPTION
Write to 1 binary.
Write to 000_0000 binary.
DECODE
1
6:0
0000000
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Maxim Integrated | 36
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Applications Information
Power-On Programming
Preset Mode
To ensure the MAX41461/MAX41462 device enters shutdown state after power-on, the DATA pin must be held low at
power-on. If the DATA pin cannot be guaranteed low at power-on, then a high-value pulldown resistor is recommended.
After V
has settled, a logic-low-high-low transition on DATA must occur in the preset mode. If the pulse duration of
DD
low-high-low transition is longer than t
+ t
, it is a valid wake-up pulse before data transmission. It is also allowed to
XO
PLL
have a short pulse duration between 5μs and 20μs. The short pulse will not wake up the device.
Programming Mode
2
After turning on power supply in I C mode, a logic-high-low-high transition on SDA must occur to minimize leakage
2
current in shutdown state. It is highly recommended that the I C resistors are connected to the MAX41461/MAX41462
V
DD
.
2
Two I C transactions are required to initialize the PLL frequency synthesizer. The first transaction ensures register
ADDL2 at address 0x1A is written to its default of 0x80. The second transaction burst-writes 20 consecutive registers
from address 0x00 to 0x13. The device is programmed to transmit a dummy packet with 8 zero bits in ASK mode. There
is no RF emission at PA output. See Initial Programming section.
For example, the crystal frequency is 16MHz, the RF frequency is 315MHz, the 20 consecutive registers from
address 0x00 to 0x13 can be configured as:
[0x90, 0x81, 0x03, 0x00, 0x00, 0x04, 0x80, 0x80, 0x60, 0x00, 0x00, 0xC4, 0xDE, 0x98, 0x28, 0x04, 0x04, 0x00,
0xFF, 0x00]
After initial programming, the device will enter the shutdown, standby, or programming state according to the
setting of PWDN_MODE[1:0] (register CFG4, address 0x03, bit[1:0]). Configuration register values are retained
in all states unless changed by programming, or if the device is powered off or undergoes a SOFTRESET. See
Startup section for directions to program the device for data transmission.
ASK Carrier Frequency
The ASK carrier frequency is set by the FREQ bits in registers 0x0B, 0x0C, and 0x0D. The user calculates the divide
ratio based on the carrier frequency and crystal frequency. The following equation shows how to determine the correct
value to be loaded into the FREQ registers.
fRF
fXTAL
FREQ =
× 65536
(
)
For example, the desired ASK transmit frequency is 315MHz and the crystal frequency is 16MHz. 315/16 is 19.6875.
19.6875 x 65536 is 1290240. Converted into hex, the value is 0x13B000. This value is loaded into FREQ[23:0]. In the
case where the value is non-integer, the value may be rounded to the nearest integer.
Tuning Capacitor Settings
The internal variable shunt capacitor, which can be used to match the PA to the antenna with changing transmitter
frequency, is controlled by setting the 5-bit cap variable in the registers. This allows for 32 levels of shunt capacitance
control. Since the control of these 5 bits is independent of the other settings, any capacitance value can be chosen at
any frequency, making it possible to maintain maximum transmitter efficiency while moving rapidly from one frequency to
another. The internal tuning capacitor adds 0 to 5.425pF to the PA output in 0.175pF steps.
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Maxim Integrated | 37
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Crystal Frequency Selection
In order to avoid integer boundary spurs in fractional-N PLL synthesizers, the crystal should be selected so that the RF
carrier frequency is more than 0.4MHz apart from the nearest integer multiple of crystal frequency.
For example, the 16±0.002MHz crystals can be selected for the 433.92MHz RF carrier, which is more than 0.4MHz apart
from the nearest integer multiple of crystal frequency at 432±0.054MHz. However, the 16±0.002MHz crystals are not
suitable for a RF carrier at 912MHz or 928MHz.
In the programming mode, the crystal divider ratio is programmable. The crystal divider ratio should be configured so
that the divided clock frequency is 3.2±0.1MHz. In addition, the PLL synthesizer requires a reference frequency (same
as crystal frequency) between 12.8MHz and 19.2MHz. Therefore, when crystal divider ratio is 4, 5, or 6, allowed range
of crystal frequency is 12.8MHz~13.2MHz, 15.5MHz~16.5MHz, or 18.6MHz~19.2MHz.
In another example, desired RF frequencies are 319.5MHz, 345.0MHz, and 433.92MHz, and recommended crystal
selection is 13±0.002MHz so that integer boundary spurs are completely suppressed for three desired RF frequencies.
Nevertheless, the 16±0.002MHz and 19.2±0.002MHz crystals are also acceptable.
In the preset mode, the crystal divider ratio is preset at 5. When the RF carrier frequency is very close to an integer
multiple of 16MHz, the crystal selection can change to 16.384MHz or 16.128MHz, and the RF carrier frequency should
be preset through OTP memory in production.
Typical Application Circuit
CLKOUT /
GND
SCL
DATA /
SDA
SEL1
VDD
SEL0
L1A
XTAL1
PA
Y1
L2
C7
XTAL2
C6
C8
GND_PA
MAX41461-64
Ordering Information
PART NUMBER
MAX41461GUB+
TEMPERATURE RANGE
-40°C to +105°C
PIN-PACKAGE
10 µMAX
MAX41461GUB+T
MAX41462GUB+
-40°C to +105°C
-40°C to +105°C
-40°C to +105°C
10 µMAX
10 µMAX
10 µMAX
MAX41462GUB+T
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape-and-reel.
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Maxim Integrated | 38
MAX41461/MAX41462
300MHz–960MHz ASK Transmitter with I2C
Interface
Revision History
REVISION REVISION
PAGES
DESCRIPTION
CHANGED
NUMBER
DATE
10/18
3/19
0
1
Initial release
Updated TSSOP references to µMAX
—
1, 2, 9, 11, 38
For pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https://www.maximintegrated.com/en/storefront/storefront.html.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max
limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
© 2019 Maxim Integrated Products, Inc.
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