MAX4558 [MAXIM]
【15kV ESD-Protected, Low-Voltage, CMOS Analog Multiplexers/Switches; 【 15kV ESD保护，低电压， CMOS模拟多路复用器/开关
| 型号： | MAX4558 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 【15kV ESD-Protected, Low-Voltage, CMOS Analog Multiplexers/Switches |
| 文件： | 总16页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1443; Rev 0; 4/99
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX4558/MAX4559/MAX4560 a re low-volta g e ,
CMOS analog ICs configured as an 8-to-1 multiplexer
(MAX4558), a dual 4-to-1 multiplexer (MAX4559), and a
trip le s ing le -p ole /d oub le -throw (SPDT) s witc h
(MAX4560). Each switch is protected against ±15kV
electrostatic discharge (ESD) shocks, without latchup
or damage.
♦ ESD-Protected X, Y, Z and X_, Y_, Z_ Pins
±15kV (Human Body Model)
±12kV (IEC 1000-4-2, Air-Gap Discharge)
±8kV (IEC 1000-4-2, Contact Discharge)
♦ Pin-Compatible with Industry-Standard
74HC4051/74HC4052/74HC4053
These CMOS devices can operate continuously from
dual supplies of ±2V to ±6V or from a +2V to +12V sin-
gle supply. Each switch can handle Rail-to-Rail ana-
log s ig na ls . The off-le a ka g e c urre nt is only 1nA a t
+25°C or 10nA at +85°C max.
♦ Guaranteed On-Resistance
220Ω with Single +5V Supply
160Ω with ±5V Supply
®
♦ R
Match Between Channels: 2Ω (typ)
ON
All digital inputs have +0.8V to +2.4V logic thresholds,
ensuring TTL/CMOS-logic compatibility when using a
single +5V supply or dual ±5V supplies.
♦ Guaranteed Low leakage Currents
1nA Off-Leakage (at +25°C)
1nA On-Leakage (at +25°C)
♦ TTL-Compatible Inputs with +5V/±5V Supplies
♦ Low Distortion: < 0.02% (600Ω)
Ap p lic a t io n s
Battery-Operated Equipment
♦ Low Crosstalk: < -93dB (50Ω)
♦ High Off-Isolation: < -96dB (50Ω)
Audio and Video Signal Routing
Low-Voltage Data-Acquisition Systems
Communications Circuits
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
16 QSOP
MAX4558CEE
MAX4558CSE
MAX4558CPE
High-ESD Environments
16 Narrow SO
16 Plastic DIP
Ordering Information continued at end of data sheet.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
P in Co n fig u ra t io n s /Fu n c t io n a l Dia g ra m s
TOP VIEW
MAX4559
MAX4560
MAX4558
Y0
Y2
Y1
Y0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
X4
X6
X
V
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
16
15
14
13
12
11
10
9
V
16
15
14
CC
CC
X2
X1
X
Y
X
X1
X0
A
B
X2
X1
Y
Z1
Y3
Z
X7
X5
13 X0
12 X3
Y1
Z0
X0
ENABLE
ENABLE
ENABLE
11 X3
11
10
9
A
B
C
V
EE
V
EE
V
EE
10
9
A
B
LOGIC
LOGIC
GND
GND
GND
C
DIP/SO/QSOP
DIP/SO/QSOP
DIP/SO/QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to V
)
EE
Continuous Power Dissipation (T = +70°C)
A
V
........................................................................ -0.3V to +13V
QSOP (derate 8.00mW/°C above +70°C).................... 640mW
Narrow SO (derate 8.70mW/°C above +70°C) .............696mW
DIP (derate 10.53mW/°C above +70°C) .......................842mW
Operating Temperature Ranges
CC
Voltage into Any Terminal (Note 1).... (V - 0.3V) to (V + 0.3V)
Continuous Current into Any Terminal .............................±10mA
Peak Current, X, Y, Z, X_, Y_, Z_
EE
CC
(pulsed at 1ms, 10% duty cycle) ..................................±30mA
ESD per Method IEC 1000-4-2 (X, Y, Z, X_, Y_, Z_)
Air-Gap Discharge ......................................................... ±12kV
Contact Discharge ............................................................±8kV
ESD per Method 3015.7
MAX45_ _C_E ......................................................0°C to +70°C
MAX45_ _E_E ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
V
, V , A, B, C, ENABLE, GND ................................ ±2.5kV
CC EE
X, Y, Z, X_, Y_, Z_............................................................±15kV
Note 1: Signals on any terminal exceeding V or V are clamped by internal diodes. Limit forward diode current to maximum cur-
CC
EE
rent rating.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies
(V = +4.5V to +5.5V, V = -4.5V to -5.5V, V = +2.4V, V = +0.8V, T = T
to T , unless otherwise noted. Typical values
MAX
CC
EE
_H
_L
A
MIN
are at T = +25°C.)
A
MIN TYP MAX
PARAMETER
SYMBOL
CONDITIONS
T
UNITS
A
(Note 2)
ANALOG SWITCH
V
, V ,
X_ Y_
Analog Signal Range
V
Z_
, V ,
C, E
V-
V+
V
X
V , V
Y
Z
89/MAX4560
+25°C
C, E
110
2
160
180
6
V
= 4.5V; V = -4.5V;
EE
CC
On-Resistance
R
Ω
Ω
Ω
ON
I , I , I = 1mA; V , V , V = ±3V
X
Y
Z
X_ Y_ Z_
+25°C
C, E
On-Resistance Match
Between Channels (Note 3)
V
= 4.5V; V = -4.5V;
CC EE
∆R
ON
I , I , I = 1mA; V , V , V = ±3V
X Y Z X_ Y_ Z_
8
+25°C
C, E
3
8
On-Resistance Flatness
(Note 4)
V
= 4.5V; V = -4.5V;
CC EE
R
FLAT(ON)
I , I , I = 1mA; V , V , V = -3V, 0V, 3V
X
Y
Z
X_ Y_ Z_
10
I
,
,
V
= 5.5V; V = -5.5V;
, V , V = 4.5V, -4.5V;
+25°C
C, E
-1
0.002
1
X_(OFF)
CC EE
X_, Y_ , Z_ Off-Leakage
Current (Note 5)
I
V
nA
nA
Y_(OFF)
X_ Y_ Z_
-10
10
I
V , V , V = -4.5V, 4.5V
X Y Z
Z_(OFF)
+25°C
C, E
-2
-20
-1
0.002
0.002
2
20
1
MAX4558
I
,
,
V
= 5.5V; V = -5.5V;
X(OFF)
CC EE
X, Y, Z Off-Leakage Current
(Note 5)
I
V , V , V = 4.5V, -4.5V;
X_ Y_ Z_
V , V , V = -4.5V, 4.5V
X Y Z
Y(OFF)
+25°C
C, E
MAX4559
MAX4560
I
Z(OFF)
-10 0.002
10
2
+25°C
C, E
-2
-20
-1
0.002
MAX4558
I
I
I
,
,
V
= 5.5V; V = -5.5V;
, V , V = 4.5V, 4.5V;
X(ON)
CC EE
20
1
X, Y, Z On-Leakage Current
(Note 5)
V
nA
Y(ON)
X_ Y_ Z_
+25°C
C, E
0.002
MAX4559
MAX4560
V , V , V = 4.5V, -4.5V
X Y Z
Z(ON)
-10 0.002
10
2
_______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)
(V = +4.5V to +5.5V, V = -4.5V to -5.5V, V = +2.4V, V = +0.8V, T = T
to T , unless otherwise noted. Typical values
MAX
CC
EE
_H
_L
A
MIN
are at T = +25°C.)
A
MIN TYP MAX
PARAMETER
SYMBOL
CONDITIONS
T
UNITS
A
(Note 2)
DIGITAL I/O
V
, V ,
, V
A_ B_
Input Logic High
C, E
C, E
C, E
2.4
V
V
V
C_ EN
V
, V ,
, V
A_ B_
Input Logic Low
0.8
V
C_ EN
Input Current Logic
High or Low
V , V ,
A_ B_
V , V , V , V = V or 0
-1
1
µA
A
B
C
EN
CC
V
, V
C_ EN
POWER SUPPLY
Power-Supply Range
V
, V
C, E
+25°C
C, E
±2
-1
±6
1
V
CC EE
Supply Current,
V
= 5.5V; V = -5.5V;
CC EE
I
CC
µA
V
CC
or V
V , V , V , V = 0 or V
A B C EN CC
EE
-10
10
SWITCH DYNAMIC CHARACTERISTICS
+25°C
C, E
90
55
90
150
175
120
150
150
175
V
, V , V = 3V; R = 300Ω; C = 35pF;
L L
X_ Y_ Z_
Figure 1
Turn-On Time
t
ns
ns
ns
ns
pC
ON
+25°C
C, E
V
, V , V = 3V; R = 300Ω; C = 35pF;
L L
X_ Y_ Z_
Turn-Off Time
t
OFF
Figure 1
+25°C
C, E
V
, V , V = 3V; R = 300Ω; C = 35pF;
X_ Y_ Z_
L
L
Address Transition Time
Break-Before-Make Delay
Charge Injection
t
TRANS
Figure 1
V
, V , V = 3V; R = 300Ω; C = 35pF;
X_ Y_ Z_
L
L
t
+25°C
+25°C
4
15
OPEN
Figure 2
V , V , V = 0; R = 0; C = 1nF;
X
Y
Z
S
L
Q
2.4
Figure 3
C
C
C
,
,
X_(OFF)
V
, V , V = 0; f = 1MHz;
X_ Y_ Z_
Figure 5
V
, V , V Off-Capacitance
+25°C
+25°C
+25°C
2.5
pF
pF
pF
X_ Y_ Z_
Y_(OFF)
Z_(OFF)
MAX4558
MAX4559
MAX4560
MAX4558
MAX4559
MAX4560
10
6
C
C
C
),
),
X(OFF
V , V , V = GND; f = 1MHz;
Figure 5
X
Y
Z
V , V , V Off-Capacitance
X
Y
Z
Y(OFF
Z(OFF)
4
15
11
9
V
, V , V = GND;
X_ Y_ Z_
Switch On-Capacitance
C
ON
f = 1MHz; Figure 5
_______________________________________________________________________________________
3
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)
(V = +4.5V to +5.5V, V = -4.5V to -5.5V, V = +2.4V, V = +0.8V, T = T
to T , unless otherwise noted. Typical values
MAX
CC
EE
_H
_L
A
MIN
are at T = +25°C.)
A
MIN TYP MAX
PARAMETER
Off-Isolation
SYMBOL
CONDITIONS
T
UNITS
A
(Note 2)
C
= 15pF; R = 50Ω; f = 100kHz;
L
L
V
ISO
+25°C
+25°C
-96
-93
dB
dB
V
, V , V = 1V
; Figure 4
X_ Y_ Z_
RMS
C
= 15pF; R = 50Ω; f = 100kHz;
L
L
Channel-to-Channel Crosstalk
V
CT
V
, V , V = 1V
; Figure 4
X_ Y_ Z_
RMS
Total Harmonic Distortion
THD
R = 600Ω; V , V , V = 5Vp-p;
L
X_ Y_ Z_
+25°C
0.02
%
f = 20Hz to 20kHz
+25°C
+85°C
+25°C
+85°C
110
70
ESD SCR Positive Holding
Current
I
mA
mA
H+
95
ESD SCR Negative Holding
Current
I
H-
65
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V
= +4.5V to +5.5V, V = 0, V = +2.4V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at
CC
EE
_H
_L
A
MIN
MAX
T
A
= +25°C.)
MIN TYP MAX
PARAMETER
SYMBOL
CONDITIONS
T
A
UNITS
(Note 2)
ANALOG SWITCH
V
, V ,
X_ Y_
Analog Signal Range
V
Z_
, V ,
C, E
0
V+
V
X
89/MAX4560
V , V
Y
Z
+25°C
C, E
150
3
220
350
V
= 4.5V; I , I , I = 1mA;
X Y Z
CC
On-Resistance
R
Ω
ON
V , V , V = 3V
X
Y
Z
On-Resistance Match
Between Channels
(Note 3, 6)
+25°C
10
V
= 4.5V; I , I , I = 1mA;
X Y Z
CC
∆R
Ω
ON
V , V , V = 3V
X
Y
Z
C, E
+25°C
C, E
12
1
I
I
I
,
,
X_(OFF)
-1
0.002
X_, Y_ , Z_ Off-Leakage
Current (Note 6)
V
= 5.5V; V , V , V = 1V, 4.5V,
CC X Y Z
nA
Y_(OFF)
V , V , V = 4.5V, 1V
X
Y
Z
-10
10
Z_(OFF)
+25°C
C, E
-2
-20
-1
0.002
0.002
0.002
0.002
2
20
1
MAX4558
I
,
,
V
= 5.5V;
, V , V = 1V, 4.5V;
X(OFF)
CC
X, Y, Z Off-Leakage Current
(Note 6)
I
V
nA
nA
Y(OFF)
X_ Y_ Z_
+25°C
C, E
MAX4559
MAX4560
I
V , V , V = 4.5V, 1V
X Y Z
Z(OFF)
-10
-2
10
2
+25°C
C, E
MAX4558
I
I
I
,
,
V
= 5.5V;
X(ON)
CC
-20
-1
20
1
X, Y, Z On-Leakage Current
(Note 6)
V , V , V = 1V, 4.5V;
X_ Y_ Z_
V , V , V = 1V, 4.5V
X Y Z
Y(ON)
+25°C
C, E
MAX4559
MAX4560
Z(ON)
-10 0.002
10
4
_______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V
CC
= +4.5V to +5.5V, V = 0, V = +2.4V, V = +0.8V, T = T
to T , unless otherwise noted. Typical values are at
EE
_H
_L
A
MIN
MAX
T
A
= +25°C.)
MIN TYP MAX
PARAMETER
SYMBOL
CONDITIONS
T
UNITS
A
(Note 2)
DIGITAL I/O
V
, V ,
, V
A_ B_
Input Logic High
C, E
C, E
C, E
2.4
-1
V
V
V
C_ EN
V
, V ,
, V
A_ B_
Input Logic Low
0.8
1
V
C_ EN
Input Current Logic
High or Low
V , V ,
A_ B_
V , V , V
V
C, EN
= V or 0
µA
A
B
CC
V
, V
C_ EN
SWITCH DYNAMIC CHARACTERISTICS (Note 6)
+25°C
C, E
110
50
250
300
150
200
250
300
V
, V , V = 3V; R = 300Ω; C = 35pF;
L L
X_ Y_ Z_
Turn-On Time
t
ns
ns
ns
ns
pC
ON
Figure 1
+25°C
C, E
V
, V , V = 3V; R = 300Ω; C = 35pF;
X_ Y_ Z_
L
L
Turn-Off Time
t
OFF
Figure 1
+25°C
C, E
110
V
, V , V = 3V; R = 300Ω; C = 35pF;
X_ Y_ Z_
L
L
Address Transition Time
Break-Before-Make Delay
t
TRANS
Figure 1
V
, V , V = 3V; R = 300Ω; C = 35pF;
X_ Y_ Z_
L
L
t
C, E
10
OPEN
Figure 3
V , V , V = 2.5V; R = 0; C = 1nF;
X
Y
Z
S
L
Charge Injection
Q
+25°C
1
Figure 3
POWER SUPPLY
+25°C
C, E
-1
1
V
Supply Current
I
CC
V
= 5.5V; V , V , V , V = 0 or V
CC
µA
V
CC
CC
AH BH CH EN
-10
10
Power-Supply Range
V
, V
C, E
+2
+12
CC EE
_______________________________________________________________________________________
5
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V = +2.7V to +3.6V, V = +2.0V, V = +0.8V, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
CC
_H
_L
A
MIN
MAX
A
MIN TYP MAX
PARAMETER
SYMBOL
CONDITIONS
T
UNITS
A
(Note 2)
ANALOG SWITCH
On-Resistance
DIGITAL I/O
+25°C
C, E
220
400
450
V
= 2.7V; I , I , I = 0.1mA;
X Y Z
CC
R
Ω
ON
V , V , V = 1.5V
X
Y
Z
V
, V ,
, V
A_ B_
Input Logic High
C, E
C, E
C, E
1.5
-1
V
V
V
C_ EN
V
, V ,
, V
A_ B_
Input Logic Low
0.5
1
V
C_ EN
Input Current Logic
High or Low
V , V ,
A_ B_
V , V , V , V = V or 0
µA
A
B
C
EN
CC
V
, V
C_ EN
SWITCH DYNAMIC CHARACTERISTICS (Note 6)
+25°C
C, E
180
90
350
400
250
300
350
400
V
C
, V , V = 1.5V; R = 1kΩ;
L
= 35pF; Figure 1
X_ Y_ Z_
Turn-On Time
t
ns
ns
ns
ns
pC
ON
L
+25°C
C, E
V
, V , V = 1.5V; R = 1kΩ;
L
= 35pF; Figure 1
X_ Y_ Z_
Turn-Off Time
t
OFF
C
L
+25°C
C, E
180
V
, V , V = 1.5V; R = 1kΩ;
L
= 35pF; Figure 1
X_ Y_ Z_
Address Transition Time
Break-Before-Make Delay
t
TRANS
C
L
V
, V , V = 1.5V; R = 1kΩ;
L
= 35pF; Figure 2
X_ Y_ Z_
t
C, E
1.5
OPEN
Q
C
L
89/MAX4560
V , V , V = 1.5V; R = 0; C = 1nF;
X
Y
Z
S
L
Charge Injection
+25°C
0.5
0.5
Figure 3
POWER SUPPLY
+25°C
C, E
1
1
V
CC
Supply Current
I
V
CC
= 3.6V; V , V , V , V = 0 or V
µA
CC
A_ B_ C_ EN
CC
-10
10
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: ∆R = R - R
.
ON(MIN)
ON
ON(MAX)
Note 4: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges; i.e., V = 3V to 0 and 0 to -3V.
ON
Note 5: Leakage parameters are 100% tested at the maximum-rated hot operating temperature and are guaranteed by correlation
at T = +25°C.
A
Note 6: Guaranteed by design, not production tested.
6
_______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, V = -5V, T = +25°C, unless otherwise noted.)
CC
EE
A
ON-RESISTANCE vs. V , V , V AND
ON-RESISTANCE vs. V , V , V
ON-RESISTANCE vs. V , V , V
X
Y
Z
X
Y
Z
X
Y
Z
TEMPERATURE (DUAL SUPPLIES)
(DUAL SUPPLIES)
(SINGLE SUPPLY)
140
130
120
110
100
90
180
480
420
360
300
240
180
T = +85°C
A
V
V
EE
= +2V
= -2V
CC
T = +70°C
A
V
CC
= +2V
160
140
120
100
80
V
CC
= +2.7V
V
V
EE
= +3V
= -3V
CC
T = 0°C
A
V
= +5V
= -5V
T = +25°C
A
CC
V
CC
= +3.3V
80
T = -40°C
A
V
EE
60
70
120
60
0
40
60
V
V
EE
= +5V
= -5V
V
= +5V
CC
CC
20
50
V
EE
= 0
40
0
-5 -4 -3 -2 -1
0
1
2
3
4
5
-5 -4 -3 -2 -1
0
1
2
3
4
5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V , V , V (V)
V , V , V (V)
X
V , V , V (V)
X
Y Z
Y Z
X
Y Z
ON-RESISTANCE vs. V , V , V AND
TEMPERATURE (SINGLE SUPPLY)
CHARGE INJECTION vs.
V , V , V
X
Y
Z
ON/OFF-LEAKAGE CURRENT
vs. TEMPERATURE
X
Y
Z
170
160
150
140
130
120
110
100
90
12
10
8
1000
T = +85°C
A
ON_LEAKAGE I , I , I
Y Z
100
10
1
X
6
4
OFF_LEAKAGE I , I , I
Y Z
X
T = +70°C
A
2
0
T = +25°C
A
V
V
EE
= +5V
= -5V
T = 0°C
A
CC
T = -40°C
A
-2
80
70
V
CC
= +5V
-4
-6
OFF_LEAKAGE I , I , I
X_ Y_ Z_
V
V
EE
= +3V
= 0
CC
V
EE
= 0
60
V
V
= +5V
0.1
CC
V
= +5V
= -5V
CC
-8
= 0
50
40
EE
V
EE
-10
0.01
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V , V , V (V)
-5 -4 -3 -2 -1
0
1
2
3
4
5
-50 -35 -20 -5 10 25 40 55 70 85 100
TEMPERATURE (°C)
V , V , V (V)
X
Y Z
X
Y Z
TURN-ON/TURN-OFF TIME
vs. SUPPLY VOLTAGE
POWER-SUPPLY CURRENT
vs. TEMPERATURE
SCR HOLDING CURRENT
vs. TEMPERATURE
170
150
10
200
V
V
EE
= +5V
= -5V
CC
180
160
140
120
100
80
V , V , V , V = 0.5V
A ENABLE
B
C
1
0.1
130
110
I +
H
I
CC
t
ON
I
EE
I -
H
90
70
50
30
0.01
60
t
OFF
40
0.001
20
0.0001
0
±2.0 ±2.5 ±3.0 ±3.5 ±4.0 ±4.5 ±5.0 ±5.5 ±6.0
-50 -30 -10 10 30 50 70
TEMPERATURE (°C)
90 100
-60 -40 -20
0
20 40 60 80 100
SUPPLY VOLTAGE (V , V )
CC EE
TEMPERATURE (°C)
_______________________________________________________________________________________
7
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, V = -5V, T = +25°C, unless otherwise noted.)
CC
EE
A
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
TURN-ON/TURN-OFF TIME
vs. TEMPERATURE
FREQUENCY RESPONSE
0.025
0.024
110
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
V
= +5V
= -5V
EE
CC
INSERTION LOSS
100
600Ω IN AND OUT
t
ON
0.023
0.022
0.021
0.020
0.019
0.018
90
80
70
60
50
40
t
OFF
OFF-ISOLATION
CROSSTALK
100k
V
V
EE
= +5V
= -5V
CC
V
V
EE
= +5V
= -5V
CC
10
100
1k
10k
100k
-40 -20
0
20
40
60
80
10k
1M
10M
100M
1G
FREQUENCY (Hz)
TEMPERATURE (°C)
FREQUENCY (Hz)
P in De s c rip t io n
PIN
NAME
FUNCTION
MAX4558
MAX4559
MAX4560
1, 2, 4, 5,
12–15
—
—
X0–X7
X
Analog Switch Inputs 0–7
Analog Switch Output
3
—
—
—
14
13
12
1
89/MAX4560
—
—
—
—
—
—
11, 12, 14, 15
X0, X1, X2, X3
Analog Switch “X” Inputs 0–3
Analog Switch “X” Output
13
—
—
—
—
X
X1
X0
Y1
Y0
Analog Switch “X” Normally Open Input
Analog Switch “X” Normally Closed Input
Analog Switch “C” Normally Open Input
Analog Switch “C” Normally Closed Input
2
Digital Enable Input. Connect to GND to enable device. Drive
high to set all switches off.
6
7
6
7
6
7
ENABLE
Negative Analog Supply Voltage Input. Connect to GND for
single-supply operation.
V
EE
8
8
8
11
10
9
GND
Ground
11
10
9
10
A
Digital Address “A” Input
9
B
Digital Address “B” Input
—
C
Digital Address “C” Input
—
—
—
—
—
16
1, 2, 4, 5
—
15
5
Y0, Y1, Y2, Y3
Analog Switch “Y” Inputs 0–3
Analog Switch “Y” Output
3
Y
Z0
Z1
Z
—
—
—
16
Analog Switch “Z” Normally Closed Input
Analog Switch “Z” Normally Open Input
Analog Switch “Z” Output
3
4
16
V
CC
Positive Analog and Digital Supply Voltage Input
8
_______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
the X, Y, Z or X_, Y_, Z_ pins are current limited to a
_______________De t a ile d De s c rip t io n
value below the holding current. This ensures that the
The MAX4558/MAX4559/MAX4560 are ESD protected
SCR turns off and normal operation resumes after an
(per IEC 1000-4-2) at their X, Y, Z output pins and X_,
ESD event.
Y_, Z_ input pins. These ICs feature on-chip bidirection-
Keep in mind that the holding currents vary significantly
with temperature; they drop to 70mA (typ) in the posi-
tive direction and 65mA (typ) in the negative direction,
at +85°C worst case. To guarantee turn-off of the SCRs
under all conditions, current limit the sources connect-
ed to these pins to not more than half of these typical
values. When the SCR is latched, the voltage across it
is about ±3V, depending on the polarity of the pin cur-
rent. The supply voltages do not affect the holding cur-
rents appreciably. When one or more SCRs turn on
because of an ESD event, all switches in the part turn
off to prevent current through the switch(es) from sus-
taining latchup.
al silicon-controlled rectifiers (SCRs) between the pro-
tected pins and GND. The SCRs are normally off and
have a negligible effect on the switches’ performance.
During an ESD strike, the voltages at the protected pins
g o Be yond -the -Ra ils ™, c a us ing the c orre s p ond ing
SCR(s) to turn on in a few nanoseconds. This bypasses
the surge current safely to ground. This protection
method is superior to using diode clamps to the sup-
plies. Unless the supplies are very carefully decoupled
through low-ESR capacitors, the ESD current through a
diode clamp could cause a significant spike in the sup-
plies, which might damage or compromise the reliabili-
ty of any other chip powered by those same supplies.
Even though most of the ESD current flows to GND
through the SCRs, a small portion of it goes into the
supplies. Therefore, it is a good idea to bypass the
supply pins with 100nF capacitors to the ground plane.
In addition to the SCRs at the ESD-protected pins,
these devices provide internal diodes connected to the
supplies. Resistors placed in series with these diodes
limit the current flowing into the supplies during an ESD
strike. The diodes protect the X, Y, Z and X_, Y_, Z_
pins from overvoltages due to improper power-supply
sequencing.
__________Ap p lic a t io n s In fo rm a t io n
ES D P ro t e c t io n
The MAX4558/MAX4559/MAX4560 are characterized
for protection to the following:
Once the SCR turns on because of an ESD strike, it
remains on until the current through it falls below its
“hold ing c urre nt.” The hold ing c urre nt is typ ic a lly
110mA in the positive direction (current flowing into the
pin) and 95mA in the negative direction at room tem-
perature (see SCR Holding Current vs. Temperature in
the Typical Operating Characteristics). The system
should be designed so that any sources connected to
•
•
±15kV using the Human Body Model
±8kV using the Contact Discharge method specified
in IEC 1000-4-2 (formerly IEC 801-2)
•
±12kV using the Air-Gap Discharge method speci-
fied in IEC 1000-4-2 (formerly IEC 801-2).
Beyond-the-Rails is a trademark of Maxim Integrated Products.
Table 1. Truth Table/Switch Programming
SELECT INPUTS
ON SWITCHES
ENABLE
INPUT
C*
X
L
B
X
L
A
X
L
MAX4558
MAX4559
All switches open
X-X0, Y-Y0
X-X1, Y-Y1
X-X2, Y-Y2
X-X3, Y-Y3
X-X0, Y-Y0
X-X1, Y-Y1
X-X2, Y-Y2
X-X3, Y-Y3
MAX4560
H
L
L
L
L
L
L
L
L
All switches open
All switches open
X-X0, Y-Y0, Z-Z0
X-X1, Y-Y0, Z-Z0
X-X0, Y-Y1, Z-Z0
X-X1, Y-Y1, Z-Z0
X-X0, Y-Y0, Z-Z1
X-X1, Y-Y0, Z-Z1
X-X0, Y-Y1, Z-Z1
X-X1, Y-Y1, Z-Z1
X-X0
X-X1
X-X2
X-X3
X-X4
X-X5
X-X6
X-X7
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
X = Don’t care * C not present on MAX4559.
Note: Input and output pins are identical and interchangeable. Either may be considered an input or output; signals pass equally well in
either direction.
_______________________________________________________________________________________
9
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
terminals, not to the other switch terminal. This is why
both sides of a given switch can show leakage currents
of either the same or opposite polarity.
ES D Te s t Co n d it io n s
ESD p e rforma nc e d e p e nd s on s e ve ra l c ond itions .
Contact Maxim for a reliability report that documents
test setup, methodology, and results.
V
and GND power the internal logic and logic-level
CC
translators, and set the input logic limits. The logic-level
translators convert the logic levels into switched V
Hu m a n Bo d y Mo d e l
Figure 6 shows the Human Body Model, and Figure 7
shows the current waveform it generates when dis -
charged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of inter-
e s t, whic h is the n d is c ha rg e d into the te s t d e vic e
through a 1.5kΩ resistor.
CC
and V signals to drive the gates of the analog switch.
EE
This drive signal is the only connection between the
logic supplies and logic signals and the analog sup-
plie s. V
a nd V ha ve ESD-prote c tion diode s to
CC
EE
GND.
The logic-level thresholds are TTL/CMOS compatible
P o w e r-S u p p ly Co n s id e ra t io n s
The MAX4558/MAX4559/MAX4560 are typical of most
CMOS analog switches. They have three supply pins:
when V is +5V. As V rises, the threshold increases
CC
CC
s lig htly. Whe n V
re a c he s +12V, the thre s hold is
CC
about 3.1V (above the TTL-guaranteed high-level mini-
mum of 2.4V, but still compatible with CMOS outputs).
V
CC
, V , and GND. V
and V drive the internal
CC EE
EE
CMOS switches and set the limits of the analog voltage
on every switch. Internal reverse ESD-protection diodes
Hig h -Fre q u e n c y P e rfo rm a n c e
In 50Ω systems, signal response is reasonably flat up
to 50MHz (s e e Typ ic a l Op e ra ting Cha ra c te ris tic s ).
Ab ove 20MHz, the on re s p ons e ha s s e ve ra l minor
peaks that are highly layout dependent. The problem is
not turning the switch on, but turning it off. The off-state
switch acts like a capacitor and passes higher frequen-
c ie s with le ss a tte nua tion. At 1MHz, off-isola tion is
about -68dB in 50Ω systems, becoming worse (approx-
imately 20dB per decade) as the frequency increases.
Higher circuit impedance also degrades off-isolation.
Adjacent channel attenuation is about 3dB above that
of a bare IC socket and is entirely due to capacitive
coupling.
connect between each analog signal pin and both V
CC
and V . If any analog signal exceeds V or V , one
EE
CC
EE
of these diodes conducts. The only currents drawn
from V or V during normal operation are the leak-
CC
EE
age currents of these ESD diodes.
Although the ESD diodes on a given signal pin are
identical and therefore fairly well balanced, they are
reverse biased differently. Each is biased by either V
CC
or V and the analog signal. Their leakage currents
EE
vary as the signal varies. The difference in the two
89/MAX4560
diode leakages to the V and V pins constitutes the
CC
EE
analog signal-path leakage current. All analog leakage
current flows between each input and one of the supply
10 ______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
Te s t Circ u it s /Tim in g Dia g ra m s
V
CC
V
CC
V
ENABLE
50%
V
CC
X0
A
B
C
V
CC
0V
X1–X7
V
X0
90%
MAX4558
V
ENABLE
V
OUT
V
OUT
ENABLE
X
90%
GND
V
EE
35pF
50Ω
50Ω
50Ω
0V
300Ω
V
EE
t
t
OFF
ON
V
CC
V
CC
50%
V
ENABLE
V
CC
X0, Y0
A
B
V
CC
0V
X1–X3, Y1–Y3
V ,
X0
V
Y0
90%
MAX4559
V
ENABLE
ENABLE
X, Y
V
OUT
V
EE
V
OUT
GND
90%
35pF
0V
300Ω
V
EE
t
t
ON
OFF
V
CC
V
CC
V
ENABLE
50%
V
CC
A
B
C
X1, Y1, Z1
V
CC
0V
V ,
X0
V ,
Y0
MAX4560
V
Z0
X0, Y0, Z0
V
EE
90%
V
ENABLE
ENABLE
X, Y, Z
V
OUT
V
EE
GND
V
OUT
90%
35pF
300Ω
0V
V
EE
t
t
ON
OFF
V- = 0 FOR SINGLE-SUPPLY OPERATION.
REPEAT TEST FOR EACH SECTION.
Figure 1. Switching Times
______________________________________________________________________________________ 11
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
Te s t Circ u it s /Tim in g Dia g ra m s (c o n t in u e d )
V
CC
V
CC
V , V V
B C
,
A
V , V
V
CC
A
B
V
CC
X0–X7
X0–X3,
Y0–Y3
A
B
C
A
B
V
CC
V
CC
50Ω
50Ω
MAX4559
GND
MAX4558
V
OUT
ENABLE
ENABLE
X
X, Y
V
OUT
V
EE
V
GND
EE
35pF
35pF
300Ω
300Ω
V
EE
V
EE
V
CC
t < 20ns
t < 20ns
F
R
V , V V
A
B
,
C
V+
0V
V
CC
V , V , V
A B C
50%
A, B, C
V
CC
X0, X1, Y0,
Y1, Z0, Z1
50Ω
V , V , V
X
Y
Z
MAX4560
80%
ENABLE
X, Y, Z
EE
V
OUT
V
GND
35pF
V
OUT
300Ω
V
EE
0V
V
= 0 FOR SINGLE-SUPPLY OPERATION.
EE
t
89/MAX4560
BBM
TEST EACH SECTION INDIVIDUALLY.
Figure 2. Break-Before-Make Interval
V
CC
V
CC
V
ENABLE
V
CC
X_, Y_, Z_
A
B
C
0V
CHANNEL
SELECT
MAX4558
MAX4559
MAX4560
∆ V
OUT
V
OUT
V
ENABLE
V
OUT
ENABLE
X, Y, Z
GND
V
EE
C = 1000pF
L
50Ω
∆ V IS THE MEASURED VOLTAGE DUE TO CHARGE
TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF.
OUT
V
EE
V
= 0V FOR SINGLE-SUPPLY OPERATION.
EE
Q = ∆ V • C
OUT
L
TEST EACH SECTION INDIVIDUALLY.
Figure 3. Charge Injection
12 ______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
Te s t Circ u it s /Tim in g Dia g ra m s (c o n t in u e d )
10nF
V+
V+
NETWORK
ANALYZER
V
IN
V
OUT
50Ω
50Ω
OFF-ISOLATION = 20log
V
X_, Y_, Z_
A
B
C
IN
CHANNEL
SELECT
MAX4558
MAX4559
MAX4560
V
OUT
ON-LOSS = 20log
V
IN
V
OUT
MEAS.
REF.
ENABLE
X, Y, Z
V
OUT
CROSSTALK = 20log
V
GND
EE
V
IN
50Ω
50Ω
10nF
V
EE
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT SOCKET TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM AND "OFF" NO TERMINAL ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN COM AND "ON" NO TERMINAL ON EACH SWITCH.
CROSSTALK (MAX4559/MAX4560) IS MEASURED FROM ONE CHANNEL X_, Y_, Z_ TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 4. Off-Isolation/On-Channel Bandwidth and Crosstalk
V
CC
V
CC
X_, Y_, Z_
A
B
C
CHANNEL
SELECT
MAX4558
MAX4559
MAX4560
1MHz
ENABLE
X, Y, Z
CAPACITANCE
ANALYZER
GND
V
EE
V
EE
Figure 5. Channel Off/On-Capacitance
______________________________________________________________________________________ 13
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
Te s t Circ u it s /Tim in g Dia g ra m s (c o n t in u e d )
R
C
R
D
1M
1500Ω
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
C
s
100pF
STORAGE
CAPACITOR
36.8%
SOURCE
10%
0
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 6. Human Body ESD Test Model
Figure 7. Human Body Model Current Waveform
89/MAX4560
Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 221
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
PIN-PACKAGE
16 QSOP
MAX4558EEE
MAX4558ESE
MAX4558EPE
MAX4559CEE
MAX4559CSE
MAX4559CPE
MAX4559EEE
MAX4559ESE
MAX4559EPE
MAX4560CEE
MAX4560CSE
MAX4560CPE
MAX4560EEE
MAX4560ESE
MAX4560EPE
16 Narrow SO
16 Plastic DIP
16 QSOP
0°C to +70°C
16 Narrow SO
16 Plastic DIP
16 QSOP
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
16 Narrow SO
16 Plastic DIP
16 QSOP
0°C to +70°C
16 Narrow SO
16 Plastic DIP
16 QSOP
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 Narrow SO
16 Plastic DIP
14 ______________________________________________________________________________________
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
89/MAX4560
P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
±1 5 k V ES D-P ro t e c t e d , Lo w -Vo lt a g e , CMOS
An a lo g Mu lt ip le x e rs /S w it c h e s
P a c k a g e In fo rm a t io n (c o n t in u e d )
89/MAX4560
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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