MAX4567CEE_技术文档

19-1252; Rev 0; 7/97

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

♦ High 50Ω Off Isolation: -83dB at 10MHz

♦ Low 50Ω Crosstalk: -87dB at 10MHz

The MAX4565/MAX4566/MAX4567 a re low-volta g e

T-switches designed for switching RF and video signals

from DC to 350MHz in 50Ω a nd 75Ω s ys te ms . The

MAX4565 contains four normally open single-pole/single-

throw (SPST) switches. The MAX4566 contains two dual

SPST switches (one normally open, one normally closed.)

The MAX4567 contains two single-pole/double-throw

(SPDT) switches.

♦ DC to 350MHz -3dB Signal Bandwidth

♦ 60Ω Signal Paths with ±5V Supplies

♦ 2.5Ω Signal-Path Matching with ±5V Supplies

♦ 2Ω Signal-Path Flatness with ±5V Supplies

♦ Low 50Ω Insertion Loss: 2.5dB at 100MHz

Each switch is constructed in a “T” configuration, ensuring

excellent high-frequency off isolation and crosstalk of

®

-83dB at 10MHz. They can handle Rail-to-Rail analog sig-

♦ ±2.7V to ±6V Dual Supplies

nals in either direction. On-resistance (60Ω max) is

matched between switches to 2.5Ω max and is flat (2Ω

max) over the specified signal range, using ±5V supplies.

The off leakage current is less than 5nA at +25°C and

50nA at +85°C.

+2.7V to +12V Single Supply

♦ Low Power Consumption: <1µW

♦ Rail-to-Rail Bidirectional Signal Handling

♦ Pin Compatible with Industry-Standard DG540,

These CMOS switches can operate with dual power sup-

plies ranging from ±2.7V to ±6V or a single supply

between +2.7V and +12V. All digital inputs have 0.8V/2.4V

logic thresholds, ensuring both TTL- and CMOS-logic com-

patibility when using ±5V or a single +5V supply.

DG542, DG643

♦ >2kV ESD Protection per Method 3015.7

♦ TTL/CMOS-Compatible Inputs

with Single +5V or ±5V

________________________Ap p lic a t io n s

RF Switching

______________Ord e rin g In fo rm a t io n

Video Signal Routing

PART

TEMP. RANGE

0°C to +70°C

PIN-PACKAGE

20 Plastic DIP

20 Wide SO

MAX4565CPP

MAX4565CWP

High-Speed Data Acquisition

Test Equipment

Ordering Information continued at end of data sheet.

ATE Equipment

____^N_^e_^t_^w_^o_^rk_ⁱⁿ_^g__________P in Co n fig u ra t io n s /Fu n c t io n a l Dia g ra m s /Tru t h Ta b le s

TOP VIEW

IN1

COM1

GND1

N01

1

2

3

4

5

6

7

8

9

20 IN2

MAX4566

MAX4567

19 COM2

18 GND2

17 NO2

16 V+

1

2

3

4

5

6

7

8

16

15

1

2

3

4

5

6

7

8

16

15

IN1

COM1

GND1

N01

IN2

IN1

N01

N02

V+

COM2

V-

14 GND2

13 NO2

12 V+

V-

14 GND2

13 COM2

12 GND3

MAX4565

GND5

N04

15 GND6

14 N03

13 GND3

12 COM3

11 IN3

GND1

COM1

GND4

V+

V-

GND4

COM4

NC4

NC3

V-

11

10 GND3

COM3

11

10 NC2

IN2

GND4

COM4

IN4 10

9

NC1

9

DIP/SO/SSOP

DIP/SO/QSOP

MAX4567

MAX4565

MAX4566

1, 2

LOGIC

SWITCH

LOGIC

3, 4

LOGIC

NO-COM

NC-COM

0

1

OFF

ON

0

1

OFF

ON

OFF

0

1

OFF

ON

OFF

SWITCHES SHOWN

FOR LOGIC “0” INPUT

Rail-to-Rail is a registered trademark of Nippon Motorola Ltd.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.

For small orders, phone 408-737-7600 ext. 3468.

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

ABSOLUTE MAXIMUM RATINGS

(Voltages Referenced to GND)

16-Pin Narrow SO

V+ ...........................................................................-0.3V, +13.0V

V- ............................................................................-13.0V, +0.3V

V+ to V-...................................................................-0.3V, +13.0V

All Other Pins (Note 1)..........................(V- - 0.3V) to (V+ + 0.3V)

Continuous Current into Any Terminal..............................±25mA

Peak Current into Any Terminal

(derate 8.70mW/°C above +70°C)............................696mW

16-Pin QSOP (derate 8.3mW/°C above +70°C).......... 667mW

20-Pin Plastic DIP (derate 8.0mW/°C above +70°C) ...640mW

20-Pin Wide SO (derate 10.00mW/°C above +70°C) .. 800mW

20-Pin SSOP (derate 8.0mW/°C above +70°C) .......... 640mW

Operating Temperature Ranges

(pulsed at 1ms, 10% duty cycle)..................................±50mA

ESD per Method 3015.7 ..................................................>2000V

MAX456_C_ E .....................................................0°C to +70°C

MAX456_E_ E ..................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

Continuous Power Dissipation (T = +70°C) (Note 2)

A

16-Pin Plastic DIP

(derate 10.53mW/°C above +70°C)..........................842mW

Note 1: Voltages on all other pins exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum cur-

rent rating.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—Dual Supplies

(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, V

= 0.8V, V

= 2.4V, V

= 0V, T = T

to T , unless otherwise noted. Typical

MAX

GND_

INL

INH

A

MIN

values are at T = +25°C.)

A

MIN

TYP

(Note 2)

MAX

PARAMETER

ANALOG SWITCH

SYMBOL

CONDITIONS

T

A

UNITS

V

,

COM_

,V

Analog Signal Range

(Note 3)

C, E

V-

V+

V

Ω

V

NO_ NC_

/MAX4567

+25°C

C, E

46

1

60

80

2.5

3

V+ = 4.5V, V- = -4.5V,

= ±2V, I

Signal-Path On-Resistance

R

ON

V

COM_

= 10mA

COM_

+25°C

C, E

Signal-Path On-Resistance Match

Between Channels (Note 4)

V+ = 4.5V, V- = -4.5V,

= ±2V, I

∆R

Ω

ON

V

COM_

Signal-Path On-Resistance

Flatness (Note 5)

V+ = 5V; V- = -5V; V

= 1V,

COM_

R

+25°C

0.3

2

Ω

FLAT(ON)

0V, -1V; I

= 10mA

COM

+25°C

C, E

-1

-10

-1

0.02

1

10

1

NO_, NC_ Off Leakage Current

(Note 6)

I

,

V+ = 5.5V, V- = -5.5V,

NO_(OFF)

nA

±

V

COM_

= ±4.5V, V =

N_

4.5V

NC_(OFF)

+25°C

C, E

0.02

0.04

COM_ Off Leakage Current

(Note 6)

V+ = 5.5V, V- = -5.5V,

= ±4.5V, V

I

COM_(OFF)

V

COM_

=

N_

-10

-2

10

2

+25°C

C, E

COM_ On Leakage Current

(Note 6)

V+ = 5.5V, V- = -5.5V,

I

COM_(ON)

V

COM_

= ±4.5V

-20

20

LOGIC INPUT

IN_ Input Logic Threshold High

IN_ Input Logic Threshold Low

V

C, E

1.5

2.4

1

V

IN_H

V

IN_L

0.8

-1

IN_ Input Current Logic High or

Low

I

, I

V

IN_

= 0.8V or 2.4V

C, E

0.03

µA

INH_ INL_

2

_______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

ELECTRICAL CHARACTERISTICS—Dual Supplies (continued)

(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, V

= 0.8V, V

= 2.4V, V

= 0V, T = T

to T

, unless otherwise noted. Typical

MAX

GND_

INL

INH

A

MIN

values are at T = +25°C.)

A

MIN

TYP

(Note 2)

MAX

PARAMETER

SYMBOL

CONDITIONS

T

UNITS

A

SWITCH DYNAMIC CHARACTERISTICS

+25°C

C, E

75

30

150

200

100

120

V

= ±3V, V+ = 5V, V- = -5V,

COM_

Turn-On Time

Turn-Off Time

t

ns

ON

Figure 3

+25°C

C, E

V

COM_

= ±3V, V+ = 5V, V- = -5V,

t

OFF

Figure 3

V = ±3V, V+ = 5V, V- = -5V,

COM_

Break-Before-Make Time Delay

(MAX4566/MAX4567 only)

t

+25°C

5

30

BBM

Q

Figure 4

Charge Injection

(Note 3)

C

= 1.0nF, V

= 0V, R = 0Ω,

S

NO_

L

+25°C

25

60

pC

pF

Figure 5

NO_, NC_ Off Capacitance

C

V

NO_

= GND, f = 1MHz, Figure 7

2.5

N_(OFF)

V

= 0V,

MAX4565

MAX4565,

MAX4566

COM_

COM_ Off Capacitance

C

f = 1MHz,

Figure 7

+25°C

2.5

pF

dB

COM_(OFF)

MAX4565

MAX4566

MAX4567

MAX4565

MAX4566

MAX4567

MAX4565

MAX4566

MAX4567

6

V

= V

= 0V,

COM_

NO_

COM_ On Capacitance

Off Isolation (Note 7)

C

6

COM_(ON)

f = 1MHz, Figure 7

7

-83

-82

-83

-92

-85

-87

350

R

= 50Ω,

L

V

ISO

V

COM_

= 1V

,

RMS

f = 10MHz, Figure 6

R

= 50Ω, V

=

COM_

L

Channel-to-Channel Crosstalk

(Note 8)

V

CT

1V

Figure 6

, f = 10MHz,

RMS

-3dB Bandwidth (Note 9)

Distortion

BW

Figure 6, R = 50Ω

+25°C

MHz

%

L

V

= 5Vp-p, f < 20kHz,

IN

THD+N

0.02

600Ω in and out

POWER SUPPLY

Power-Supply Range

V+, V-

I+

C, E

+25°C

C, E

-6

-1

+6

1

V

0.05

V+ Supply Current

V - Supply Current

V+ = 5.5V, all V = 0V or V+

IN_

µA

-10

-1

10

1

+25°C

C, E

I-

V- = -5.5V

µA

-10

10

_______________________________________________________________________________________

3

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(V+ = +4.5V to +5.5V, V- = 0V, V

= 0.8V, V

= 2.4V, V

= 0V, T = T

to T

, unless otherwise noted. Typical values are

MAX

GND_

INL

INH

A

MIN

at T = +25°C.)

A

MIN

TYP

(Note 2)

MAX

PARAMETER

SYMBOL

CONDITIONS

T

UNITS

A

ANALOG SWITCH

V

,

COM_

, V

Analog Signal Range

(Note 3)

V+ = 4.5V, V

+25°C

0

V+

V

Ω

V

NO_ NC_

+25°C

C, E

68

2

120

150

5

= 3.5V,

= 1V,

COM_

Signal-Path On-Resistance

R

ON

I

= 1mA

COM_

+25°C

C, E

Signal-Path On-Resistance

Match

V+ = 4.5V, V

= 1mA

∆R

Ω

ON

I

COM_

6

+25°C

C, E

-1

-10

-1

1

NO_, NC_ Off Leakage Current

(Notes 6, 10)

I

,

V+ = 5.5V, V

= 4.5V

NO_(OFF)

nA

V

N_

NC_(OFF)

10

1

+25°C

C, E

COM_ Off Leakage Current

(Notes 6, 10)

V+ = 5.5V, V

= 4.5V

= 1V,

I

COM_(OFF)

V

N_

-10

-2

10

2

+25°C

C, E

COM_ On Leakage Current

(Notes 6, 10)

I

V+ = 5.5V; V

= 1V, 4.5V

COM_(ON)

COM_

-20

20

LOGIC INPUT

IN_ Input Logic Threshold High

IN_ Input Logic Threshold Low

V

C, E

1.5

2.4

1

V

IN_H

V

IN_L

0.8

-1

IN_ Input Current Logic High or

Low

I

, I

V

IN_

= 0.8V or 2.4V

C, E

0.001

µA

INH_ INL_

SWITCH DYNAMIC CHARACTERISTICS

/MAX4567

+25°C

C, E

130

30

200

250

120

150

V

= 3V, V+ = 5V,

COM_

Turn-On Time

Turn-Off Time

t

ns

ON

Figure 3

+25°C

C, E

V

COM_

= 3V, V+ = 5V,

t

OFF

Figure 3

V = 3V, V+ = 5V,

COM_

Break-Before-Make Time Delay

(MAX4566/MAX4567 only)

t

+25°C

10

90

7

ns

BBM

Q

Figure 4

C

R

= 1.0nF, V = 2.5V,

NO

= 0Ω, Figure 5

L

S

Charge Injection

25

pC

R = 50Ω, f = 10MHz,

L

Off-Isolation

(Note 7)

V

ISO

V

COM_

= 1V ,

RMS

+25°C

-81

dB

Figure 6

R = 50Ω, f = 10MHz,

L

Channel-to-Channel Crosstalk

(Note 8)

V

CT

V

COM_

= 1V ,

RMS

MAX4567

+25°C

-86

320

0.05

dB

Figure 6

R

= 50Ω, Figure 6

-3dB Bandwidth (Note 9)

BW

I+

MHz

L

POWER SUPPLY

+25°C

C, E

-1

1

V+ Supply Current

V+ = 5.5V, all V = 0V or V+

µA

IN_

-10

10

4

_______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

ELECTRICAL CHARACTERISTICS—Single +3V Supply

(V+ = +2.7V to +3.6V, V- = 0V, V

= 0.8V, V

= 2.4V, V

= 0V, T = T

to T

, unless otherwise noted. Typical values are

MAX

GND_

INL

INH

A

MIN

at T = +25°C.)

A

MIN

TYP

(Note 2)

MAX

PARAMETER

SYMBOL

CONDITIONS

T

UNITS

A

ANALOG SWITCH

V

,

COM_

, V

Analog Signal Range

(Note 3)

V+ = 2.7V, V

+25°C

0

V+

V

NO_ NC_

+25°C

C, E

150

350

450

= 1V,

COM_

Signal-Path On-Resistance

R

Ω

ON

I

= 1mA

COM_

LOGIC INPUT

IN_ Input Logic Threshold High

IN_ Input Logic Threshold Low

V

(Note 3)

C, E

1.0

2.4

1

V

IN_H

V

IN_L

0.8

-1

IN_ Input Current Logic High or

Low

I

, I

V

= 0.8V or 2.4V (Note 3)

C, E

µA

INH_ INL_

IN_

SWITCH DYNAMIC CHARACTERISTICS (Note 3)

+25°C

C, E

270

40

500

600

100

120

V

= 1.5V, V+ = 2.7V,

COM_

Turn-On Time

Turn-Off Time

t

ns

ON

Figure 3 (Note 3)

+25°C

C, E

V

COM_

= 1.5V, V+ = 2.7V,

t

OFF

Figure 3 (Note 3)

V = 1.5V, V+ = 2.7V,

COM_

Break-Before-Make Time Delay

(MAX4566/MAX4567 only)

t

+25°C

10

120

BBM

I+

Figure 4 (Note 3)

POWER SUPPLY

+25°C

C, E

-1

0.05

1

V+ Supply Current

V+ = 3.6V, all V = 0V or V+

µA

IN_

-10

10

Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.

Note 3: Guaranteed by design.

Note 4: ∆R

= ∆R

- ∆R

.

ON(MIN)

ON

ON(MAX)

Note 5: Resistance flatness is defined as the difference between the maximum and the minimum value of on-resistance as mea-

sured over the specified analog signal range.

Note 6: Leakage parameters are 100% tested at the maximum rated hot temperature and guaranteed by correlation at +25°C.

Note 7: Off isolation = 20log [V

/ (V or V )], V

= output, V or V = input to off switch.

COM NC NO

10 COM

NC

NO

Note 8: Between any two switches.

Note 9: -3dB bandwidth is measured relative to 100kHz.

Note 10: Leakage testing for single-supply operation is guaranteed by testing with dual supplies.

_______________________________________________________________________________________

5

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V+ = +5V, V- = -5V, T = +25°C, GND = 0V, packages are surface mount, unless otherwise noted.)

A

ON-RESISTANCE vs. V

AND TEMPERATURE

(DUAL SUPPLIES)

COM

ON RESISTANCE vs. V

COM

(SINGLE SUPPLY)

(DUAL SUPPLIES)

1000

100

10

1000

100

10

65

55

45

V+ = 1.2V,

V- = -1.2V

T = +125°C

A

V+ = 2V

T = +85°C

A

V+ = 2V,

V- = -2V

V+ = 2.7V,

V- = -2.7V

V+ = 2.7V

V+ = 3.3V

T = +25°C

A

V+ = 5V

35

25

15

5

V+ = 7.5V

T = 0°C

A

T = -40°C

A

V+ = 10V

V+ = 3.3V,

V- = -3.3V

V+ = 5V,

V- = -5V

V- = 0V

0

1

2

3

4

5

6

7

8

9

10

-5 -4 -3 -2 -1

0

1

2

3

4

5

-5 -4 -3 -2 -1

0

1

2

3

4

5

V

COM

(V)

V

COM

(V)

V

COM

(V)

ON-RESISTANCE vs. V

COM

ON/OFF-LEAKAGE CURRENT vs.

TEMPERATURE

AND TEMPERATURE

(SINGLE SUPPLY)

CHARGE INJECTION vs. V

COM

10

1

60

50

40

30

20

10

0

130

110

90

T = +125°C

A

T = +85°C

A

ON LEAKAGE

OFF LEAKAGE

DUAL

0.1

/MAX4567

SUPPLIES

T = +25°C

A

70

0.01

0.001

0.0001

T = 0°C

A

SINGLE

SUPPLY

50

T = -55°C

A

30

-10

10

-5 -4 -3 -2 -1

V

0

1

2

3

4

5

-75 -50 -25

0

25 50 75 100 125

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(V)

COM

TEMPERATURE (°C)

V

COM

POWER-SUPPLY CURRENT

vs. TEMPERATURE

ON/OFF TIME vs.

SUPPLY VOLTAGE

ON/OFF TIME vs.

TEMPERATURE

1

250

200

150

100

50

110

100

90

80

70

60

50

40

30

20

10

t

ON

0.1

0.01

t

ON

I+

I-

0.001

t

OFF

t

ON

0.0001

0.00001

t

OFF

t

OFF

0

-75 -50 -25

0

25 50 75 100 125

±2

±3

±4

±5

±6

±8

-75 -50 -25

0

25 50 75 100 125

TEMPERATURE (°C)

V+, V- (V)

TEMPERATURE (°C)

6

_______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V+ = +5V, V- = -5V, T = +25°C, GND = 0V, packages are surface mount, unless otherwise noted.)

A

MAX4567

LOGIC-LEVEL THRESHOLD VOLTAGE vs.

V+ SUPPLY VOLTAGE

TOTAL HARMONIC DISTORTION

vs. FREQUENCY

100

10

3.0

2.5

2.0

1.5

1.0

0.5

0

V+ = +5V

V- = -5V

SIGNAL = 5Vp-p

600Ω IN AND OUT

1

0.1

0.01

10

100

1k

10k

100k

0

2

4

6

8

10

12

FREQUENCY (Hz)

V+ (V)

MAX4565

MAX4566

FREQUENCY RESPONSE

MAX14565 TOC11

MAX4565 TOC12

120

100

80

0

60

50

ON LOSS

-10

-20

-10

-20

-30

-40

-50

INSERTION LOSS (ON)

OPPOSITE

CHANNEL

CROSSTALK (ON)

40

60

30

-30

ADJACENT CHANNEL

CROSSTALK

40

20

-40

20

10

-50

ON PHASE

PHASE (ON)

0

-60

0

-60

-70

-20

-40

-60

-80

OFF

ISOLATION

-10

-20

-30

-40

-50

-60

-70

OFF ISOLATION

-80

-90

ADJACENT

CHANNEL

CROSSTALK

(ON)

OPPOSITE

CHANNEL

CROSSTALK

-100

-110

-120

-100

-120

-110

-120

1

10

100

1000

0

0.1

1

10

FREQUENCY (MHz)

100

1000

FREQUENCY (MHz)

MAX4567

FREQUENCY RESPONSE

100

80

ON LOSS

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

60

40

20

ON PHASE

0

-20

-40

-60

-80

OFF

ISOLATION

CROSSTALK

100

-100

1

10

1000

FREQUENCY (MHz)

_______________________________________________________________________________________

7

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION*

MAX4565

MAX4566

MAX4567

1, 10, 11,

20

1, 16

1, 9

IN_

Digital Control Input

3, 6, 8, 13,

15, 18

RF and Logic Ground. Grounds are not internally connected to each other,

and should all be connected to a ground plane (see Grounding section).

3, 7, 10, 14 4, 6, 12, 14

GND_

V+

16

5

12

5

7, 15

3, 11

Positive Supply-Voltage Input (analog and digital)

Negative Supply-Voltage Input. Connect to ground plane for single-supply

operation.

V-

4, 7, 14, 17

—

4, 13

6, 11

2, 16

8, 10

5, 13

NO_

NC_

Analog Switch Normally Open** Terminals

Analog Switch Normally Closed** Terminals

Analog Switch Common** Terminals

2, 9, 12, 19

2, 8, 9, 15

COM_

*

All pins have ESD diodes to V- and V+.

** NO_ (or NC_) and COM_ pins are identical and interchangeable. Either may be considered as an input or output; signals pass

equally well in either direction.

_______________Th e o ry o f Op e ra t io n

The MAX4565/MAX4566/MAX4567 are high-frequency

“T” switches. Each “T” switch consists of two series

NORMALLY OPEN SWITCH CONSTRUCTION

CMOS switches, with a third N-channel switch at the

N1

N2

COM_

NO_

D

S

D

S

junction that shunts capacitively-coupled signals to

ground when the series switches are off. This produces

s up e rior hig h-fre q ue nc y s ig na l is ola tion whe n the

switch is turned off.

/MAX4567

IN_ COM_ - NO_

P1

P2

0

1

OFF

ON

S

D

S

D

V+

Lo g ic -Le ve l Tra n s la t o rs

The MAX4565/MAX4566/MAX4567 are constructed as

high-frequency “T” switches, as shown in Figure 1. The

logic-level input, IN_, is translated by amplifier A1 into a

V+ to V- logic signal that drives amplifier A2. (Amplifier

A2 is a n inve rte r for norma lly c los e d s witc he s .)

Amplifier A2 drives the gates of N-channel MOSFETs

N1 and N2 from V+ to V-, turning them fully on or off.

The same signal drives inverter A3 (which drives the

P-channel MOSFETs P1 and P2) from V+ to V-, turning

them fully on or off, and drives the N-channel MOSFET

N3 off and on.

D

A1

A2

A3

IN_

N3

S

GND_

V-

V+

ESD DIODES

ON GND_, IN_,

COM_, NO_, AND NC_

A2

(NC)

V-

Figure 1. T-Switch Construction

The log ic -le ve l thre s hold is d e te rmine d b y V+ a nd

GND_. The volta g e on GND_ is us ua lly a t g round

potential, but it may be set to any voltage between

(V+ - 2V) and V-. When the voltage between V+ and

GND_ is less than 2V, the level translators become very

slow and unreliable. Since individual switches in each

package have individual GND_ pins, they may be set to

different voltages. Normally, however, they should all

be connected to the ground plane.

S w it c h On Co n d it io n

When the switch is on, MOSFETs N1, N2, P1, and P2

are on and MOSFET N3 is off. The signal path is COM_

to NO_, and because both N-channel and P-channel

MOSFETs act as pure resistances, it is symmetrical

(i.e ., s ig na ls ma y p a s s in e ithe r d ire c tion). The off

MOSFET, N3, has no DC conduction, but has a small

8

_______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

a mount of c a p a c ita nc e to GND_. The four on

leakages vary as the signal varies. The difference in the

two diode leakages from the signal path to the V+ and

V- pins constitutes the analog signal-path leakage cur-

rent. All analog leakage current flows to the supply ter-

minals, not to the other switch terminal. This explains

how both sides of a given switch can show leakage

currents of either the same or opposite polarity.

MOSFETs a ls o ha ve c a p a c ita nc e to g round tha t,

together with the series resistance, forms a lowpass fil-

ter. All of these capacitances are distributed evenly

along the series resistance, so they act as a transmis-

sion line rather than a simple R-C filter. This helps to

explain the exceptional 350MHz bandwidth when the

switches are on.

The re is no c onne c tion b e twe e n the a na log s ig na l

paths and GND. The analog signal paths consist of an

N-channel and P-channel MOSFET with their sources

and drains paralleled and their gates driven out of

phase with V+ and V- by the logic-level translators.

Typical attenuation in 50Ω systems is -2.5dB and is

reasonably flat up to 300MHz. Higher-impedance cir-

cuits show even lower attenuation (and vice versa), but

slightly lower bandwidth due to the increased effect of

the internal and external capacitance and the switch’s

internal resistance.

V+ and GND power the internal logic and logic-level

translators, and set the input logic thresholds. The

log ic -le ve l tra ns la tors c onve rt the log ic le ve ls to

switched V+ and V- signals to drive the gates of the

analog switches. This drive signal is the only connec-

tion between the logic supplies and the analog sup-

plies. All pins have ESD protection to V+ and to V-.

The MAX4565/MAX4566/MAX4567 are optimized for

±5V operation. Using lower supply voltages or a single

supply increases switching time, increases on-resis-

tance (and therefore on-state attenuation), and increas-

es nonlinearity.

Increasing V- has no effect on the logic-level thresh-

olds, but it does increase the drive to the P-channel

switches, reducing their on-resistance. V- also sets the

negative limit of the analog signal voltage.

S w it c h Off Co n d it io n

When the switch is off, MOSFETs N1, N2, P1, and P2

a re off a nd MOSFET N3 is on. The s ig na l p a th is

through the off-capacitances of the series MOSFETs,

but it is shunted to ground by N3. This forms a high-

pass filter whose exact characteristics are dependent

on the source and load impedances. In 50Ω systems,

and below 10MHz, the attenuation can exceed 80dB.

This value decreases with increasing frequency and

increasing circuit impedances. External capacitance

and board layout have a major role in determining over-

all performance.

The logic-level thresholds are CMOS and TTL compati-

ble when V+ is +5V. As V+ is raised, the threshold

increases slightly; when V+ reaches +12V, the level

threshold is about 3.1V, which is above the TTL output

high-level minimum of 2.8V, but still compatible with

CMOS outputs.

Bipolar-Supply Operation

The MAX4565/MAX4566/MAX4567 operate with bipolar

supplies between ±2.7V and ±6V. The V+ and V- sup-

plies need not be symmetrical, but their sum cannot

exceed the absolute maximum rating of 13.0V. Do not

connect the MAX4565/MAX4566/MAX4567 V+ pin to

+3V and connect the logic-level input pins to TTL

logic-level signals. TTL logic-level outputs can

exceed the absolute maximum ratings, causing

damage to the part and/or external circuits.

__________Ap p lic a t io n s In fo rm a t io n

P o w e r-S u p p ly Co n s id e ra t io n s

Overview

The MAX4565/MAX4566/MAX4567 construction is typi-

cal of most CMOS analog switches. It has three supply

pins: V+, V-, and GND. V+ and V- are used to drive the

internal CMOS switches and set the limits of the analog

voltage on any switch. Reverse ESD protection diodes

are internally connected between each analog signal

p in a nd b oth V+ a nd V-. If the volta g e on a ny p in

exceeds V+ or V-, one of these diodes will conduct.

During normal operation these reverse-biased ESD

diodes leak, forming the only current drawn from V-.

CAUTION:

The absolute maximum V+ to V- differential

voltage is 13.0V. Typical “±6-Volt” or “12-Volt”

supplies with ±10% tolerances can be as high

as 13.2V. This voltage can damage the

MAX4565/MAX4566/MAX4567. Even ±5% toler-

ance supplies may have overshoot or noise

spikes that exceed 13.0V.

Virtually all the analog leakage current is through the

ESD diodes. Although the ESD diodes on a given sig-

nal pin are identical, and therefore fairly well balanced,

they are reverse biased differently. Each is biased by

either V+ or V- and the analog signal. This means their

_______________________________________________________________________________________

9

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

Single-Supply Operation

The MAX4565/MAX4566/MAX4567 operate from a sin-

gle supply between +2.7V and +12V when V- is con-

nected to GND. All of the bipolar precautions must be

observed. Note, however, that these parts are opti-

mized for ±5V operation, and most AC and DC charac-

teristics are degraded significantly when departing

from ±5V. As the overall supply voltage (V+ to V-) is

lowered, switching speed, on-resistance, off isolation,

and distortion are degraded. (See Typical Operating

Characteristics.)

not a normal logic signal. (The GND_ voltages cannot

exceed (V+ - 2V) or V-.) Elevating GND_ reduces off

isolation. For example, using the MAX4565, if GND2–

GND6 are connected to 0V and GND1 is connected to

V-, then switches 2, 3, and 4 would be TTL/CMOS com-

patible, but switch 1 (IN1) could be driven with the rail-

to-rail output of an op amp operating from V+ and V-.

Note, however, that IN_ can be driven more negative

than GND_, as far as V-. GND_ does not have to be

re move d from 0V whe n IN_ is d rive n from b ip ola r

sources, but the voltage on IN_ should never exceed V-.

GND_ should be separated from 0V only if the logic-

level threshold has to be changed.

Single-supply operation also limits signal levels and

interferes with grounded signals. When V- = 0V, AC sig-

nals are limited to -0.3V. Voltages below -0.3V can be

clipped by the internal ESD-protection diodes, and the

parts can be damaged if excessive current flows.

Any GND_ p in not c onne c te d to 0V s hould b e

bypassed to the ground plane with a surface-mount

10nF capacitor to maintain good RF grounding. DC

current in the IN_ and GND_ pins is less than 1nA, but

increases with switching frequency.

Power Off

When power to the MAX4565/MAX4566/MAX4567 is off

(i.e., V+ = 0V and V- = 0V), the Absolute Maximum

Ratings still apply. This means that neither logic-level

inputs on IN_ nor signals on COM_, NO_, or NC_ can

exceed ±0.3V. Voltages beyond ±0.3V cause the inter-

nal ESD-protection diodes to conduct, and the parts

can be damaged if excessive current flows.

On the MAX4565 only, two extra ground pins—GND5

a nd GND6—a re p rovid e d to imp rove is ola tion a nd

crosstalk. They are not connected to the logic-level cir-

cuit. These pins should always be connected to the

ground plane with solid copper.

AC Ground and Bypassing

A ground plane is mandatory for satisfactory high-

frequency operation. (Prototyping using hand wiring or

wire-wrap boards is strongly discouraged.) Connect all

0V GND_ pins to the ground plane with solid copper.

(The GND_ pins extend the high-frequency ground

through the package wire-frame, into the silicon itself,

thus improving isolation.) The ground plane should be

solid metal underneath the device, without interruptions.

There should be no traces under the device itself. For

DIP packages, this applies to both sides of a two-

sided board. Failure to observe this will have a minimal

effect on the “on” characteristics of the switch at high

frequencies, but it will degrade the off isolation and

crosstalk.

Gro u n d in g

DC Ground Considerations

Satisfactory high-frequency operation requires that

careful consideration be given to grounding. For most

applications, a ground plane is strongly recom-

mended, and all GND_ pins should be connected to

it with solid copper. While the V+ and V- power-supply

pins are common to all switches in a given package,

each switch has separate ground pins that are not

internally connected to each other. This contributes to

the overall high-frequency performance and provides

added flexibility in some applications, but it can cause

problems if it is overlooked. All the GND_ pins have

ESD diodes to V+ and V-.

/MAX4567

Bypass all V+ and V- pins to the ground plane with sur-

face-mount 10nF capacitors. For DIP packages, mount

the capacitors as close as possible to the pins on the

s a me s id e of the b oa rd a s the d e vic e . Do not us e

feedthroughs or vias for bypass capacitors.

In systems that have separate digital and analog (sig-

nal) grounds, connect these switch GND_ pins to ana-

log ground. Preserving a good signal ground is much

more important than preserving a digital ground.

The logic-level inputs, IN_, have voltage thresholds

determined by V+ and GND_. (V- does not influence

the logic-level threshold.) With +5V and 0V applied to

V+ and GND_, the threshold is about 1.6V, ensuring

compatibility with TTL- and CMOS-logic drivers.

For s urfa c e -mount p a c ka g e s , b yp a s s c a p a c itors

should be mounted on the opposite side of the board

from the device. In this case, use short feedthroughs or

vias, directly under the V+ and V- pins. Any GND_ pin

not connected to 0V should be similarly bypassed. If V-

is 0V, connect it directly to the ground plane with solid

copper. Keep all leads short.

The various GND_ pins can be connected to separate

voltage potentials if any or all of the logic-level inputs is

10 ______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

The MAX4567 has two V+ and two V- pins. Make DC

S ig n a l Ro u t in g

Keep all signal leads as short as possible. Separate all

signal leads from each other and other traces with the

ground plane on both sides of the board. Where possible,

use coaxial cable instead of printed circuit board traces.

connections to only one of each to minimize crosstalk.

Do not route DC current into one of the V+ or V- pins

and out the other V+ or V- pin to other devices. The

second set of V+ and V- pins is for AC bypassing only.

For dual-supply operation, the MAX4567 should have

four 10nF bypass capacitors connected to each V+

and V- pin as close to the package as possible. For sin-

gle-supply operation, the MAX4567 should have two

10nF bypass capacitors connected (one to each V+

pin) as close to the package as possible.

Bo a rd La yo u t

IC sockets degrade high-frequency performance and

should not be used if signal bandwidth exceeds 5MHz.

Surfa c e -mount p a rts , ha ving s horte r inte rna l le a d

frames, provide the best high-frequency performance.

Keep all bypass capacitors close to the device, and

separate all signal leads with ground planes. Such

grounds tend to be wedge-shaped as they get closer to

the device. Use vias to connect the ground planes on

each side of the board, and place the vias in the apex of

the wedge-shaped grounds that separate signal leads.

Logic-level signal lead placement is not critical.

On the MAX4565, GND5 and GND6 should always be

connected to the ground plane with solid copper to

improve isolation and crosstalk.

V+

10nF

V+

GND5

1

2

OUT

1

GND6 MAX4565

2

COM1

GND1

MAX4565

3

4

3

NO1

1

2

OUT

4

50/75Ω

OUT/IN

COM2

GND2

NO2

NO3

NO4

3

4

MAX4565

COM3

GND3

50/75Ω

OUT/IN

ADDRESS

DECODING

COM4

GND4

IN1

IN2

IN3

IN4

IN1

IN2

IN3

IN4

OUT

1

2

5

TO

6

ADDITIONAL

MUXES

MAX4565

3

4

7

8

V-

10nF

Figure 2. 4-Channel Multiplexer

______________________________________________________________________________________ 11

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

Stray capacitance of traces and the output capacitance

Mu lt ip le x e r

With its excellent off isolation, the MAX4565 is ideal for

us e in hig h-fre q ue nc y vid e o multip le xe rs . Fig ure 2

shows such an application for switching any one of four

video inputs to a single output. The same circuit may

be used as a demultiplexer by simply reversing the sig-

nal direction.

of switches placed in parallel reduces bandwidth, so the

outputs of no more than four individual switches should

be placed in parallel to maintain a high bandwidth. If

more than four mux channels are needed, the 4-channel

circuit should be duplicated and cascaded.

______________________________________________Te s t Circ u it s /Tim in g Dia g ra m s

+5V

10nF

V+

0V

V+

V

IN_

50%

NO_OR NC_

3V

MAX4565

MAX4566

MAX4567

90%

V

IN_

V

OUT

IN_

COM_

V-

V

OUT

90%

GND_

0V

R = 300Ω

L

t

ON

OFF

50Ω

10nF

-5V

ALL GND_ PINS ARE CONNECTED TO GROUND PLANE (OV).

REPEAT TEST FOR EACH SWITCH.

V- IS CONNECTED TO GND (OV) FOR SINGLE-SUPPLY OPERATION.

/MAX4567

Figure 3. Switching Time

12 ______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

_________________________________Te s t Circ u it s /Tim in g Dia g ra m s (c o n t in u e d )

10nF +5V

V+

* COM3

* COM2

3V

MAX4566

* N02

* NC3

V

IN_

V

OUT

t

< 20ns

R

V+

0V

GND_

V-

t < 20ns

F

50%

V

IN_

R = 300Ω

L

50Ω

10nF

-5V

80%

* REPEAT TEST FOR OTHER PAIR OF SWITCHES.

10nF +5V

V

OUT

0V

t

BBM

V+

**NC_

**NO_

1V

ALL GND_ PINS ARE CONNECTED TO GROUND PLANE (OV).

V+ IS CONNECTED TO GND (OV) FOR SINGLE-SUPPLY OPERATION.

MAX4567

V

IN_

**COM_

V-

V

OUT

GND_

R = 300Ω

L

50Ω

10nF

-5V

** REPEAT TEST FOR OTHER SWITCH.

Figure 4. Break-Before-Make Interval (MAX4566/MAX4567 only)

______________________________________________________________________________________ 13

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

_________________________________Te s t Circ u it s /Tim in g Dia g ra m s (c o n t in u e d )

10nF

+5V

V+

0V

V

IN_

NO_ OR NC_

V

NO

= 0V

MAX4565

MAX4566

MAX4567

V

IN_

V

OUT

∆V

OUT

IN_

COM_

V

OUT

GND_

V-

C = 1000pF

L

50Ω

10nF

∆V IS THE MEASURED VOLTAGE DUE TO CHARGE TRANSFER

ERROR Q WHEN THE CHANNEL TURNS OFF.

OUT

-5V

Q = ∆V x C

OUT

L

V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.

Figure 5. Charge Injection

10nF

+5V

V+

/MAX4567

V

OUT

OFF ISOLATION = 20log

ON LOSS = 20log

IN

NETWORK

ANALYZER

V

50Ω

OUT

V

IN

0V OR V+

IN_

V

IN

NO_

V

OUT

MAX4565

MAX4566

MAX4567

CROSSTALK = 20log

IN

MEAS

REF

V

OUT

COM_

GND_

V-

50Ω

-5V

10nF

MEASUREMENTS ARE STANDARDIZED AGAINST SHORT AT IC TERMINALS.

OFF ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH.

ON LOSS IS MEASURED BETWEEN COM_ AND "ON" NO_ OR NC_TERMINAL ON EACH SWITCH.

CROSSTALK IS MEASURED FROM ONE CHANNEL TO ALL OTHER CHANNELS.

SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.

V- IS CONNECTED TO GND (0V) FOR SINGLE-SUPPLY OPERATION.

Figure 6. On Loss, Off Isolation, and Crosstalk

14 ______________________________________________________________________________________

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

/MAX4567

Te s t Circ u it s /Tim in g

______________Dia g ra m s (c o n t in u e d )

_________________Ch ip To p o g ra p h ie s

MAX4565

10nF +5V

V+

COM1 IN1 IN2 COM2

0V OR V+

IN_

NO_

NC_

N.C.

GND2

MAX4565

MAX4566

MAX4567

GND1

NO1

NO2

V+

1MHz

CAPACITANCE

ANALYZER

COM_

0.082"

GND6

V-

(2.08mm)

GND_

V-

GND5

NO4

NO3

10nF

GND3

N.C.

GND4

-5V

ALL GND_ PINS ARE CONNECTED TO GROUND PLANE (0V).

COM4 IN4 IN3

COM3

Figure 7. NO_, NC_, COM_ Capacitance

0.072"

(1.83mm)

MAX4566

MAX4567

NO1 IN1 NO2 V+

COM1 IN1 IN2 COM2

V-

N.C.

GND2

N.C.

GND2

NO2

GND1

N.C.

NO1

V-

N.C.

V+

0.082"

COM2

N.C.

(2.08mm)

COM1

N.C.

NC4

N.C.

NC3

GND3

V-

N.C.

GND4

N.C.

V+ NC1 IN2

NC2

GND4 COM4 COM3

GND3

0.072"

(1.83mm)

TRANSISTOR COUNT: 257

SUBSTRATE INTERNALLY CONNECTED TO V+

______________________________________________________________________________________ 15

Qu a d /Du a l, Lo w -Vo lt a g e ,

Bid ire c t io n a l RF/Vid e o S w it c h e s

___________________________________________Ord e rin g In fo rm a t io n (c o n t in u e d )

PART

TEMP. RANGE

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

20 SSOP

PART

TEMP. RANGE

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

PIN-PACKAGE

16 QSOP

MAX4565CAP

MAX4565C/D

MAX4565EPP

MAX4565EWP

MAX4565EAP

MAX4566CPE

MAX4566CSE

MAX4566CEE

MAX4566C/D

MAX4566EPE

MAX4566ESE

MAX4566EEE

MAX4567CPE

MAX4567CSE

MAX4567CEE

MAX4567C/D

MAX4567EPE

MAX4567ESE

MAX4567EEE

Dice*

16 Plastic DIP

16 Narrow SO

16 QSOP

20 Plastic DIP

20 Wide SO

20 SSOP

Dice*

16 Plastic DIP

16 Narrow SO

16 QSOP

16 Plastic DIP

16 Narrow SO

16 QSOP

Dice*

*Contact factory for dice specifications.

16 Plastic DIP

16 Narrow SO

________________________________________________________P a c k a g e In fo rm a t io n

/MAX4567

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX4567CEE
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Quad/Dual, Low-Voltage, Bidirectional RF/Video Switches 四核/双通道，低电压，双向RF /视频开关复用器开关复用器或开关信号电路光电二极管
文件：	总16页 (文件大小：169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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