MAX456CQH-TD [MAXIM]
Cross Point Switch, 1 Func, 8 Channel, CMOS, PQCC44, PLASTIC, LCC-44;
| 型号： | MAX456CQH-TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Cross Point Switch, 1 Func, 8 Channel, CMOS, PQCC44, PLASTIC, LCC-44 开关 |
| 文件： | 总12页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2858; Rev 2; 2/94
8 x 8 Vid e o Cro s s p o in t S w it c h
MAX456
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ Routes Any Input Channel to Any Output Channel
♦ Switches Standard Video Signals
The MAX456 is the first monolithic CMOS 8 x 8 video
crosspoint switch that significantly reduces component
count, board space, and cost. The crosspoint switch
contains a digitally controlled matrix of 64 T-switches
that connect eight video input signals to any, or all, out-
put channels. Each matrix output connects to eight
internal, high-speed (250V/µs), unity-gain-stable buffers
capable of driving 400Ω and 20pF to ±1.3V. For appli-
c a tions re q uiring inc re a s e d d rive c a p a b ility, the
MAX456 outp uts c a n b e c onne c te d d ire c tly to two
MAX470 quad, gain-of-two video buffers, which are
capable of driving 75Ω loads.
♦ Serial or Parallel Digital Interface
♦ Expandable for Larger Switch Matrices
♦ 80dB All-Channel Off Isolation at 5MHz
♦ 8 Internal Buffers with:
250V/µs Slew Rate, Three-State Output Capability,
Power-Saving Disable Feature, 35MHz Bandwidth
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
PIN-PACKAGE
40 Plastic DIP
44 PLCC
Three-state output capability and internal, programma-
ble active loads make it feasible to parallel multiple
MAX456s and form larger switch matrices.
MAX456CPL
MAX456CQH
MAX456C/D
Dice*
In the 40-pin DIP package, crosstalk (70dB at 5MHz) is
minimized, and board area and complexity are simpli-
fied by using a straight-through pinout. The analog
inputs and outputs are on opposite sides, and each
channel is separated by a power-supply line or quiet
digital logic line.
Ordering Information continued on last page.
* Dice are specified at TA = +25°C, DC parameters only.
_________________P in Co n fig u ra t io n s
TOP VIEW
________________________Ap p lic a t io n s
Video Test Equipment
D1/SER OUT
V+
1
2
40
39
38
37
36
35
34
33
32
31
D0/SER IN
OUT0
D2
Video Security Systems
A2
A1
3
Video Editing
OUT1
D3
4
MAX456
IN0
A0
5
________Typ ic a l Ap p lic a t io n Circ u it
OUT2
V-
6
8 INPUT CHANNELS
IN1
7
LOAD
IN2
MAX470
OUT3
AGND
OUT4
AGND
OUT5
AGND
OUT6
V+
8
A = 2
V
75Ω
9
WR
DGND
10
11
12
13
14
15
16
17
18
19
20
LATCH
75Ω
IN3
DGND
30
29
28
27
26
25
24
23
22
21
MAX456
IN4
A2
A1
EDGE/LEVEL
OUTPUT
SELECT
A0
IN5
V+
8 X 8
OUT7
CE
T-SWITCH
MATRIX
IN6
INPUT
SELECT
OR
SERIAL
I/O
D3
D2
SER/PAR
IN7
CE
D1/SER OUT
D0/SER IN
LATCH
WR
V-
A = 2
V
MAX470
DIP
PLCC on last page
________________________________________________________________ Maxim Integrated Products
1
Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .
8 x 8 Vid e o Cro s s p o in t S w it c h
ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V+ to V-) ...........................................+12V
Positive Supply Voltage V+ Referred to AGND......-0.3V to +12V
Negative Supply Voltage V- Referred to AGND.....-12V to +0.3V
DGND Voltage .........................................................AGND ±0.3V
Buffer Short Circuit to Ground when
Continuous Power Dissipation (T = +70°C)
40-Pin Plastic DIP (derate 11.3mW/°C above +70°C)....889mW
40-Pin CERDIP (derate 20.0mW/°C above +70°C)....1600mW
44-Pin PLCC (derate 13.3mW/°C above +70°C) .......1066mW
Operating Temperature Ranges:
A
Not Exceeding Package Power Dissipation .............Indefinite
Analog Input Voltage ............................(V+ + 0.3V) to (V- - 0.3V)
Digital Input Voltage .............................(V+ + 0.3V) to (V- - 0.3V)
Input Current, Power On or Off
MAX456C _ _ ......................................................0°C to +70°C
MAX456E _ _ ...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10 sec) ............................+300°C
MAX456
Digital Inputs.................................................................±20mA
Analog Inputs ...............................................................±50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = 5.0V, V- = -5.0V, -1.3V ≤ V ≤ +1.3V; LOAD = +5V; internal load resistors on; AGND = DGND = 0V; T = +25°C,
IN
A
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range
-1.3
1.3
V
Internal load
resistors on, no
external load,
T
= +25°C
0.99
0.98
1.0
1.0
1.01
1.02
A
Voltage Gain
V/V
T
A
= T
to T
MIN MAX
V
IN
= 0V to 1V
T
= +25°C
±7
A
Buffer Offset Voltage
mV
T
A
= T
to T
MAX
±12
MIN
Offset Voltage Drift
T
= T
to T
MAX
20
39
µV/°C
V
A
MIN
Operating Supply Voltage
±4.5
±5.5
45
T
A
= +25°C
Supply Current, All Buffers On
(No External Load)
mA
mA
T
A
= T
MIN
to T
MAX
60
T
A
= +25°C
1.5
3.0
4
Supply Current, All Buffers Off
T
A
= T
MIN MAX
to T
Power-Supply Rejection Ratio
Analog Input Current
±4.5V to ±5.5V, DC measurement
= T to T
50
64
dB
nA
T
A
±0.1
±10
MIN
MAX
Internal load resistors off, all buffers
Output Leakage Current
±100
nA
off, T = T
to T
MAX
A
MIN
T
= +25°C
250
200
400
10
600
765
A
Internal Amplifier Load Resistor
(LOAD Pin = 5V)
Ω
T
A
= T
to T
MIN MAX
Buffer Output Voltage Swing
Digital Input Current
Internal load resistors on, no external load
= T to T
±1.3
V
µA
Ω
T
A
±1
0.8
0.4
MIN
MAX
Output Impedance at DC
Input Logic Low Threshold
Input Logic High Threshold
SER OUT Output Logic Low
SER OUT Output Logic High
V
2.4
4
V
I
= 1.6mA
= -0.4mA
Serial mode,
–——–
SER/PAR = 5V
OL
V
I
OH
2
_______________________________________________________________________________________
8 x 8 Vid e o Cro s s p o in t S w it c h
MAX456
ELECTRICAL CHARACTERISTICS
(V+ = 5.0V, V- = -5.0V, -1.3V ≤ V ≤ +1.3V, LOAD = +5V, internal load resistors on, AGND = DGND = 0V, T = +25°C,
IN
A
unless otherwise noted.)
PARAMETER
CONDITIONS
MIN
60
TYP
MAX
UNITS
DYNAMIC SPECIFICATIONS (Note 1)
Output-Buffer Slew Rate
Single-Channel Crosstalk
All-Channel Crosstalk
All-Channel Off Isolation
-3dB Bandwidth
Internal load resistors on, 10pF load
250
70
57
80
35
1.0
0.5
0.3
6
V/µs
dB
5MHz, V = 2V (Note 2)
IN
P-P
5MHz, V = 2V (Notes 2, 3)
dB
IN
P-P
5MHz, V = 2V (Note 2)
dB
IN
P-P
10pF load, V = 2V (Note 2)
25
MHz
deg
%
IN
P-P
Differential Phase Error
Differential Gain Error
Input Noise
(Note 4)
(Note 4)
DC to 40MHz
1.0
mV
RMS
Input Capacitance
All buffer inputs grounded
pF
Additional capacitance for each out-
put buffer connected to channel input
Buffer Input Capacitance
Output Capacitance
2
7
pF
pF
Output buffer off
SWITCHING CHARACTERISTICS (Note 1)
(Fig ure 4, V+ = 5.0V, V- = -5.0V, -1.3V ≤ V ≤ + 1.3V, LOAD = + 5V, inte rna l loa d re s is tors on, AGND = DGND = 0V,
IN
T
A
= T
to T , unless otherwise noted.)
MAX
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
ns
Chip-Enable to Write Setup
Write Pulse Width High
Write Pulse Width Low
t
CE
t
80
80
240
160
0
ns
WH
t
ns
WL
Parallel mode
32-bit serial mode
Data Setup
t
DS
ns
Data Hold
t
ns
ns
ns
ns
ns
ns
DH
Latch Pulse Width
t
L
80
80
Latch Delay
t
D
Switch Break-Before-Make Delay
LATCH Edge to Switch Off
LATCH Edge to Switch On
t
t
15
35
50
ON - OFF
t
LATCH on
OFF
t
ON
Note 1: Guaranteed by design.
Note 2: See Dynamic Test Circuits on page 11.
Note 3: 3dB typical crosstalk improvement when R = 0Ω.
S
Note 4: Input test signal: 3.58MHz sine wave of amplitude 40IRE superimposed on a linear ramp (0 to 100IRE). IRE is a unit of
video-signal amplitude developed by the International Radio Engineers. 140IRE = 1.0V.
_______________________________________________________________________________________
3
8 x 8 Vid e o Cro s s p o in t S w it c h
______________________________________________________________P in De s c rip t io n
PIN
NAME
N.C.
FUNCTION
DIP
PLCC
—
1, 12, 23, 34
No connect. Not internally connected.
——–
Parallel Data Bit D1 when SER/PAR = 0V. Serial Output for cascading
——–
1
2
D1/SER OUT
multiple parts when SER/PAR = 5V.
MAX456
——–
Parallel Data Bit D0 when SER/PAR = 0V. A Serial Input when
SER/PAR = 5V.
2
3
D0/SER IN
A2, A1, A0
IN0–IN7
——–
3, 4, 6
4, 5, 7
Output Buffer Address Lines
Video lnput Lines
5, 7, 9, 11,
13, 15, 17, 19
6, 8, 10, 13,
15, 17, 19, 21
Asynchronous control line. When LOAD = 1, all the 400Ω internal active
loads are on. When LOAD = 0, external 400Ω loads must be used. The
buffers MUST have a resistive load to maintain stability.
8
9
LOAD
DGND
Digital Ground Pins. Both DGND pins must have the same potential and
be bypassed to AGND. DGND should be within ±0.3V of AGND.
10, 12
11, 14
When this control line is high, the 2nd-rank registers are loaded with the
rising edge of the LATCH line. If this control line is low, the 2nd-rank reg-
isters are transparant when LATCH is low, passing data directly from the
1st-rank registers to the decoders.
–————–
14
16
EDGE/LEVEL
All V+ pins must be tied to each other and bypassed to AGND
separately (Figure 2).
16, 26, 40
18
18, 29, 44
20
V+
——–
SER/PAR
5V = 32-Bit Serial, 0V = 7-Bit Parallel
Both V- pins must be tied to each other and bypassed to AGND
separately (Figure 2).
20, 34
22, 38
V-
WRITE in the serial mode, shifts data in. In the parallel mode, WR loads
data into the 1st-rank registers. Data is latched on the rising edge.
21
24
WR
–————–
If EDGE/LEVEL = 5V, data is loaded from the 1st-rank registers to the 2nd-
–————–
rank registers on the rising edge of LATCH. If EDGE/LEVEL = 0V, data is
22
25
LATCH
loaded while LATCH = 0V. In addition, data is loaded during the execution
of parallel-mode functions 1011 through 1110, or if LATCH = 5V during the
execution of the parallel-mode "software-LATCH" command (1111).
—–
–——————————–
–—–
23
24
26
27
CE
Chip Enable. When CE = 0V and CE = 5V, the WR line is enabled.
–—–
CE
Chip Enable. When CE = 0V and CE = 5V, the WR line is enabled.
25, 27, 29, 31,
33, 35, 37, 39
28, 30, 32, 35,
37, 39, 41, 43
OUT7-OUT0
Output Buffers 7-0 (Note 1)
Analog Ground must be at 0.0V since the gain resistors of the buffers are
tied to these 3 pins.
28, 30, 32
31, 33, 36
AGND
–——–
Parallel Data Bit D3 when SER/ PAR = 0V. When D3 = 0V, D0-D2 specifies
36
38
40
42
D3
D2
the input channel to be connected to buffer. When D3 = 5V, then D0-D2
–——–
specify control codes. D3 is not used when SER/PAR = 5V.
–——–
Parallel Data Bit D2 when SER/ PAR = 0V. Not used when
–——–
SER/ PAR = 5V.
Note 1: Buffer inputs are internally grounded with a 1000 or 1001 command from the D3-D0 lines. AGND must be at 0.0V since the
gain setting resistors of the buffers are internally tied to AGND.
4
_______________________________________________________________________________________
8 x 8 Vid e o Cro s s p o in t S w it c h
MAX456
_______________De t a ile d De s c rip t io n
___________________Dig it a l In t e rfa c e
The desired switch state can be loaded in a 7-bit paral-
lel-interface mode or 32-bit serial-interface mode (see
Table 3 and Figures 4-6). All action associated with the
Ou t p u t Bu ffe rs
The MAX456 video crosspoint switch consists of 64
T-switches in an 8 x 8 grid (Figure 1). The 8 matrix out-
puts are followed by 8 wideband buffers optimized for
driving 400Ω and 20pF loads. Each buffer has an
internal active load on the output that can be readily
shut off via the LOAD input (off when LOAD = 0V). The
shut-off is useful when two or more MAX456 circuits are
connected in parallel to create more input channels.
With more input channels, only one set of buffers can
be active and only one set of loads can be driven.
And , whe n a c tive , the b uffe r mus t ha ve e ithe r
1) an internal load, 2) the internal load of another buffer
in another MAX456, or 3) an external load.
WR line occurs on its rising edge. The same is true for
–————–
the LATCH line if EDGE/LEVEL is high. Otherwise, the
s e c ond -ra nk re g is te rs up d a te while LATCH is low
–————–
(when EDGE/LEVEL is low). WR is logically ANDed with
–—–
CE a nd CE to a llow a c tive -hig h or a c tive -low c hip
enable.
7 -Bit P a ra lle l Mo d e
In the parallel-interface mode, the 7 data bits A2-A0
and D3-D0 specify an output channel (A2-A0) and the
input channel to which it connects (D3-D0). The data is
loaded on the rising edge of WR. The 8 input channels
a re s e le c te d b y 0000 throug h 0111 (D3-D0). The
remaining 8 codes (1000-1111) control other MAX456
functions, as listed in Table 1.
Each MAX456 output can be disabled under logic con-
trol. When a buffer is disabled, its output enters a high-
impedance state. In multichip parallel applications, the
disable function prevents inactive outputs from loading
lines driven by other devices. Disabling the inactive
buffers reduces power consumption.
3 2 -Bit S e ria l-In t e rfa c e Mo d e
–——–
In serial mode (SER/PAR = high), all first-rank registers
are loaded with data, making it unnecessary to specify
an output address (A2, A1, A0). The input data format
is D3-D0, starting with OUT0 and ending with OUT7 for
32 total bits. Only codes 0000 through 1010 are valid.
Code 1010 disables a buffer, while code 1001 enables
it. After data is shifted into the 32-bit first-rank register,
it is transferred to the second rank by the LATCH line
(see Table 2).
The MAX456 outputs connect easily to MAX470 quad,
gain-of-two buffers when 75Ω loads must be driven.
P o w e r-On RES ET
The MAX456 has an internal power-on reset (POR) cir-
cuit that remains low for 5µs when power is applied.
POR also remains low if the total supply voltage is less
than 4V. The POR disables all buffer outputs at
power-up, but the switch matrix is not preset to any ini-
tial condition. The desired switch state should be pro-
grammed before the buffer outputs are enabled.
_______________________________________________________________________________________
5
8 x 8 Vid e o Cro s s p o in t S w it c h
Table 1. Parallel-Interface Mode Functions
A2-A0
D3-D0
FUNCTION
0000 to 0111
Connect the buffer selected by A2-A0 to the input channel selected by D3-D0.
Connect the buffer selected by A2-A0 to DGND. Note, if the buffer output is on, its output
is its offset voltage.
1000
1011
1100
1101
1110
MAX456
Shut off the buffer selected by A2-A0, and retain 2nd-rank contents.
Turn on the buffer selected by A2-A0, or restore the previously connected channel.
Turn off all buffers, or leave 2nd-rank registers unchanged.
Selects
Output
Buffer,
OUT0
to
OUT7
Turn on all buffers, or restore the previously connected channels.
Send a pulse to the 2nd-rank registers to load them with the contents of the 1st-rank
registers. When latch is held high, this "software-LATCH" command performs the same
function as pulsing LATCH low.
1111
Do not use these codes in the parallel-interface mode. These codes are for the serial-
interface mode only.
1001 and 1010
Table 2. Serial-Interface Mode Functions
D3-D0
FUNCTION
Connect the selected buffer to the input
channel selected by D3-D0.
0000 to 0111
Connect the input of the selected buffer to
GND. Note, if the buffer output remains
on, its input is its offset voltage.
1000
1001
Turn on the selected buffer and connect
its input to GND. Use this code to turn on
buffers after power is applied. The default
power-up state is all buffers disabled.
Shut off the selected buffer at the speci-
fied channel, and erase data stored in the
2nd rank of registers. The 2nd rank now
holds the command word 1010.
1010
Do not use these codes in the serial-inter-
face mode. They inhibit the latching of the
2nd-rank registers, which prevents proper
data loading.
1011 to 1111
6
_______________________________________________________________________________________
8 x 8 Vid e o Cro s s p o in t S w it c h
MAX456
IN4
IN5
IN1
IN2
IN3
IN6
IN7
IN0
OUTPUT
BUFFERS
A = 1
OUT0
400Ω
MAX456
8 x 8
SWITCH
MATRIX
LOAD
A = 1
OUT7
LATCH
400Ω
2nd-RANK REGISTERS
1st-RANK REGISTERS
EDGE/LEVEL
WR
CE
SER/PAR
CE
V+ V- AGND DGND
A0 A1 A2
D0/SER IN
D2 D3
D1/SER OUT
Figure 1. MAX456 Functional Diagram
Table 3. Input/Output Line Configurations
SERIAL/
PARALLEL
D3
D2
D1
D0
A2-A0
COMMENT
Serial
Output
H
X
X
Serial Input
X
32-Bit Serial Mode
Output
Buffer
Address
Parallel
Input
Parallel
Input
Parallel
Input
Parallel Mode,
D0-D2 = Control Code
L
L
H
L
Output
Buffer
Address
Parallel
Input
Parallel
Input
Parallel
Input
Parallel Mode,
D0-D2 = Input Address
Note : X = Don't Care, H = 5V, L = 0V
_______________________________________________________________________________________
7
8 x 8 Vid e o Cro s s p o in t S w it c h
Each 7-bit word updates only one output buffer at a
________________Typ ic a l Ap p lic a t io n
time. If several buffers are to be updated, the data is
individually loaded into the 1st-rank registers. Then, a
single LATCH pulse is used to reconfigure all channels
simultaneously.
Figure 2 shows a typical application of the MAX456 with
MAX470 quad, gain-of-two buffers at the outputs to
drive 75Ω loads. This application shows the MAX456
digital-switch control interface set up in the 7-bit paral-
lel mode. The MAX456 uses 7 data lines and 2 control
lines (WR and LATCH). Two additional lines may be
needed to control CE and LOAD when using multiple
MAX456s.
The short Basic program in Figure 3 loads programming
data into the MAX456 from any IBM PC or compatible.
It uses the computer’s “LPT1” output to interface to the
circuit, then automatically finds the address for LPT1
and displays a table of valid input values to be used.
The program does not keep track of previous com-
mands, but it does display the last data sent to LPT1,
which is written and latched with each transmission.
MAX456
The input/output information is presented to the chip at
A2-A0 and D3-D0 by a parallel printer port. The data is
stored in the 1st-rank registers on the rising edge of
WR. When the LATCH line goes high, the switch con-
figuration is loaded into the 2nd-rank registers, and all 8
outputs enter the new configuration at the same time.
MAX470
75Ω
IN0
OUT0
5
39
1
16
OUT0
IN0
A = 2
V
7
9
37
35
33
31
3
6
8
14
11
9
IN1
IN2
OUT1
OUT2
OUT3
IN1
IN2
IN3
OUT1
OUT2
OUT3
75Ω
11
13
8-INPUT
VIDEO
CHANNELS
IN3
IN4
IN5
IN6
IN7
OUT4
OUT5
OUT6
OUT7
CE
15
17
19
29
27
25
24
14
8
MAX456
V+
GND
V-
10
2,7,15 4,5,12,13
-5V
EDGE/LEVEL
DB-25
22
21
LOAD
V+
V+
LATCH
WR
1
2
40
26
14
+5V
3
4
5
2
1
38
36
6
28, 30, 32
10, 12
20
34
23
AGND
DGND
D0/SER IN
D1/SER OUT
18
19
20
21
22
23
24
25
6
7
8
V-
V-
CE
SER/PAR
V+
D2
D3
A0
A1
A2
-5V
4
3
18
16
+5V
ALL BYPASS CAPACITORS 0.1µF CERAMIC
Figure 2. Typical Application Circuit
8
_______________________________________________________________________________________
8 x 8 Vid e o Cro s s p o in t S w it c h
MAX456
Figure 3. BASIC Program for Loading Data into the MAX456 from a PC Using Figure 2's Circuit
____________________________________________________________Tim in g Dia g ra m s
A0-A2
VALID DATA N-1
VALID DATA N
D0-D3
t
DS
t
DH
t
WL
t
WH
WR
t
D
t
L
LATCH
Figure 4. Write Timing for Serial- and Parallel-Interface Modes
_______________________________________________________________________________________
9
8 x 8 Vid e o Cro s s p o in t S w it c h
_______________________________________________Tim in g Dia g ra m s (c o n t in u e d )
SEE FIGURE 4 FOR WR
AND LATCH TIMING
DATA (N)
DATA (N + 1)
DATA (N + 2)
MAX456
WR
LATCH
FIRST-RANK REGISTER DATA
DATA (N)
DATA (N)
DATA (N + 1)
DATA (N + 2)
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = Low)
DATA (N + 1)
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = High)
DATA (N)
DATA (N + 1)
–——–
Figure 5. Parallel-Interface Mode Format (SER/ PAR = Low)
SEE TABLE 2 FOR
INPUT DATA
INPUT DATA FOR OUT0
INPUT DATA FOR OUT1 TO OUT6
INPUT DATA FOR OUT7
SEE FIGURE 4 FOR WR
AND LATCH TIMING
0D3
0D2
0D1
0D0
1D3
1D2
7D3
7D2
7D1
7D0
WR
LATCH
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = Low)
DATA VALID
SECOND-RANK REGISTER DATA
(EDGE/LEVEL = High)
DATA VALID
–——–
Figure 6. 32-Bit Serial-Mode Interface Format (SER/PAR = High)
10 ______________________________________________________________________________________
8 x 8 Vid e o Cro s s p o in t S w it c h
MAX456
_______________________________________________________Dyn a m ic Te s t Circ u it s
IN0
OUT0
OUT1
OUT2
OUT0
OUT1
OUT2
IN0
V
OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
V
OUT
IN1
IN2
V
OUT
V
OUT
IN3
IN4
IN5
IN6
IN7
MAX456
OUT3
OUT4
OUT5
OUT6
OUT3
OUT4
OUT5
OUT6
MAX456
V
OUT
V
OUT
V
OUT
V
OUT
OUT7
LOAD
OUT7
LOAD
V
OUT
+5V
+5V
V
IN
= 2Vp-p @ 5MHz
V
IN
= 2Vp-p, SWEEP FREQUENCY
R = 75Ω
S
R = 75Ω
S
-3dB Bandwidth (Notes 1-4)
All-Channel Off Isolation (Notes 1, 5-8)
IN0
IN0
OUT0
OUT1
OUT2
V
OUT
OUT0
V
OUT
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN1
IN2
IN3
IN4
IN5
IN6
IN7
V
OUT
OUT1
OUT2
75Ω
V
OUT
V
OUT
OUT3
OUT4
OUT5
OUT6
OUT3
OUT4
OUT5
OUT6
MAX456
MAX456
7x 75Ω
V
OUT
V
OUT
V
OUT
OUT7
LOAD
OUT7
LOAD
+5V
+5V
V
IN
= 2Vp-p @ 5MHz
V
IN
= 2Vp-p @ 5MHz
R = 75Ω
S
R = 75Ω
S
Single-Channel Crosstalk (Notes 1, 5, 9-11)
Connect LOAD (pin 8) to +5V (internal 400Ω loads on at all outputs).
Program any one input to connect to any one output (see Table 1 or 2 for programming codes).
Turn on buffer at the selected output (see Table 1 or 2).
All-Channel Crosstalk (Notes 1, 5, 9, 11, 12)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Drive the selected input with V , and measure V
at the -3dB frequency at the selected output.
IN
OUT
Program each numbered input to connect to the same numbered output (IN0 to OUT0, IN1 to OUT1, etc.).
See Table 1 or 2 for programming codes.
Note 6:
Note 7:
Note 8:
Note 9:
Turn off all output buffers (see Table 1 or 2).
Drive all inputs with V and measure V
at any output.
IN
OUT
Isolation (in dB) = 20log (V
/V ).
10 OUT IN
Turn on all output buffers (see Table 1 or 2).
Note 10: Drive any one input with V and measure V
at any undriven output.
IN
OUT
Note 11: Crosstalk (in dB) = 20log (V
/V ).
10 OUT IN
Note 12: Drive all but one input with V and measure V
at the undriven output.
IN
OUT
______________________________________________________________________________________ 11
8 x 8 Vid e o Cro s s p o in t S w it c h
____P in Co n fig u ra t io n s (c o n t in u e d )
__Ord e rin g In fo rm a t io n (c o n t in u e d )
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
40 Plastic DIP
44 PLCC
MAX456EPL
MAX456EQH
MAX456EJL
TOP VIEW
40 CERDIP
44
43 42 41 40
6
5
4
3
2
1
MAX456
A0
IN1
39 OUT2
38 V-
7
8
___________________Ch ip To p o g ra p h y
LOAD
IN2
9
37 OUT3
36 AGND
10
DGND 11
N.C. 12
35
34
33
32
OUT4
N.C.
MAX456
IN3 13
AGND
OUT5
DGND 14
IN4 15
31 AGND
30 OUT6
EDGE/LEVEL 16
IN5 17
V+
IN0
29
V+
IN6
SER/PAR
A1
A2
18 19 20 21 22 23 24 25 26 27 28
IN7
D0/SER IN
D1/SER OUT
V-
V+
WR
LATCH
CE
CE
OUT7
0. 167"
(4. 242mm)
OUT0
D2
OUT1
D3
PLCC
0. 184"
(4. 674mm)
TRANSISTOR COUNT: 3820;
SUBSTRATE CONNECTED TO V+.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1994 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX456EQH+D
Cross Point Switch, 1 Func, 8 Channel, CMOS, PQCC44, ROHS COMPLIANT, PLASTIC, LCC-44
MAXIM
MAX4570
Single/Dual.+3V/+5V Dual-Speed Comparators with Auto Standby[MAX975/MAX977/MAX975/MAX977/MAX975/MAX977/MAX975ESA/MAX975ESA-T/MAX975EUA/MAX975EUA-T/MAX977EEE/MAX977EEE-T/MAX977ESD/MAX977ESD-T ]
MAXIM
MAX4570CAI+
Cross Point Switch, 2 Func, 4 Channel, PDSO28, 5.30 X 0.65 MM, ROHS COMPLIANT, SSOP-28
MAXIM
MAX4570CAI+T
Cross Point Switch, 2 Func, 4 Channel, PDSO28, 5.30 X 0.65 MM, ROHS COMPLIANT, SSOP-28
MAXIM
©2020 ICPDF网 联系我们和版权申明