MAX4693 [MAXIM]
Low-Voltage.8:1 Mux/Dual 4:1 Mux/Triple SPDT/Quad SPDT in UCSP Package ; 低Voltage.8 ： 1复用/双路4 ： 1多路复用器/三SPDT /四路SPDT在UCSP封装\n
| 型号： | MAX4693 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Voltage.8:1 Mux/Dual 4:1 Mux/Triple SPDT/Quad SPDT in UCSP Package
|
| 文件： | 总22页 (文件大小：488K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1945; Rev 1; 5/01
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
General Description
Features
The MAX4691–MAX4694 are low-voltage CMOS analog
ICs configured as an 8-channel multiplexer (MAX4691),
two 4-channel multiplexers (MAX4692), three single-
pole/double-throw (SPDT) switches (MAX4693), and
four SPDT switches (MAX4694).
ꢀ 16 bump, 0.5mm-Pitch UCSP (Package pending
full qualification-expected completion date
9/30/01- see UCSP Reliability section for more
details).
ꢀ 1.8V Logic Compatibility
The MAX4691/MAX4692/MAX4693 operate from either
a single +2V to +11V power supply or dual ±2V to
±±.±V power supplies. ꢀhen operating from ±±V sup-
ꢀ Guaranteed On-Resistance
70Ω (max) with +2.7V Supply
35Ω (max) with +5V Supply
plies they offer 2±Ω on-resistance (R ), 3.±Ω (max)
ON
R
flatness, and 3Ω (max) matching between chan-
ON
25Ω (max) with ±±.5V ꢀual Supplies
nels. The MAX4694 operates from a single +2V to +11V
supply. Each switch has Rail-to-Rail® signal handling
and a low 1nA leakage current.
ꢀ Guaranteed Match Between Channels
5Ω (max) with +2.7V Supply
3Ω (max) with ±±.5V ꢀual Supplies
All digital inputs are 1.8V logic-compatible when oper-
ating from a +3V supply and TTL compatible when
operating from a +±V supply.
ꢀ Guaranteed Flatness Over Signal Range
3.5Ω (max) with ±±.5V ꢀual Supplies
The MAX4691–MAX4694 are available in a 16-pin,
ꢀ Low Leakage Currents Over Temperature
✕
4mm
4mm QFN package. In the future, the
20nA (max) at +85°C
MAX4691–MAX4694 will be offered in the chip-scale
package (UCSP™), significantly reducing the required
PC board area.
ꢀ Fast 90ns Transition Time
ꢀ Guaranteed Break-Before-Make
ꢀ Single-Supply Operation from +2V to +11V
Applications
Audio and Video Signal Routing
Cellular Phones
ꢀ ꢀual-Supply Operation from ±2V to ±5.5V
(MAX±691/MAX±692/MAX±693)
Battery-Operated Equipment
Communications Circuits
Modems
ꢀ V+ to V- Signal Handling
ꢀ Low Crosstalk: -90dB (100kHz)
ꢀ High Off-Isolation: -88dB (100kHz)
Functional Diagrams
Ordering Information
MAX4691
TEMP.
RANGE
PIN-
PACKAGE
PART
X0
X1
MAX4691EBE-T
MAX4691EGE
MAX4692EBE-T
MAX4692EGE
MAX4693EBE-T
MAX4693EGE
MAX4694EBE-T
MAX4694EGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16-Bump UCSP*
16 QFN
X2
X3
16-Bump UCSP*
16 QFN
X
X4
X5
16-Bump UCSP*
16 QFN
X6
X7
16-Bump UCSP*
16 QFN
LOGIC
B
EN
*Requires special solder temperature profile described in the
Absolute Maximum Ratings section.
A
C
*UCSP reliability is integrally linked to the user’s assembly meth-
ods, circuit board, and environment. See the UCSP Reliability
Notice in the UCSP Reliability section for information.
Pin Configurations appear at end of data sheet.
Functional Diagrams continued at end of data sheet.
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
UCSP is a trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +12V
V+ to V- (MAX4691/MAX4692/MAX4693) ..............-0.3V to +12V
Voltage into any Terminal (Note 1) ...... (V- - 0.3V) to (V+ + 0.3V)
Continuous Current into any Terminal ............................. 20mA
Peak Current W_, X_, Y_, Z_ (pulsed at 1ms,
Operating Temperature Range .......................... -40°C to +85°C
Storage Temperature Range............................ -65°C to +150°C
Lead Temperature (Soldering)
16-Bump UCSP (Note 2) Infrared (15s)..................... +220°C
Vapor Phase (60s)..................................................... +215°C
16-Pin QFN................................................................. +300°C
10% duty cycle)........................................................... 40mA
ESD per Method 3015.7.......................................................>2kV
Continuous Power Dissipation (T = +70°C)
A
16-Bump UCSP (derate 8.3mW/°C above +70°C) .... 659mW
16-Pin QFN (derate 18.5mW/°C above +70°C) ....... 1481mW
Note 1: Voltages exceeding V+ or V- on any signal terminal are clamped by internal diodes. Limit forward-diode current to maxi-
mum current rating.
Note 2: This device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device
can be exposed to during board level solder attach and rework. This limit permits only the use of the solder profiles recom-
mended in the industry standard specification, JEDEC 020A, paragraph 7.6, Table 3 for IR/VPR and convection reflow.
Preheating is required. Hand or wave soldering is not allowed.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(V+ = +2.7V to +3.6V, V- = 0, V = +1.4V, V = +0.4V, T = -40°C to +85°C, unless otherwise noted. Typical values are at
IH
IL
A
T
A
= +25°C.) (Notes 3, 4, 5)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH
V , V , V ,
W
X
Y
V ,V _,
Z
W
Analog Signal Range
-40°C to +85°C
0
V+
V
V _, V _,
X
Y
V _
Z
+25ºC
45
2
70
80
V+ = 2.7V; I , I , I , I = 1mA
W
X Y Z
On-Resistance (Note 6)
R
Ω
Ω
ON
V _, V _, V _, V _ = 1.5V
W
X
Y
Z
-40°C to +85°C
+25°C
5
6
On-Resistance Match
Between Channels
(Notes 6, 7)
V+ = 2.7V; I , I , I , I = 1mA
W
X Y Z
∆R
ON
V _, V _, V _, V _ = 1.5V
W
X
Y
Z
-40°C to +85°C
V+ = 3.6V; V , V , V , V = 3V,
+25°C
-1
1
W
X
Y
Z
W_, X_, Y_, Z_ Off-Leakage
Current (Note 9)
I _, I _,
W X
0.6V; V _, V _, V _, V _ = 0.6V,
nA
nA
W
X
Y
Z
I _, I _
Y
Z
-40°C to +85°C
-10
10
3V
I
I
I
I
,
,
,
W(OFF)
+25°C
-2
-20
-2
2
20
2
V+ = 3.6V; V , V , V , V = 3V,
W
X
Y
Z
W, X, Y, Z Off-Leakage
Current (Note 9)
X(OFF)
Y(OFF)
0.6V; V _, V _, V _, V _ = 0.6V,
W
X
Y
Z
3V
-40°C to +85°C
+25°C
Z(OFF)
I
,
,
,
W(ON)
V+ = 3.6V; V , V , V , V = 0.6V,
W
X
Y
Z
W, X, Y, Z On-Leakage
Current (Note 9)
I
X(ON)
3V; V _, V _, V _, V _ = 0.6V, 3V,
nA
W
X
Y
Z
I
Y(ON)
or floating
-40°C to +85°C
-20
20
I
Z(ON)
2
_______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
ELECTRICAL CHARACTERISTICS—Single +3V Supply (continued)
(V+ = +2.7V to +3.6V, V- = 0, V = +1.4V, V = +0.4V, T = -40°C to +85°C, unless otherwise noted. Typical values are at
IH
IL
A
T
A
= +25°C.) (Notes 3, 4, 5)
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
C _
,
W (OFF)
C _
,
,
X (OFF)
Input Off-Capacitance
Output Off-Capacitance
f = 1MHz, Figure 7
+25°C
+25°C
+25°C
9
pF
C _
Y (OFF)
C _
Z (OFF)
MAX4691
68
36
20
78
C
C
,
,
X(OFF)
f = 1MHz,
Figure 7
pF
pF
MAX4692
MAX4693
MAX4691
Y(OFF)
C
Z(OFF)
C
,
,
,
W(ON)
C
C
f = 1MHz,
Figure 7
X(ON)
MAX4692
MAX4693
46
30
On-Capacitance
Y(ON)
C
Z(ON)
DYNAMIC
Enable Turn-On Time
(MAX4691/MAX4692/
MAX4693)
+25°C
180
70
300
350
100
120
V _, V _, V _, V _ = 1.5V;
W
X
Y
Z
t
ns
ns
ON
R = 300Ω,C = 35pF, Figure 2
L
L
-40°C to +85°C
+25°C
Enable Turn-Off Time
(MAX4691/MAX4692/
MAX4693)
V _, V _, V _, V _ = 1.5V;
W
X
Y
Z
t
OFF
R = 300Ω,C = 35pF, Figure 2
L
L
-40°C to +85°C
+25°C
200
90
350
400
V _, V _, V _, V _ = 0, 1.5V;
W
X
Y
Z
Address Transition Time
Break-Before-Make
Charge Injection
t
ns
ns
TRANS
R = 300Ω, C = 35pF, Figure 3
-40°C to +85°C
+25°C
L
L
2
2
V _, V _, V _, V _ = 1.5V;
W
X
Y
Z
t
BBM
Q
R = 300Ω, C = 35pF, Figure 4
L
L
-40°C to +85°C
V
GEN
= 0; R = 0; C = 1nF,
GEN L
+25°C
+25°C
+25°C
0.1
-70
-75
pC
dB
dB
Figure 5
f = 0.1MHz, R = 50Ω, C = 5pF,
L
L
Off-Isolation (Note 10)
Crosstalk (Note 11)
V
ISO
Figure 6
f = 0.1MHz, R = 50Ω, C = 5pF,
L
L
V
CT
Figure 6
DIGITAL I/O
Input Logic High
Input Logic Low
Input Leakage Current
SUPPLY
V
1.4
-1
V
V
IH
V
0.4
+1
IL
I
V , V , V , V
= 0 or V+
µA
IN
A
B
C
EN
+25°C
0.1
1
V+ = 3.6V, V , V , V , V = 0
or V+
A
B
C
EN
Positive Supply Current
I+
µA
-40°C to +85°C
_______________________________________________________________________________________
3
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V+ = +4.5V to +5.5V, V- = 0, V = +2V, V = +0.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at
IH
IL
A
T
= +25°C.) (Notes 3, 4, 5)
A
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH
V , V , V ,
W
X
Y
V , V _, V _,
Analog Signal Range
-40°C to +85°C
0
V+
V
Z
W
X
V _, V _
Y
Z _
+25°C
25
2
35
40
V+ = 4.5V; I , I , I , I = 1mA;
W
X Y Z
On-Resistance (Note 6)
R
Ω
ON
V _,V _, V _, V _ = 3.5V
W
X
Y
Z
-40°C to +85°C
+25°C
-40°C to +85°C
+25°C
4
5
On-Resistance Match
Between Channels
(Notes 6, 7)
V+ = 4.5V; I , I , I , I = 1mA;
W
X Y Z
∆R
Ω
Ω
ON
V _,V _, V _, V _ = 3.5V
W
X
Y
Z
2
6
V+ = 4.5V; I , I , I , I = 1mA;
W
X Y Z
On-Resistance Flatness
(Note 8)
R
V _,V _, V _, V _ = 1V, 2.25V,
FLAT(ON)
W
X
Y
Z
3.5V
-40°C to +85°C
+25°C
8
-1
-10
-2
1
V+ = 5.5V; V , V , V ,
W
X
Y
W_, X_ , Y_, Z_ Off-Leakage
Current (Note 9)
I
,I ,
, I
W_ X_
V = 4.5V, 1V_; V _,V _, V _,
nA
Z
W
X
Y
I
Y_ Z_
V _ = 1V, 4.5V
Z
-40°C to +85°C
+25°C
10
2
I
I
I
,
,
,
W(OFF)
X (OFF)
V+ = 5.5V; V , V , V ,
W
X
Y
W, X, Y, Z Off-Leakage
Current (Note 9)
V
= 4.5V, 1V_; V _,V _, V _,
W X Y
nA
nA
Z
Y(OFF)
V _ = 1V, 4.5V
Z
-40°C to +85°C
+25°C
-20
-2
20
2
I
Z(OFF)
I
I
I
I
,
W(ON)
,
X(ON)
V+ = 5.5V; V ,V , V , V = 1V,
W
X
Y
Z
W, X, Y, Z On-Leakage
Current (Note 9)
4.5V_; V _,V _, V _, V _ = 1V,
W
X
Y
Z
,
Y(ON)
4.5V, or floating
-40°C to +85°C
-20
20
Z(ON)
DYNAMIC
+25°C
90
130
150
Enable Turn-On Time
(MAX4691/MAX4692/MAX4693)
V _,V _, V _, V _ = 3V; R =
W X Y Z L
300Ω, C = 35pF, Figure 2
L
t
ns
ns
ON
-40°C to +85°C
+25°C
-40°C to +85°C
+25°C
45
60
70
Enable Turn-Off Time
(MAX4691/MAX4692/MAX4693)
V _,V _, V _, V _ = 3V; R =
W X Y Z L
300Ω, C = 35pF, Figure 2
L
t
OFF
V _,V _, V _, V _ = 0, 3V;
100
140
W
X
Y
Z
Address Transition Time
t
R = 300Ω, C = 35pF,
Figure 3
ns
TRANS
L
L
-40°C to +85°C
160
+25°C
2
2
35
V _,V _, V _, V _ = 3V; R =
W
X
Y
Z
L
Break-Before-Make
Charge Injection
t
ns
BBM
Q
300Ω, C = 35pF, Figure 4
L
-40°C to +85°C
V
= 0; R
= 0; C = 1nF,
GEN L
GEN
+25°C
0.2
pC
Figure 5
4
_______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V+ = +4.5V to +5.5V, V- = 0, V = +2V, V = +0.8V, T = -40°C to +85°C, unless otherwise noted. Typical values are at
IH
IL
A
T
= +25°C.) (Notes 3, 4, 5)
A
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
f = 0.1MHz, R = 50Ω,
C = 5pF, Figure 6
L
L
Off-Isolation (Note 10)
Crosstalk (Note 11)
V
+25°C
+25°C
-80
dB
ISO
f = 0.1MHz, R = 50Ω,
L
V
-87
dB
CT
C = 5pF, Figure 6
L
DIGITAL I/O
Input Logic High
Input Logic Low
Input Leakage Current
SUPPLY
V
2
V
V
IH
V
0.8
+1
IL
I
IN
V , V , V , V = 0 or V+
-1
µA
A
B
C
EN
+25°C
0.1
1
V+ = 5.5V; V , V , V , V = 0
or V+
A
B
C
EN
Positive Supply Current
I+
µA
-40°C to +85°C
ELECTRICAL CHARACTERISTICS—Dual 5V Supplieꢀ
(MAX4691/MAX4692/MAX4693 only)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, V = +2V, V = +0.8V, T = -40°C to +85°C, unless otherwise noted.) (Notes 3, 4, 5)
IH
IL
A
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
ANALOG SWITCH
V , V , V ,
X
Y
Z
Analog Signal Range
-40°C to +85°C
V-
V+
V
V _, V _, V _
X
Y
Z
+25°C
18
2
25
30
V+ = 4.5V; I , I , I = 10mA;
X
Y Z
On-Resistance (Note 6)
R
Ω
ON
V- = -4.5V; V _, V _, V _ = 3.5V
X
Y
Z
-40°C to +85°C
+25°C
-40°C to +85°C
+25°C
3
4
On-Resistance Match
Between Channels
(Notes 6, 7)
V+ = 4.5V; V- = -4.5V; I , I , I =
X
Y Z
∆R
Ω
Ω
ON
10mA;V _, V _, V _ = 3.5V
X
Y
Z
2.5
3.5
4
V+ = 4.5V; V- = -4.5V; I , I , I =
X
Y Z
On-Resistance Flatness
(Note 8)
R
10mA; V , V , V = 3.5V, 0,
X Y Z
-3.5V
FLAT(ON)
-40°C to +85°C
+25°C
-1
1
X_ , Y_, Z_ Off-Leakage
Current (Note 9)
I _,
V+ = 5.5V; V- = -5.5V; V , V , V
X Y Z
= +4.5V;V _, V _, V _ = 4.5V
X Y Z
X
nA
nA
I _, I _
Y
Z
-40°C to +85°C
-10
10
+25°C
-2
2
I
I
,
,
V+ = 5.5V; V- = -5.5V; V , V ,
X Y
X (OFF)
X, Y, Z Off-Leakage Current
(Note 9)
V = +4.5V;V _, V _, V _ =
Y(OFF)
Z
X
Y
Z
-40°C to +85°C
-20
20
I
4.5V
Z(OFF)
_______________________________________________________________________________________
5
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
ELECTRICAL CHARACTERISTICS—Dual 5V Supplieꢀ (continued)
(MAX4691/MAX4692/MAX4693 only)
(V+ = +4.5V to +5.5V, V- = -4.5V to -5.5V, V = +2V, V = +0.8V, T = -40°C to +85°C, unless otherwise noted.) (Notes 3, 4, 5)
IH
IL
A
PARAMETER
SYMBOL
CONDITIONS
T
MIN
TYP
MAX
UNITS
A
V+ = 5.5V; V- = -5.5V;
V , V , V = 4.5V;
+25°C
-2
2
I
I
I
,
X(ON)
X, Y, Z On-Leakage Current
(Note 9)
X
Y
Z
,
nA
Y(ON)
V _, V _, V _ = 4.5V,
X
Y
Z
-40°C to +85°C
-20
20
Z(ON)
or floating
DYNAMIC
+25°C
55
80
90
V _, V _, V _ = 3V; R = 300Ω,
C = 35pF, Figure 2
L
X
Y
Z
L
Enable Turn-On Time
t
ns
ns
ON
-40°C to +85°C
+25°C
35
60
50
60
V _, V _, V _ = 3V; R = 300Ω,
X
Y
Z
L
Enable Turn-Off Time
Address Transition Time
t
OFF
C = 35pF, Figure 2
L
-40°C to +85°C
V _, V _, V _ = 0, 3V;
+25°C
90
X
Y
Z
t
ns
R = 300Ω, C = 35pF,
TRANS
L
L
-40°C to +85°C
100
Figure 3
+25°C
2
2
20
V _, V _, V _ = 3V; R = 300Ω,
C = 35pF, Figure 4
L
X
Y
Z
L
Break-Before-Make
Charge Injection
t
ns
pC
dB
dB
%
BBM
Q
-40°C to +85°C
V
= 0; R
= 0;
GEN
GEN
+25°C
+25°C
+25°C
+25°C
1.8
-82
C = 1nF, Figure 5
L
f = 0.1MHz, R = 50Ω,
L
Off-Isolation (Note 10)
Crosstalk (Note 11)
Total Harmonic Distortion
V
ISO
C = 5pF, Figure 6
L
f = 0.1MHz, R = 50Ω,
L
V
-84
CT
C = 5pF, Figure 7
L
f = 20Hz to 20kHz, V , V , V =
X
Y
Z
THD
0.02
5Vp-p; R = 600Ω,
L
DIGITAL I/O
Input Logic High
Input Logic Low
Input Leakage Current
SUPPLY
V
2
V
V
IH
V
0.8
+1
IL
I
IN
V , V , V , V = 0 or V+
-1
µA
A
B
C
EN
+25°C
0.1
1
V+ = 5.5V; V- = 5.5V;
V , V , V , V = 0 or V+
Positive Supply Current
I+
µA
A
B
C
EN
-40°C to +85°C
Note 3: The algebraic convention, where the most negative value is a minimum and the most positive value is a maximum, is used
in this data sheet.
Note 4: UCSP parts are 100% tested at T = +25°C. Limits across the full temperature range are guaranteed by correlation.
A
Note 5: QFN parts are 100% tested at T = +85°C. Limits across the full temperature range are guaranteed by correlation.
A
Note 6: UCSP R
and R
match are guaranteed by design.
ON
ON
Note 7: ∆R
= R
- R
.
ON
ON(MAX)
ON(MIN)
Note 8: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Note 9: Leakage parameters are guaranteed by design.
Note 10:Off-isolation = 20log (V
/ V
), V
W_,X_,Y_,Z_
= output, V
= input to off switch.
W_,X_,Y_,Z_
W,X,Y,Z
W,X,Y,Z
10
Note 11:Between any two switches.
6
_______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V , V , V , V
ON-RESISTANCE vs. V , V , V
ON-RESISTANCE vs. V , V , V AND
TEMPERATURE (DUAL SUPPLIES)
W
X
Y
Z
X
Y
Z
X
Y
Z
(SINGLE SUPPLY)
(DUAL SUPPLIES)
100
90
80
70
60
50
40
30
20
10
0
24
22
20
18
16
14
12
10
8
40
30
20
10
0
V+ = +2V
V+ = +2V
V- = -2V
V+ = +5V
V- = -5V
T
= +85°C
A
V+ = +2.7V
V- = -2.7V
V+ = +3.3V
V- = -3.3V
V+ = +2.7V
V+ = +3.3V
V+ = +5V
V+ = +7.5V
T
= +25°C
A
V+ = +5V
V- = -5V
T
= -40°C
V+ = +10V
6
A
6
0
2
4
8
10
12
-6
-4
-2
0
2
4
6
-5
-3
-1
1
3
5
V , V , V , V (V)
V , V , V (V)
V , V , V (V)
X Y Z
W
X
Y
Z
X
Y
Z
SUPPLY CURRENT vs. TEMPERATURE
(DUAL SUPPLIES)
ON-RESISTANCE vs. V , V , V , V AND
ON-RESISTANCE vs. V , V , V , V AND
W
X
Y
Z
W
X
Y
Z
TEMPERATURE (SINGLE SUPPLY)
TEMPERATURE (SINGLE SUPPLY)
34
50
40
10
1
V+ = +5V
V+ = +3.3V
32
30
28
26
24
22
20
18
16
14
12
10
V+ = +5V
V- = -5V
T
= +85°C
T
= +85°C
A
A
V , V , V , V = 0, +5V
A
B
C
EN
I+
30
0.1
T
= +25°C
A
I-
0.01
0.001
20
10
T
= +25°C
T
= -40°C
A
A
T
= -40°C
A
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3
V , V , V , V (V)
-40
-15
10
35
60
85
0
1
2
3
4
5
TEMPERATURE (°C)
W
X
Y
Z
V , V , V , V (V)
W
X
Y
Z
SUPPLY CURRENT vs. TEMPERATURE
(SINGLE SUPPLY)
I+ vs. LOGIC LEVEL
LOGIC-LEVEL THRESHOLD vs. V+
1A
0.1A
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10
1
V+ = +5V
0.01A
1mA
V , V , V , V = 0, +5V
A
B
C
EN
0.1mA
0.01mA
1µA
0.1µA
0.01µA
1nA
0.1
0.01
0.001
0.1nA
0.01nA
1pA
0
1
2
3
4
5
2
3
4
5
6
7
8
9
10 11
-40
-15
10
35
60
85
V , V , V , V (V)
A
B
C
ENB
V+ (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
TURN-ON/TURN-OFF TIME
vs. TEMPERATURE (DUAL SUPPLY)
ON-LEAKAGE CURRENT vs. TEMPERATURE
OFF-LEAKAGE CURRENT vs. TEMPERATURE
65
60
55
50
45
40
35
30
10
10
V+ = +5.5V
V- = -5.5V
V+ = +5.5V
V- = -5.5V
V+ = +5.5V
V- = -5.5V
1
1
0.1
TURN-ON
W, X, Y, Z
0.1
0.01
TURN-OFF
0.01
W_, X_, Y_, Z_
0.001
0.0001
0.001
0.0001
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
TURN-ON/TURN-OFF TIME
vs. SUPPLY VOLTAGE
TURN-ON/TURN-OFF TIME
vs. TEMPERATURE (SINGLE SUPPLY)
CHARGE INJECTION vs. V , V , V , V
W
X
Y
Z
90
80
380
330
280
230
180
130
80
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V+ = +5.5V
TURN-ON
70
60
50
V+ = +5V
V- = -5V
V+ = +5V
V- = 0
TURN-ON
TURN-OFF
V+ = +3V
V- = 0
TURN-OFF
40
30
30
-40
-15
10
35
60
85
-5 -4 -3 -2 -1
0
1
2
3
4
5
2
3
4
5
6
TEMPERATURE (°C)
SUPPLY VOLTAGE V+, V- (V)
V , V , V , V (V)
W
X
Y
Z
FREQUENCY RESPONSE
vs. 5V SUPPLIES
FREQUENCY RESPONSE
vs. +3V SUPPLIES
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
0.1
0.01
0
-20
0
-20
ON-RESPONSE
OFF-ISOLATION
ON-RESPONSE
OFF-ISOLATION
V+ = +3V
V- = 0
-40
-40
-60
-60
V+ = +5V
V- = -5V
-80
-80
CROSSTALK
CROSSTALK
-100
-120
-140
-100
-120
-140
0.001
0.001
0.01
0.1
1
10
100
0.001
0.01
0.1
1
10
100
10k
100k
10
100
1k
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (Hz)
8
_______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Pin Description
MAX4691
PIN
NAME
FUNCTION
UCSP
QFN
A4, B4, C4,
D4, A1, B1,
C1, D1
16, 1, 3, 4,
12, 11, 9,
8
X0–X7
Analog Switch Inputs 0–7
A2
13
X
Analog Switch Common
Digital Address Inputs
D3, D2, A3
5, 7, 15
A, B, C
B2
14
V-
Negative Analog Supply Voltage Input. Connect to GND for single-supply operation.
Ground. Connect to digital ground. (Analog signals have no ground reference; they
are limited to V+ and V-.)
B3
2
GND
Digital Enable Input. Normally connect to GND. Can be driven to logic high to set all
switches off.
C2
C3
10
6
EN
V+
Positive Analog and Digital Supply Voltage Input
MAX4692
PIN
NAME
FUNCTION
UCSP
QFN
A1, B1, C1,
D1
12, 11, 9,
8
X0–X3
Y0–Y3
Analog Switch “X” Inputs 0–3
Analog Switch “Y” Inputs 0–3
A4, B4, C4,
D4
16, 1, 3, 4
A2
A3
13
15
X
Y
Analog Switch “X” Common
Analog Switch “Y” Common
D3, D2
5, 7
A, B
Digital Address Inputs for both “X” and “Y” Analog Switches
B2
14
V-
Negative Analog Supply Voltage Input. Connect to GND for single-supply operation.
Ground. Connect to digital ground. (Analog signals have no ground reference;
they are limited to V+ and V-.)
B3
2
GND
Digital Enable Input. Normally connect to GND. Can be driven to logic high to
set all switches off.
C2
C3
10
6
EN
V+
Positive Analog and Digital Supply Voltage Input
_______________________________________________________________________________________
9
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Pin Description (continued)
MAX4693
PIN
NAME
FUNCTION
UCSP
QFN
A1
B1
A4
B4
D1
C1
A2
A3
D2
C4
D4
D3
B2
12
11
16
1
X0
X1
Y0
Y1
Z0
Z1
X
Analog Switch “X” Normally Closed Input
Analog Switch “X” Normally Open Input
Analog Switch “Y” Normally Closed Input
Analog Switch “Y” Normally Open Input
Analog Switch “Z” Normally Closed Input
Analog Switch “Z” Normally Open Input
Analog Switch “X” Common
8
9
13
15
7
Y
Analog Switch “Y” Common
Z
Analog Switch “Z” Common
3
A
Analog Switch “X” Digital Control Input
Analog Switch “Y” Digital Control Input
Analog Switch “Z” Digital Control Input
4
B
5
C
14
V-
Negative Analog Supply Voltage Input. Connect to GND for single-supply operation.
Ground. Connect to digital ground. (Analog signals have no ground reference; they
are limited to V+ and V-.)
B3
2
GND
Digital Enable Input. Normally connect to GND. Can be driven to logic high to set all
switches off.
C2
C3
10
6
EN
V+
Positive Analog and Digital Supply Voltage Input
10 ______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Pin Description (continued)
MAX4694
PIN
NAME
FUNCTION
Analog Switch “W” Normally Closed Input
USCP
QFN
D4
4
W0
W1
X0
X1
Y0
Y1
Z0
Z1
W
C4
A1
B1
A4
B4
D1
C1
D3
A2
A3
D2
B2
B3
C2
C3
3
12
11
16
1
Analog Switch “W” Normally Open Input
Analog Switch “X” Normally Closed Input
Analog Switch “X” Normally Open Input
Analog Switch “Y” Normally Closed Input
Analog Switch “Y” Normally Open Input
Analog Switch “Z” Normally Closed Input
Analog Switch “Z” Normally Open Input
Analog Switch “W” Common
8
9
5
13
15
7
X
Analog Switch “X” Common
Y
Analog Switch “Y” Common
Z
Analog Switch “Z” Common
14
2
GND
A
Ground
Analog Switch “W” and “Y” Digital Control Input
Analog Switch “X” and “Z” Digital Control Input
Positive Analog and Digital Supply Voltage Input
10
6
B
V+
______________________________________________________________________________________ 11
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Table 1. Truth Table/Switch Programming
ADDRESS BITS
2
ON SWITCHES
1
EN
1
C
B
A
MAX4691
MAX4692
MAX4693
MAX4694
X
0
X
X
0
All switches open
All switches open
All switches open
—
W-W0, X-X0,
Y-Y0, Z-Z0
0
0
0
1
1
0
0
1
1
X-X0
X-X1
X-X2
X-X3
X-X4
X-X5
X-X6
X-X7
X-X0, Y-Y0
X-X0, Y-Y0, Z-Z0
X-X1, Y-Y0, Z-Z0
X-X0, Y-Y1, Z-Z0
X-X1, Y-Y1, Z-Z0
X-X0, Y-Y0, Z-Z1
X-X1, Y-Y0, Z-Z1
X-X0, Y-Y1, Z-Z1
X-X1, Y-Y1, Z-Z1
W-W1, X-X0,
Y-Y1, Z-Z0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
X-X1, Y-Y1
X-X2, Y-Y2
X-X3, Y-Y3
X-X0, Y-Y0
X-X1, Y-Y1
X-X2, Y-Y2
X-X3, Y-Y3
W-W0, X-X1,
Y-Y0, Z-Z1
W-W1, X-X1,
Y-Y1, Z-Z1
W-W0, X-X0,
Y-Y0, Z-Z0
W-W1, X-X0,
Y-Y1, Z-Z0
W-W0, X-X1,
Y-Y0, Z-Z1
W-W1, X-X1,
Y-Y1, Z-Z1
X = Don’t care
1. EN is not present on the MAX4694.
2. C is not present on the MAX4692 and MAX4694.
A, B, C determine which switch is closed. The two 4-1
muxes in the MAX4692 are controlled by the same
address pins (A and B). (Table 1)
Detailed Description
The MAX4691–MAX4694 are low-voltage CMOS analog
ICs configured as an 8-channel multiplexer (MAX4691),
two 4-channel multiplexers (MAX4692), three SPDT
switches (MAX4693), and four SPDT switches
(MAX4694). All switches are bidirectional.
The MAX4693 and MAX4694 offer SPDT switches in
triple and quadruple packages. In the MAX4693, each
switch has a unique control input. The MAX4694 has
two digital control inputs: A (for switches “W” and “Y”)
and B (for switches “X” and “Z”). (Table 1)
The MAX4691/MAX4692/MAX4693 operate from either
a single +2V to +11V power supply or dual 2V to
5.5V power supplies. When operating from 5V sup-
Applications Information
Power-Supply Considerations
plies they offer 25Ω on-resistance (R ), 3.5Ω max
ON
R
flatness, and 3Ω max matching between channels.
ON
The MAX4694 operates from a single +2V to +11V sup-
Overview
The MAX4691–MAX4694 construction is typical of most
CMOS analog switches. V+ and V-* are used to drive
the internal CMOS switches and set the limits of the
analog voltage on any switch. Reverse ESD-protection
diodes are internally connected between each analog
signal pin and both V+ and V-. If any analog signal
exceeds V+ or V-, one of these diodes will conduct.
ply. Each switch has rail-to-rail signal handling, fast
switching times of t
1nA leakage current.
= 80ns, t
= 50ns, and a low
ON
OFF
All digital inputs are 1.8V logic-compatible when oper-
ating from a +3V supply and TTL-compatible when
operating from a +5V supply.
Digital Inputs
The MAX4691 and MAX4692 include address pins that
allow control of the multiplexers. For the MAX4691, pins
*V- is found only on the MAX4691/MAX4692/MAX4693.
12 ______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
During normal operation, these (and other) reverse-
biased ESD diodes leak, forming the only current
drawn from V+ or V-.
unchanged, and the difference between V+ and V-
should not exceed 12V. These protection diodes are
not recommended when using a single supply if signal
levels must extend to ground.
Virtually all the analog leakage current comes from the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical, and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either V+ or V- and the analog signal. This means their
leakages will vary as the signal varies. The difference in
the two diode leakages to the V+ and V- pins consti-
tutes the analog signal path leakage current. All analog
leakage current flows between each pin and one of the
supply terminals, not to the other switch terminal. This
is why both sides of a given switch can show leakage
currents of either the same or opposite polarity.
UCSP Reliability
The chip-scale package (UCSP) represents a unique
package that greatly reduces board space compared to
other packages. UCSP reliability is integrally linked to the
user’s assembly methods, circuit board material, and
usage environment. The user should closely review these
areas when considering a UCSP. Performance through
Operating Life Test and Moisture Resistance is equal to
conventional package technology as it is primarily deter-
mined by the wafer-fabrication process. However, this
form factor may not perform equally to a packaged prod-
uct through traditional mechanical reliability tests.
V+ and GND power the internal logic and logic-level
translators, and set both the input and output logic lim-
its. The logic-level translators convert the logic levels
into switched V+ and V- signals to drive the gates of
the analog signals. This drive signal is the only connec-
tion between the logic supplies (and signals) and the
analog supplies. V+ and V- have ESD-protection
diodes on GND.
Mechanical stress performance is a greater considera-
tion for a UCSP. UCSP solder joint contact integrity
must be considered since the package is attached
through direct solder contact to the user’s PC board.
Testing done to characterize the UCSP reliability per-
formance shows that it is capable of performing reli-
ably through environmental stresses. Results of
environmental stress tests and additional usage data
and recommendations are detailed in the UCSP appli-
cation note, which can be found on Maxim’s website,
at www.maxim-ic.com.
Bipolar Supplies
The MAX4691/MAX4692/MAX4693 operate with bipolar
supplies between 2V and 5.5V. The V+ and V- sup-
plies need not be symmetrical, but their difference can-
not exceed the absolute maximum rating of +12V.
V+
Single Supply
These devices operate from a single supply between +2V
and +11V when V- is connected to GND. All of the bipolar
precautions must be observed. At room temperature,
they operate with a single supply at near or below +2V,
although as supply voltage decreases, switch on-resis-
tance and switching times become very high.
EXTERNAL BLOCKING DIODE
D1
MAX4691
MAX4692
MAX4693
MAX4694
V+
*
*
*
COM
NO
Always bypass supplies with a 0.1µF capacitor.
*
Overvoltage Protection
Proper power-supply sequencing is recommended for
all CMOS devices. Do not exceed the absolute maxi-
mum ratings, because stresses beyond the listed rat-
ings can cause permanent damage to the devices.
Always sequence V+ on first, then V-, followed by the
logic inputs and by W, X, Y, Z. If power-supply
sequencing is not possible, add two small signal
diodes (D1, D2) in series with the supply pins for over-
voltage protection (Figure 1).
V- (GND)
EXTERNAL BLOCKING DIODE
D2
V- (GND )
*INTERNAL PROTECTION DIODES
Adding diodes reduces the analog signal range to one
diode drop below V+ and one diode drop above V-, but
does not affect the devices’ low switch resistance and
low leakage characteristics. Device operation is
( ) ARE FOR THE MAX4694 ONLY, REPLACE V- WITH GND.
Figure 1. Overvoltage Protection
______________________________________________________________________________________ 13
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Test Circuits/Timing Diagrams
V+
V+
V
50%
50%
50%
EN
V+
X0
A
B
C
V+
0
X1–X7
V
X0
90%
MAX4691
V
EN
V
OUT
V
OUT
EN
X
GND
V-
90%
90%
90%
35pF
35pF
35pF
50Ω
0
300Ω
300Ω
300Ω
V-
t
t
ON
OFF
V+
V+
V+
V
EN
X0, Y0
A
B
V+
0
X1, X2, X3, Y1, Y2, Y3
V
V
,
X0
Y0
90%
MAX4692
V
EN
EN
X, Y
V
OUT
V
GND
V-
V-
OUT
50Ω
0
t
t
ON
OFF
V+
V+
V+
0
V
EN
X1, Y1, Z1
A
B
C
V+
V-
V
V
V
,
,
,
W0
X0
Y0
MAX4693
X0, Y0, Z0
X, Y, Z
V-
90%
V
Z0
V
EN
EN
V
OUT
V
OUT
GND
V
V
V
,
,
,
50Ω
W1
X1
Y1
V-
t
t
ON
OFF
V
Z1
V- = 0 FOR SINGLE-SUPPLY OPERATION.
TEST EACH SECTION INDIVIDUALLY.
Figure 2. Enable Transition Time
14 ______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Test Circuits/Timing Diagrams (continued)
V+
V+
V , V , V
50%
50%
50%
A
B
C
V , V , V
A
B
C
V+
X0
A
B
C
V+
0
X1–X6
50Ω
V
X0
90%
X7
X
V-
MAX4691
V
EN
OUT
0
V
GND
90%
90%
90%
V-
OUT
35pF
V
X7
300Ω
V-
t
t
TRANS
TRANS
V+
V+
V+
0
V , V
A
B
V , V
A
B
X0, Y0
A
B
V+
X1, X2, Y1, Y2
50Ω
V
,
X0
V
Y0
90%
MAX4692
X3, Y3
X, Y
V-
EN
0
V
OUT
GND
V
V-
OUT
35pF
V
,
Y3
X3
V
300Ω
V-
t
t
TRANS
TRANS
V+
V+
V+
V , V , V
A
B
C
V , V , V
A
B
C
W1, X1, Y1, Z1
V-
A, B, C
0
V
,
,
,
W0
50Ω
MAX4693
MAX4694
V
X0
Y0
V
V
90%
V+
W0, X2, Y2, Z2,
Z0
X0, Y0, Z0
EN
0
V
OUT
X, Y, Z
GND
V-
V
OUT
V
,
,
,
W1
35pF
V
X1
Y1
300Ω
V
V
V-
Z1
t
t
TRANS
TRANS
V- = 0 FOR SINGLE-SUPPLY OPERATION. (NOT PRESENT ON THE MAX4694)
TEST EACH SECTION INDIVIDUALLY.
Figure 3. Address Transition Time
______________________________________________________________________________________ 15
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Test Circuits/Timing Diagrams (continued)
V+
V+
V+
V+
V , V , V
V , V
A
B
C
A
B
X0–X7
X0–X3,
Y0–Y3
A
B
C
A
B
V+
V+
50Ω
50Ω
MAX4692
MAX4691
V
OUT
EN
EN
X
X, Y
V
OUT
GND
GND
V-
V-
35pF
35pF
300Ω
300Ω
V-
V-
V+
V+
t < 20ns
F
R
V , V , V
V+
0
A
B
C
t < 20ns
V , V , V
C
50%
A
B
W0, W1, X0, X1,
Y0, Y1, Z0, Z1
V+
A, B, C
50Ω
MAX4693
MAX4694
V , V , V , V
W
X
Y
Z
90%
EN
W, X, Y, Z
V-
V
OUT
GND
35pF
V
OUT
300Ω
V-
0
V- = 0 FOR SINGLE-SUPPLY OPERATION. (NOT PRESENT ON THE MAX4694)
TEST EACH SECTION INDIVIDUALLY.
t
BBM
Figure 4. Break-Before-Make Interval
V+
V+
V+
0
V
EN
W_, X_, Y_, Z_
A
B
C
CHANNEL
SELECT
MAX4691–
MAX4694
∆ V
V
OUT
OUT
V
EN
V
EN
OUT
W, X, Y, Z
GND
V-
C = 1000pF
L
50Ω
∆ V
IS THE MEASURED VOLTAGE DUE TO CHARGE
OUT
V-
TRANSFER ERROR Q WHEN THE CHANNEL TURNS OFF.
V- = 0 FOR SINGLE-SUPPLY OPERATION. (NOT PRESENT ON THE MAX4694)
TEST EACH SECTION INDIVIDUALLY.
Q = ∆ V
X C
L
OUT
Figure 5. Charge Injection
16 ______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Test Circuits/Timing Diagrams (continued)
V+
10nF
NETWORK
ANALYZER
V
V
IN
50Ω
50Ω
OUT
V+
OFF-ISOLATION = 20log
V
W_, X_, Y_, Z_
A
B
C
IN
CHANNEL
SELECT
V
MAX4691–
MAX4694
OUT
ON-LOSS = 20log
V
IN
V
EN
V
OUT
MEAS.
REF.
EN
W, X, Y, Z
V-
V
OUT
CROSSTALK = 20log
GND
V
IN
50Ω
50Ω
10nF
V-
MEASUREMENTS ARE STANDARDIZED AGAINST SHORT AT SOCKET TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN COM AND “OFF” NO TERMINAL ON EACH SWITCH.
ON LOSS IS MEASURED BETWEEN COM AND “ON” NO TERMINAL ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL (A, B, C) TO ALL OTHER CHANNELS.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
V- IS NOT PRESENT ON THE MAX4694.
Figure 6. Off-Isolation, On-Loss, and Crosstalk
V+
V+
W_, X_, Y_, Z_
A
B
C
CHANNEL
SELECT
MAX4691–
MAX4694
1MHz
CAPACITANCE
ANALYZER
EN
W, X, Y, Z
V-
GND
V-
V- IS NOT PRESENT ON THE MAX4694.
Figure 7. Capacitance
______________________________________________________________________________________ 17
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Functional Diagrams (continued)
MAX4692
X0
X1
X
X2
X3
X0
X1
Y
X2
X3
LOGIC
EN
A
B
MAX4693
MAX4694
X0
W0
Z0
X
W
W1
Z
Z1
X1
Y0
Y0
Y
Z0
Y
Y1
Z
X0
Z1
Y1
X
X1
EN
A
B
C
B
A
Chip Information
TRANSISTOR COUNT: 292
18 ______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Pin Configurations
TOP VIEW
MAX4691
X0
16
C
V-
14
X
1
2
3
4
15
13
X4
X
C
X0
A
B
C
D
X1
GND
X2
1
2
3
12
11
10
X4
X5
EN
X5
X6
X7
GND
V+
A
X1
X2
X3
V-
EN
B
MAX4691
X3
4
9
X6
5
6
7
8
UCSP
A
V+
B
X7
QFN
MAX4692
Y0
16
Y
V-
14
X
1
2
3
4
15
13
X0
X
Y
Y0
A
B
C
D
Y1
GND
Y2
1
2
3
12
11
10
X0
X1
EN
X1
X2
X3
GND
V+
A
Y1
Y2
Y3
V-
EN
B
MAX4692
Y3
4
9
X2
5
6
7
8
UCSP
A
V+
B
X3
QFN
______________________________________________________________________________________ 19
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Pin Configurations (continued)
TOP VIEW
MAX4693
Y0
16
Y
V-
14
X
1
2
3
4
15
13
X0
X
Y
Y0
A
B
C
D
Y1
GND
A
1
2
3
12
11
10
X0
X1
EN
X1
Z1
Z0
GND
V+
Y1
A
V-
EN
Z
MAX4693
B
4
9
Z1
C
B
5
6
7
Z
8
UCSP
C
V+
Z0
QFN
MAX4694
Y0
16
Y
GND
14
X
1
2
3
4
15
13
X0
X
Y
Y0
A
B
C
D
Y1
A
1
2
3
12
11
10
X0
X1
B
X1
Z1
Z0
A
Y1
W1
W0
GND
B
MAX4694
W1
V+
W
W0
4
9
Z1
Z
5
6
7
Z
8
UCSP
W
V+
Z0
QFN
20 ______________________________________________________________________________________
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Package Information
______________________________________________________________________________________ 21
Low-Voltage 8:1 Mux/Dual 4:1 Mux/Triple SPDT/
Quad SPDT in UCSP Package
Package Information (continued)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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