MAX5038AEAI15 [MAXIM]
Dual-Phase, Parallelable, Average-Current-Mode Controllers; 双相，可并联，平均电流模式控制器
| 型号： | MAX5038AEAI15 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual-Phase, Parallelable, Average-Current-Mode Controllers |
| 文件： | 总26页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3034; Rev 0; 10/03
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
General Description
Features
The MAX5038A/MAX5041A dual-phase, PWM controllers
provide high-output-current capability in a compact
package with a minimum number of external compo-
nents. The MAX5038A/MAX5041A utilize a dual-phase,
average-current-mode control that enables optimal use
ꢀ +4.75V to +5.5V or +8V to +28V Input Voltage
Range
ꢀ Up to 60A Output Current
ꢀ Internal Voltage Regulator for a +12V or +24V
of low R
MOSFETs, eliminating the need for exter-
DS(ON)
Power Bus
nal heatsinks even when delivering high output currents.
ꢀ True Differential Remote Output Sensing
Differential sensing enables accurate control of the out-
put voltage, while adaptive voltage positioning provides
optimum transient response. An internal regulator
enables operation with input voltage ranges of +4.75V to
+5.5V or +8V to +28V. The high switching frequency, up
to 500kHz per phase, and dual-phase operation allow
the use of low-output inductor values and input capacitor
values. This accommodates the use of PC board-
embedded planar magnetics achieving superior reliabili-
ty, current sharing, thermal management, compact size,
and low system cost.
ꢀ Two Out-Of-Phase Controllers Reduce Input
Capacitance Requirement and Distribute Power
Dissipation
ꢀ Average-Current-Mode Control
Superior Current Sharing Between Individual
Phases and Paralleled Modules
Accurate Current Limit Eliminates MOSFET and
Inductor Derating
ꢀ Limits Reverse-Current Sinking in Paralleled
The MAX5038A/MAX5041A also feature a clock input
(CLKIN) for synchronization to an external clock, and a
clock output (CLKOUT) with programmable phase delay
(relative to CLKIN) for paralleling multiple phases. The
MAX5038A/MAX5041A also limit the reverse current in
case the bus voltage becomes higher than the regulat-
ed output voltage. The MAX5038A offers a variety of fac-
tory-trimmed preset output voltages (see Selector Guide)
and the MAX5041A offers an adjustable output voltage
between +1.0V to +3.3V.
Modules
ꢀ Integrated 4A Gate Drivers
ꢀ Selectable Fixed Frequency 250kHz or 500kHz per
Phase (Up to 1MHz for Two Phases)
ꢀ Fixed (MAX5038A) or Adjustable (MAX5041A)
Output Voltages
ꢀ External Frequency Synchronization from 125kHz
to 600kHz
The MAX5038A/MAX5041A operate over the extended
temperature range (-40°C to +85°C) and are available
in a 28-pin SSOP package. Refer to the MAX5037A and
MAX5065/MAX5067 data sheets for a VRM 9.0/VRM 9.1-
compatible, VID-controlled, adjustable output voltage
controller in a 44-pin MQFP/thin QFN or 28-pin SSOP
package.
ꢀ Internal PLL with Clock Output for Paralleling
Multiple DC-DC Converters
ꢀ Thermal Protection
ꢀ 28-Pin SSOP Package
Ordering Information
Applications
OUTPUT
VOLTAGE
(V)
Servers and Workstations
PIN-
PACKAGE
PART
TEMP RANGE
Point-of-Load High-Current/High-Density
Telecom DC-DC Regulators
MAX5038AEAI12 -40°C to +85°C 28 SSOP
MAX5038AEAI15 -40°C to +85°C 28 SSOP
MAX5038AEAI18 -40°C to +85°C 28 SSOP
MAX5038AEAI25 -40°C to +85°C 28 SSOP
MAX5038AEAI33 -40°C to +85°C 28 SSOP
Fixed +1.2
Fixed +1.5
Fixed +1.8
Fixed +2.5
Fixed +3.3
Networking Systems
Large-Memory Arrays
RAID Systems
High-End Desktop Computers
Adj +1.0 to
+3.3
MAX5041AEAI
-40°C to +85°C 28 SSOP
Pin Configuration appears at end of data sheet.
________________________________________________________________Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
ABSOLUTE MAXIMUM RATINGS
IN to SGND.............................................................-0.3V to +30V
BST_ to SGND........................................................-0.3V to +35V
All Other Pins to SGND...............................-0.3V to (V
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
DH_ to LX_ ................................-0.3V to [(V
DL_ to PGND..............................................-0.3V to (V
BST_ to LX_ ..............................................................-0.3V to +6V
_ - V _) + 0.3V]
28-Pin SSOP (derate 9.5mW/°C above +70°C) ..........762mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
BST
LX
+ 0.3V)
CC
V
V
to SGND............................................................-0.3V to +6V
to PGND............................................................-0.3V to +6V
CC
CC
SGND to PGND .....................................................-0.3V to +0.3V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted. Typical specifications are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SYSTEM SPECIFICATIONS
8
28
5.5
10
Input Voltage Range
V
V
IN
Short IN and V
operation
together for +5V input
CC
4.75
Quiescent Supply Current
Efficiency
I
EN = V
or SGND
4
mA
%
Q
CC
I
= 52A (26A per phase)
90
LOAD
OUTPUT VOLTAGE
MAX5038A only, no load
MAX5038A only, no load, V = V
+4.75V to +5.5V or V = +8V to +28V
IN
-0.8
-1
+0.8
+1
Nominal Output Voltage
Accuracy (Note 4)
=
CC
IN
%
V
(Note 2)
MAX5041A only, no load
0.992
0.990
1.008
1.010
SENSE+ to SENSE- Voltage
Accuracy (Note 4)
MAX5041A only, no load, V = V
=
CC
IN
+4.75V to +5.5V or V = +8V to +28V
IN
STARTUP/INTERNAL REGULATOR
V
Undervoltage Lockout
UVLO
V
V
rising
CC
4.0
4.15
200
5.1
4.5
V
mV
V
CC
V
Undervoltage Lockout
CC
Hysteresis
Output Accuracy
V
= +8V to +28V, I = 0 to 80mA
SOURCE
4.85
5.30
3
CC
IN
MOSFET DRIVERS
Output Driver Impedance
R
Low or high output
1
4
ON
Output Driver Source/Sink
Current
I
_, I
DH
_
DL
A
Nonoverlap Time
t
C
_ _ = 5nF
DH /DL
60
ns
NO
OSCILLATOR AND PLL
CLKIN = SGND
CLKIN = V
238
475
125
250
500
262
525
600
Switching Frequency
f
kHz
SW
CC
PLL Lock Range
PLL Locking Time
f
t
kHz
µs
PLL
PLL
200
2
_______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted. Typical specifications are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
115
85
TYP
120
90
60
5
MAX
125
95
UNITS
PHASE = V
CC
CLKOUT Phase Shift
(at f = 125kHz)
PHASE = unconnected
PHASE = SGND
Degrees
CLKOUT
SW
55
65
CLKIN Input Pulldown Current
CLKIN High Threshold
CLKIN Low Threshold
I
3
7
µA
V
CLKIN
V
2.4
CLKINH
V
0.8
V
CLKINL
CLKIN High Pulse Width
PHASE High Threshold
PHASE Low Threshold
PHASE Input Bias Current
CLKOUT Output Low Level
CLKOUT Output High Level
CURRENT LIMIT
t
200
4
ns
V
CLKIN
V
PHASEH
V
1
V
PHASEL
I
-50
4.5
+50
100
µA
mV
V
PHASEBIA
V
I
= 2mA (Note 2)
SINK
CLKOUTL
V
I
= 2mA (Note 2)
CLKOUTH SOURCE
Average Current-Limit Threshold
Reverse Current-Limit Threshold
Cycle-by-Cycle Current Limit
V
CSP_ to CSN_
45
-3.9
90
48
51
mV
mV
mV
CL
V
CSP_ to CSN_
-0.2
130
CLR
V
CSP_ to CSN_ (Note 3)
112
260
CLPK
Cycle-by-Cycle Overload
Response Time
t
V
_ to V _ = +150mV
CSN
ns
R
CSP
CURRENT-SENSE AMPLIFIER
CSP_ to CSN_ Input Resistance
Common-Mode Range
Input Offset Voltage
R
_
4
k
CS
V
-0.3
-1
+3.6
+1
V
CMR(CS)
V
mV
V/V
MHz
OS(CS)
Amplifier Gain
A
18
4
V(CS)
3dB Bandwidth
f
3dB
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
Transconductance
Open-Loop Gain
gm
ca
VOL(CE)
550
50
µS
dB
A
No load
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Common-Mode Voltage Range
DIFF Output Voltage
V
-0.3
+1.0
V
V
CMR(DIFF)
V
V
= V = 0
SENSE-
0.6
1
CM
OS(DIFF)
SENSE+
Input Offset Voltage
V
-1
+1
mV
MAX5038A (+1.2V, +1.5V, +1.8V output
versions), MAX5041A
0.997
0.495
1.003
0.505
Amplifier Gain
A
V/V
V(DIFF)
MAX5038A (+2.5Vand+3.3V output versions)
0.5
3
3dB Bandwidth
f
C
= 20pF
DIFF
MHz
mA
3dB
Minimum Output Current Drive
I
1.0
50
OUT(DIFF)
SENSE+ to SENSE- Input
Resistance
R
_
100
k
VS
_______________________________________________________________________________________
3
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V, circuit of Figure 1, T = -40°C to +85°C, unless otherwise noted. Typical specifications are at T = +25°C.) (Note 1)
CC
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE-ERROR AMPLIFIER (EAOUT)
Open-Loop Gain
A
70
3
dB
MHz
nA
VOL(EA)
Unity-Gain Bandwidth
EAN Input Bias Current
f
UGEA
I
V
= +2.0V
EAN
-100
810
+100
918
B(EA)
Error-Amplifier Output Clamping
Voltage
V
With respect to V
mV
CLAMP(EA)
CM
THERMAL SHUTDOWN
Thermal Shutdown
T
150
8
°C
°C
SHDN
Thermal-Shutdown Hysteresis
EN INPUT
EN Input Low Voltage
EN Input High Voltage
EN Pullup Current
V
1
V
V
ENL
V
3
ENH
I
4.5
5
5.5
µA
EN
Note 1: Specifications from -40°C to 0°C are guaranteed by characterization but not production tested.
Note 2: Guaranteed by design. Not production tested.
Note 3: See Peak-Current Comparator section.
Note 4: Does not include an error due to finite error amplifier gain (see the Voltage-Error Amplifier section).
4
_______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Typical Operating Characteristics
(Circuit of Figure 1. T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. OUTPUT CURRENT AND
INTERNAL OSCILLATOR FREQUENCY
EFFICIENCY vs. OUTPUT CURRENT
AND INPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
100
90
80
70
60
50
40
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
f = 500kHz
f = 250kHz
V = +12V
IN
V
= +5V
IN
V
V
SW
= +24V
OUT
= 125kHz
IN
V
f
= +1.8V
= +1.8V
V
V
= +5V
OUT
OUT
IN
= 250kHz
f
= +1.8V
SW
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
I
I
OUT
I
OUT
OUT
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
EFFICIENCY vs. OUTPUT CURRENT
AND OUTPUT VOLTAGE
SUPPLY CURRENT
vs. FREQUENCY AND INPUT VOLTAGE
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
12.0
11.5
11.0
10.5
10.0
9.5
V
= +1.5V
V
= +24V
OUT
IN
V
= +1.5V
OUT
V
= +1.8V
OUT
V
= +1.8V
OUT
V
= +1.1V
OUT
9.0
V
= +1.1V
OUT
8.5
V
= +12V
IN
8.0
7.5
7.0
V
f
= +12V
V
= +5V
IN
V
f
= +5V
IN
IN
EXTERNALCLOCK
NO DRIVER LOAD
6.5
= 250kHz
SW
= 500kHz
SW
6.0
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
0
4
8
12 16 20 24 28 32 36 40 44 48 52
(A)
100 150 200 250 300 350 400 450 500 550 600
FREQUENCY (kHz)
I
OUT
I
OUT
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. TEMPERATURE AND FREQUENCY
SUPPLY CURRENT
vs. LOAD CAPACITANCE PER DRIVER
100
90
80
70
60
50
40
30
20
10
0
175
150
125
100
75
100
90
80
70
60
50
40
30
20
10
0
600kHz
500kHz
250kHz
125kHz
V
C
C
= +5V
= 22nF
= 8.2nF
IN
DL_
DH_
V
C
C
= +12V
= 22nF
DH_
IN
DL_
50
V
f
= +12V
IN
= 250kHz
= 8.2nF
SW
11
25
-40
-15
10
35
60
85
-40
-15
10
35
60
85
1
3
5
7
9
13
15
TEMPERATURE (°C)
TEMPERATURE (°C)
C
(nF)
DRIVER
_______________________________________________________________________________________
5
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
OUTPUT VOLTAGE vs. OUTPUT CURRENT
CURRENT-SENSE THRESHOLD
vs. OUTPUT VOLTAGE
DIFFERENTIAL AMPLIFIER BANDWIDTH
AND ERROR AMP GAIN (R / R )
F
IN
MAX5038A/41A toc12
90
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
55
54
53
52
51
50
49
48
47
46
45
1.85
1.80
1.75
1.70
1.65
1.60
V
V
= +12V
OUT
IN
= +1.8V
45
RF / RIN = 15
PHASE
0
RF / RIN = 12.5
-45
-90
-135
-180
-225
PHASE 2
GAIN
RF / RIN = 7.5
PHASE 1
RF / RIN = 10
-270
0.01
0.1
1
10
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
0
5
10 15 20 25 30 35 40 45 50 55
(A)
FREQUENCY (MHz)
V
(V)
I
LOAD
OUT
DIFF OUTPUT ERROR
vs. SENSE+ TO SENSE- VOLTAGE
V
LOAD REGULATION
vs. INPUT VOLTAGE
CC
V
LINE REGULATION
CC
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
0.200
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
V
= +12V
IN
V
= +24V
IN
NO DRIVER
I
= 0
CC
V
= +12V
IN
I
= 40mA
CC
V
= +8V
IN
DC LOAD
15 30 45 60 75 90 105 120 135 150
(mA)
8
10 12 14 16 18 20 22 24 26 28
(V)
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
0
V
∆V
(V)
I
CC
IN
SENSE
DRIVER RISE TIME
vs. DRIVER LOAD CAPACITANCE
DRIVER FALL TIME
vs. DRIVER LOAD CAPACITANCE
V
LINE REGULATION
CC
120
110
100
90
80
70
60
50
40
30
20
10
0
120
110
100
90
80
70
60
50
40
30
20
10
0
5.25
5.20
5.15
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
DL_
DH_
DL_
DH_
V
SW
= +12V
= 250kHz
V = +12V
IN
SW
IN
f
f
= 250kHz
I
= 80mA
9
CC
1
6
11
16
21
26
31
36
1
6
11
16
21
26
31
36
8
10
11
12
13
C
(nF)
C
(nF)
V
(V)
DRIVER
DRIVER
IN
6
_______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
PLL LOCKING TIME
250kHz TO 350kHz AND
350kHz TO 250kHz
HIGH-SIDE DRIVER (DH_)
LOW-SIDE DRIVER (DL_)
SINK AND SOURCE CURRENT
SINK AND SOURCE CURRENT
MAX5038A/41A toc19
MAX5038A/41A toc20
MAX5038A/41A toc21
CLKOUT
5V/div
350kHz
DH_
1.6A/div
PLLCMP
DL_
1.6A/div
200mV/div
250kHz
= +12V
0
V
= +12V
= 22nF
V
= +12V
DH_
IN
IN
C
V
IN
C
DL_
= 22nF
NO LOAD
100ns/div
100ns/div
100µs/div
PLL LOCKING TIME
PLL LOCKING TIME
250kHz TO 150kHz AND
150kHz TO 250kHz
250kHz TO 500kHz AND
500kHz TO 250kHz
HIGH-SIDE DRIVER (DH_)
RISE TIME
MAX5038A/41A toc22
MAX5038A/41A toc24
MAX5038A/41A toc23
CLKOUT
5V/div
CLKOUT
5V/div
DH_
2V/div
250kHz
PLLCMP
200mV/div
500kHz
PLLCMP
200mV/div
150kHz
0
250kHz
V
= +12V
V = +12V
IN
DH_
IN
V
= +12V
IN
NO LOAD
C
= 22nF
NO LOAD
0
100µs/div
40ns/div
100µs/div
HIGH-SIDE DRIVER (DH_)
FALL TIME
LOW-SIDE DRIVER (DL_)
RISE TIME
LOW-SIDE DRIVER (DL_)
FALL TIME
MAX5038A/41A toc25
MAX5038A/41A toc26
MAX5038A/41A toc27
DH_
2V/div
DL_
2V/div
DL_
2V/div
V
= +12V
DH_
V
= +12V
DL_
IN
C
IN
C
V
= +12V
DL_
IN
C
= 22nF
= 22nF
= 22nF
40ns/div
40ns/div
40ns/div
_______________________________________________________________________________________
7
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Typical Operating Characteristics (continued)
(Circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
OUTPUT RIPPLE
ENABLE STARTUP RESPONSE
MAX5038A/41A toc30
INPUT STARTUP RESPONSE
MAX5038A/41A toc28
MAX5038A/41A toc29
V
PGOOD
1V/div
V
PGOOD
1V/div
V
V
OUT
1V/div
OUT
1V/div
V
OUT
(AC-COUPLED)
10mV/div
V
IN
5V/div
V
EN
2V/div
V
= +12V
= +1.75V
= 52A
V
= +12V
V
V
I
= +12V
IN
IN
IN
V
V
= +1.75V
= +1.75V
= 52A
OUT
I
OUT
I
OUT
OUT
= 52A
OUT
OUT
500ns/div
1ms/div
2ms/div
REVERSE-CURRENT SINK
AT INPUT TURN-ON
REVERSE-CURRENT SINK vs.
TEMPERATURE
LOAD-TRANSIENT RESPONSE
MAX5038A/41A toc33
MAX5038A/41A toc31
2.8
2.7
2.6
2.5
2.4
2.3
V
V
V
= +12V
OUT
EXTERNAL
R1 = R2 = 1.5mΩ
IN
R1 = R2 = 1.5mΩ
= +1.5V
= 2.5V
REVERSE
CURRENT
5A/div
V
= +3.3V
EXTERNAL
V
OUT
0A
50mV/div
V
V
I
t
= +12V
V
= +2V
35
IN
EXTERNAL
= +1.75V
= 8A TO 52A
= 1µs
OUT
STEP
RISE
V
V
= +12V
OUT
IN
= +1.5V
200µs/div
40µs/div
-40
-15
10
60
85
TEMPERATURE (°C)
REVERSE-CURRENT SINK
AT ENABLE TURN-ON
REVERSE-CURRENT SINK
AT ENABLE TURN-ON
REVERSE-CURRENT SINK
AT INPUT TURN-ON
MAX5038A/41 toc35
MAX5038A/41 toc36
MAX5038A/41A toc34
V
V
V
= +12V
OUT
EXTERNAL
R1 = R2 = 1.5mΩ
V
V
V
= +12V
OUT
EXTERNAL
R1 = R2 = 1.5mΩ
V
V
V
= +12V
OUT
EXTERNAL
R1 = R2 = 1.5mΩ
IN
IN
IN
= +1.5V
= +1.5V
= +1.5V
REVERSE
CURRENT
10A/div
= 2.5V
= 3.3V
= 3.3V
REVERSE
CURRENT
5A/div
REVERSE
CURRENT
10A/div
0A
0A
0A
200µs/div
200µs/div
200µs/div
8
_______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Pin Description
PIN
NAME
FUNCTION
CSP2,
CSP1
Current-Sense Differential Amplifier Positive Input. Senses the inductor current. The differential voltage
between CSP_ and CSN_ is amplified internally by the current-sense amplifier gain of 18.
1, 13
CSN2,
CSN1
2, 14
Current-Sense Differential Amplifier Negative Input. Together with CSP_, senses the inductor current.
Phase-Shift Setting Input. Connect PHASE to V
PHASE to SGND for 60 of phase shift between the rising edges of CLKOUT and CLKIN/DH1.
for 120 , leave PHASE unconnected for 90 , or connect
CC
3
4
PHASE
External Loop-Compensation Input. Connect compensation network for the phase-locked loop (see Phase-
Locked Loop section).
PLLCMP
CLP2,
CLP1
5, 7
6
Current-Error Amplifier Output. Compensate the current loop by connecting an RC network to ground.
SGND
Signal Ground. Ground connection for the internal control circuitry.
Differential Output Voltage-Sensing Positive Input. Used to sense a remote load. Connect SENSE+ to
V
at the load. The MAX5038A regulates the difference between SENSE+ and SENSE- according to the
8
SENSE+
OUT+
factory preset output voltage. The MAX5041A regulates the SENSE+ to SENSE- difference to +1.0V.
Differential Output Voltage-Sensing Negative Input. Used to sense a remote load. Connect SENSE- to
9
SENSE-
DIFF
V
or PGND at the load.
OUT-
10
11
Differential Remote-Sense Amplifier Output. DIFF is the output of a precision unity-gain amplifier.
Voltage-Error Amplifier Inverting Input. Receives the output of the differential remote-sense amplifier.
Referenced to SGND.
EAN
Voltage-Error Amplifier Output. Connect to the external gain-setting feedback resistor. The external error
amplifier gain-setting resistors determine the amount of adaptive voltage positioning
12
15
EAOUT
EN
Output Enable. A logic low shuts down the power drivers. EN has an internal 5µA pullup current.
BST1,
BST2
Boost Flying-Capacitor Connection. Reservoir capacitor connection for the high-side FET driver supply.
Connect a 0.47µF ceramic capacitor between BST_ and LX_.
16, 26
DH1,
DH2
17, 25
18, 24
19, 23
20
High-Side Gate Driver Output. Drives the gate of the high-side MOSFET.
Inductor Connection. Source connection for the high-side MOSFETs. Also serves as the return terminal for
the high-side driver.
LX1, LX2
DL1,
DL2
Low-Side Gate Driver Output. Synchronous MOSFET gate drivers for the two phases.
Internal +5V Regulator Output. V
and 0.1µF ceramic capacitors.
is derived internally from the IN voltage. Bypass to SGND with 4.7µF
CC
V
CC
Supply Voltage Connection. Connect IN to V
RC lowpass filter, a 2.2 resistor, and a 0.1µF ceramic capacitor.
for a +5V system. Connect the VRM input to IN through an
CC
21
IN
Power Ground. Connect PGND, low-side synchronous MOSFET’s source, and V
together.
bypass capacitor returns
CC
22
PGND
CLKOUT
Oscillator Output. CLKOUT is phase shifted from CLKIN by the amount specified by PHASE. Use CLKOUT
to parallel additional MAX5038A/MAX5041As.
27
CMOS Logic Clock Input. Drive the internal oscillator with a frequency range between 125kHz and 600kHz,
or connect to V or SGND. Connect CLKIN to SGND to set the internal oscillator to 250kHz or connect to
CC
28
CLKIN
V
to set the internal oscillator to 500kHz. CLKIN has an internal 5µA pulldown current.
CC
_______________________________________________________________________________________
9
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Functional Diagram
EN
+5V
LDO
REGULATOR
UVLO
POR
TEMP SENSOR
IN
V
CC
DRV_V
SHDN
CC
TO INTERNAL CIRCUITS
CSP1
CSN1
CLP1
BST1
CSP1
CSN1
CLP1
DH1
LX1
DL1
PHASE 1
RAMP1
CLK
SGND
MAX5038A
MAX5041A
GM
IN
PGND
PHASE-
LOCKED
LOOP
CLKIN
PHASE
CLKOUT
PLLCMP
RAMP
GENERATOR
DIFF
SENSE-
0.6V
DIFF
AMP
PGND
SENSE+
EAOUT
EAN
ERROR
AMP
DRV_V
SHDN
PGND
CC
CLK
V
REF
V
REF
V
REF
= V
for V ≤ 1.8V (MAX5038A)
OUT OUT
= V /2 for V > 1.8V (MAX5038A)
OUT
OUT
= +1.0V (MAX5041A)
RAMP2
DH2
LX2
PHASE 2
GM
IN
CLP2
CSN2
CSP2
CLP2
DL2
CSN2
CSP2
BST2
10 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
the output current capacity. For maximum ripple rejec-
Detailed Description
tion at the input, set the phase shift between phases to
The MAX5038A/MAX5041A (Figures 1 and 2) average-
90° for two paralleled converters, or 60° for three paral-
current-mode PWM controllers drive two out-of-phase
leled converters. The paralleling capability of the
buck converter channels. Average-current-mode con-
MAX5038A/MAX5041A improves design flexibility in
trol improves current sharing between the channels
applications requiring upgrades (higher load).
while minimizing component derating and size. Parallel
multiple MAX5038A/MAX5041A regulators to increase
9
SENSE-
8
SENSE+
14
3
CSN1
CSP1
PHASE
13
V
IN
15
EN
IN
R1
V
= +12V
C3–C7
IN
21
C1, C2
17
18
19
C39
DH1
LX1
DL1
Q1
R2
L1
V
CC
C12
Q2
28
4
CLKIN
D1
MAX5038A
16
20
BST1
D3
PLLCMP
+1.8V AT 60A
V
CC
V
OUT
R4
C25
C34
C32
C31
C26
R7
R8
V
10
11
12
CC
D4
DIFF
EAN
V
IN
C14,
C15
C16–C24,
C33
C8–C11
LOAD
R
X
EAOUT
25
24
23
DH2
LX2
DL2
Q1
Q2
R3
L2
7
5
R6
CLP1
C29
C13
D2
C30
C28
26
BST2
CLP2
R5
C27
1
2
6
SGND
PGND
CSP2
CSN2
22
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
Figure 1. MAX5038A Typical Application Circuit, V = +12V
IN
______________________________________________________________________________________ 11
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Dual-phase converters with an out-of-phase locking
arrangement reduce the input and output capacitor
ripple current, effectively multiplying the switching fre-
quency by the number of phases. Each phase of the
MAX5038A/MAX5041A consists of an inner average
current loop controlled by a common outer-loop volt-
age-error amplifier (VEA). The combined action of the
two inner current loops and the outer voltage loop cor-
rects the output voltage errors and forces the phase
currents to be equal.
9
SENSE-
8
SENSE+
14
3
CSN1
CSP1
PHASE
13
V
IN
15
EN
IN
C3–C7
R1
V
= +12V
IN
21
C1,
C2
17
18
19
C39
DH1
LX1
DL1
Q1
R2
L1
V
CC
C12
Q2
28
4
CLKIN
D1
MAX5041A
16
20
BST1
D3
PLLCMP
+1.8V AT 60A
V
CC
R4
V
OUT
C25
C34
C32
C31
R
R
H
L
C26
R7
R8
10
11
12
D4
R3
DIFF
EAN
V
V
IN
C14,
C15
C16–C24,
C33
CC
C8–C11
LOAD
R
X
EAOUT
25
24
23
DH2
LX2
DL2
Q1
Q2
L2
7
5
R6
CLP1
C29
C13
D2
C30
C28
26
BST2
CLP2
R5
C27
1
2
6
SGND
PGND
CSP2
CSN2
22
NOTE: SEE TABLE 1 FOR COMPONENT VALUES.
Figure 2. MAX5041A Typical Application Circuit, V = +12V
IN
12 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
V
and V
Internal Oscillator
The internal oscillator generates the 180° out-of-phase
clock signals required by the pulse-width modulation
IN
CC
The MAX5038A/MAX5041A accept an input voltage
range of +4.75V to +5.5V or +8V to +28V. All internal
control circuitry operates from an internally regulated
(PWM) circuits. The oscillator also generates the 2V
P-P
nominal voltage of +5V (V ). For input voltages of +8V
voltage ramp signals necessary for the PWM compara-
tors. Connect CLKIN to SGND to set the internal oscillator
CC
CC
or greater, the internal V
regulator steps the voltage
output voltage is a regulated +5V
down to +5V. The V
frequency to 250kHz or connect CLKIN to V
to set the
CC
CC
output capable of sourcing up to 80mA. Bypass V
to
internal oscillator to 500kHz.
CC
SGND with 4.7µF and 0.1µF low-ESR ceramic capacitors
in parallel for high-frequency noise rejection and stable
operation (Figures 1 and 2).
CLKIN is a CMOS logic clock input for the phase-
locked loop (PLL). When driven externally, the internal
oscillator locks to the signal at CLKIN. A rising edge at
CLKIN starts the ON cycle of the PWM. Ensure that the
external clock pulse width is at least 200ns. CLKOUT
provides a phase-shifted output with respect to the ris-
ing edge of the signal at CLKIN. PHASE sets the
amount of phase shift at CLKOUT. Connect PHASE to
Calculate power dissipation in the MAX5038A/
MAX5041A as a product of the input voltage and the
total V
regulator output current (I ). I
includes
DD
CC
CC
CC
quiescent current (I ) and gate drive current (I ):
Q
P = V x I
(1)
(2)
D
IN CC
V
for 120° of phase shift, leave PHASE unconnected
CC
I
= I + f
x (Q + Q + Q + Q
)
CC
Q
SW
G1
G2
G3
G4
for 90° of phase shift, or connect PHASE to SGND for
60° of phase shift with respect to CLKIN.
where Q , Q , Q
and Q
are the total gate
G4
G1
G2
G3,
charge of the low-side and high-side external
MOSFETs, I is 4mA (typ), and f is the switching fre-
The MAX5038A/MAX5041A require compensation on
PLLCMP even when operating from the internal oscillator.
The device requires an active PLL in order to generate
the proper clock signal required for PWM operation.
Q
SW
quency of each individual phase.
For applications utilizing a +5V input voltage, disable
the V regulator by connecting IN and V together.
CC
CC
Control Loop
The MAX5038A/MAX5041A use an average-current-
mode control scheme to regulate the output voltage
(Figures 3a and 3b). The main control loop consists of
an inner current loop and an outer voltage loop. The
Undervoltage Lockout (UVLO)/Soft-Start
The MAX5038A/MAX5041A include an undervoltage
lockout with hysteresis and a power-on reset circuit for
converter turn-on and monotonic rise of the output volt-
age. The UVLO threshold is internally set between
+4.0V and +4.5V with a 200mV hysteresis. Hysteresis
at UVLO eliminates “chattering” during startup.
inner loop controls the output currents (I
PHASE2
and
PHASE1
I
) while the outer loop controls the output volt-
age. The inner current loop absorbs the inductor pole
reducing the order of the outer voltage loop to that of a
single-pole system.
Most of the internal circuitry, including the oscillator,
turns on when the input voltage reaches +4V. The
MAX5038A/MAX5041A draw up to 4mA of current before
the input voltage reaches the UVLO threshold.
The current loop consists of a current-sense resistor
(R ), a current-sense amplifier (CA_), a current-error
S
amplifier (CEA_), an oscillator providing the carrier
ramp, and a PWM comparator (CPWM_). The precision
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes a parallel combination of
capacitors (C28, C30) and resistors (R5, R6) in series
with other capacitors (C27, C29) (see Figures 1 and 2).
The voltage at CLP_ limits the maximum current avail-
able to charge output capacitors. The capacitor on
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus the output voltage.
CA_ amplifies the sense voltage across R by a factor
S
of 18. The inverting input to the CEA_ senses the CA_
output. The CEA_ output is the difference between the
voltage-error amplifier output (EAOUT) and the ampli-
fied voltage from the CA_. The RC compensation net-
work connected to CLP1 and CLP2 provides external
frequency compensation for the respective CEA_. The
start of every clock cycle enables the high-side drivers
and initiates a PWM ON cycle. Comparator CPWM_
compares the output voltage from the CEA_ with a 0 to
+2V ramp from the oscillator. The PWM ON cycle termi-
nates when the ramp voltage exceeds the error voltage.
______________________________________________________________________________________ 13
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
C
CF
R
CF
C
CFF
MAX5038A
CA1
V
IN
I
PHASE1
R *
F
CEA1
DRIVE 1
SENSE+
SENSE-
CPWM1
R
S
R *
IN
DIFF
AMP
VEA
V
OUT
V
IN
C
OUT
CEA2
R
S
V
LOAD
REF
I
PHASE2
CPWM2
DRIVE 2
CA2
C
CF
R
CF
*R AND R ARE EXTERNAL TO MAX5038A
F
IN
C
(R = R8, R = R7, FIGURE 1).
CCF
F
IN
Figure 3a. MAX5038A Control Loop
C
CF
R
CF
C
CFF
MAX5041A
CA1
V
IN
I
PHASE1
R *
F
CEA1
DRIVE 1
SENSE+
SENSE-
CPWM1
R
R
S
R *
IN
DIFF
AMP
VEA
V
OUT
V
IN
C
OUT
CEA2
V
=
REF
+1.0V
S
LOAD
I
PHASE2
CPWM2
DRIVE 2
CA2
C
CF
R
CF
*R AND R ARE
IN
F
EXTERNAL TO MAX5041A
C
(R = R8, R = R7, FIGURE 2).
CCF
F
IN
Figure 3b. MAX5041A Control Loop
14 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
The outer voltage control loop consists of the differen-
tial amplifier (DIFF AMP), reference voltage, and VEA.
The unity-gain differential amplifier provides true differ-
ential remote sensing of the output voltage. The differ-
ential amplifier output connects to the inverting input
(EAN) of the VEA. The noninverting input of the VEA is
internally connected to an internal precision reference
voltage. The MAX5041A reference voltage is set to
+1.0V and the MAX5038A reference is set to the preset
output voltage. The VEA controls the two inner current
loops (Figures 3a and 3b). Use a resistive feedback
network to set the VEA gain as required by the adaptive
voltage-positioning circuit (see the Adaptive Voltage
Positioning section).
than the average current limit (48mV). Proper inductor
selection ensures that only extreme conditions trip the
peak-current comparator, such as a broken output
inductor. The 112mV voltage threshold for triggering
the peak-current limit is twice the full-scale average
current-limit voltage threshold. The peak-current com-
parator has a delay of only 260ns.
Current-Error Amplifier
Each phase of the MAX5038A/MAX5041A has a dedi-
cated transconductance current-error amplifier (CEA_)
with a typical g of 550µS and 320µA output sink and
m
source current capability. The current-error amplifier
outputs, CLP1 and CLP2, serve as the inverting input to
the PWM comparator. CLP1 and CLP2 are externally
accessible to provide frequency compensation for the
inner current loops (Figures 3a and 3b). Compensate
CEA_ such that the inductor current down slope, which
becomes the up slope to the inverting input of the PWM
comparator, is less than the slope of the internally gen-
erated voltage ramp (see the Compensation section).
Current-Sense Amplifier
The differential current-sense amplifier (CA_) provides a
DC gain of 18. The maximum input offset voltage of the
current-sense amplifier is 1mV and the common-mode
voltage range is -0.3V to +3.6V. The current-sense ampli-
fier senses the voltage across a current-sense resistor.
Peak-Current Comparator
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 4).
Note that the average-current-limit threshold of 48mV
still limits the output current during short-circuit condi-
tions. To prevent inductor saturation, select an output
inductor with a saturation current specification greater
PWM Comparator and R-S Flip-Flop
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V
ramp. At the start of each clock
P-P
cycle, an R-S flip-flop resets and the high-side driver
(DH_) turns on. The comparator sets the flip-flop as
soon as the ramp voltage exceeds the CLP_ voltage,
thus terminating the ON cycle (Figure 4).
DRV_V
CC
PEAK-CURRENT
COMPARATOR
112mV
CLP_
CSP_
A = 18
V
G
=
m
CSN_
550µS
BST_
DH_
LX_
PWM
COMPARATOR
GM
IN
Q
Q
S
R
RAMP
CLK
2 x f (V/s)
s
DL_
PGND
SHDN
Figure 4. Phase Circuit (Phase 1/Phase 2)
______________________________________________________________________________________ 15
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Differential Amplifier
The differential amplifier (DIFF AMP) facilitates output
voltage remote sensing at the load (Figures 3a and 3b).
It provides true differential output voltage sensing while
rejecting the common-mode voltage errors due to high-
current ground paths. Sensing the output voltage
directly at the load provides accurate load voltage
sensing in high-current environments. The VEA pro-
vides the difference between the differential amplifier
output (DIFF) and the desired output voltage. The dif-
ferential amplifier has a bandwidth of 3MHz. The differ-
ence between SENSE+ and SENSE- regulates to the
preset output voltage for the MAX5038A and regulates
to +1V for the MAX5041A.
Use the following equations to calculate the value of R .
X
For MAX5038A versions of V
≤ +1.8V:
OUT(NOM)
R
F
R
= [V − (V + 0.6)]×
NOM
(5)
(6)
(7)
X
CC
V
NOM
For MAX5038A versions of V
> +1.8V:
OUT(NOM)
R
F
R
= [2V − (V +1.2)]×
NOM
X
CC
V
NOM
For MAX5041A:
R
F
R
= [V −1.6]×
X
CC
V
REF
The VEA output clamps to +0.9V (plus the common-
mode voltage of +0.6V), thus limiting the average maxi-
mum current from individual phases. The maximum
average-current-limit threshold for each phase is equal
to the maximum clamp voltage of the VEA divided by
the gain (18) of the current-sense amplifier. This allows
for accurate settings for the average maximum current
Voltage-Error Amplifier
The VEA sets the gain of the voltage control loop and
determines the error between the differential amplifier
output and the internal reference voltage (V
).
REF
V
equals V
for the +1.8V or lower voltage
REF
OUT(NOM)
versions of the MAX5038A and V
equals V
/2
REF
OUT(NOM)
for the +2.5V and +3.3V versions. For MAX5041A, V
equals +1V.
REF
for each phase. Set the VEA gain using R and R for
F
IN
the amount of output voltage positioning required as
discussed in the Adaptive Voltage Positioning section
(Figures 3a and 3b).
An offset is added to the output voltage of the
MAX5038A/MAX5041A with a finite gain (R /R ) of the
F
IN
VEA such that the no-load output voltage is higher than
Adaptive Voltage Positioning
Powering new-generation processors requires new
techniques to reduce cost, size, and power dissipation.
Voltage positioning reduces the total number of output
capacitors to meet a given transient response require-
ment. Setting the no-load output voltage slightly higher
than the output voltage during nominally loaded condi-
tions allows a larger downward voltage excursion when
the output current suddenly increases. Regulating at a
lower output voltage under a heavy load allows a larger
upward-voltage excursion when the output current sud-
denly decreases. A larger allowed, voltage-step excur-
sion reduces the required number of output capacitors
or allows for the use of higher ESR capacitors.
the nominal value. Choose R and R
from the
IN
F
Adaptive Voltage Positioning section and use the follow-
ing equations to calculate the no-load output voltage.
MAX5038A:
R
IN
(3)
V
= 1+
× V
OUT(NOM)
OUT(NL)
R
F
MAX5041A:
R
R + R
H L
IN
(4)
V
= 1+
×
× V
REF
OUT(NL)
R
F
R
L
where R and R are the feedback resistor network
H
L
Voltage positioning and the ability to operate with multiple
reference voltages may require the output to regulate
away from a center value. Define the center value as the
(Figure 2).
Some applications require V
equal to V
at
OUT
OUT(NOM)
voltage where the output drops (∆V
/2) at one half the
OUT
no load. To ensure that the output voltage does not
exceed the nominal output voltage (V ), add a
maximum output current (Figure 5).
OUT(NOM)
resistor R from V
to EAN.
CC
X
16 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Phase-Locked Loop: Operation and
Compensation
The PLL synchronizes the internal oscillator to the exter-
V
+ ∆V /2
CNTR
OUT
nal frequency source when driving CLKIN. Connecting
CLKIN to V
or SGND forces the PWM frequency to
CC
V
default to the internal oscillator frequency of 500kHz or
250kHz, respectively. The PLL uses a conventional
architecture consisting of a phase detector and a
charge pump capable of providing 20µA of output cur-
rent. Connect an external series combination capacitor
(C25) and resistor (R4) and a parallel capacitor (C26)
from PLLCMP to SGND to provide frequency compen-
sation for the PLL (Figure 1). The pole-zero pair com-
CNTR
V
- ∆V /2
OUT
CNTR
FULL LOAD
1/2 LOAD
LOAD (A)
NO LOAD
pensation provides a zero at f defined by 1 / [R4 x
Z
(C25 + C26)] and a pole at f defined by 1 / (R4 x C26).
P
Use the following typical values for compensating the
PLL: R4 = 7.5kΩ, C25 = 4.7nF, C26 = 470pF. If chang-
ing the PLL frequency, expect a finite locking time of
approximately 200µs.
Figure 5. Defining the Voltage-Positioning Window
Set the voltage-positioning window (∆V
) using the
OUT
resistive feedback of the VEA. Use the following equa-
tions to calculate the voltage-positioning window for the
MAX5038A:
The MAX5038A/MAX5041A require compensation on
PLLCMP even when operating from the internal oscilla-
tor. The device requires an active PLL in order to gen-
erate the proper internal PWM clocks.
I
× R
IN
OUT
(8)
∆V
=
OUT
MOSFET Gate Drivers (DH_, DL_)
The high-side (DH_) and low-side (DL_) drivers drive
the gates of external N-channel MOSFETs (Figures 1
and 2). The drivers’ high-peak sink and source current
capability provides ample drive for the fast rise and fall
times of the switching MOSFETs. Faster rise and fall
times result in reduced cross-conduction losses. For
modern CPU voltage-regulating module applications
where the duty cycle is less than 50%, choose high-
2 × G × R
C
F
0.05
(9)
G
=
C
R
S
Use the following equation to calculate the voltage-posi-
tioning window for the MAX5041A:
side MOSFETs (Q1 and Q3) with a moderate R
DS(ON)
and a very low gate charge. Choose low-side MOSFETs
(Q2 and Q4) with very low R
charge.
and moderate gate
I
×R
R +R
H L
DS(ON)
(10)
OUT
IN
∆V
=
×
OUT
2×G ×R
R
(
)
C
F
L
The driver block also includes a logic circuit that pro-
vides an adaptive nonoverlap time to prevent shoot-
through currents during transition. The typical
nonoverlap time is 60ns between the high-side and low-
side MOSFETs.
0.05
(11)
G
=
C
R
S
BST_
V
powers the low- and high-side MOSFET drivers.
CC
where R and R are the input and feedback resistors of
IN
F
Connect a 0.47µF low-ESR ceramic capacitor between
BST_ and LX_. Bypass V to SGND with 4.7µF and
the VEA, G is the current-loop transconductance, and
C
CC
R is the current-sense resistor or, if using lossless induc-
S
0.1µF low-ESR ceramic capacitors. For high-current
applications, bypass V to PGND with one or more
tor current sensing, the DC resistance of the inductor.
CC
0.1µF, low-ESR ceramic capacitor(s). Reduce the PC
board area formed by these capacitors, the rectifier
diodes between V
and the boost capacitor, the
CC
MAX5038A/MAX5041A, and the switching MOSFETs.
______________________________________________________________________________________ 17
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
The examples discussed in this data sheet pertain to a
typical application with the following specifications:
Overload Conditions
Average-current-mode control has the ability to limit the
average current sourced by the converter during a fault
condition. When a fault condition occurs, the VEA out-
put clamps to +0.9V with respect to the common-mode
VIN = +12V
VOUT = +1.8V
IOUT(MAX) = 52A
voltage (V
= +0.6V) and is compared with the output
CM
of the current-sense amplifiers (CA1 and CA2) (see
Figures 3a and 3b). The current-sense amplifier’s gain
of 18 limits the maximum current in the inductor or
fSW = 250kHz
Peak-to-Peak Inductor Current (∆IL) = 10A
Table 1 shows a list of recommended external compo-
nents (Figure 1) and Table 2 provides component sup-
plier information.
sense resistor to I
= 50mV/R .
S
LIMIT
Parallel Operation
For applications requiring large output current, parallel
up to three MAX5038A/MAX5041As (six phases) to triple
the available output current. The paralleled converters
operate at the same switching frequency but different
phases keep the capacitor ripple RMS currents to a mini-
mum. Three parallel MAX5038A/MAX5041A converters
deliver up to 180A of output current. To set the phase
shift of the on-board PLL, leave PHASE unconnected for
90° of phase shift (two paralleled converters), or connect
PHASE to SGND for 60° of phase shift (three converters
in parallel). Designate one converter as master and the
remaining converters as slaves. Connect the master and
slave controllers in a daisy-chain configuration as shown
in Figure 6. Connect CLKOUT from the master controller
to CLKIN of the first slaved controller, and CLKOUT from
the first slaved controller to CLKIN of the second slaved
controller. Choose the appropriate phase shift for mini-
mum ripple currents at the input and output capacitors.
The master controller senses the output differential volt-
age through SENSE+ and SENSE- and generates the
DIFF voltage. Disable the voltage sensing of the slaved
controllers by leaving DIFF unconnected (floating).
Figure 7 shows a detailed typical parallel application cir-
cuit using two MAX5038As. This circuit provides four
phases at an input voltage of +12V and an output volt-
age range of +1V to +3.3V at 104A.
Number of Phases
Selecting the number of phases for a voltage regulator
depends mainly on the ratio of input-to-output voltage
(operating duty cycle). Optimum output-ripple cancella-
tion depends on the right combination of operating duty
cycle and the number of phases. Use the following
equation as a starting point to choose the number of
phases:
(12)
NPH ≈ K/D
where K = 1, 2, or 3 and the duty cycle is D = VOUT/VIN.
Choose K to make NPH an integer number. For exam-
ple, converting VIN = +12V to VOUT = +1.8V yields
better ripple cancellation in the six-phase converter
than in the four-phase converter. Ensure that the output
load justifies the greater number of components for
multiphase conversion. Generally limiting the maximum
output current to 25A per phase yields the most cost-
effective solution. The maximum ripple cancellation
occurs when NPH = K/D.
Single-phase conversion requires greater size and power
dissipation for external components such as the switch-
ing MOSFETs and the inductor. Multiphase conversion
eliminates the heatsink by distributing the power dissipa-
tion in the external components. The multiple phases
operating at given phase shifts effectively increase the
switching frequency seen by the input/output capacitors,
thereby reducing the input/output capacitance require-
ment for the same ripple performance. The lower induc-
tance value improves the large-signal response of the
converter during a transient load at the output. Consider
all these issues when determining the number of phases
necessary for the voltage regulator application.
Applications Information
Each MAX5038A/MAX5041A circuit drives two 180° out-
of-phase channels. Parallel two or three MAX5038A/
MAX5041A circuits to achieve four- or six-phase opera-
tion, respectively. Figure 1 shows the typical application
circuit for a two-phase operation. The design criteria for
a two-phase converter includes frequency selection,
inductor value, input/output capacitance, switching
MOSFETs, sense resistors, and the compensation net-
work. Follow the same procedure for the four- and six-
phase converter design, except for the input and output
capacitance. The input and output capacitance require-
ments vary depending on the operating duty cycle.
Inductor Selection
The switching frequency per phase, peak-to-peak rip-
ple current in each phase, and allowable ripple at the
output determine the inductance value.
18 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
CSN1
CSP1
SENSE+
SENSE-
V
IN
DH1
LX1
DL1
V
CC
PHASE
V
CC
MAX5038A/
MAX5041A
V
IN
CLKIN
IN
DH2
LX2
DL2
V
IN
DIFF
EAN
CSP2
CSN2
EAOUT
PGND SGND CLKOUT
CSN1
CSP1
CLKIN
PHASE
V
V
IN
DH1
LX1
DL1
V
CC
MAX5038A/
MAX5041A
IN
IN
DH2
LX2
DL2
*
*
DIFF
LOAD
EAN
CSP2
CSN2
EAOUT
PGND SGND CLKOUT
CSN1
CSP1
CLKIN
PHASE
V
V
IN
DH1
LX1
DL1
V
CC
MAX5038A/
MAX5041A
IN
IN
DH2
LX2
DL2
DIFF
EAN
CSP2
CSN2
EAOUT
*FOR MAX5041A ONLY.
PGND SGND CLKOUT
TO OTHER MAX5038A/MAX5041As
Figure 6. Parallel Configuration of Multiple MAX5038A/MAX5041As
______________________________________________________________________________________ 19
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
V
IN
= +12V
C1, C2
2 x 47µF
V
CC
C31
R3
2.2Ω
C32
C39
0.1µF
R4
V
IN
C3–C7
5 x 22µF
PLLCMP CLKIN
IN
SENSE- SENSE+ CSN1 CSP1
DH1
LX1
DL1
Q1
L1
0.6µH
R1
1.35mΩ
C12
0.47µF
Q2
D1
BST1
D3
V
CC
V
EN
CC
C38
4.7µF
C40
0.1µF
D4
OVPIN
DIFF
V
CC
R7
R8
V
IN
MAX5038A
(MASTER)
4 x 22µF
C8–C11
EAN
DH2
LX2
DL2
Q3
L2
0.6µH
R2
1.35mΩ
R
X
EAOUT
C13
0.47µF
Q4
D2
BST2
CLP1
CLP2 PGND SGND CLKOUT PHASE PGOOD CSN2 CSP2
R9
R6
R5
C36
C34
PGOOD
V
CC
C35
C33
R18
C26–C30,
C37
LOAD
6 x 10µF
C14, C15,
C41, C42
2 x 100µF
V
= +1.2V TO
OUT
+3.3V AT 104A
C62
R13
C16–C25,
C43–C46
R12
2.2Ω
C63
14 x 270µF
R19
C47
0.1µF
V
IN
C48–C51
5 x 22µF
EN
PLLCMP IN
CLKIN SENSE-SENSE+ CSN1 CSP1
DH1
LX1
DL1
Q5
Q6
L3
0.6µH
R10
1.35mΩ
C57
0.47µF
D5
BST1
D7
V
CC
C65
4.7µF
C64
0.1µF
D8
MAX5038A
(SLAVE)
R16
V
CC
V
IN
C52–C55
4 x 22µF
EAN
R11
1.35mΩ
DH2
LX2
DL2
Q7
L4
0.6µH
R
X
R17
EAOUT
DIFF
C56
0.47µF
Q8
D6
BST2
CLP1
CLP2
R14
PGND
SGND
PHASE
CSN2 CSP2
R15
C59
C58
C61
V
CC
C60
Figure 7. Four-Phase Parallel Application Circuit (V = +12V, V
= +1.2V to +3.3V at 104A)
IN
OUT
20 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Table 1. Component List
DESIGNATION
C1, C2
QTY
2
DESCRIPTION
47µF,16V X5R input-filter capacitors, TDK C5750X5R1C476M
22µF, 16V input-filter capacitors, TDK C4532X5R1C226M
0.47µF, 16V capacitors, TDK C1608X5R1A474K
C3–C11
C12, C13
C14, C15
C16–C24, C33
C25
9
2
2
100µF, 6.3V output-filter capacitors, Murata GRM44-1X5R107K6.3
270µF, 2V output-filter capacitors, Panasonic EEFUE0D271R
4700pF, 16V X7R capacitor, Vishay-Siliconix VJ0603Y471JXJ
470pF, 16V capacitors, Murata GRM1885C1H471JAB01
0.01µF, 50V X7R capacitors, Murata GRM188R71H103KA01
4.7µF, 16V X5R capacitor, Murata GRM40-034X5R475k6.3
0.1µF, 16V X7R capacitors, Murata GRM188R71C104KA01
Schottky diodes, ON Semiconductor MBRS340T3
10
1
C26, C28, C30
C27, C29
C31
3
2
1
C32, C34, C39
D1, D2
3
2
D3, D4
2
Schottky diodes, ON Semiconductor MBR0520LT1
L1, L2
2
0.6µH, 27A inductors, Panasonic ETQP1H0R6BFX
Q1, Q3
Q2, Q4
R1
2
Upper power MOSFETs, Vishay-Siliconix Si7860DP
Lower power MOSFETs, Vishay-Siliconix Si7886DP
2
1
2.2
1% resistor
R2, R3
4
Current-sense resistors, use two 2.7m resistors in parallel, Panasonic ERJM1WSF2M7U
R4
1
7.5k
1k
1% resistor
1% resistors
1% resistor
1% resistors
R5, R6
2
R7
1
4.99k
37.4k
R8, R9
2
Table 2. Component Suppliers
SUPPLIER
PHONE
770-436-1300
FAX
WEBSITE
www.murata.com
Murata
770-436-3030
602-244-3345
714-373-7183
847-390-4405
619-474-8920
ON Semiconductor
Panasonic
602-244-6600
714-373-7939
847-803-6100
1-800-551-6933
www.on-semi.com
www.panasonic.com
www.tcs.tdk.com
www.vishay.com
TDK
Vishay-Siliconix
______________________________________________________________________________________ 21
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Selecting higher switching frequencies reduces the
inductance requirement, but at the cost of lower efficien-
cy. The charge/discharge cycle of the gate and drain
capacitances in the switching MOSFETs create switching
losses. The situation worsens at higher input voltages,
since switching losses are proportional to the square of
input voltage. Use 500kHz per phase for VIN = +5V and
250kHz or less per phase for VIN > +12V.
Use the following equation to determine the worst-case
inductor current for each phase:
∆I
2
0.051
L
(15)
I
=
+
L_PEAK
R
SENSE
where RSENSE is the sense resistor in each phase.
Although lower switching frequencies per phase increase
the peak-to-peak inductor ripple current (∆IL), the ripple
cancellation in the multiphase topology reduces the RMS
ripple current of the input and output capacitors.
Switching MOSFETs
When choosing a MOSFET for voltage regulators,
consider the total gate charge, RDS(ON), power dissipa-
tion, and package thermal impedance. The product of
the MOSFET gate charge and on-resistance is a figure of
merit, with a lower number signifying better performance.
Choose MOSFETs optimized for high-frequency switch-
ing applications.
Use the following equation to determine the minimum
inductance value:
V
− V
× V
OUT
(
)
INMAX
OUT
L
=
MIN
The average current from the MAX5038A/MAX5041A
gate-drive output is proportional to the total capacitance
it drives from DH1, DH2, DL1, and DL2. The power dissi-
pated in the MAX5038A/MAX5041A is proportional to the
input voltage and the average drive current. See the VIN
and VCC section to determine the maximum total gate
charge allowed from all the driver outputs combined.
(13)
V
× f
× ∆I
IN SW
L
Choose ∆IL equal to about 40% of the output current
per phase. Since ∆IL affects the output-ripple voltage,
the inductance value may need minor adjustment after
choosing the output capacitors for full-rated efficiency.
Choose inductors from the standard high-current,
surface-mount inductor series available from various
manufacturers. Particular applications may require cus-
tom-made inductors. Use high-frequency core material
for custom inductors. High ∆IL causes large peak-to-peak
flux excursion increasing the core losses at higher fre-
quencies. The high-frequency operation coupled with
high ∆IL, reduces the required minimum inductance
and even makes the use of planar inductors possible.
The advantages of using planar magnetics include low-
profile design, excellent current-sharing between phas-
es due to the tight control of parasitics, and low cost.
The gate charge and drain capacitance (CV2) loss, the
cross-conduction loss in the upper MOSFET due to finite
rise/fall time, and the I2R loss due to RMS current in the
MOSFET RDS(ON) account for the total losses in the MOS-
FET. Estimate the power loss (PDMOS_) in the high-side
and low-side MOSFETs using following equations:
PD
= Q × V × f
+
(
)
MOS−HI
×I
G
DD SW
(16)
V
× t + t × f
(
)
IN OUT
R
F
SW
2
+1.4R
DS(ON)
×I
RMS−HI
4
For example, calculate the minimum inductance at
where QG, RDS(ON), tR, and tF are the upper-switching
MOSFET’s total gate charge, on-resistance at +25°C,
rise time, and fall time, respectively:
VIN(MAX) = +13.2V, VOUT = +1.8V, ∆IL = 10A, and fSW
=
250kHz:
13.2 −1.8 ×1.8
(
)
(14)
L
=
= 0.6µH
D
3
MIN
2
2
(17)
13.2 × 250k ×10
I
=
I
+I
+I ×I
PK
×
DC
RMS−HI
DC PK
(
)
The average-current-mode control feature of the
MAX5038A/MAX5041A limits the maximum peak induc-
tor current and prevents the inductor from saturating.
Choose an inductor with a saturating current greater
than the worst-case peak inductor current.
where D = VOUT/VIN, IDC = (IOUT - ∆IL)/2, and IPK
(IOUT + ∆IL)/2.
=
22 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Input Capacitors
PD
= Q × V × f
+
(
)
MOS−LO
G
DD SW
The discontinuous input-current waveform of the buck
converter causes large ripple currents in the input
capacitor. The switching frequency, peak inductor cur-
rent, and the allowable peak-to-peak voltage ripple
reflected back to the source dictate the capacitance
requirement. Increasing the number of phases increas-
es the effective switching frequency and lowers the
peak-to-average current ratio, yielding a lower input
capacitance requirement.
2
(18)
2 × C
× V
3
× f
2
OSS
IN
SW
+1.4R
×I
RMS−LO
DS(ON)
1−D
(
)
2
2
(19)
I
=
I
+I
+I ×I
PK
×
DC
RMS−LO
DC PK
(
)
3
The input ripple comprises ∆VQ (caused by the capaci-
tor discharge) and ∆VESR (caused by the ESR of the
capacitor). Use low-ESR ceramic capacitors with high
ripple-current capability at the input. Assume the contri-
butions from the ESR and capacitor discharge are
equal to 30% and 70%, respectively. Calculate the
input capacitance and ESR required for a specified rip-
ple using the following equations:
where C
tance.
is the MOSFET drain-to-source capaci-
OSS
For example, from the typical specifications in the
Applications Information section with VOUT = +1.8V, the
high-side and low-side MOSFET RMS currents are 9.9A
and 24.1A, respectively. Ensure that the thermal imped-
ance of the MOSFET package keeps the junction tem-
perature at least 25°C below the absolute maximum
rating. Use the following equation to calculate maxi-
mum junction temperature:
∆V
(
)
ESR
ESR
=
IN
I
∆I
(21)
OUT
N
L
+
T = PD
J
x θ
+ T
A
(20)
MOS
J-A
2
Table 3. Peak-to-Peak Output Ripple
Current Calculations
I
OUT
N
∆V × f
×D 1−D
(
)
(22)
C
=
IN
Q
SW
NO. OF
PHASES (N)
DUTY CYCLE
(D) (%)
EQUATION FOR
I
P-P
where IOUT is the total output current of the multiphase
converter and N is the number of phases.
V (1−2D)
O
∆I=
For example, at VOUT = +1.8V, the ESR and input
capacitance are calculated for the input peak-to-peak
ripple of 100mV or less yielding an ESR and capaci-
tance value of 1mΩ and 200µF.
2
2
4
4
4
6
< 50
> 50
L × f
SW
V
− V 2D−1
)(
(
)
IN
O
∆I=
Output Capacitors
The worst-case peak-to-peak and capacitor RMS ripple
current, the allowable peak-to-peak output ripple volt-
age, and the maximum deviation of the output voltage
during step loads determine the capacitance and the
ESR requirements for the output capacitors.
L × f
SW
V (1− 4D)
O
0 to 25
25 to 50
> 50
∆I=
L × f
SW
V (1−2D)(4D−1)
In multiphase converter design, the ripple currents from
the individual phases cancel each other and lower the
ripple current. The degree of ripple cancellation
depends on the operating duty cycle and the number of
phases. Choose the right equation from Table 3 to calcu-
late the peak-to-peak output ripple for a given duty
cycle of two-, four-, and six-phase converters. The max-
imum ripple cancellation occurs when NPH = K / D.
O
∆I=
∆I=
2×D×L × f
SW
V (2D−1)(3− 4D)
O
D×L × f
SW
V (1− 6D)
O
< 17
∆I=
L × f
SW
______________________________________________________________________________________ 23
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
The allowable deviation of the output voltage during the
fast transient load dictates the output capacitance and
ESR. The output capacitors supply the load step until
the controller responds with a greater duty cycle. The
response time (tRESPONSE) depends on the closed-loop
bandwidth of the converter. The resistive drop across
the capacitor ESR and capacitor discharge causes a
voltage drop during a step load. Use a combination of
SP polymer and ceramic capacitors for better transient
load and ripple/noise performance.
Reverse Current Limit
The MAX5038A/MAX5041A limit the reverse current in
the case that VBUS is higher than the preset output volt-
age setting.
Calculate the maximum reverse current based on V
,
CLR
the reverse current-limit threshold, and the current-
sense resistor:
(27)
2 × V
CLR
I
=
REVERSE
R
Keep the maximum output voltage deviation less than
or equal to the adaptive voltage-positioning window
(∆VOUT). Assume 50% contribution each from the out-
put capacitance discharge and the ESR drop. Use the
following equations to calculate the required ESR and
capacitance value:
SENSE
Compensation
The main control loop consists of an inner current loop
and an outer voltage loop. The MAX5038A/MAX5041A
use an average-current-mode control scheme to regu-
late the output voltage (Figures 3a and 3b). IPHASE1 and
IPHASE2 are the inner average current loops. The VEA
output provides the controlling voltage for these current
sources. The inner current loop absorbs the inductor
pole reducing the order of the outer voltage loop to that
of a single-pole system.
∆V
ESR
(23)
ESR
=
OUT
I
STEP
I
× t
STEP
RESPONSE
(24)
C
=
OUT
∆V
Q
A resistive feedback network around the VEA provides
the best possible response, since there are no capaci-
tors to charge and discharge during large-signal excur-
where ISTEP is the load step and tRESPONSE is the
response time of the controller. Controller response
time depends on the control-loop bandwidth.
sions, R and R determine the VEA gain. Use the
F
IN
following equation to calculate the value for RF:
Current Limit
The average-current-mode control technique of the
MAX5038A/MAX5041A accurately limits the maximum
output current per phase. The MAX5038A/MAX5041A
sense the voltage across the sense resistor and limit
the peak inductor current (IL-PK) accordingly. The ON
cycle terminates when the current-sense voltage reach-
es 45mV (min). Use the following equation to calculate
maximum current-sense resistor value:
(28)
I
× R
OUT
IN
R
=
F
N× G × ∆V
C
OUT
(29)
0.05
G
=
C
R
S
where GC is the current-loop transconductance and N
is the number of phases.
0.045
R
=
SENSE
(25)
I
When designing the current-control loop ensure that the
inductor downslope (when it becomes an upslope at the
CEA output) does not exceed the ramp slope. This is a
necessary condition to avoid subharmonic oscillations
similar to those in peak-current-mode control with insuf-
ficient slope compensation. Use the following equation
OUT
N
−3
2.5×10
R
(26)
PD =
R
SENSE
where PDR is the power dissipation in sense resistors.
Select 5% lower value of RSENSE to compensate for any
parasitics associated with the PC board. Also, select a
noninductive resistor with the appropriate wattage rating.
to calculate the resistor RCF
:
(30)
2
2× f ×L ×10
SW
R
≤
CF
V
×R
OUT
SENSE
For example, the maximum RCF is 12kΩ for RSENSE
1.35mΩ.
=
24 ______________________________________________________________________________________
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
CCF provides a low-frequency pole while RCF provides a
midband zero. Place a zero (fZ) to obtain a phase bump
at the crossover frequency. Place a high-frequency pole
Pin Configuration
TOP VIEW
(fP) at least a decade away from the crossover frequency
to reduce the influence of the switching noise and
achieve maximum phase margin. Use the following
CSP2
CSN2
1
2
3
4
5
6
7
8
9
28 CLKIN
27 CLKOUT
26 BST2
25 DH2
24 LX2
equations to calculate CCF and CCFF
:
PHASE
PLLCMP
CLP2
1
C
C
=
(31)
(32)
CF
2× π × f ×R
Z
CF
MAX5038A
MAX5041A
1
SGND
23 DL2
=
CFF
2× π × f ×R
P
CF
CLP1
22 PGND
21 IN
SENSE+
SENSE-
PC Board Layout
Use the following guidelines to lay out the switching
voltage regulator:
20
V
CC
DIFF 10
EAN 11
19 DL1
18 LX1
17 DH1
16 BST1
15 EN
1) Place the VIN and VCC bypass capacitors close to
the MAX5038A/MAX5041A.
EAOUT 12
CSP1 13
CSN1 14
2) Minimize the area and length of the high-current
loops from the input capacitor, upper switching
MOSFET, inductor, and output capacitor back to
the input capacitor negative terminal.
SSOP
3) Keep short the current loop formed by the lower
switching MOSFET, inductor, and output capacitor.
4) Place the Schottky diodes close to the lower
MOSFETs and on the same side of the PC board.
9) Distribute the power components evenly across the
board for proper heat dissipation.
5) Keep the SGND and PGND isolated and connect
them at one single point close to the negative termi-
nal of the input filter capacitor.
10) Provide enough copper area at and around the
switching MOSFETs, inductor, and sense resistors
to aid in thermal dissipation.
6) Run the current-sense lines CS+ and CS- very
close to each other to minimize the loop area.
Similarly, run the remote voltage sense lines
SENSE+ and SENSE- close to each other. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
11) Use 4oz copper to keep the trace inductance and
resistance to a minimum. Thin copper PC boards
can compromise efficiency since high currents are
involved in the application. Also, thicker copper
conducts heat more effectively, thereby reducing
thermal impedance.
7) Avoid long traces between the VCC bypass capaci-
tors, driver output of the MAX5038A/MAX5041A,
MOSFET gates, and PGND. Minimize the loop
formed by the VCC bypass capacitors, bootstrap
diode, bootstrap capacitor, MAX5038A/MAX5041A,
and upper MOSFET gate.
Chip Information
TRANSISTOR COUNT: 5431
PROCESS: BiCMOS
8) Place the bank of output capacitors close to the load.
______________________________________________________________________________________ 25
Dual-Phase, Parallelable, Average-Current-Mode
Controllers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.
2
1
INCHES
MILLIMETERS
MAX
MAX
1.99
0.21
0.38
0.20
DIM
A
MIN
0.068
MIN
1.73
0.05
0.25
0.09
INCHES
MAX
MILLIMETERS
MAX
6.33
6.33
7.33
MIN
MIN
6.07
6.07
7.07
8.07
N
0.078
14L
16L
20L
A1
B
D
D
D
D
D
0.239 0.249
0.239 0.249
0.278 0.289
0.317 0.328
0.002 0.008
0.010 0.015
0.004 0.008
C
8.33 24L
E
H
SEE VARIATIONS
0.205 0.212 5.20
0.0256 BSC
D
0.397 0.407 10.07 10.33
28L
E
5.38
e
0.65 BSC
H
0.301 0.311 7.65
0.025 0.037 0.63
7.90
0.95
8∞
L
0∞
8∞
0∞
N
A
C
B
L
e
A1
D
NOTES:
1. D&E DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006").
3. CONTROLLING DIMENSION: MILLIMETERS.
4. MEETS JEDEC MO150.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL
DOCUMENT CONTROL NO.
REV.
5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
1
21-0056
C
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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