MAX503CNG_技术文档

19-0279; Rev 0; 8/94

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

♦ Buffered Voltage Output

♦ Internal 2.048V Voltage Reference

The MAX503 is a low-power, 10-bit, voltage-output digital-

to-analog converter (DAC) that uses single 5V or dual ±5V

supplies. This device has an internal voltage reference plus

an output buffer amplifier. Operating current is only 250µA

from a single 5V supply, making it ideal for portable and

battery-powered applications. In addition, the shrink small-

outline package (SSOP) measures only 0.1 square inches,

using less board area than an 8-pin DIP. 10-bit resolution is

achieved through laser trimming of the DAC, op amp, and

reference. No further adjustments are necessary.

♦ Operates from Single 5V or Dual ±5V Supplies

♦ Low Power Consumption:

250µA Operating Current

40µA Shutdown-Mode Current

♦ SSOP Package Saves Space

♦ Relative Accuracy: ±¹₂LSB Max Over

/

Temperature

Internal gain-setting resistors can be used to define a DAC

output voltage range of 0V to +2.048V, 0V to +4.096V, or

±2.048V. Four-quadrant multiplication is possible without

the use of external resistors or op amps. The parallel logic

inputs are double buffered and are compatible with 4-bit, 8-

bit, and 16-bit microprocessors. For a hardware and soft-

ware compatible 12-bit upgrade, refer to the MAX530 data

sheet. For DACs with similar features but with a serial data

interface, refer to the MAX504/MAX515 data sheet.

♦ Guaranteed Monotonic Over Temperature

♦ 4-Quadrant Multiplication with No External

Components

♦ Power-On Reset

♦ Double-Buffered Parallel Logic Inputs

______________Ord e rin g In fo rm a t io n

PART

TEMP. RANGE

PIN-PACKAGE

________________________Ap p lic a t io n s

Battery-Powered Data-Conversion Products

Minimum Component-Count Analog Systems

Digital Offset/Gain Adjustment

MAX503CNG

MAX503CWG

MAX503CAG

MAX503ENG

MAX503EWG

MAX503EAG

0°C to +70°C

-40°C to +85°C

24 Narrow Plastic DIP

24 Wide SO

24 SSOP

24 Narrow Plastic DIP

24 Wide SO

Industrial Process Control

Arbitrary Function Generators

24 SSOP

Automatic Test Equipment

Refer to the MAX530 for military temperature or die equivalents.

Microprocessor-Controlled Calibration

________________Fu n c t io n a l Dia g ra m

__________________P in Co n fig u ra t io n

TOP VIEW

REFOUT

18

REFIN ROFS

13

22

D7/S1

D8/D0

D9/D1

D2

1

2

3

4

5

6

7

8

9

24

D6/S0

21

20

RFB

V

DD

23

22

2.048V

REFERENCE

ROFS

RFB

17

14

VOUT

REFGND

AGND

21

20

19

18

17

DAC

MAX503

D3

D4

D5

A0

VOUT

POWER-ON

RESET

23

12

19

V

DD

V

SS

MAX503

10D-BAICT DLATCCLHATCH

DGND

REFOUT

REFGND

LDAC

15

8

V

SS

CLR

A0

9

A1

NBL

INPUT

LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

A1

16

15

14

13

CONTROL

LOGIC

11

10

16

CS

WR 10

WR

CLR

LDAC

CS

11

AGND

REFIN

24

D6/S0

D7/S1

1

2

3

4

5 6 7

DGND

12

D2

D8/D0

D9/D1 D3 D5

D4

DIP/SO/SSOP

________________________________________________________________ Maxim Integrated Products

1

Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

VOUT to AGND (Note 1) .............................................. V

V

SS, DD

ABSOLUTE MAXIMUM RATINGS

Continuous Current, Any Input ........................................±20mA

V

DD

to DGND and V to AGND ................................-0.3V, +6V

DD

Continuous Power Dissipation (T = +70°C)

A

V

SS

to DGND and V to AGND .................................-6V, +0.3V

SS

Narrow Plastic DIP (derate 13.33mW/°C above +70°C)...1067mW

Wide SO (derate 11.76mW/°C above +70°C)............... 941mW

SSOP (derate 8.00mW/°C above +70°C) ......................640mW

Operating Temperature Ranges

MAX503C_G .........................................................0°C to +70°C

MAX503E_G ......................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +165°C

Lead Temperature (soldering, 10sec) ........................... +300°C

V

DD

to V ............................................................... -0.3V, +12V

SS

AGND to DGND........................................................-0.3V, +0.3V

REFGND to AGND.........................................-0.3V, (V + 0.3V)

Digital Input Voltage to DGND .................... -0.3V, (V + 0.3V)

DD

REFIN..................................................(V - 0.3V), (V + 0.3V)

SS

MAX503

REFOUT ..............................................(V - 0.3V), (V + 0.3V)

SS

REFOUT to REFGND.................................... -0.3V, (V + 0.3V)

RFB ....................................................(V - 0.3V), (V + 0.3V)

SS

ROFS ..................................................(V - 0.3V), (V + 0.3V)

SS

DD

Note 1: The output may be shorted to V , V , DGND, or AGND if the continuous package power dissipation and current ratings

DD SS

are not exceeded. Typical short-circuit currents are 20mA.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(V = 5V, V = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 33µF,

DD

SS

REFOUT

R

= 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted.)

CONDITIONS

L

A

MIN

MAX

PARAMETER

SYMBOL

MIN

TYP

MAX UNITS

STATIC PERFORMANCE

Resolution

N

10

Bits

Relative Accuracy

Differential Nonlinearity

Unipolar Offset Error

INL

DNL

(Note 2)

±0.5

±1

3

LSB

Guaranteed monotonic

V

OS

0

0.25

3

Unipolar Offset

Temperature Coefficient

TCV

ppm/°C

LSB/V

OS

Unipolar Offset-Error

Supply Rejection

PSRR

GE

4.5V ≤ V ≤ 5.5V

0.1

DD

DAC latch = all 1s,

VOUT < V - 0.4V (Note 2)

Gain Error (Note 2)

±1

LSB

DD

Gain-Error Temperature Coefficient

Gain-Error Power-Supply Rejection

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range

1

ppm/°C

LSB/V

PSRR

4.5V ≤ V ≤ 5.5V

0.1

DD

0

2

V

DD

- 0.4

V

kΩ

Ω

Resistive Load

VOUT = 2V, load regulation ≤ ±0.5LSB

DC Output Impedance

0.2

12

Short-Circuit Current

I

SC

mA

REFERENCE INPUT (REFIN)

Reference Input Range

0

V

DD

- 2

V

Reference Input Resistance

Reference Input Capacitance

AC Feedthrough

Code dependent, minimum at code 0101...

Code dependent (Note 3)

(Note 4)

40

10

kΩ

pF

dB

50

-80

2

_______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(V = 5V, V = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 33µF,

DD

SS

REFOUT

R

= 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

REFERENCE OUTPUT (REFOUT)

T

= +25°C

2.024

2.015

2.011

2.048

2.072

2.081

2.085

2

A

Reference Tolerance

V

MAX503C

MAX503E

(Note 5)

V

REFOUT

Reference Output Resistance

Power-Supply Rejection Ratio

Noise Voltage

R

Ω

µV/V

µVp-p

ppm/°C

µF

REFOUT

PSRR

4.5V ≤ V ≤ 5.5V

200

400

30

DD

e

0.1Hz to 10kHz

n

Temperature Coefficient

Required External Capacitor

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

Voltage Output Settling Time

Digital Feedthrough

C

3.3

REFOUT

T

A

= +25°C

0.15

0.25

25

5

V/µs

µs

To ±0.5LSB, VOUT = 2V

WR = V , digital inputs all 1s to all 0s

DD

nV-s

Unity gain (Note 4)

Gain = 2 (Note 4)

68

Signal-to-Noise Plus

Distortion Ratio

SINAD

dB

DIGITAL INPUTS (S0, S1, D0–D9, LDAC, CLR, CS, WR, A0, A1)

Logic High Input

V

2.4

4.5

V

IH

Logic Low Input

V

IL

0.8

±1

Digital Leakage Current

Digital Input Capacitance

POWER SUPPLIES

Positive Supply-Voltage Range

Positive Supply Current

SWITCHING CHARACTERISTICS

Address to WR Setup

Address to WR Hold

CS to WR Setup

V

= 0V or V

µA

pF

IN

DD

8

V

DD

5.5

V

I

DD

Outputs unloaded, all digital inputs = 0V or V

250

400

µA

DD

t

5

ns

AWS

t

AWH

t

0

CWS

CS to WR Hold

t

0

CWH

t_DS

Data to WR Setup

45

0

t_DH

Data to WR Hold

WR Pulse Width

t

45

WR

LDAC Pulse Width

t

LDAC

CLR Pulse Width

t

CLR

Internal Power-On Reset

Pulse Width

t

(Note 3)

1.3

10

µs

POR

_______________________________________________________________________________________

3

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies

(V = 5V, V = -5V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 33µF,

DD

SS

REFOUT

R

= 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

STATIC PERFORMANCE

Resolution

N

10

Bits

MAX503

Relative Accuracy

Differential Nonlinearity

Bipolar Offset Error

INL

DNL

+0.5

±1

LSB

Guaranteed monotonic

V

OS

±3

Bipolar Offset

TCV

3

ppm/°C

LSB/V

OS

Temperature Coefficient

Bipolar Offset-Error

Power-Supply Rejection

PSRR

4.5V ≤ V ≤ 5.5V, -5.5V ≤ V ≤ -4.5V

0.1

DD

SS

Gain Error

±1

LSB

Gain-Error Temperature Coefficient

Gain-Error Power-Supply Rejection

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range

TC

1

ppm/°C

LSB/V

PSRR

4.5V ≤ V ≤ 5.5V, -5.5V ≤ V ≤ -4.5V

0.1

DD

SS

V

+ 0.4

V

DD

- 0.4

V

kΩ

Ω

SS

Resistive Load

VOUT = 2V, load regulation ≤ ±0.5LSB

2

DC Output Impedance

0.2

20

Short-Circuit Current

I

SC

mA

REFERENCE INPUT (REFIN)

Reference Input Range

V

SS

+ 2

V

DD

- 2

V

Reference Input Resistance

Reference Input Capacitance

AC Feedthrough

Code dependent, minimum at code 0101...

Code dependent (Note 3)

(Note 4)

40

10

kΩ

pF

dB

50

-80

REFERENCE OUTPUT (REFOUT)—Specifications are identical to those under Single +5V Supply

DYNAMIC PERFORMANCE—Specifications are identical to those under Single +5V Supply

DIGITAL INPUTS (S0, S1, D0–D9, LDAC, CLR, CS, WR, A0, A1)—Specifications are identical to those under Single +5V Supply

POWER SUPPLIES

Positive Supply Voltage

Negative Supply Voltage

Positive Supply Current

Negative Supply Current

V

4.5

5.5

0

V

DD

V

SS

-5.5

I

DD

Outputs unloaded, all digital inputs = 0V or V

250

150

400

200

µA

DD

I

SS

Outputs unloaded, all digital inputs = 0V or V

DD

SWITCHING CHARACTERISTICS—Specifications are identical to those under Single +5V Supply

Note 2: In single supply, INL and GE are calculated from code 3 to code 1023 (code excludes S0 and S1).

Note 3: Guaranteed by design.

Note 4: REFIN = 1kHz, 2.0Vp-p.

Note 5: Tested at I

= 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics).

OUT

4

_______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(Single +5V supply, unity gain, code = all 1s, T = +25°C, unless otherwise noted.)

A

OUTPUT SINK CAPABILITY vs.

OUTPUT PULL-DOWN VOLTAGE

OUTPUT SOURCE CAPABILITY vs.

OUTPUT PULL-UP VOLTAGE

ANALOG FEEDTHROUGH vs.

FREQUENCY

-110

-100

-90

16

14

12

10

8

7

6

5

4

3

-80

-70

REFIN = 2V

p-p

-60

-50

-40

6

-30

-20

-10

4

2

1

0

2

CODE = ALL 0s,

DUAL SUPPLIES (±5V)

0

0.2

0.4

0.6

0.8

1.0

0

1

2

3

4

5

1

10

100

1k

10k 100k 1M

OUTPUT PULL-DOWN VOLTAGE (V)

OUTPUT PULL-UP VOLTAGE (V)

FREQUENCY (Hz)

REFERENCE VOLTAGE vs.

TEMPERATURE

SUPPLY CURRENT vs. TEMPERATURE

GAIN vs. FREQUENCY

300

290

4

2

2.055

REFIN = 4Vp-p

0

280

270

260

250

-2

-4

2.050

2.045

-6

-8

DUAL SUPPLIES (±5V)

-10

-12

240

230

-14

-60 -40 -20

0

20 40 60 80 100 120 140

1

100

1k

10k

100k

-60 -40 -20

0 20 40 60 80 100 120

140

TEMPERATURE (°C)

FREQUENCY (Hz)

GAIN AND PHASE vs.

FREQUENCY

AMPLIFIER SIGNAL-TO- NOISE RATIO

80

70

60

50

40

30

20

10

200

100

180

REFIN = 4Vp-p

(G = 2)

(G = 1)

GAIN

0

-100

-200

0

PHASE

DUAL SUPPLIES (±5V)

0

-180

800

-300

10

100

1k

10k

100k

1

10

100

FREQUENCY (Hz)

FREQUENCY (kHz)

_______________________________________________________________________________________

5

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(Single +5V supply, unity gain, code = all 1s, T = +25°C, unless otherwise noted.)

A

REFERENCE OUTPUT VOLTAGE

vs. REFERENCE LOAD CURRENT

SUPPLY CURRENT vs. REFIN

2.0480

2.0475

250

200

REFGND = AGND

MAX503

2.0470

2.0465

2.0460

2.0455

2.0450

150

100

50

REFGND = V

DD

EXTERNAL REFERENCE

0

50 100 150 200 250 300 350 400 450 500

REFIN (mV)

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

REFERENCE LOAD CURRENT (mA)

DIGITAL FEEDTHROUGH

A

B

2µs/div

A: S0, S1, D0–D9 = 100kHz, 4Vp-p

B: VOUT, 10mV/div

LDAC = CS = HIGH

SETTLING TIME (RISING)

SETTLING TIME (FALLING)

A

B

A

B

5µs/div

A: DIGITAL INPUTS RISING EDGE,

A: DIGITAL INPUTS FALLING EDGE, 5V/div

B: VOUT, NO LOAD, 1V/div

DUAL SUPPLY (±5V)

LDAC = LOW

BIPOLAR CONFIGURATION

B: VOUT NO LOAD, 1V/div

,

DUAL SUPPLY (±5V)

LDAC = LOW

BIPOLAR CONFIGURATION

V

REFIN

= 2V

V

REFIN

= 2V

6

_______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

1

2

3

4

5

6

7

D7/ S1

D8/ D0

D9/ D1

D2

D7 input when A0 = A1 = 1, or S1 input when A0 = 0 and A1 = 1. Always set S1 to 0.*

D8 input when A0 = A1 = 1, or D0 input when A0 = 0 and A1 = 1.*

D9 input when A0 = A1 = 1, or D1 input when A0 = 0 and A1 = 1.*

D2 Input Data, or tie to S0 and multiplex when A0 = 1 and A1 = 0.*

D3 Input Data, or tie to S1 and multiplex when A0 = 1 and A1 = 0.*

D4 Input Data, or tie to D0 and multiplex when A0 = 1 and A1 = 0.*

D5 Input Data, or tie to D1 and multiplex when A0 = 1 and A1 = 0.*

D3

D4

D5

Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM),

and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.)

8

9

A0

A1

Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and A1 =

0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing.

10

11

12

WR

CS

Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1.

Chip Select (active low). Enables addressing and writing to this chip from common bus lines.

Digital Ground

DGND

Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to

REFOUT (pin 18) to use the internal 2.048V reference.

13

REFIN

14

15

AGND

CLR

Analog Ground

Clear (active low). A low on CLR resets the DAC latches to all 0s.

Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input

latch to the DAC latch and updates VOUT.

16

17

LDAC

Reference Ground must be connected to AGND when using the internal reference. Connect to V

DD

REFGND

REFOUT

to disable the internal reference and save power.

18

19

20

21

22

23

24

Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC.

Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation.

Voltage Output. Op-amp buffered DAC output.

V

SS

VOUT

RFB

Feedback Pin. Op-amp feedback resistor. Always connect to VOUT.

Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output.

Positive Power Supply (+5V)

ROFS

V

DD

D6/S0

D6 input when A0 = A1 = 1, or S0 input when A0 = 0 and A1 = 1. Always set S0 to 0.*

* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode.

_______________________________________________________________________________________

7

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

the reference voltage. The MAX503’s topology makes the

________________De ta ile d De s c ription

ladder output voltage the same polarity as the reference

input, making the device suitable for single-supply oper-

ation. The BiCMOS op amp is then used to buffer, invert,

or amplify the ladder signal.

The MAX503 consists of a parallel-input logic interface, a

10-bit R-2R ladder, a reference, and an op amp. The

Functional Diagram shows the control lines and signal

flow through the input data latch to the DAC latch, as well

as the 2.048V reference and output op amp. Total supply

current is typically 250µA with a single +5V supply. This

circuit is ideal for battery-powered, microprocessor-con-

trolled applications where high accuracy, no adjustments,

and minimum component count are key requirements.

Ladder resistors are nominally 80kΩ to conserve power

and are laser trimmed for gain and linearity. The input

impedance at REFIN is code dependent. When the DAC

register is all 0s, all rungs of the ladder are grounded

and REFIN is open or no load. Maximum loading (mini-

mum REFIN impedance) occurs at code 010101....

Minimum reference input impedance at this code is guar-

anteed to be not less than 40kΩ.

MAX503

R-2R La dde r

The MAX503 uses an “inverted” R-2R ladder network with

a BiCMOS op amp to convert 10-bit digital data to analog

voltage levels. Figure 1 shows a simplified diagram of the

R-2R DAC and op amp. Unlike a standard DAC, the

MAX503 uses an “inverted” ladder network. Normally, the

REFIN pin is the current output of a standard DAC and

would be connected to the summing junction, or virtual

ground, of an op amp. In this standard DAC configura-

tion, however, the output voltage would be the inverse of

The REFIN and REFOUT pins allow the user to choose

between driving the R-2R ladder with the on-chip refer-

ence or an external reference. REFIN may be below ana-

log ground when using dual supplies. See the External

Reference and Four-Quadrant Multiplication sections for

more information.

In t e rn a l Re fe re n c e

The on-chip reference is laser trimmed to generate

2.048V at REFOUT. The output stage can source and

sink current so REFOUT can settle to the correct volt-

age quickly in response to code-dependent loading

changes. Typically, source current is 5mA and sink

current is 100µA.

2R

ROFS

2R

MAX503

RFB

REFOUT connects the internal reference to the R-2R

DAC ladder at REFIN. The R-2R ladder draws 50µA

maximum load current. If any other connection is made

to REFOUT, ensure that the total load current is less

than 100µA to avoid gain errors.

VOUT

OUTPUT

R

BUFFER

2R 2R

2R

A separate REFGND pin is provided to isolate refer-

ence currents from other analog and digital ground

currents. To achieve specified noise performance, con-

nect a 33µF capacitor from REFOUT to REFGND (see

Figure 2). Using smaller capacitance values increases

noise, and values less than 3.3µF may compromise the

reference’s stability. For applications requiring the low-

est noise, insert a buffered RC filter between REFOUT

a nd REFIN. Whe n us ing the inte rna l re fe re nc e ,

REFGND must be connected to AGND. In applications

not requiring the internal reference, connect REFGND

LSB

MSB

*

R = 80kΩ

REFIN

AGND

REFOUT

2.048V

CLR

DAC LATCH

MSB

LSB

NBL

INPUT

LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

REFGND

to V , which shuts down the reference. This saves

DD

typically 100µA of V

supply current and eliminates

DD

.

D6/S0

D2

D8/D0

D4

the need for C

*SHOWN FOR ALL 1s

REFOUT

D7/S1

D9/D1

D3 D5

Figure 1. Simplified MAX503 DAC Circuit

8

_______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

Ex t e rn a l Re fe re n c e

R

S

REFOUT

An e xte rna l re fe re nc e in the ra ng e (V

+ 2V) to

SS

TOTAL

REFERENCE

NOISE

C

S

(V

DD

- 2V) may be used with the MAX503 in dual-sup-

ply, unity-gain operation. In single-supply, unity-gain

operation, the reference must be positive and may not

C

REFOUT

TEK 7A22

exceed (V

the DAC’s full-scale output.

- 2V). The reference voltage determines

DD

300

250

200

150

100

50

1.8

1.6

1.4

1.2

1.0

0.8

SINGLE POLE ROLLOFF

If an upgrade to the internal reference is required, the

2.5V MAX873A is id e a l: ± 15mV initia l a c c ura c y,

7ppm/°C (max) temperature coefficient.

C

= 3.3µF

REFOUT

P o w e r-On Re s e t

An internal power-on reset (POR) circuit forces the

DAC register to reset to all 0s when V is first applied.

The POR pulse is typically 1.3µs; however, it may take

2ms for the internal reference to charge its large filter

capacitor and settle to its trimmed value.

DD

0.6

0.4

0.2

0.0

C

= 47µF

REFOUT

0

In addition to POR, a clear (CLR) pin, when held low,

sets the DAC register to all 0s. CLR operates asynchro-

nously and independently from chip select (CS). With

the DAC input at all 0s, the op-amp output is at zero for

0.1

1

10

100

1000

FREQUENCY (kHz)

Figure 2. Reference Noise vs. Frequency

unity-gain and G = 2 configurations, but it is at -V

REF

for the bipolar configuration.

Ou t p u t Bu ffe r

S h u t d o w n Mo d e

The output amplifier uses a folded cascode input stage

and a type AB output stage. Large output devices with

low s e rie s re s is ta nc e a llow the outp ut to s wing to

ground in single-supply operation. The output buffer is

unity-gain stable. Input offset voltage and supply cur-

rent are laser trimmed. Settling time is 25µs to 0.01% of

final value. The output is short-circuit protected and

can drive a 2kΩ load with more than 100pF of load

capacitance. The op amp may be placed in unity-gain

(G = 1), in a gain of two (G = 2), or in a bipolar-output

mode by using the ROFS and RFB pins. These pins are

used to define a DAC output voltage range of 0V to

+2.048V, 0V to +4.096V or ±2.048V, by connecting

ROFS to VOUT, GND, or REFIN. RFB is always con-

nected to VOUT. Table 1 summarizes ROFS usage.

The MAX503 is designed for low power consumption.

Understanding the circuit allows power consumption

management for maximum efficiency. In single-supply

mode (V

= +5V, V = GND) the initial supply cur-

DD

SS

rent is typically only 160µA, including the reference, op

a mp , a nd DAC. This low c urre nt oc c urs whe n the

power-on reset circuit clears the DAC to all 0s and

forces the op-amp output to zero (unipolar mode only).

See the Supply Current vs. REFIN graph in the Typical

Operating Characteristics. Under this condition, there

is no internal load on the reference (DAC = all 0s,

REFIN is open circuit) and the op amp operates at its

minimum quiescent current. The CLR signal resets the

MAX503 to these same conditions and can be used to

control a power-saving mode when the DAC is not

being used by the system.

Table 1. ROFS Usage

ROFS

CONNECTED TO:

DAC OUTPUT

RANGE

OP-AMP

GAIN

VOUT

AGND

REFIN

0V to 2.048V

0V to 4.096V

G = 1

G = 2

-2.048V to +2.048V

Bipolar

Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V

_______________________________________________________________________________________

9

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

REFOUT

REFIN

ROFS

33µF

2.048V

REFERENCE

MAX503

RFB

REFGND

V

OUT

2N7002

DAC

AGND

DGND

POWER-ON

RESET

MAX503

V

DD

+5V

10-BIT DAC LATCH

CLR

V

SS

NBL

INPUT

LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

A0

A1

CS

CONTROL

LOGIC

WR

LDAC

D6/S0

D7/S1

D2

D8/D0

D4

D9/D1

D3 D5

Figure 3. Low-Current Shutdown Mode

An additional 110µA of supply current can be saved

when the internal reference is not used by connecting

Table 2. Input Latch Addressing

REFGND to V . A low on-resistance N-channel FET,

DD

CLR CS WR LDAC A0 A1

DATA UPDATED

Reset DAC latches

such as the 2N7002, can be used to turn off the internal

reference to create a shutdown mode with minimum

current drain (Figure 3). When CLR is high, the transis-

tor pulls REFGND to AGND and the reference and DAC

operate normally. When CLR goes low, REFGND is

L

H

X

H

X

L

X

H

L

X

H

X

H

X

H

L

No operation

NBH (D6–D9)

NBM (D2–D5)

pulled up to V and the reference is shut down. At the

L

DD

same time, CLR resets the DAC register to all 0s, and

the op -a mp outp ut g oe s to 0V for unity-g a in a nd

G = 2 modes. This reduces the total single-supply

operating current from 250µA (400µA max) to typically

40µA in shutdown mode.

NBL (S0 = 0, S1 = 0,

D0, D1)

H

L

H

L

H

X

H

X

Update DAC only

NBL and NBM (S0, S1,

D0–D5), DAC not

updated

H

L

X

L

H

NBH and update DAC

10 ______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

ADDRESS BUS VALID

V

IH

A0–A1

CS

V

IL

t

AWH

t

CWS

t

CWH

WR

t

WR

t

AWS

t

DS

t

DH

V

IL

IH

DATA BITS

(8-BIT BYTE

OR 4-BIT NIBBLE)

DATA BUS

VALID

CLR

t

CLR

LDAC

t

LDAC

V

IH + IL

2

NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS

Figure 4. MAX503 Write-Cycle Timing Diagram

A small error voltage is added to the reference output

by the reference current flowing through the N-channel

pull-down transistor. The switch’s on resistance should

be less than 5Ω. A typical reference current of 100µA

would add 0.5mV to REFOUT. Since the reference cur-

rent and on resistance increase with temperature, the

overall temperature coefficient will degrade slightly.

P a ra lle l Lo g ic In t e rfa c e

In order to provide hardware and software compatibility

with the 12-bit MAX530, the MAX503 employs a 12-bit

digital interface. As shown in Figure 3, there is actually

a 12-bit input latch, and therefore 12 bits of data should

be written. The two least significant bits (S1 and S0) are

sub-LSB, and must always be 0s. Designed to interface

with 4-bit, 8-bit, and 16-bit microprocessors (µPs), the

MAX503 uses 8 data pins and double-buffered logic

inputs to load data as 4 + 4 + 4 or 8 + 4. The 12-bit

DAC latch is updated simultaneously through the con-

trol signal LDAC. Signals A0, A1, WR, and CS select

which input latches to update. The 12-bit data is bro-

ken down into nibbles (NB); NBL is the enable signal

for the lowe s t 4 b its (S0, S1, D0, D1), NBM is the

enable for the middle 4 bits, and NBH is the enable for

the highest and most significant 4 bits. Table 2 lists the

address decoding scheme.

As data is loaded into the DAC and the output moves

above GND, the op-amp quiescent current increases to

its nominal value and the total operating current aver-

ages 250µA. Using dual supplies (±5V), the op amp is

fully biased continuously, and the V supply current is

DD

more constant at 250µA. The V current is typically

SS

150µA.

The MAX503 logic inputs are compatible with TTL and

CMOS logic levels. However, to achieve the lowest

power dissipation, drive the digital inputs with rail-to-rail

CMOS logic. With TTL logic levels, the power require-

ment increases by a factor of approximately 2.

Refer to Figure 4 for the MAX503 write-cycle timing

diagram.

______________________________________________________________________________________ 11

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

DATA BUS

D0–D7

D0–D3

DATA BUS

D0–D3

D2–D5

FROM

SYSTEM

RESET

FROM

SYSTEM

RESET

S0, S1, D0, D1

CLR

S0, S1, D0–D5

MAX503

CLR

MAX503

A0, A1

WR

MAX503

A0–A1

WR

MC6800

MC6809

CS LDAC

E

2

DECODER

R/W

EN

EN DECODER

A13–A15

R/W

ADDRESS BUS A0, A1

A0

A0–A15 ADDRESS BUS

A13–A15

A0–A15

Figure 7. 8-Bit and 16-Bit µP Interface

Figure 5. 4-Bit µP Interface

A0 = 1, A1 = 1

NBH

NBM

A0 = 1, A1 = 0

NBL

CS

A0 = 0, A1 = 1

WR

LDAC

DAC UPDATE

Figure 6. 4-Bit µP Timing Sequence

A0 = A1 = 1

NBH

A0 = A1 = 0

NBL & NBM

CS

WR

LDAC

DAC UPDATE

Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC

12 ______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

A0 = A1 = 0

NBL & NBM

A0 = A1 = 1

NBH

CS

WR

LDAC = 0 (DAC LATCH IS TRANSPARENT)

DAC UPDATE

Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0

+5V

V

DD

V

DD

REFIN

ROFS

REFOUT

33µF

MAX503

ROFS

AGND

RFB

AGND

DGND

V

OUT

VOUT

DGND

V

OUT

VOUT

REFGND

G = 2

V

SS

V

SS

G = 1

0V TO -5V

Figure 9. Unipolar Configuration (0V to +2.048V Output)

Figure 10. Unipolar Configuration (0V to +4.096V Output)

Figure 5 shows the circuit configuration for a 4-bit µP

application. Figure 6 shows the corresponding timing

sequence. The 4 low bits (S0, S1, D0, D1) are connect-

ed in parallel to the other 4 bits (D2–D5) and then to the

µP bus. Address lines A0 and A1 enable the input data

latches for the high, middle, or low data nibbles. The µP

sends chip select (CS) and write (WR) signals to latch

in each of three nibbles in three cycles when the data is

valid.

LDAC is asynchronous with respect to WR. If LDAC is

brought low before or at the same time WR goes high,

LDAC must remain low for at least 50ns to ensure the

correct data is latched. Data is latched into DAC regis-

ters on LDAC’s rising edge.

Un ip o la r Co n fig u ra t io n

The MAX503 is configured for a 0V to V

unipolar

REFIN

output range by connecting ROFS and RFB to VOUT

(Figure 9). The converter operates from either single or

dual supplies in this configuration. See Table 3 for the

Figure 7 shows a typical interface to an 8-bit or a 16-bit

µP. Connect 8 data bits from the data bus to pins S0,

S1, and D0–D5 on the MAX503. With LDAC held high,

the user can load NBH or NBL + NBM in any order.

Figure 8a shows the corresponding timing sequence.

For fa s te s t throug hp ut, us e Fig ure 8b ’s s e q ue nc e .

Address lines A0 and A1 are tied together and the DAC

is loaded in 2 cycles as 8 + 4. In this scheme, with

LDAC held low, the DAC latch is transparent. Always

load NBL and NBM first, followed by NBH.

DAC-latch contents (input) vs. the analog VOUT (output).

-10

In this range, 1LSB = V

(2

).

REFIN

A 0V to 2V

unipolar output range is set up by con-

REFIN

necting ROFS to AGND and RFB to VOUT (Figure 10).

Table 4 shows the DAC-latch contents vs. VOUT. The

MAX503 operates from either single or dual supplies in

-10

this mode. In this range, 1LSB = (2)(V

)(2

) =

REFIN

-9

(V )(2 ).

REFIN

______________________________________________________________________________________ 13

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

Table 3. Unipolar Binary Code Table

Table 4. Unipolar Binary Code Table

(0V to V

Output), Gain = 1

(0V to 2V

Output), Gain = 2

REFIN

OUTPUT

INPUT*

OUTPUT

INPUT*

1023

1024

1023

1024

(V

)

1111 1111

11(00)

01(00)

00(00)

REFIN

+2 (V

)

1111 1111

1000 0000

11(00)

01(00)

00(00)

REFIN

MAX503

513

1024

513

1024

(V

REFIN

)

1000 0000

+2 (V

)

REFIN

512

1024

(V

)

= +V

/2

REFIN

= +V

+2 (V

)

REFIN

1024

511

1024

511

1024

11(00)

0111 1111

(V

)

REFIN

11(00)

+2 (V

)

0111 1111

REFIN

1

1024

1

1024

0000 0000

(V

)

01(00)

00(00)

REFIN

0000 0000

+2 (V

)

01(00)

00(00)

REFIN

OV

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

Table 5. Bipolar (Offset Binary) Code

Bip o la r Co n fig u ra t io n

bipolar range is set up by con-

necting ROFS to REFIN and RFB to VOUT, and operat-

ing from d ua l (± 5V) s up p lie s (Fig ure 11). Ta b le 5

A -V

to +V

Table (-V

to +V

Output)

REFIN

OUTPUT

INPUT*

shows the DAC-latch contents (input) vs. VOUT (out-

-9

put). In this range, 1LSB = V

(2 ).

REFIN

511

512

(+V

)

1111 1111

11(00)

REFIN

Fo u r-Qu a d ra n t Mu lt ip lic a t io n

The MAX503 can be used as a four-quadrant multiplier

by connecting ROFS to REFIN and RFB to VOUT, and

us ing (1) a n offs e t b ina ry d ig ita l c od e , (2) b ip ola r

p owe r s up p lie s , a nd (3) a b ip ola r a na log inp ut a t

1

512

1000 0000

0111 1111

(+V

)

01(00)

00(00)

11(00)

REFIN

0V

REFIN within the range V + 2V to V - 2V, as shown

SS

DD

in Figure 12.

1

512

(-V

REFIN

)

In ge ne ra l, a 10-bit DAC’s output is D(V

)(G),

REFIN

where “G” is the gain (1 or 2) and “D” is the binary rep-

10

resentation of the digital input divided by 2 or 1,024.

511

512

0000 0000

(-V

)

01(00)

00(00)

REFIN

This formula is precise for unipolar operation. However,

for bipolar, offset binary operation, the MSB is really a

polarity bit. No resolution is lost because the number of

steps is the same. The output voltage, however, has

b e e n s hifte d from a ra ng e of, for e xa mp le , 0V to

4.096V (G = 2) to a range of -2.048V to +2.048V.

512

)

= -V

REFIN

* Write 10-bit data words with two sub-LSB 0s because the

DAC input latch is 12 bits wide.

Keep in mind that when using the DAC as a four-quad-

rant multiplier, the scale is skewed. The negative full

s c a le is -V

, while the p os itive full s c a le is

REFIN

+V

- 1LSB.

REFIN

14 ______________________________________________________________________________________

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

MAX503

+5V

V

DD

REFIN

ROFS

REFIN

ROFS

REFOUT

REFGND

33µF

MAX503

AGND

DGND

MAX503

RFB

AGND

V

OUT

V

OUT

VOUT

DGND

VOUT

REFGND

V

SS

-5V

Figure 11. Bipolar Configuration (-2.048V to +2.048V Output)

Figure 12. Four-Quadrant Multiplying Circuit

ground connection may be achieved by connecting

the AGND, REFGND, and DGND pins together and

connecting that point to the system analog ground

plane. If DGND is connected to the system digital

ground, digital noise may get through to the DAC’s ana-

log portion.

__________Ap p lic a t io n s In fo rm a t io n

S in g le -S u p p ly Lin e a rit y

As with any amplifier, the MAX503’s output op amp off-

set can be positive or negative. When the offset is posi-

tive, it is easily accounted for. However, when the offset

is negative, the output cannot follow linearly when there

is no negative supply. In that case, the amplifier output

(VOUT) remains at ground until the DAC voltage is suffi-

cient to overcome the offset and the output becomes

positive. The resulting transfer function is shown in

Figure 13.

Bypass V

(and V in dual-supply mode) with a

SS

DD

0.1µF ceramic capacitor connected between V

and

DD

AGND (a nd b e twe e n V

a nd AGND). Mount the

SS

capacitors with short leads close to the device.

AC Co n s id e ra t io n s

Normally, linearity is measured after allowing for zero

error and gain error. Since, in single-supply operation,

the actual value of a negative offset is unknown, it can-

not be accounted for during test. In the MAX503, linear-

ity and gain error are measured from code 3 to code

1023 (see Note 2 under Electrical Characteristics). The

output amplifier offset does not affect monotonicity, and

these DACs are guaranteed monotonic starting with

code zero. In dual-supply operation, linearity and gain

error are measured from code 0 to 1023.

Digital Feedthrough

High-speed data at any of the digital input pins may

couple through the DAC package and cause internal

stray capacitance to appear as noise at the DAC out-

put, even though LDAC and CS are held high (see

Typ ic a l Op e ra ting Cha ra c te ris tic s ). This d ig ita l

feedthrough is tested by holding LDAC and CS high

and toggling the data inputs from all 1s to all 0s.

Analog Feedthrough

Because of internal stray capacitance, higher-frequen-

cy analog input signals at REFIN may couple to the

output, even when the input digital code is all 0s, as

shown in the Typical Operating Characteristics graph

Analog Feedthrough vs. Frequency. It is tested by set-

ting CLR to low (which sets the DAC latches to all 0s)

and sweeping REFIN.

P o w e r-S u p p ly Byp a s s in g

a n d Gro u n d Ma n a g e m e n t

Best system performance is obtained with printed cir-

cuit boards that use separate analog and digital ground

planes. Wire-wrap boards are not recommended. The

two ground planes should be connected together at the

low-impedance power-supply source.

AGND and REFGND should be connected together,

and then to DGND at the chip. For single-supply appli-

cations, connect V to AGND at the chip. The best

SS

______________________________________________________________________________________ 15

5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 0 -Bit DAC

5

POSITIVE OFFSET

4

MAX503

3

2

NEGATIVE OFFSET

1

0

1

2

3

4

5

DAC CODE (LSBs)

Figure 13. Single-Supply DAC Transfer Function

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX503CNG
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	5V, Low-Power, Parallel-Input, Voltage-Output, 10-Bit DAC 5V ，低功耗，并行输入，电压输出， 10位DAC
文件：	总16页 (文件大小：119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX503CNG [MAXIM]

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