MAX5054BATA+ [MAXIM]
4A, 20ns, Dual MOSFET Drivers;
| 型号： | MAX5054BATA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 4A, 20ns, Dual MOSFET Drivers |
| 文件： | 总17页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3348; Rev 0; 8/04
4A, 20ns, Dual MOSFET Drivers
General Description
Features
The MAX5054–MAX5057 dual, high-speed MOSFET
drivers source and sink up to 4A peak current. These
devices feature a fast 20ns propagation delay and 20ns
rise and fall times while driving a 5000pF capacitive
load. Propagation delay time is minimized and matched
between the inverting and noninverting inputs and
between channels. High sourcing/sinking peak cur-
rents, low propagation delay, and thermally enhanced
packages make the MAX5054–MAX5057 ideal for high-
frequency and high-power circuits.
♦ 4V to 15V Single Power Supply
♦ 4A Peak Source/Sink Drive Current
♦ 20ns (typ) Propagation Delay
♦ Matching Delay Between Inverting and
Noninverting Inputs
♦ Matching Propagation Delay Between Two
Channels
♦ V
/ 2 CMOS Logic Inputs (MAX5054AATA)
DD
The MAX5054–MAX5057 operate from a 4V to 15V single
power supply and consume 40µA (typ) of supply current
when not switching. These devices have internal logic
circuitry that prevents shoot-through during output state
changes to minimize the operating current at high
switching frequency. The logic inputs are protected
♦ TTL Logic Inputs
(MAX5054B/MAX5055/MAX5056/MAX5057)
♦ 0.1 x V
(CMOS) and 0.3V (TTL) Logic-Input
DD
Hysteresis
against voltage spikes up to +18V, regardless of the V
DD
♦ Up to +18V Logic Inputs (Regardless of V
DD
voltage. The MAX5054A is the only version that has
CMOS input logic levels while the MAX5054B/MAX5055/
MAX5056/MAX5057 have TTL input logic levels.
Voltage)
♦ Low Input Capacitance: 2.5pF (typ)
♦ 40µA (typ) Quiescent Current
The MAX5055–MAX5057 provide the combination of dual
inverting, dual noninverting, and inverting/noninverting
input drivers. The MAX5054 feature both inverting and
noninverting inputs per driver for greater flexibility. They
are available in 8-pin TDFN (3mm x 3mm), standard SO,
and thermally enhanced SO packages. These devices
operate over the automotive temperature range of -40°C
to +125°C.
♦ -40°C to +125°C Operating Temperature Range
♦ 8-Pin TDFN and SO Packages
Ordering Information
PIN-
PACKAGE
TOP
MARK
Applications
PART
TEMP RANGE
Power MOSFET Switching
Motor Control
MAX5054AATA
MAX5054BATA
MAX5055AASA
MAX5055BASA
MAX5056AASA
MAX5056BASA
MAX5057AASA
MAX5057BASA
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
8 TDFN-EP*
8 TDFN-EP*
8 SO-EP*
8 SO
AGS
AGR
—
Switch-Mode Power Supplies Power-Supply Modules
DC-DC Converters
Typical Operating Circuit
—
8 SO-EP*
8 SO
—
V
IN
V
OUT
—
8 SO-EP*
8 SO
—
—
*EP = Exposed pad. Package code S8E-14.
Selector Guide and Pin Configurations appear at end of
data sheet.
MAX5054
V
DD
INA+
INA-
OUTA
INB+
INB-
OUTB
GND
PWM IN
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
4A, 20ns, Dual MOSFET Drivers
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
8-Pin SO-EP (derate 19.2mW/°C above +70°C)… ........1538mW
V
...............................................................................-0.3V to +18V
Junction-to-Case Thermal Resistance (θ ) ......................6°C/W
DD
JC
INA+, INA-, INB+, INB- ...............................................-0.3V to +18V
8-Pin SO (derate 5.9mW/°C above +70°C)…..................471mW
OUTA, OUTB...................................................-0.3V to (V + 0.3V)
OUTA, OUTB Short-Circuit Duration ........................................10ms
Junction-to-Case Thermal Resistance (θ ) ....................40°C/W
DD
JC
Operating Temperature Range..............................-40°C to +125°C
Storage Temperature Range .................................-65°C to +150°C
Junction Temperature...........................................................+150°C
Lead Temperature (soldering, 10s)......................................+300°C
Continuous Source/Sink Current at OUT_ (P < P
).....200mA
DMAX
D
Continuous Power Dissipation (T = +70°C)
A
8-Pin TDFN-EP (derate 24.4mW/°C above +70°C)........1951mW
Junction-to-Case Thermal Resistance (θ ) ......................2°C/W
JC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 4V to 15V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V
= 15V and T = +25°C.) (Note 1)
DD A
DD
A
PARAMETER
POWER SUPPLY
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Operating Range
V
4
15
V
V
DD
DD
DD
Undervoltage Lockout
UVLO
V
V
rising
rising
3.00
3.50
200
3.85
DD
DD
V
Undervoltage Lockout
DD
mV
µs
Hysteresis
V
Undervoltage Lockout to
DD
12
Output Delay
INA- = INB- = V
INA+ = INB+ = 0V
(not switching)
,
V
V
= 4V
28
40
55
75
DD
DD
DD
I
µA
DD
= 15V
V
Supply Current
DD
INA- = 0V, INB+ = V
= 15V,
DD
I
INA+ = INB- both channels switching at
250kHz, C = 0
1
2.4
4
mA
DD-SW
L
DRIVER OUTPUT (SINK)
T
T
T
T
= +25°C
= +125°C
= +25°C
= +125°C
1.1
1.5
2.2
3.0
4
1.8
2.4
3.3
4.5
A
A
A
A
V
= 15V,
= -100mA
DD
I
OUT_
Driver Output Resistance Pulling
Down
R
Ω
ON-N
V
= 4.5V,
= -100mA
DD
I
OUT_
Peak Output Current (Sinking)
Output-Voltage Low
I
V
= 15V, C = 10,000pF
A
V
PK-N
DD
L
V
= 4.5V
= 15V
0.45
0.24
DD
DD
I
= -100mA
OUT_
V
Latchup Protection
I
Reverse current I
(Note 2)
OUT_
400
mA
LUP
DRIVER OUTPUT (SOURCE)
T
T
T
T
= +25°C
= +125°C
= +25°C
= +125°C
1.5
1.9
2.75
3.75
4
2.1
2.75
4
A
A
A
A
V
= 15V,
= 100mA
DD
I
OUT_
Driver Output Resistance Pulling
Up
R
Ω
ON-P
V
= 4.5V,
= 100mA
DD
I
OUT_
5.5
Peak Output Current (Sourcing)
I
V
= 15V, C = 10,000pF
A
PK-P
DD
L
2
_______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= 4V to 15V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V
= 15V and T = +25°C.) (Note 1)
DD A
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
0.55
-
DD
V
V
= 4.5V
= 15V
DD
DD
Output-Voltage High
LOGIC INPUT (Note 3)
Logic 1 Input Voltage
I
= 100mA
V
OUT_
V
-
DD
0.275
0.7 x
MAX5054A
V
DD
V
V
IH
MAX5054B/MAX5055/MAX5056/MAX5057
(Note 4)
2.1
0.3 x
MAX5054A
V
Logic 0 Input Voltage
Logic-Input Hysteresis
V
DD
V
V
IL
MAX5054B/MAX5055/MAX5056/MAX5057
MAX5054A
0.8
0.1 x
V
V
DD
HYS
MAX5054B/MAX5055/MAX5056/MAX5057
0.3
+0.1
2.5
Logic-Input-Current Leakage
Input Capacitance
INA+, INB+, INA-, INB- = 0V or V
-1
+1
µA
pF
DD
C
IN
SWITCHING CHARACTERISTICS FOR V
= 15V (Figure 1)
DD
C = 1000pF
L
4
OUT_ Rise Time
OUT_ Fall Time
t
C = 5000pF
18
32
4
ns
ns
R
L
C = 10,000pF
L
C = 1000pF
L
t
C = 5000pF
L
15
26
20
20
F
C = 10,000pF
L
Turn-On Delay Time
Turn-Off Delay Time
t
C = 10,000pF (Note 2)
L
10
10
34
34
ns
ns
D-ON
t
C = 10,000pF (Note 2)
L
D-OFF
SWITCHING CHARACTERISTICS FOR V
= 4.5V (Figure 1)
DD
C = 1000pF
L
7
OUT_ Rise Time
OUT_ Fall Time
t
C = 5000pF
37
85
7
ns
ns
R
L
C = 10,000pF
L
C = 1000pF
L
t
C = 5000pF
L
30
75
35
35
F
C = 10,000pF
L
Turn-On Delay Time
Turn-Off Delay Time
t
C = 10,000pF (Note 2)
L
18
18
70
70
ns
ns
D-ON
t
C = 10,000pF (Note 2)
L
D-OFF
_______________________________________________________________________________________
3
4A, 20ns, Dual MOSFET Drivers
ELECTRICAL CHARACTERISTICS (continued)
(V
= 4V to 15V, T = -40°C to +125°C, unless otherwise noted. Typical values are at V
= 15V and T = +25°C.) (Note 1)
DD A
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MATCHING CHARACTERISTICS
Mismatch Propagation Delays from
Inverting and Noninverting Inputs
to Output
V
V
= 15V, C = 10,000pF
L
2
4
DD
DD
∆t
ns
ns
ON-OFF
= 4.5V, C = 10,000pF
L
V
V
= 15V, C = 10,000pF
1
2
DD
DD
L
Mismatch Propagation Delays
Between Channel A and Channel B
∆t
A-B
= 4.5V, C = 10,000pF
L
Note 1: All devices are 100% tested at T = +25°C. Specifications over -40°C to +125°C are guaranteed by design.
A
Note 2: Limits are guaranteed by design, not production tested.
Note 3: The logic-input thresholds are tested at V
= 4V and V
= 15V.
DD
DD
Note 4: TTL compatible with reduced noise immunity.
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
PROPAGATION DELAY TIME,
LOW-TO-HIGH vs. SUPPLY VOLTAGE
FALL TIME vs. SUPPLY VOLTAGE
RISE TIME vs. SUPPLY VOLTAGE
(C = 5000pF)
L
(C = 5000pF)
L
(C = 5000pF)
L
60
50
60
50
40
30
20
10
0
60
50
40
30
20
10
0
T
= +125°C
A
T
= +125°C
A
T
= +125°C
A
40
30
20
10
0
T
= +25°C
A
T
= +25°C
A
T
= +25°C
A
T
= -40°C
A
T
= -40°C
A
6
T
= -40°C
A
4
6
8
10
12
14
16
4
8
10
12
14
16
4
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
PROPAGATION DELAY TIME,
HIGH-TO-LOW vs. SUPPLY VOLTAGE
I
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
DD-SW
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(C = 5000pF)
L
100
90
80
70
60
50
40
30
20
10
0
6
5
4
3
2
1
0
60
50
40
30
20
10
0
DUTY CYCLE = 50%
= 15V, C = 0
1 CHANNEL SWITCHING
DUTY CYCLE = 50%
V
V
= 15V, C = 4700pF
DD
L
DD
L
T
= +125°C
A
1 CHANNEL SWITCHING
1MHz
1MHz
T
= +25°C
A
500kHz
500kHz
50kHz
50kHz
100kHz
100kHz
T
= -40°C
A
4
6
8
10
12
14
16
4
6
8
10
12
14
16
4
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
I
SUPPLY CURRENT
vs. TEMPERATURE
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
DD-SW
4.0
3.5
3.0
2.5
2.0
1.5
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
V
= 15V,
f = 250kHz, C = 0
DUTY CYCLE = 50%
BOTH CHANNELS SWITCHING
TTL INPUT VERSIONS
DD
MAX5054AATA
(CMOS INPUT)
L
V
RISING
V
RISING
IN
IN
V
FALLING
IN
V
FALLING
IN
-50 -25
0
25
50
75 100 125
4
6
8
10
12
14
16
4
6
8
10
12
14
16
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT HIGH-TO-LOW)
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT LOW-TO-HIGH)
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT LOW-TO-HIGH)
500
400
300
200
100
0
500
400
300
200
100
0
5
4
3
2
1
0
TTL INPUT VERSIONS
TTL INPUT VERSIONS
MAX5054AATA (CMOS INPUT)
V
= 15V
DD
V
= 15V
V
= 15V
DD
DD
0
2
4
6
8
10 12 14 16
0
2
4
6
8
10 12 14 16
0
2
4
6
8
10 12 14 16
LOGIC-INPUT VOLTAGE (V)
LOGIC-INPUT VOLTAGE (V)
LOGIC-INPUT VOLTAGE (V)
SUPPLY CURRENT vs. LOGIC-INPUT
VOLTAGE (INPUT HIGH-TO-LOW)
DELAY MISMATCH BETWEEN IN_+
AND IN_- TO OUT_ vs. TEMPERATURE
DELAY MISMATCH BETWEEN IN_+
AND IN_- TO OUT_ vs. TEMPERATURE
5
4
3
2
1
0
6
4
6
4
MAX5054AATA (CMOS INPUT)
OUTPUT FALLING
V
= +15V
DD
OUTPUT RISING
2
2
OUTPUT RISING
0
0
-2
-4
-6
-2
-4
-6
OUTPUT FALLING
MAX5054AATA (CMOS INPUT)
MAX5054AATA (CMOS INPUT)
V
= 4.5V, C = 10,000pF
V
= 15V, C = 10,000pF
DD
L
DD
L
0
2
4
6
8
10 12 14 16
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
LOGIC-INPUT VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
4A, 20ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
DELAY MISMATCH BETWEEN 2 CHANNELS
vs. TEMPERATURE
DELAY MISMATCH BETWEEN 2 CHANNELS
vs. TEMPERATURE
4
3
4
3
V
= 15V, C = 10,000pF
L
DD
V
= 4.5V, C = 10,000pF
DD
L
OUTPUT RISING
OUTPUT FALLING
2
2
1
1
0
0
-1
-2
-3
-4
-1
-2
-3
-4
OUTPUT RISING
OUTPUT FALLING
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 4V, C = 5000pF)
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 4V, C = 10,000pF)
DD
L
DD
L
MAX5054 toc18
MAX5054 toc19
IN_-
2V/div
IN_-
2V/div
OUT_
2V/div
OUT_
2V/div
MAX5055 (TTL INPUT)
20ns/div
MAX5055 (TTL INPUT)
40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 4V, C = 5000pF)
(V = 4V, C = 10,000pF)
DD
L
DD
L
MAX5054 toc21
MAX5054 toc20
IN_-
2V/div
IN_-
2V/div
OUT_
2V/div
OUT_
2V/div
MAX5055 (TTL INPUT)
MAX5055 (TTL INPUT)
20ns/div
40ns/div
6
_______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 15V, C = 10,000pF)
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 15V, C = 5000pF)
DD
L
DD
L
MAX5054 toc22
MAX5054 toc23
IN_-
2V/div
IN_-
2V/div
OUT_
5V/div
OUT_
5V/div
MAX5055
MAX5055
20ns/div
40ns/div
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 15V, C = 5000pF)
LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V = 15V, C = 10,000pF)
DD
L
DD
L
MAX5054 toc24
MAX5054 toc25
IN_-
IN_-
2V/div
2V/div
OUT_
5V/div
OUT_
5V/div
MAX5055
MAX5055
20ns/div
40ns/div
V
DD
vs. OUTPUT VOLTAGE
V vs. OUTPUT VOLTAGE
DD
MAX5054 toc27
MAX5054 toc26
MAX5055
INA- = INB- = GND
V
DD
5V/div
C
= C = 10,000pF
LB
LA
OUTA
5V/div
V
DD
OUTB
5V/div
5V/div
OUTA
5V/div
MAX5055
INA- = INB- = GND
OUTB
5V/div
C
= C = 10,000pF
LB
LA
2ms/div
2ms/div
_______________________________________________________________________________________
7
4A, 20ns, Dual MOSFET Drivers
Pin Descriptions
MAX5054
PIN
1
NAME
INA-
FUNCTION
Inverting Logic-Input Terminal for Driver A. Connect to GND when not used.
Inverting Logic-Input Terminal for Driver B. Connect to GND when not used.
Ground
2
INB-
3
GND
OUTB
4
Driver B Output. Sources or sinks current for channel B to turn the external MOSFET on or off.
Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors.
Driver A Output. Sources or sinks current for channel A to turn the external MOSFET on or off.
5
V
DD
6
OUTA
INB+
INA+
7
Noninverting Logic-Input Terminal for Driver B. Connect to V when not used.
DD
8
Noninverting Logic-Input Terminal for Driver A. Connect to V when not used.
DD
Exposed Pad. Internally connected to GND. Do not use the exposed pad as the only electrical
ground connection.
—
EP
MAX5055/MAX5056/MAX5057
PIN
NAME
FUNCTION
No Connection. Not internally connected.
MAX5055 MAX5056 MAX5057
1, 8
2
1, 8
—
3
1, 8
2
N.C.
INA-
GND
INB-
Inverting Logic-Input Terminal for Driver A. Connect to GND if not used.
Ground
3
3
4
—
—
Inverting Logic-Input Terminal for Driver B. Connect to GND if not used.
Driver B Output. Sources or sinks current for channel B to turn the external
MOSFET on or off.
5
6
7
5
6
7
5
6
7
OUTB
V
Power Supply. Bypass to GND with one or more 0.1µF ceramic capacitors.
DD
Driver A Output. Sources or sinks current for channel A to turn the external
MOSFET on or off.
OUTA
—
—
4
2
4
INB+
INA+
Noninverting Logic-Input Terminal for Driver B. Connect to V if not used.
DD
—
Noninverting Logic-Input Terminal for Driver A. Connect to V if not used.
DD
Exposed Pad. Internally connected to GND. Do not use the exposed pad as
the only electrical ground connection.
—
—
—
EP
8
_______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
V
IH
IN_+
V
IL
V
DD
MAX5055
MAX5056
MAX5057
90%
10%
OUT_
P
BREAK-
BEFORE-
MAKE
t
t
D-OFF1
D-ON1
IN_+
OUT_
GND
t
t
R
F
CONTROL
N
V
IN_-
IH
V
IL
t
t
D-OFF2
D-ON2
RISING MISMATCH = t
- t
D-ON2 D-ON1
FALLING MISMATCH = t
- t
D-OFF2 D-OFF1
NONINVERTING INPUT DRIVER
Figure 1. Timing Diagram
V
DD
MAX5055
MAX5056
MAX5057
V
DD
MAX5054
P
BREAK-
BEFORE-
MAKE
IN_-
P
IN_-
OUT_
GND
BREAK-
BEFORE-
MAKE
CONTROL
OUT_
GND
N
CONTROL
IN_+
N
INVERTING INPUT DRIVER
Figure 2. MAX5054 Block Diagram (1 Driver)
Figure 3. MAX5055/MAX5056/MAX5057 Functional Diagrams
(1 Driver)
Logic Inputs
The MAX5054B–MAX5057 have TTL-compatible logic
inputs, while the MAX5054A is a CMOS logic-input dri-
ver. The logic-input signals can be independent of the
Detailed Description
V
Undervoltage Lockout (UVLO)
DD
The MAX5054–MAX5057 have internal undervoltage
lockout for V . When V
is below the UVLO thresh-
DD
DD
V
voltage. For example, the device can be powered
DD
old, OUT_ is low, independent of the state of the inputs.
The undervoltage lockout is typically 3.5V with 200mV
by a 5V supply while the logic inputs are provided from
CMOS logic. Also, the logic inputs are protected against
typical hysteresis to avoid chattering. When V
rises
DD
the voltage spikes up to 18V, regardless of the V
volt-
DD
above the UVLO threshold, the outputs go high or low
age. The TTL and CMOS logic inputs have 300mV and
0.1 x V hysteresis, respectively, to avoid possible dou-
depending upon the logic-input levels. Bypass V
DD
DD
using low-ESR ceramic capacitors for proper operation
ble pulsing during transition. The low 2.5pF input capaci-
tance reduces loading and increases switching speed.
(see the Applications Information section).
_______________________________________________________________________________________
9
4A, 20ns, Dual MOSFET Drivers
Table 1. MAX5054 Truth Table
INA+/INB+
Low
INA-/INB-
Low
OUTA/OUTB
Low
V
DD
Low
High
Low
MAX5054A
PWM
INPUT
High
Low
High
INA+
OUTA
High
High
Low
OFF
Table 2. MAX5055/MAX5056/MAX5057
Truth Table
INA-
GND
ON
NONINVERTING
Figure 4. Unused Input as an ON/OFF Function (1/2 MAX5054A)
IN_+
Low
OUT_
Low
Applications Information
High
High
RLC Series Circuit
INVERTING
The driver’s R
(R ), internal bond and lead
ON
DS(ON)
IN_-
Low
High
OUT_
High
Low
inductance (L ), trace inductance (L ), gate inductance
P
S
(L ), and gate capacitance (C ) form a series RLC
G
G
circuit with a second-order characteristic equation. The
series RLC circuit has an undamped natural frequency
(ϖ ) and a damping ratio (ζ) where:
0
The logic inputs are high impedance and must not be left
floating. If the inputs are left open, OUT_ can go to an
1
undefined state as soon as V
rises above the UVLO
ϖ
=
DD
0
(L + L + L ) × C
threshold. Therefore, the PWM output from the controller
must assume proper state when powering up the device.
P
S
G
G
The MAX5054 has two logic inputs per driver providing
greater flexibility in controlling the MOSFET. Use IN_+ for
noninverting logic and IN_- for inverting logic operation.
R
ON
ξ =
(L + L + L )
P
S
G
2 ×
Connect IN_+ to V
and IN_- to GND if not used.
DD
C
G
Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low shutdown logic
and IN_- for active-high shutdown logic (see Figure 4).
See Table 1 for all possible input combinations.
The damping ratio needs to be greater than 0.5 (ideally 1)
to avoid ringing. Add a small resistor (R ) in series
with the gate when driving a very low gate-charge
MOSFET, or when the driver is placed away from the
MOSFET. Use the following equation to calculate the
series resistor:
GATE
Driver Output
The MAX5054–MAX5057 have low R
p-channel
DS(ON)
and n-channel devices (totem pole) in the output stage
for the fast turn-on and turn-off high gate-charge switch-
ing MOSFETs. The peak source or sink current is typically
(L + L + L )
P
S
G
R
≥
− R
ON
GATE
4A. The OUT_ voltage is approximately equal to V
DD
C
G
when in high state and is ground when in low state. The
driver R is lower at higher V , thus higher
DS(ON)
DD
L
P
can be approximated as 3nH and 2nH for SO and
source-/sink-current capability and faster switching
speeds. The propagation delays from the noninverting
and inverting logic inputs to outputs are matched to 2ns.
The break-before-make logic avoids any cross-conduc-
tion between the internal p- and n-channel devices, and
eliminates shoot-through currents reducing the quiescent
supply current.
TDFN packages, respectively. L is on the order of
S
20nH/in. Verify L with the MOSFET vendor.
G
10 ______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
where D (duty cycle) is the fraction of the period the
MAX5054–MAX5057’s output pulls high duty cycle,
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5054–MAX5057. Peak supply and output currents
may exceed 8A when both drivers drive large external
capacitive loads in phase. Supply voltage drops and
ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition times.
Ground shifts due to insufficient device grounding may
also disturb other circuits sharing the same AC ground
R
is the maximum on-resistance of the device
ON(MAX)
with the output high, and I
of the MAX5054–MAX5057.
is the output load current
LOAD
Layout Information
The MAX5054–MAX5057 MOSFET drivers source and
sink large currents to create very fast rising and falling
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use the
following PC board layout guidelines when designing
with the MAX5054–MAX5057:
return path. Any series inductance in the V , OUT_,
DD
and/or GND paths can cause oscillations due to the very
high di/dt when switching the MAX5054–MAX5057 with
any capacitive load. Place one or more 0.1µF ceramic
capacitors in parallel as close to the device as possible to
•
Place one or more 0.1µF decoupling ceramic
capacitors from V to GND as close to the device
bypass V
to GND. Use a ground plane to minimize
DD
DD
ground return resistance and series inductance. Place
the external MOSFET as close as possible to the
MAX5054–MAX5057 to further minimize board induc-
tance and AC path impedance.
as possible. Connect V
and GND to large copper
DD
areas. Place one bulk capacitor of 10µF (min) on
the PC board with a low resistance path to the V
input and GND of the MAX5054–MAX5057.
DD
Power Dissipation
Power dissipation of the MAX5054–MAX5057 consists
of three components: caused by the quiescent current,
capacitive charge/discharge of internal nodes, and the
output current (either capacitive or resistive load).
Maintain the sum of these components below the maxi-
mum power dissipation limit.
•
Two AC current loops form between the device and
the gate of the driven MOSFET. The MOSFET looks
like a large capacitance from gate to source when the
gate pulls low. The active current loop is from the
MOSFET gate to OUT_ of the MAX5054–MAX5057, to
GND of the MAX5054–MAX5057, and to the source of
the MOSFET. When the gate of the MOSFET pulls
The current required to charge and discharge the internal
nodes is frequency dependent (see the Supply Current
vs. Supply Voltage graph in the Typical Operating
high, the active current is from the V
terminal of the
DD
decoupling capacitor, to V
of the MAX5054–
DD
MAX5057, to OUT_ of the MAX5054–MAX5057, to the
MOSFET gate, to the MOSFET source, and to the
negative terminal of the decoupling capacitor. Both
charging current and discharging current loops are
important. Minimize the physical distance and the
impedance in these AC current paths.
Characteristics). The power dissipation (P ) due to the
Q
quiescent switching supply current (I
can be calculated as:
) per driver
DD-SW
P
Q
= V
x I
DD DD-SW
For capacitive loads, use the following equation to esti-
mate the power dissipation per driver:
•
•
Keep the device as close to the MOSFET as possible.
x (V )2 x f
In a multilayer PC board, the inner layers should
consist of a GND plane containing the discharging
and charging current loops.
P
= C
CLOAD
LOAD DD SW
where C
is the capacitive load, V
SW
is the supply
LOAD
voltage, and f
DD
is the switching frequency.
•
Pay extra attention to the ground loop and use a
low-impedance source when using a TTL logic-
input device. Fast fall time at OUT_ may corrupt the
input during transition.
Calculate the total power dissipation (P ) per driver as
T
follows:
P = P + P
CLOAD
T
Q
Use the following equation to estimate the MAX5054–
MAX5057 total power dissipation per driver when driving
a ground-referenced resistive load:
P = P + P
RLOAD
T
Q
2
P
= D x R
x I
RLOAD
ON(MAX) LOAD
______________________________________________________________________________________ 11
4A, 20ns, Dual MOSFET Drivers
ground plane to dissipate 1.5W and 1.9W in SO-EP and
Exposed Pad
Both the SO-EP and TDFN-EP packages have an
exposed pad on the bottom of their package. These
pads are internally connected to GND. For the best
thermal conductivity, solder the exposed pad to the
TDFN-EP packages, respectively. Do not use the
ground-connected pads as the only electrical ground
connection or ground return. Use GND (pin 3) as the
primary electrical ground connection.
Additional Application Circuits
V
OUT
V
IN
MAX5054
V
DD
INA+
INA-
OUTA
MAX5054
V
DD
V
DD
INA+
INA-
INB+
INB-
PWM IN
PWM IN
OUTA
OUTB
GND
PWM IN
INB+
INB-
OUTB
GND
Figure 5. Push-Pull Converter with Synchronous Rectification Drive Using MAX5054
12 ______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Figure 6. Schematic of a 48V Input, 3.3V at 15A Output Synchronously Rectified, Isolated Power Supply
______________________________________________________________________________________ 13
4A, 20ns, Dual MOSFET Drivers
Pin Configurations
TOP VIEW
MAX5054
MAX5055
INA-
INB-
1
2
3
4
8
7
6
5
INA+
INB+
OUTA
N.C.
INA-
GND
INB-
1
2
3
4
8
7
6
5
N.C.
OUTA
GND
V
DD
OUTB
V
OUTB
DD
TDFN-EP
SO/SO-EP
MAX5056
MAX5057
N.C.
INA+
GND
INB+
1
2
3
4
8
7
6
5
N.C.
N.C.
INA-
GND
INB+
1
2
3
4
8
7
6
5
N.C.
OUTA
OUTA
V
DD
V
DD
OUTB
OUTB
SO/SO-EP
SO/SO-EP
Selector Guide
Chip Information
TRANSISTOR COUNT: 258
PROCESS: CMOS
PIN-
PACKAGE
PART
LOGIC INPUT
V
/ 2 CMOS Dual Inverting
DD
MAX5054AATA 8 TDFN-EP*
MAX5054BATA 8 TDFN-EP*
and Dual Noninverting Inputs
TTL Dual Inverting and Dual
Noninverting Inputs
MAX5055AASA 8 SO-EP*
MAX5055BASA 8 SO
MAX5056AASA 8 SO-EP*
MAX5056BASA 8 SO
TTL Dual Inverting Inputs
TTL Dual Inverting Inputs
TTL Dual Noninverting Inputs
TTL Dual Noninverting Inputs
TTL Inverting and
Noninverting Inputs
MAX5057AASA 8 SO-EP*
TTL Inverting and
Noninverting Inputs
MAX5057BASA 8 SO
*EP = Exposed pad.
14 ______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0∞-8∞
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
______________________________________________________________________________________ 15
4A, 20ns, Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
8L SOIC, .150" EXPOSED PAD
1
21-0111
B
1
16 ______________________________________________________________________________________
4A, 20ns, Dual MOSFET Drivers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D
N
PIN 1
INDEX
AREA
E
E2
DETAIL A
C
C
L
L
L
L
A
e
e
PACKAGE OUTLINE, 6, 8, 10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
21-0137
F
2
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
0.80
3.10
3.10
0.05
0.40
A
D
E
A1
L
k
0.25 MIN.
0.20 REF.
A2
PACKAGE VARIATIONS
PKG. CODE
T633-1
N
6
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
1.50 0.10 2.30 0.10 0.95 BSC
1.50 0.10 2.30 0.10 0.65 BSC
MO229 / WEEA
MO229 / WEEC
0.40 0.05
0.30 0.05
1.90 REF
1.95 REF
2.00 REF
2.40 REF
2.40 REF
T833-1
8
T1033-1
T1433-1
T1433-2
10
14
14
1.50 0.10 2.30 0.10 0.50 BSC MO229 / WEED-3 0.25 0.05
1.70 0.10 2.30 0.10 0.40 BSC
1.70 0.10 2.30 0.10 0.40 BSC
- - - -
- - - -
0.20 0.03
0.20 0.03
PACKAGE OUTLINE, 6, 8, 10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
21-0137
F
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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