MAX5069AAUE-T [MAXIM]
Switching Controller, Current-mode, 1A, 2500kHz Switching Freq-Max, BICMOS, PDSO16, 4.40 MM, MO-153-ABT, TSSOP-16;
| 型号： | MAX5069AAUE-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 1A, 2500kHz Switching Freq-Max, BICMOS, PDSO16, 4.40 MM, MO-153-ABT, TSSOP-16 信息通信管理 开关 光电二极管 |
| 文件： | 总19页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3175; Rev 1; 7/04
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Ge n e ra l De s c rip t io n
Fe a t u re s
♦ Current-Mode Control with 47µA (typ) Startup
The MAX5069 is a hig h-fre q ue nc y, c urre nt-mod e ,
pulse-width modulation (PWM) controller (with dual
MOSFET drivers) that integrates all the building blocks
necessary for implementing AC-DC or DC-DC fixed-fre-
quency power supplies. Isolated or nonisolated push-
p ull a nd ha lf/full-b rid g e p owe r s up p lie s a re e a s ily
constructed using either primary- or secondary-side
regulation. Current-mode control with leading-edge
blanking simplifies control-loop design and a program-
mable internal slope-compensation circuit stabilizes the
current loop when operating at duty cycles above 50%.
Current
♦ Oscillator Frequency Programmable to 2.5MHz
♦ Resistor-Programmable ±4.5% Accurate
Switching Frequency
♦ Dual Gate-Drive Output for Half/Full-Bridge or
Push-Pull Applications
♦ Rectified 85VAC to 265VAC, or 36VDC to 72VDC
Input (MAX5069A/B)
♦ Input Directly Driven from 10.8V to 24V
(MAX5069C/D)
An input undervoltage lockout (UVLO) programs the
input-supply startup voltage and ensures proper opera-
tion during brownout conditions.
♦ Programmable Dead Time and Slope
Compensation
♦ Programmable Startup Voltage (UVLO)
A single external resistor programs the oscillator frequen-
cy from 50kHz to 2.5MHz. The MAX5069A/D provide a
SYNC input for synchronization to an external clock. The
maximum FET-driver duty cycle for the MAX5069 is 50%.
Programmable dead time allows additional flexibility in
optimizing magnetic design and overcoming parasitic
effects. Programmable hiccup current limit provides
additional protection under severe faults.
♦ Programmable UVLO Hysteresis (MAX5069B/C)
♦ Frequency Synchronization Input (MAX5069A/D)
♦ -40°C to +125°C Automotive Temperature Range
♦ 16-Pin Thermally Enhanced TSSOP-EP Package
The MAX5069 is specified over the -40°C to +125°C auto-
motive te mp e ra ture ra ng e a nd is a va ila b le in a
16-pin thermally enhanced TSSOP-EP package. Refer to
the MAX5068 data sheet for single FET-driver applications.
Ord e rin g In fo rm a t io n
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
16 TSSOP-EP*
16 TSSOP-EP*
16 TSSOP-EP*
16 TSSOP-EP*
MAX5069AAUE
MAX5069BAUE
MAX5069CAUE
MAX5069DAUE
*EP = Exposed pad.
Warning: The MAX5069 is designed to work with high
voltages. Exercise caution.
Ap p lic a t io n s
Universal-Input AC Power Supplies
Isolated Telecom Power Supplies
Networking System Power Supplies
Server Power Supplies
P in Co n fig u ra t io n
TOP VIEW
RT
1
2
3
4
5
6
7
8
16 REG5
15 IN
Industrial Power Conversion
SYNC(HYST*)
SCOMP
DT
14
V
CC
MAX5069
13 NDRVA
12 NDRVB
11 PGND
10 AGND
UVLO/EN
FB
COMP
FLTINT
9 CS
TSSOP-EP
*MAX5069B/C.
Selector Guide appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
ABSOLUTE MAXIMUM RATINGS
IN to PGND ............................................................-0.3V to +30V
IN to AGND.............................................................-0.3V to +30V
AGND to PGND.....................................................-0.3V to +0.3V
Continuous Power Dissipation (T = +70°C)
A
V
to PGND..........................................................-0.3V to +13V
to AGND..........................................................-0.3V to +13V
16-Pin TSSOP-EP (derate 21.3mW/°C above +70°C)...1702mW
Operating Temperature Range..........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CC
V
CC
FB, COMP, CS, HYST, SYNC, REG5 to AGND ........-0.3V to +6V
UVLO/EN, RT, DT, SCOMP, FLTINT to AGND .........-0.3V to +6V
NDRVA, NDRVB to PGND..........................-0.3V to (V + 0.3V)
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +12V for the MAX5069C/D, V = +23.6V for the MAX5069A/B at startup, then reduces to +12V, C = C
= 0.1µF,
IN
IN
IN
REG5
C
= 1µF, R = 100kΩ, NDRV_ = floating, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
VCC
RT
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UNDERVOLTAGE LOCKOUT/STARTUP
Bootstrap UVLO Wake-Up Level
Bootstrap UVLO Shutdown Level
UVLO/EN Wake-Up Threshold
UVLO/EN Shutdown Threshold
V
V
rising, MAX5069A/B
falling, MAX5069A/B
19.68
9.05
21.6
9.74
23.60
10.43
V
V
V
V
SUVR
IN
V
SUVF
V
IN
V
ULR2
UVLO/EN rising
UVLO/EN falling
1.205 1.230 1.255
1.18
V
ULF2
MAX5069B/C only, sinking 50mA,
HYST FET On-Resistance
HYST FET Leakage Current
R
10
3
Ω
nA
µA
V
DS(ON)_H
V
= 0V
UVLO/EN
I
V
= 2V, V
= 5V
LEAK_H
UVLO/EN
HYST
IN Supply Current In
Undervoltage Lockout
I
V
IN
= +19V, V
< V
ULF2
47
90
START
UVLO/EN
IN Range
V
IN
10.8
24.0
INTERNAL SUPPLIES (V
and REG5)
CC
V
Regulator Set Point
V
V
= +10.8V to +24V, V sourcing 1µA to 25mA
7.0
10.5
5.15
V
V
CC
CCSP
IN
CC
REG5 Output Voltage
V
REG5
I
= 0 to 1mA
4.85
5.00
18
7
REG5
REG5 Short-Circuit Current Limit
I
mA
REG5_SC
f
= 1.25MHz
= 100kHz
SW
IN Supply Current After Startup
I
IN
V
IN
= +24V
mA
µA
f
3
SW
Shutdown Supply Current
I
90
VIN_SD
GATE DRIVER (NDRVA, NDRVB)
Z
NDRVA/NDRVB sinking 100mA
NDRVA/NDRVB sourcing 25mA
Sinking
2
3
4
6
OUT(LOW)
Driver Output Impedance
Driver Peak Output Current
Ω
Z
OUT(HIGH)
1000
650
I
mA
NDRV
Sourcing
PWM COMPARATOR
Comparator Offset Voltage
Comparator Propagation Delay
Minimum On-Time
V
V
> V
CS
1.30
298
1.60
40
2.00
330
V
ns
ns
OS_PWM
COMP
t
V
CS
= 0.1V
PD_PWM
t
Includes t
110
ON(MIN)
CS_BLANK
CURRENT-LIMIT COMPARATOR
Current-Limit Trip Threshold
V
CS
314
mV
2
_______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
ELECTRICAL CHARACTERISTICS (continued)
(V = +12V for the MAX5069C/D, V = +23.6V for the MAX5069A/B at startup, then reduces to +12V, C = C
= 0.1µF,
IN
IN
IN
REG5
C
= 1µF, R = 100kΩ, NDRV_ = floating, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
VCC
RT
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
µA
CS Input Bias Current
CS Blanking Time
I
V
= 0V
0
+2
B_CL
CS_BLANK
CS
t
70
40
ns
Propagation Delay from
Comparator Input to NDRV_
t
50mV overdrive
ns
V
PD_CL
IN CLAMP VOLTAGE
IN Clamp Voltage
V
IN sinking 2mA (Note 2)
24.0
26.0
29.0
IN_CLAMP
ERROR AMPLIFIER (FB, COMP)
Voltage Gain
A
V
R
= 100kΩ to AGND
80
5
dB
COMP
R
C
= 100kΩ to AGND,
= 100pF to AGND
COMP
Unity-Gain Bandwidth
BW
PM
MHz
LOAD
R
COMP
C
= 100kΩ to AGND,
= 100pF to AGND
Phase Margin
65
Degrees
mV
LOAD
FB Input Offset Voltage
COMP Clamp Voltage
Error-Amplifier Output Current
V
3
OS_FB
High
Low
2.6
0.4
0.5
3.8
1.1
V
V
COMP
I
Sinking or sourcing
+25°C ≤ T ≤ +125°C (Note 3)
mA
COMP
1.215 1.230 1.245
1.205 1.230 1.242
A
Reference Voltage
V
REF
V
-40°C ≤ T ≤ +125°C (Note 3)
A
Input Bias Current
I
100
12
300
nA
B_EA
COMP Short-Circuit Current
THERMAL SHUTDOWN
Thermal-Shutdown Temperature
Thermal Hysteresis
I
mA
COMP_SC
T
SD
+170
25
°C
°C
T
HYST
OSCILLATOR SYNC INPUT (MAX5069A/D only)
SYNC High-Level Voltage
SYNC Low-Level Voltage
SYNC Input Bias Current
Maximum SYNC Frequency
SYNC High-Level Pulse Width
SYNC Low-Level Pulse Width
DIGITAL SOFT-START
Soft-Start Duration
V
2.4
V
V
IH_SYNC
V
0.4
IL_SYNC
I
10
nA
MHz
ns
B_SYNC
f
f
= 2.5MHz (Note 4)
3.125
30
SYNC
OSC
t
SYNC_HI
t
30
ns
SYNC_LO
t
(Note 5)
2047
9.7
Cycles
mV
SS
Reference-Voltage Step
V
STEP
Reference-Voltage Steps During
Soft-Start
127
Steps
OSCILLATOR
Oscillator Frequency Range
f
f
= (1011 / R
)
RT
50
2500
kHz
OSC
OSC
_______________________________________________________________________________________
3
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
ELECTRICAL CHARACTERISTICS (continued)
(V = +12V for the MAX5069C/D, V = +23.6V for the MAX5069A/B at startup, then reduces to +12V, C = C
= 0.1µF,
IN
IN
IN
REG5
C
= 1µF, R = 100kΩ, NDRV_ = floating, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Note 1)
VCC
RT
A
MIN
MAX
A
PARAMETER
SYMBOL
CONDITIONS
= 1011 / (2 x R
MIN
TYP
MAX
UNITS
kHz
V
NDRV_ Switching Frequency
RT Voltage
f
f
)
RT
25
1250
SW
SW
V
RT
40kΩ < R < 500kΩ
2.0
RT
f
≤ 500kHz
> 500kHz
≤ 500kHz
> 500kHz
-2.5
-4
+2.5
+4
OSC
T
= +25°C
A
f
OSC
Oscillator Accuracy
%
%
f
-4.5
-6
+4.5
+6
OSC
T
A
= -40°C to +125°C
f
OSC
Maximum Duty Cycle
DEAD-TIME CONTROL (DT)
Dead Time
D
DT connected to REG5
100
60
MAX
t
R
DT
= 24.9kΩ
ns
V
DT
V
DT_DISABLE
V
REG5
0.5V
-
Dead-Time Disable Voltage
Dead-Time Regulation Voltage
V
DT
1.23
V
INTEGRATING FAULT PROTECTION (FLTINT)
FLTINT Source Current
FLTINT Shutdown Threshold
FLTINT Restart Threshold
SLOPE COMPENSATION
Slope Compensation
I
V
= 0V
rising
falling
60
2.8
1.6
µA
V
FLTINT
FLTINT
V
V
FLTINT
FLTINT_SD
V
V
FLTINT
V
FLTINT_RS
V
C
= 100pf, RT = 110kΩ
SLOPE
15
mV/µs
mV/µs
SLOPE
Slope-Compensation Range
V
0
0
90
SLOPER
Slope-Compensation Voltage
Range
V
2.7
V
SCOMP
Note 1: The MAX5069 is 100% tested at T = +25°C. All limits over temperature are guaranteed by design.
A
Note 2: The MAX5069A/B are intended for use in universal-input power supplies. The internal clamp circuit is used to prevent the
bootstrap capacitor (C1 in Figure 1) from charging to a voltage beyond the absolute maximum rating of the device when
UVLO/EN is low. The maximum current to V (hence to clamp) when UVLO is low (device is in shutdown) must be external-
IN
ly limited to 2mA. Clamp currents higher than 2mA may result in clamp voltages higher than 30V, thus exceeding the
absolute maximum rating for V . For the MAX5069C/D, do not exceed the 24V maximum operating voltage of the device.
IN
Note 3: Reference voltage (V ) is measured with FB connected to COMP (see the Functional Diagram).
REF
Note 4: The SYNC frequency must be at least 25% higher than the programmed oscillator frequency.
Note 5: The internal oscillator clock cycle.
4
_______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +23.6V for MAX5069A/B at startup, then reduces to +12V, V = +12V for the MAX5069C/D, C = C
= 0.1µF, C
= 1µF,
VCC
IN
IN
IN
REG5
R
RT
= 100kΩ, NDRV_ = floating, V = 0V, V
= floating, V = 0V, T = +25°C, unless otherwise noted.)
COMP CS A
FB
BOOTSTRAP UVLO WAKE-UP LEVEL
vs. TEMPERATURE
BOOTSTRAP UVLO SHUTDOWN LEVEL
vs. TEMPERATURE
UVLO/EN WAKE-UP THRESHOLD
vs. TEMPERATURE
21.6
10.0
9.9
1.245
1.240
MAX5069A/B
MAX5069A/B
UVLO/EN RISING
21.5
21.4
21.3
21.2
21.1
21.0
9.8
9.7
9.6
9.5
1.235
1.230
1.225
1.220
-40 -15
10
35
60
85
110
-40
-15
10
35
60
85
110
-40
-15
10
35
60
85
110
°
°
°
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
UVLO/EN SHUTDOWN THRESHOLD
vs. TEMPERATURE
V
IN
SUPPLY CURRENT IN UNDERVOLTAGE
LOCKOUT vs. TEMPERATURE
V
IN
SUPPLY CURRENT AFTER STARTUP
vs. TEMPERATURE
1.20
1.19
1.18
1.17
8
60
56
UVLO/EN FALLING
f
= 1.25MHz
V
= 19V
SW
IN
V = 24V
IN
WHEN IN BOOTSTRAP UVLO (MAX5069A/B)
UVLO/EN (MAX5069C/D) IS LOW
7
6
5
4
3
2
f
SW
= 500kHz
1.16
1.15
1.14
1.13
1.12
1.11
1.10
52
48
44
40
f
SW
= 250kHz
f
= 100kHz
SW
f
SW
= 50kHz
1
-40 -15
10
35
60
85
110
-40 -15
10
35
60
85
110
-40 -15
10
35
60
85
110
°
TEMPERATURE ( C)
°
TEMPERATURE ( C)
TEMPERATURE (°C)
REG5 OUTPUT VOLTAGE
vs. OUTPUT CURRENT
REG5 vs. TEMPERATURE
V
CC
vs. TEMPERATURE
10.0
9.7
9.4
9.1
8.8
8.5
8.2
7.9
7.6
7.3
7.0
4.980
4.975
4.970
4.965
4.960
4.955
4.950
5.00
4.99
4.98
4.97
V
IN
= 10.8V
R
RT
= 100kΩ
V
= 19V, I = 10mA
IN
IN
100µA LOAD
V
= 19V, I = 25mA
IN
IN
4.96
4.95
4.94
4.93
4.92
4.91
4.90
1mA LOAD
V
IN
= 10.8V, I = 10mA
IN
V
IN
= 10.8V, I = 25mA
IN
-40 -15
10
35
60
85
110
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
OUTPUT CURRENT (mA)
-40
-15
10
35
60
°
85
110
TEMPERATURE (°C)
TEMPERATURE ( C)
_______________________________________________________________________________________
5
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +23.6V for MAX5069A/B at startup, then reduces to +12V, V = +12V for the MAX5069C/D, C = C
= 0.1µF, C
= 1µF,
VCC
IN
IN
IN
REG5
R
RT
= 100kΩ, NDRV_ = floating, V = 0V, V
= floating, V = 0V, T = +25°C, unless otherwise noted.)
COMP CS A
FB
CS TRIP THRESHOLD
vs. TEMPERATURE
SWITCHING FREQUENCY
vs. TEMPERATURE
REG5 OUTPUT VOLTAGE vs. V
IN
330
327
324
321
318
315
312
4.985
530
525
520
515
510
505
500
f
= 500kHz
SW
TOTAL NUMBER OF
DEVICES = 200
I
= 100µA
REG5
4.984
4.983
4.982
4.981
4.980
4.979
4.978
4.977
4.976
4.975
+3σ
MEAN
309
306
303
-3σ
495
490
485
300
-40
480
-40
110
-15
10
35
60
85
10
12
14
16
18
(V)
20
22
24
10
TEMPERATURE (°C)
35
60
85
110
-15
TEMPERATURE (°C)
V
IN
PROPAGATION DELAY FROM CS COMPARATOR
INPUT CLAMP VOLTAGE
vs. TEMPERATURE
INPUT CURRENT
vs. INPUT CLAMP VOLTAGE
INPUT TO NDRV vs. TEMPERATURE
50
27.0
14
12
10
8
I
= 2mA
SINK
48
46
44
42
40
38
36
34
32
30
26.8
26.6
26.4
26.2
26.0
25.8
25.6
25.4
25.2
25.0
6
4
2
0
-40 -15
10
35
60
85
110
-40 -15
10
35
60
85
110
10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0
INPUT CLAMP VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
NDRVA/NDRVB OUTPUT IMPEDANCE
vs. TEMPERATURE
ERROR AMPLIFIER OPEN-LOOP GAIN
NDRVA/NDRVB OUTPUT IMPEDANCE
vs. TEMPERATURE
AND PHASE vs. FREQUENCY
MAX5069 toc18
120
100
80
30
4.0
3.8
3.6
3.4
3.0
2.8
2.6
2.4
V
= 24V
IN
V
= 24V
IN
SOURCING 25mA
SINKING 100mA
0
-30
-60
-90
-120
-150
-180
-210
GAIN
60
3.2
3.0
2.8
2.6
2.4
2.2
2.0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
40
PHASE
20
0
-20
-40
-40
-15
10
35
60
85
110
0.1
10
1k
100k
10M
-40 -15
10
35
60
85
110
°
°
TEMPERATURE ( C)
FREQUENCY (Hz)
TEMPERATURE ( C)
6
_______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +23.6V for MAX5069A/B at startup, then reduces to +12V, V = +12V for the MAX5069C/D, C = C
= 0.1µF, C
= 1µF,
VCC
IN
IN
IN
REG5
R
RT
= 100kΩ, NDRV_ = floating, V = 0V, V
= floating, V = 0V, T = +25°C, unless otherwise noted.)
COMP CS A
FB
NDRVA SWITCHING FREQUENCY (f
SW)
FLTINT CURRENT vs. TEMPERATURE
HYST R vs. TEMPERATURE
ON
vs. R
RT
63.0
62.9
62.8
62.7
13.0
12.5
12.0
11.5
2
1
V
= 24V
IN
SINKING 50mA
62.6
62.5
62.4
62.3
62.2
62.1
62.0
11.0
10.5
10.0
9.5
0.1
9.0
8.5
8.0
0.01
-40 -15
10
35
60
85
110
-40
-15
10
35
60
85
110
0.03
0.1
1
2
°
°
TEMPERATURE ( C)
TEMPERATURE ( C)
R
RT
(MΩ)
NDRV SWITCHING FREQUENCY
vs. TEMPERATURE
NDRV SWITCHING FREQUENCY
vs. TEMPERATURE
NDRV SWITCHING FREQUENCY
vs. TEMPERATURE
505
504
52.0
51.6
51.2
50.8
50.4
50.0
49.6
49.2
48.8
48.4
48.0
1.40
1.35
1.30
1.25
1.20
1.15
1.10
f
SW
= 500kHz
f
SW
= 1.25MHz
f
SW
= 50kHz
503
502
501
500
499
498
497
496
495
-25
0
25
100
125
-50
50
75
-40 -15
10
35
60
85
110
-15
10
35
110
-40
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
DEAD TIME vs. TEMPERATURE
DEAD TIME vs. R
DT
70
65
60
55
50
45
40
200
V
= 24V
= 24.9kΩ
= 100kΩ
IN
180
160
140
120
100
80
R
R
DT
RT
60
40
20
0
-40 -15
10
35
60
85
110
1
10
(kΩ)
100
TEMPERATURE (°C)
R
DT
_______________________________________________________________________________________
7
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w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
P in De s c rip t io n
PIN
NAME
FUNCTION
MAX5069A MAX5069B
MAX5069D MAX5069C
Oscillator-Timing Resistor. Connect a resistor from RT to AGND to set the internal oscillator
frequency.
1
1
RT
2
—
3
—
2
SYNC
HYST
External-Clock Sync Input. Connect SYNC to AGND when not using an external clock.
Hysteresis Input
3
SCOMP
Slope-Compensation Capacitor Connection
Dead-Time Resistor Connection. Connect a resistor from DT to AGND to program the
output dead time. Connect to REG5 for NDRVA and NDRVB maximum 50% duty cycle.
4
5
4
5
DT
Externally Programmable Undervoltage Lockout. UVLO/EN programs the input start
voltage. Connect UVLO/EN to AGND to disable the output.
UVLO/EN
6
7
6
7
FB
Error-Amplifier Inverting Input
Error-Amplifier Output
COMP
Fault-Integration Input. A capacitor connected to FLTINT charges with an internal 60µA
current source during persistent current-limit faults. Switching terminates when V
is
FLTINT
8
8
FLTINT
2.8V. An external resistor connected in parallel discharges the capacitor. Switching
resumes when V drops to 1.6V.
FLTINT
9
9
CS
Current-Sense Resistor Connection
10
11
12
13
10
11
12
13
AGND
PGND
NDRVB
NDRVA
Analog Ground. Connect to PGND.
Power Ground. Connect to AGND through a ground plane.
Gate-Driver Output B. Connect NDRVB to the gate of the external N-channel FET.
Gate-Driver Output A. Connect NDRVA to the gate of the external N-channel FET.
9V Linear-Regulator Output. Decouple V with a minimum 1µF ceramic capacitor to
CC
AGND; also internally connected to the FET drivers.
14
15
14
15
V
CC
Power-Supply Input. IN provides power for all internal circuitry except the gate driver.
Decouple IN with 0.1µF to AGND (see the Typical Operating Circuit).
IN
16
16
REG5
PAD
5V Linear-Regulator Output. Decouple REG5 to AGND with 0.1µF ceramic capacitor.
Exposed Paddle. Connect to GND.
EP
EP
8
_______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
driver duty cycle for each driver is limited to 50%.
De t a ile d De s c rip t io n
Programmable dead time allows additional flexibility in
The MAX5069 is a current-mode, dual MOSFET driver,
optimizing magnetic design and overcoming parasitic
PWM controller designed for isolated and nonisolated
effects. Integrating fault protection ignores transient
push-pull or half-/full-bridge power-supply applications.
overcurrent conditions for a set length of time. The
A bootstrap UVLO with a programmable hysteresis,
length of time is programmed by an external capacitor.
very low startup, and low operating current result in
The inte rna l the rma l-s hutd own c irc uit p rote c ts the
high-efficiency universal-input power supplies. In addi-
d e vic e s hould the junc tion te mp e ra ture e xc e e d
tion to the internal bootstrap UVLO, the device also
+170°C.
offers programmable input startup and turn-off volt-
ages, programmed through the UVLO/EN pin.
Power supplies designed with the MAX5069A/B use a
high-value startup resistor, R1, which charges a reser-
voir capacitor, C1 (Figure 1). During this initial period,
while the voltage is less than the internal bootstrap
UVLO threshold, the device typically consumes only
47µA of quiescent current. This low startup current and
the large bootstrap UVLO hysteresis help to minimize
the power dissipation across R1 even at the high end of
the universal AC input voltage (265VAC).
The MAX5069 includes a cycle-by-cycle current limit
that turns off the gate drive to the external MOSFET
during an overcurrent condition. The MAX5069 integrat-
ing fault protection reduces average power dissipation
during persistent fault conditions (see the Integrating
Fault Protection section).
The MAX5069 features a very accurate, wide-range,
programmable oscillator that simplifies and optimizes
the design of the magnetics. The MAX5069A/B are well
suited for universal-input (rectified 85VAC to 265VAC)
or telecom (-36VDC to -72VDC) power supplies. The
MAX5069C/D a re we ll s uite d for low-inp ut volta g e
(10.8VDC to 24VDC) power supplies.
The MAX5069 includes a cycle-by-cycle current limit
that turns off the gates to both external MOSFETs dur-
ing a n ove rc urre nt c ond ition. Whe n us ing the
MAX5069A/B in the bootstrap mode (if the power-sup-
p ly outp ut is s horte d ), the te rtia ry wind ing volta g e
drops below the 9.74V threshold, causing the UVLO to
turn off the gate to the external power MOSFETs. This
reinitiates a startup sequence with soft-start.
The MAX5069 hig h-fre q ue nc y, unive rs a l inp ut,
offline/telecom, current-mode PWM controller integrates
all the building blocks necessary for implementing AC-
DC and DC-DC fixed-frequency power supplies. Push-
pull and half-/full-bridge isolated or nonisolated power
supplies are easily constructed using either primary- or
secondary-side regulation. Current-mode control with
leading-edge blanking simplifies control-loop design
and the programmable slope compensation stabilizes
the current loop when operating both FET drivers at a
combined 100% duty cycle.
Cu rre n t -Mo d e Co n t ro l
The MAX5069 offers a current-mode control operation
feature, such as leading-edge blanking with a dual
internal path that only blanks the sensed current signal
applied to the input of the PWM controller. The current-
limit comparator monitors CS at all times and provides
cycle-by-cycle current limit without being blanked. The
leading-edge blanking of the CS signal prevents the
PWM comparator from prematurely terminating the on
cycle. The CS signal contains a leading-edge spike
that results from the MOSFET’s gate charge current,
and the capacitive and diode reverse-recovery current
of the power circuit. Since this leading-edge spike is
normally lower than the current-limit comparator thresh-
old, current limiting is provided under all conditions.
An input UVLO programs the input-supply startup volt-
age and ensures proper operation during brownout con-
ditions. An external voltage-divider programs the supply
startup voltage. The MAX5069B/C feature a programma-
ble UVLO hysteresis. The MAX5069A/B feature an addi-
tional internal bootstrap UVLO with large hysteresis that
re q uire s a minimum s ta rtup volta g e of 23.6V. The
MAX5069A/D start up from a minimum voltage of 10.8V.
Internal digital soft-start reduces output-voltage over-
shoot at startup.
Use the MAX5069 in push-pull and half-/full-bridge appli-
cations where a large duty cycle is desired. The large
duty cycle results in much lower operating primary RMS
currents through the MOSFET switches, and in most
cases it results in a smaller inductor and output filter
capacitor. The MAX5069 adjusted slope compensation
allows for easy stabilization of the inner current loop.
A single external resistor programs the switching fre-
q ue nc y of e a c h MOSFET d rive r from 25kHz to
1.25MHz. The MAX5069A/D provide a SYNC input for
synchronization to an external clock. The maximum FET
_______________________________________________________________________________________
9
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
D3
D1
V
OUT
C7
V
IN
R1
C1
R6
R2
C2
IN
D2
UVLO/EN
HYST
FLTINT
R
HYST
C3
C4
V
CC
R9
R7
MAX5069B
REG5
RT
R3
NDRVB
Q2
R10
NDRVA
Q1
R4
C5
DT
CS
FB
SCOMP
R8
AGND PGND COMP
R5
C6
Figure 1. Nonisolated Power Supply with Programmable Input Supply Voltage
Calculate R6 in Figure 2 by using the following formula:
Un d e rvo lt a g e Lo c k o u t
The MAX5069 features an input voltage UVLO/EN func-
tion to enable the PWM controller before any operation
can begin. The MAX5069A/D shut down if the voltage
a t UVLO/EN fa lls b e low its 1.18V thre s hold . The
MAX5069B/C also incorporate a UVLO hysteresis input
to set the desired turn-off voltage.
⎛
⎞
V
ON
R6 =
−1 × R7
⎜
⎟
V
⎝
⎠
ULR2
where V
is the UVLO/EN’s 1.231V rising threshold
ULR2
and V
is the desired startup voltage. Choose an R7
ON
value in the 20kΩ range.
MAX5069A/D UVLO Adjustment
The MAX5069A/D have an input voltage UVLO/EN with
a 1.231V threshold. Before any operation can com-
mence, the UVLO/EN voltage must exceed the 1.231V
threshold. The UVLO circuit keeps the PWM compara-
tor, ILIM comparator, oscillator, and output drivers shut-
d own to re d uc e c urre nt c ons ump tion (s e e the
Functional Diagram).
After a successful startup, the MAX5069A/D shut down
if the voltage at UVLO/EN drops below its 1.18V fall-
ing threshold.
MAX5069B/C UVLO with
Programmable Hysteresis
In addition to programmable undervoltage lockout dur-
ing startup, the MAX5069B/C incorporate a UVLO/EN
10 ______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
V
IN
MAX5069A/D
R6
R7
UVLO/EN
V
= V - V
HYST ON OFF
1.23V
1.18V
V
OFF
V
ON
Figure 3. MAX5069 Hysteresis
Fig ure 2. Se tting the MAX5069A/D Und e rvolta g e Loc kout
Threshold
hysteresis that allows the user to set a voltage (V
) to
OFF
disable the controller (see Figure 3).
V
IN
At the beginning of the startup sequence, UVLO/EN is
below the 1.23V threshold, and Q1 turns on connecting
MAX5069B/C
R6
R
to GND (Figure 4). Once the UVLO 1.23V thresh-
HYST
old is crossed, Q1 turns off, resulting in the series com-
bination of R6, R , and R7, placing the MAX5069 in
normal operating condition.
UVLO/EN
HYST
HYST
R
HYST
Calculate the turn-on voltage (V ) by using the fol-
ON
lowing formula:
1.23V
1.18V
⎛
⎞
Q1
V
R7
ON
R6 =
−1 × R
HYST
⎜
⎟
V
⎝
⎠
ULR2
where V
is the UVLO/EN’s 1.23V rising threshold.
ULR2
Choose an R
value in the 20kΩ range.
HYST
The MAX5069 turns off when the MAX5069 UVLO/EN
falls below the 1.18V falling threshold. The turn-off volt-
Figure 4. Setting the MAX5069B/C Turn-On/Turn-Off Voltages
age (V ) is then defined as:
OFF
power-up. The MAX5069A/B start when V exceeds
IN
the bootstrap UVLO threshold of 23.6V.
⎛
⎞
V
OFF
R7 = R6 /
−1 − R
HYST
⎜
⎟
V
⎝
⎠
ULF2
During startup, the UVLO circuit keeps the PWM com-
parator, ILIM comparator, oscillator, and output drivers
where V
is the 1.18V UVLO/EN falling threshold.
ULF2
shut down to reduce current consumption. Once V
IN
reaches 23.6V, the UVLO circuit turns on both the PWM
and ILIM comparators, as well as the oscillator, and
Bo o t s t ra p Un d e rvo lt a g e Lo c k o u t
(MAX5 0 6 9 A/B)
In addition to the externally programmable UVLO func-
tion offered by the MAX5069, the MAX5069A/B feature
an additional internal bootstrap UVLO for use in high-
voltage power supplies (see the Functional Diagram).
This allows the device to bootstrap itself during initial
allows the output driver to switch. If V drops below
IN
9.7V, the UVLO circuit shuts down the PWM compara-
tor, ILIM comparator, oscillator, and output drivers,
returning the MAX5069A/B to the startup mode.
______________________________________________________________________________________ 11
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w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
MAX5 0 6 9 A/B S t a rt u p Op e ra t io n
Normally, V is derived from the tertiary winding of the
IN
transformer. However, at startup there is no energy
delivered through the transformer; hence, a special
bootstrap sequence is required. Figure 5 shows the
V
2V/div
CC
voltages on V and V
during startup. Initially, both
IN
CC
V
and V
are 0V. After the input voltage is applied,
IN
CC
MAX5069
C1 charges through the startup resistor, R1, to an inter-
mediate voltage (see Figure 1). At this point, the inter-
nal regulator begins charging C3 (see Figure 5). Only
47µA of the current supplied by R1 is used by the
MAX5069A/B. The remaining input current charges C1
V PIN
IN
5V/div
0V
and C3. The charging of C3 stops when the V
volt-
CC
age reaches approximately 9.5V. The voltage across
C1 continues rising until it reaches the wake-up level of
100ms/div
23.6V. Once V exceeds the bootstrap UVLO thresh-
IN
old, NDRVA/NDRVB begin switching the MOSFETs and
energy is transferred to the secondary and tertiary out-
puts. If the voltage on the tertiary output builds to high-
er than 9.74V (the bootstrap UVLO lower threshold),
startup ends and sustained operation commences.
Fig ure 5. V a nd V
During Sta rtup Whe n Us ing the
MAX5069 in Bootstrapped Mode (See Figure 1)
IN CC
If V drops below 9.74V before startup is complete, the
IN
I
= Q
x f
gtot SW
g
device goes back to low-current UVLO. If this occurs,
increase the value of C1 to store enough energy to
allow for the voltage at the tertiary winding to build up.
(I + I ) x t
SS
IN
g
C1 =
V
HYST
Startup Time Considerations for
Power Supplies Using the MAX5069A/B
The V bypass capacitor, C1, supplies current imme-
diately after wakeup (see Figure 1). The size of C1 and
the connection configuration of the tertiary winding
determine the number of cycles available for startup.
Large values of C1 increase the startup time and also
supply extra gate charge for more cycles during initial
where I is the MAX5069’s internal supply current after
IN
startup (3.3mA, typ), Q
is the total gate charge for
gtot
IN
Q1 and Q2, f
is the MAX5069’s programmed output
SW
switching frequency, V
is the bootstrap UVLO hys-
HYST
teresis (12V), and t is the internal soft-start time (2047
ss
clock cycles x 1 / f
).
OSC
Example:
I = (16nC) (250kHz) ≅ 4mA
g
startup. If the value of C1 is too small, V drops below
IN
f
= 500kHz
OSC
9.74V because NDRVA/NDRVB do not have enough
time to switch and build up sufficient voltage across the
tertiary output that powers the device. The device goes
back into UVLO and does not start. Use low-leakage
capacitors for C1 and C3.
t
= 2047 x (1 / f
) = 4.1ms
SS
OSC
(3.3mA + 4mA) (4.1ms)
C1 =
= 2.5µF
12V
Use a 4.7µF ceramic capacitor for C1.
Assuming C1 > C3, calculate the value of R1 as follows:
Generally, offline power supplies keep typical startup
times to less than 500ms, even in low-line conditions
(85VAC inp ut for unive rs a l offline a p p lic a tions or
36VDC for telecom applications). Size the startup resis-
tor, R1, to supply both the maximum startup bias of the
device (90µA) and the charging current for C1 and C3.
The bypass capacitor, C3, must charge to 9.5V, and
C1 must charge to 24V, within the desired time period
of 500ms. Because of the internal soft-start time of the
MAX5069, C1 must store enough charge to deliver cur-
rent to the device for at least 2047 oscillator clock
cycles. To calculate the approximate amount of capaci-
tance required, use the following formula:
V
× C1
500ms
− 0.5 x V
SUVR
I
≅
C1
V
IN(MIN)
I
SUVR
R1 ≅
+ I
C1
START
whe re V
is the b oots tra p UVLO wa ke up le ve l
SUVR
(23.6V max), V
is the minimum input supply volt-
IN(MIN)
age for the application (36V for telecom), and I
is
START
the V supply current at startup (90µA, max).
IN
12 ______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
V
OUT
C7
V
IN
R1
C1
R6
R2
C2
IN
UVLO/EN
HYST
FLTINT
R
HYST
C3
C4
MAX5069B
V
CC
R7
REG5
RT
NDRVB
NDRVA
Q2
R3
Q1
R4
C5
DT
CS
FB
R12
C8
R8
V
CC
SCOMP
AGND PGND COMP
R5
C6
C10
R13
R14
PS2913
R10
MAX8515
R9
R11
Figure 6. Secondary-Side, Regulated, Isolated Power Supply
For example:
To minimize power loss on this resistor, choose a high-
er value for R1 than the one calculated above (if a
longer startup time can be tolerated).
24V x 4.7µF
500ms
36V − 12V
I
=
= 225µA
= 76kΩ
C1
The above startup method applies to a circuit similar to
the one shown in Figure 1. In this circuit, the tertiary
winding has the same phase as the secondary wind-
ings. Thus, the voltage on the tertiary winding at any
given time is proportional to the output voltage. The
minimum discharge time of C1 from 22V to 10V must
R1 ≅
225µA + 90µA
be greater than the soft-start time (t ).
SS
______________________________________________________________________________________ 13
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
shorting out the transformer’s primary. The MAX5069
a llows the d e a d -time d e la y re q uire d to turn on the
NDRVB FET after the NDRVA FET turns off. The dead
time can be programmed to a minimum of 30ns to 1 / (0.5
Os c illa t o r/S w it c h in g Fre q u e n c y
Use an external resistor at RT to program the MAX5069
internal oscillator frequency from 50kHz to 2.5MHz. The
MAX5069 NDRVA/NDRVB switching frequency is one
half of the programmed oscillator frequency with a
maximum 50% duty cycle.
x f ). Connect a resistor between DT and AGND to set
SW
the desired dead time. Calculate the dead time using the
following formula:
Use the following formula to calculate the internal oscil-
lator frequency:
60
Dead time =
× R (ns)
DT
11
29.4
10
f
=
osc
R
RT
where R is in kΩ and the dead time is in ns.
DT
where f
is the oscillator frequency and R
is a
RT
OSC
Ex t e rn a l S yn c h ro n iza t io n (MAX5 0 6 9 A/D)
The MAX5069A/D can be synchronized using an exter-
nal clock at the SYNC input. For proper frequency syn-
chronization, the SYNC’s input frequency must be at
least 25% higher than the MAX5069A/D programmed
internal oscillator frequency. Connect SYNC to AGND
when not using an external clock.
resistor connected from RT to AGND.
Choose the appropriate resistor at RT to calculate the
desired switching frequency (f ):
SW
11
10
=
R
RT
2f
SW
In t e g ra t in g Fa u lt P ro t e c t io n
The integrating fault-protection feature allows transient
overcurrent conditions to be ignored for a programma-
ble amount of time, giving the power supply time to
behave like a current source to the load. For example,
this can occur under load-current transients when the
control loop requests maximum current to keep the out-
put voltage from going out of regulation. Program the
fault-integration time by connecting an external suitably
sized capacitor to the FLTINT. Under sustained over-
current faults, the voltage across this capacitor ramps
up towards the FLTINT shutdown threshold (typically
2.8V). Once the threshold is reached, the power supply
shuts down. A high-value bleed resistor connected in
parallel with the FLTINT capacitor allows it to discharge
towards the restart threshold (typically 1.6V). Once this
threshold is reached, the supply restarts with a new
soft-start cycle.
For the maximum 50% duty cycle at NDRVA/NDRVB,
connect DT to REG5.
Du a l N-Ch a n n e l MOS FET S w it c h Drive r
The MAX5069 drives two external N-channel MOSFETs
in push-pull isolated power supplies. Each MOSFET
driver operates with a maximum 50% duty cycle. The
NDRV_ outputs are supplied by the internal regulator
(V ), which is internally set to approximately 9.5V. For
CC
the universal input voltage range, the MOSFETs used
must be able to withstand at least twice the DC level of
the high-line input voltage. Both NDRVA and NDRVB
can source and sink in excess of 650mA and 1000mA
peak current, respectively.
Dead-Time Control
In typical push-pull designs, it is desirable to add some
extra delay between the turning off of one MOSFET and
the turning on of the next MOSFET (Figure 7). The extra
time ensures that the first MOSFET is fully off when the
other MOSFET starts to turn on. This prevents both
MOSFETs from being on simultaneously, thus avoiding
SYNC
MAX5069A/D
RT
t
DT
DEAD TIME
NDRVA
NDRVB
<50%
PWM
<50%
PWM
AGND
Figure 7. MAX5069 Dead-Time Timing Diagram
Figure 8. External Synchronization of the MAX5069A/D
14 ______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Note that cycle-by-cycle current limiting is provided at
all times by CS with a threshold of 314mV (typ). The
fa ult-inte g ra tion c irc uit forc e s a 60µA c urre nt onto
FLTINT each time that the current-limit comparator is
tripped (see the Functional Diagram). Use the following
formula to calculate the value of the capacitor neces-
sary for the desired shutdown time of the circuit:
Erro r Am p lifie r
The MAX5069 includes an internal error amplifier that
can regulate the output voltage in the case of a noniso-
lated power supply (Figure 1). Calculate the output volt-
age using the following equation:
R9
⎛
⎞
V
=
1 +
x V
REF
⎜
⎝
⎟
⎠
OUT
R10
I
x t
SH
FLTINT
C
≅
FLTINT
2.8V
where V
= 1.23V. The amplifier’s noninverting input
REF
internally connects to a digital soft-start reference voltage.
This forces the output voltage to come up in an orderly
and well-defined manner under all load conditions.
where I
= 60µA, t
SH
is the desired fault-integra-
FLTINT
tion time during which current-limit events from the cur-
rent-limit comparator are ignored. For example, a 0.1µF
capacitor gives a fault-integration time of 4.7ms.
S lo p e Co m p e n s a t io n
The MAX5069 us e s a n inte rna l-ra mp g e ne ra tor for
slope compensation. The internal-ramp signal resets at
the beginning of each cycle and slews at the rate pro-
g ra mme d b y the e xte rna l c a p a c itor c onne c te d a t
SCOMP and the resistor at RT. Adjust the MAX5069
slew rate up to 90mV/µs using the following equation:
This is an approximate formula. Some testing may be
required to fine-tune the actual value of the capacitor. To
calculate the recovery time, use the following formula:
t
RT
R
≅
FLTINT
0.595 × C
FLTINT
−6
165 × 10
SR =
(mV/ µs)
where t is the desired recovery time.
RT
R
× C
RT
SCOMP
Choose t = 10 x t . Typical values for t range from
RT
SH
SH
a few hundred microseconds to a few milliseconds.
where R is the external resistor at RT that sets the oscil-
RT
lator frequency and C
is the capacitor at SCOMP.
SCOMP
S o ft -S t a rt
The MAX5069 soft-start feature allows the load voltage
to ramp up in a controlled manner, eliminating output-
volta g e ove rs hoot. Soft-s ta rt b e g ins a fte r UVLO is
deasserted. The voltage applied to the noninverting
node of the amplifier ramps from 0 to 1.23V in 2047
oscillator clock cycles (soft-start timeout period). Unlike
other devices, the MAX5069 reference voltage to the
internal amplifier is soft-started. This method results in
superior control of the output voltage under heavy- and
light-load conditions.
P WM Co m p a ra t o r
The PWM comparator uses the instantaneous current,
the e rror a mp lifie r, a nd the s lop e c omp e ns a tion to
determine when to switch NDRVA and NDRVB off. In
normal operation, the N-channel MOSFETs turns off
when:
I
x R > V – V
- V
PRIMARY
CS
EA
OFFSET SCOMP
where I
MOSFETs, V
amplifier, V
is the current through the N-channel
is the output voltage of the internal
PRIMARY
EA
OFFSET
is the 1.6V internal DC offset, and
In t e rn a l Re g u la t o rs
Two internal linear regulators power the MAX5069 inter-
V
is the ramp function starting at zero and slew-
SCOMP
ing at the programmed slew rate (SR). When using the
MAX5069 in a forward-converter configuration, the fol-
lowing conditions must be met to avoid current-loop
subharmonic oscillations:
nal and external control circuits. V powers the exter-
CC
na l N-c ha nne l MOSFETs a nd is inte rna lly s e t to
approximately 9.5V. The REG5 5V regulator has a 1mA
sourcing capability and may be used to provide power
to external circuitry. Bypass V
and REG5 with 1µF
CC
K ×
×
V
CS
L
N
R
S
OUT
×
= SR
and 0.1µF high quality capacitors, respectively. Use
lowe r va lue c e ra mic s in p a ra lle l to b yp a s s othe r
unwa nte d nois e s ig na ls . Boots tra p p e d op e ra tion
requires startup through a bleed resistor. Do not exces-
sively load the regulators while the MAX5069 is in the
power-up mode. Overloading the outputs may cause
the MAX5069 to fail upon startup.
N
P
where K = 0.75 and N and N are the number of turns
S
P
on the secondary and primary side of the transformer,
respectively. L is the secondary filter inductor. When
optimally compensated, the current loop responds to
input-voltage transients within one cycle.
______________________________________________________________________________________ 15
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Cu rre n t Lim it
The current-sense resistor (R ), connected between
Ap p lic a t io n s In fo rm a t io n
CS
La yo u t Re c o m m e n d a t io n s
Keep all PC board traces carrying switching currents
as short as possible, and minimize current loops.
the source of the MOSFET and ground, sets the current
limit. The CS input has a voltage trip level (V ) of
CS
314mV. Use the following equation to calculate the
value of R
:
CS
For universal AC input design, follow all applicable safe-
ty regulations. Offline power supplies may require UL,
VDE, and other similar agency approvals. Contact these
agencies for the latest layout and component rules.
V
CS
R
=
CS
I
PRI
Typically, there are two sources of noise emission in a
switching power supply: high di/dt loops and high dV/dt
surfaces. For example, traces that carry the drain cur-
rent often form high di/dt loops. Similarly, the heatsink of
the MOSFET presents a dV/dt source, thus minimize the
surface area of the heatsink as much as possible.
where I
is the peak current in the primary that flows
PRI
through the MOSFET at full load.
When the voltage produced by this current (through the
current-sense resistor) exceeds the current-limit com-
p a ra tor thre s hold , the MOSFET d rive rs (NDRVA/
NDRVB) quickly terminate the current on-cycle. In most
cases, a small RC filter is required to filter out the lead-
ing-edge spike on the sense waveform. Set the corner
frequency to a few MHz above the switching frequency.
To a c hie ve be st pe rforma nc e a nd to a void ground
loops, use a solid ground-plane connection.
S e le c t o r Gu id e
PROGRAMMABLE
BOOTSTRAP
UVLO
STARTUP
VOLTAGE (V)
UVLO
HYSTERESIS
PART
OSCILLATOR SYNC
MAX5069A
MAX5069B
MAX5069C
MAX5069D
Yes
Yes
No
23.6
23.6
10.8
10.8
No
Yes
Yes
No
Yes
No
No
No
Yes
16 ______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Typ ic a l Op e ra t in g Circ u it
______________________________________________________________________________________ 17
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
Fu n c t io n a l Dia g ra m
HYST**
BOOTSTRAP
UVLO
21.6V/
9.74V
MAX5069
UVLO/EN
UVLO
1.23V
REFERENCE
1.23V/
1.18V
IN
V
IN
CLAMP
26V
IN
2.8V/
1.6V
60µA
5V
OUT
REGULATOR
REG5
REG_OK
V
CC
R
S
Q
FLTINT
V
CC
CURRENT-LIMIT
COMPARATOR
S
Q
NDRVA
314mV
1.6V
5kΩ
R
Σ*
+
CS
+
70ns
BLANKING
AGND
NDRVB
PGND
PWM
COMPARATOR
OSC
OUT
THERMAL
SHUTDOWN
DEAD
TIME
SLOPE
COMPENSATION
SCOMP
OUT
DIGITAL
SOFT-START
1.23V
ERROR
AMP
FB
*MAX5069A/D
**MAX5069B/C
COMP
SYNC*
RT
DT
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 4266
PROCESS: BiCMOS
18 ______________________________________________________________________________________
Hig h -Fre q u e n c y, Cu rre n t -Mo d e P WM Co n t ro lle r
w it h Ac c u ra t e Os c illa t o r a n d Du a l FET Drive rs
P a c k a g e In fo rm a t io n
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY
EXPOSED PAD
1
21-0108
D
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ____________________ 19
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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