MAX5075AAUA+ [MAXIM]
Half Bridge Based MOSFET Driver, 3A, BICMOS, PDSO8, MO-187, MSOP-8;
| 型号： | MAX5075AAUA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Half Bridge Based MOSFET Driver, 3A, BICMOS, PDSO8, MO-187, MSOP-8 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3662; Rev 1; 5/07
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
General Description
Features
The MAX5075 is a +4.5V to +15V push-pull, current-fed
topology driver subsystem with an integrated oscillator
for use in telecom module power supplies. The device
drives two MOSFETs connected to a center-tapped
transformer primary providing secondary-side, isolated,
negative or positive voltages. This device features a pro-
grammable, accurate, integrated oscillator with a syn-
chronizing clock output that synchronizes an external
PWM regulator. A single external resistor programs the
internal oscillator frequency from 50kHz to 1.5MHz.
♦ Current-Fed, Push-Pull Driver Subsystem
♦ Programmable, Accurate Internal Oscillator
♦ Single +4.5V to +15V Supply Voltage Range
♦ Dual ±3A Gate-Drive Outputs
♦ 1mA Operating Current at 250kHz with No
Capacitive Load
♦ Synchronizing Clock Frequency Generation
Options
The MAX5075 incorporates a dual MOSFET driver with
±±A peak drive currents and 50ꢀ duty cycle. The
MOSFET driver generates complementary signals to
drive external ground-referenced n-channel MOSFETs.
♦ Thermally Enhanced 8-Pin µMAX Package
♦ -40°C to +125°C Operating Temperature Range
The MAX5075 is available with a clock output frequency
to MOSFET driver frequency ratio of 1x, 2x, and 4x. The
MAX5075 is available in a thermally enhanced 8-pin
µMAX® package and is specified over the -40°C to
+125°C operating temperature range.
Ordering Information
PIN-
TOP
PKG
f
/f
CLK NDRV_
PART
PACKAGE MARK CODE
RATIO
MAX5075AAUA 8 µMAX-EP* AAAU U8E-2
MAX5075BAUA 8 µMAX-EP* AAAV U8E-2
MAX5075CAUA 8 µMAX-EP* AAAW U8E-2
*EP = Exposed paddle.
1
2
4
Applications
Current-Fed, High-Efficiency Power-Supply Modules
Power-Supply Building Subsystems
Push-Pull Driver Subsystems
Note: All devices specified for -40°C to +125°C operating
temperature range.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
Pin Configuration appears at end of data sheet.
Typical Operating Circuit
V
IN
V
IN
V
OUT
DRVH
PWM
CONTROLLER
V
CC
V
CC
NDRV2
SYNCIN
CLK
RT
MAX5075
NDRV1
DRVL
4.7kΩ
I.C.
PGND
GND
1nF
GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
ABSOLUTE MAXIMUM RATINGS
V
to DGND, PGND .............................................-0.±V to +18V
Continuous Power Dissipation (T = +70°C)
CC
A
CLK, RT to DGND.....................................................-0.±V to +6V
NDRV1, NDRV2 to PGND...........................-0.±V to (V + 0.±V)
DGND to PGND.....................................................-0.±V to +0.±V
CLK Current......................................................................±20mA
NDRV1, NDRV2 Peak Current (200ns)..................................±5A
NDRV1, NDRV2 Reverse Current (Latchup Current)......±500mA
8-Pin µMAX (derate 10.±mW/°C above +70°C)...........825mW
Operating Temperature Range .........................-40°C to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+±00°C
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +12V, R = 124kΩ, NDRV1 = NDRV2 = open, T = T = -40°C to +125°C, unless otherwise noted. Typical values are measured
CC
RT
A
J
at T = +25°C.) (Note 1)
A
PARAMETER
SUPPLY
SYMBOL
CONDITIONS
MIN
4.5
±
TYP
MAX
UNITS
Input Voltage Supply Range
Switching Supply Current
Undervoltage Lockout
UVLO Hysteresis
OSCILLATOR
V
15.0
±
V
CC
I
f
= 250kHz
rising
CC
1
mA
V
CCSW
OSC
V
V
±.5
±00
4
UVLO
mV
Frequency Range
Accuracy
f
(Note 2)
50
-8
1500
+10
kHz
ꢀ
OSC
f
= 250kHz , 6V ≤ V
≤ 15V (Note ±)
OSC
CC
Oscillator Jitter
±0.6
ꢀ
7V ≤ V
≤ 15V
±.9
5.0
5.0
50
CC
CLK Output High Voltage
I
I
= 1mA
V
CLK
4.5V ≤ V
≤ 7V
±.±5
CC
CLK Output Low Voltage
CLK Output Rise Time
= -1mA
mV
ns
CLK
C
C
= ±0pF
= ±0pF
±5
10
CLK
CLK
CLK Output Fall Time
ns
GATE DRIVERS (NDRV1, NDRV2)
V
0.±
-
CC
Output High Voltage
V
I
I
= I
= I
= 100mA
V
OH
NDRV1
NDRV2
Output Low Voltage
Output Peak Current
V
= -100mA
0.±
V
A
OL
NDRV1
NDRV2
I
Sourcing and sinking
NDRV_ sourcing 100mA
NDRV_ sinking 100mA
±
P
1.8
1.6
400
10
±
Driver Output Impedance
Ω
2.6
Latchup Current Protection
Rise Time
Reverse current at NDRV1/NDRV2
mA
ns
t
C
C
= 2nF
= 2nF
R
LOAD
LOAD
Fall Time
t
10
ns
F
Note 1: The MAX5075 is 100ꢀ tested at T = T = +125°C. All limits over temperature are guaranteed by design.
A
J
Note 2: Use the following formula to calculate the MAX5075 oscillator frequency: f
= 1012/(±2 x R ).
OSC
RT
Note 3: The accuracy of the oscillator’s frequency is lower at frequencies greater than 1MHz.
2
_______________________________________________________________________________________
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
Typical Operating Characteristics
(V = +12V, R = 124kΩ, NDRV_ = open, CLK = open.)
CC
RT
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. C
SUPPLY CURRENT
vs. TEMPERATURE
CLK
7
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
1.20
1.18
1.16
1.14
1.12
1.10
1.08
1.06
1.04
1.02
1.00
R
= 124kΩ
RT
f
= 250kHz
f
= 1.25MHz
OSC
OSC
6
5
4
3
2
1
0
f
= 500kHz
OSC
f
= 250kHz
OSC
f
= 100kHz
OSC
f
= 50kHz
OSC
5
4
6
7
8
9
10 11 12 13 14 15
0
20
40
60
(pF)
80
100
-50 -25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
C
CLK
TEMPERATURE (°C)
CLK FALL TIME
vs. SUPPLY VOLTAGE
CLK RISE TIME
vs. SUPPLY VOLTAGE
CLK RISE TIME
vs. TEMPERATURE
14
12
10
8
50
45
40
35
30
25
20
15
10
5
39.5
39.0
38.5
38.0
37.5
37.0
36.5
C
= 30pF
CLK
C
= 30pF
C
= 30pF
CLK
CLK
6
4
2
0
0
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15
-50 -25
0
25
50
75 100 125
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
CLK FALL TIME
vs. TEMPERATURE
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
12
10
8
256
254
252
250
248
246
244
242
R
= 124kΩ
RT
C
= 30pF
CLK
T
= -40°C
A
T
= +25°C
A
6
4
T
= +125°C
A
2
0
-50 -25
0
25
50
75 100 125
4
5
6
7
8
9
10 11 12 13 14 15
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
3
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
Typical Operating Characteristics (continued)
(V = +12V, R = 124kΩ, NDRV_ = open, CLK = open.)
CC
RT
NDRV FREQUENCY
vs. CLK FREQUENCY
OSCILLATOR FREQUENCY vs. R
RT
MAX5075A WAVEFORM
MAX5075 toc11
10,000
1000
100
800
700
600
500
400
300
200
100
0
R
= 124kΩ
RT
NDRV1
5V/div
NDRV2
5V/div
CLK
5V/div
10
10
100
1000
0
250
500
750 1000 1250 1500
2µs/div
R
(kΩ)
CLK FREQUENCY (kHz)
RT
MAX5075B WAVEFORM
MAX5075C WAVEFORM
MAX5075 toc13
MAX5075 toc12
R
= 124kΩ
R
= 124kΩ
RT
RT
NDRV1
NDRV1
5V/div
5V/div
NDRV2
5V/div
NDRV2
5V/div
CLK
CLK
5V/div
5V/div
2µs/div
4µs/div
4
_______________________________________________________________________________________
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
Pin Description
PIN
NAME
FUNCTION
Synchronizing Clock Output. Clock output with a ±10mA peak current drive that can be used to
synchronize an external PWM regulator. CLK/NDRV1 frequency has a 1x, 2x, or 4x ratio. See the
Synchronizing Clock Output section.
1
CLK
2
±
I.C.
RT
Internal Connection. Connect to ground. Internal function.
Oscillator Timing Resistor Connection. Bypass RT with a series combination of a 4.7kΩ resistor and a
1nF capacitor to DGND. Connect a resistor from RT to DGND to set the internal oscillator.
4
5
DGND
PGND
Digital Ground. Connect DGND to ground plane.
Power Ground. Connect PGND to ground plane.
6
NDRV1
NDRV2
Gate Driver 1. Connect NDRV1 to the gate of the external n-channel FET.
Gate Driver 2. Connect NDRV2 to the gate of the external n-channel FET.
7
8
V
Power-Supply Input. Bypass V
to PGND with 0.1µF||1µF ceramic capacitors.
CC
CC
EP
EP
Exposed Pad. Internally connected to DGND. Connect exposed pad to ground plane.
MAX5075
A (1x)
B (2x)
UVLO 3.5V
V
CC
C (4x)
V
CC
NDRV2
Q
T-FF
Q
Q
5V
LDO
Q
NDRV1
PGND
CLK
Q
Q
OSC
RT
INTERNAL
FUNCTION
I.C.
DGND
Figure 1. MAX5075 Functional Diagram
_______________________________________________________________________________________
5
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
Detailed Description
Table 1. MAX5075 CLK Output Frequency
The MAX5075 is a +4.5V to +15V push-pull, current-fed
topology driver subsystem with an integrated oscillator
for use in 48V module power supplies.
f
to f
SW
RATIO
CLK
PART
f
f
NDRV1
CLK
MAX5075A
MAX5075B
MAX5075C
f
/ 2
f
/ 2
/ 2
/ 4
1
2
4
OSC
OSC
OSC
OSC
The MAX5075 features a programmable, accurate inte-
grated oscillator with a synchronizing clock output that
can be used to synchronize an external PWM stage. A
single external resistor programs the internal oscillator
frequency from 50kHz to 1.5MHz.
f
f
f
f
OSC
OSC
NDRV2
The MAX5075 incorporates a dual MOSFET driver with
±±A peak drive currents and a 50ꢀ duty cycle. The
MOSFET driver generates complementary signals to
drive external ground-referenced n-channel MOSFETs.
NDRV1
CLK
The MAX5075 is available with a clock output frequency
to MOSFET driver frequency ratios of 1x , 2x, and 4x.
OSC
MAX5075A
NDRV2
Internal Oscillator
An external resistor at RT programs the MAX5075
internal oscillator frequency from 50kHz to 1.5MHz. The
MAX5075A/B NDRV1 and NDRV2 switching frequen-
cies are one-half the programmed oscillator frequency
with a nominal 50ꢀ duty cycle. The MAX5075C NDRV1
and NDRV2 switching frequencies are one-fourth the
oscillator frequency.
NDRV1
CLK
OSC
MAX5075B
NDRV2
Use the following formula to calculate the internal oscil-
lator frequency:
NDRV1
CLK
12
10
OSC
f
=
OSC
MAX5075C
±2xR
RT
Figure 2. MAX5075 CLK Timing Diagrams
where f
is the oscillator frequency and R
is a
RT
OSC
resistor connected from RT to DGND in ohms.
Place a series combination of a 4.7kΩ resistor and a
1nF capacitor from RT to DGND for stability and to filter
out noise.
Applications Information
Supply Bypassing
Pay careful attention to bypassing and grounding the
MAX5075. Peak supply and output currents may exceed
±A when driving large MOSFETs. Ground shifts due to
insufficient device grounding may also disturb other cir-
cuits sharing the same ground-return path. Any series
Synchronizing Clock Output
The MAX5075 provides a buffered clock output that can
be used to synchronize the oscillator input of a PWM con-
troller. CLK is powered from an internal 5V regulator and
sources/sinks up to 10mA. The MAX5075 has internal
CLK output frequency to NDRV1 and NDRV2 switching
frequency ratios set to 1x, 2x, or 4x (Table 1).
inductance in the V , NDRV1, NDRV2, and/or GND
CC
paths can cause noise due to the very high di/dt when
switching the MAX5075 with any capacitive load. Place
one or more 0.1µF ceramic capacitors in parallel as close
The MAX5075A has a CLK frequency to NDRV_ frequen-
cy ratio set to 1x. The MAX5075B has a CLK frequency to
NDRV_ frequency ratio set to 2x and the MAX5075C has
a CLK frequency to NDRV_ frequency ratio set to 4x.
There is a typical ±0ns delay from CLK to NDRV_ output.
to the device as possible to bypass V
to PGND. Use a
CC
ground plane to minimize ground-return resistance and
inductance. Place the external MOSFETs as close as
possible to the MAX5075 to further minimize board induc-
tance and AC path impedance.
6
_______________________________________________________________________________________
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
•
Two AC current loops form between the device and
the gate of the driven MOSFETs. The MOSFETs
look like a large capacitance from gate to source
when the gate pulls low. The current loop is from
the MOSFET gate to NDRV1 and NDRV2 of the
MAX5075, to PGND, and to the source of the
MOSFET. When the gate of the MOSFET pulls high,
Power Dissipation
The power dissipation of the MAX5075 is a function of
the sum of the quiescent current and the output current
(either capacitive or resistive load). Maintain the sum of
the currents so the maximum power dissipation limit is
not exceeded. The power dissipation (P
) due to the
DISS
quiescent switching supply current (I ) can be cal-
CCSW
culated as:
the current is from the V
terminal of the decou-
CC
pling capacitor, to V
of the MAX5075, to NDRV1
CC
P
DISS
= V
x I
CC CCSW
and NDRV2, and to the MOSFET gate and source.
Both charging current and discharging current loops
are important. Minimize the physical distance and
the impedance in these AC current paths.
For capacitive loads, use the following equation to esti-
mate the power dissipation:
P
= 2 x C
x V 2 x f
LOAD CC NDRV_
LOAD
•
Keep the device as close to the MOSFET as possible.
where C
is the capacitive load at NDRV1 and
LOAD
NDRV2, V
MAX5075 NDRV_ switching frequency.
is the supply voltage, and f
is the
CC
NDRV_
Pin Configuration
Calculate the total power dissipation (P ) as follows:
T
P = P
+ P
LOAD
T
DISS
TOP VIEW
Layout Recommendations
The MAX5075 sources and sinks large currents that can
create very fast rise and fall edges at the gate of the
switching MOSFETs. The high di/dt can cause unaccept-
able ringing if the trace lengths and impedances are not
well controlled. Use the following PC board layout guide-
lines when designing with the MAX5075:
CLK
I.C.
1
2
3
4
8
7
6
5
V
CC
*EP
MAX5075
NDRV2
NDRV1
PGND
RT
DGND
µMAX
*EXPOSED PADDLE CONNECTED TO DGND.
•
Place one or more 0.1µF decoupling ceramic
capacitors from V to PGND as close to the
CC
device as possible. Connect V
and all ground
CC
pins to large copper areas. Place one bulk capaci-
tor of 10µF on the PC board with a low-impedance
Chip Information
TRANSISTOR COUNT: 1±±5
path to the V
input and PGND of the MAX5075.
CC
PROCESS: BiCMOS
_______________________________________________________________________________________
7
Push-Pull FET Driver with Integrated Oscillator
and Clock Output
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
1
21-0107
C
1
Revision History
Pages changed at Rev 1: 1, 2, 5, 6, 8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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