MAX5079EUD-T [MAXIM]
Buffer/Inverter Based MOSFET Driver, BICMOS, PDSO14, TSSOP-14;
| 型号： | MAX5079EUD-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Buffer/Inverter Based MOSFET Driver, BICMOS, PDSO14, TSSOP-14 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总18页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3584; Rev 0; 2/05
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
General Description
Features
The MAX5079 ORing MOSFET controller replaces
ORing diodes in high-reliability redundant, parallel-con-
nected power supplies. Despite their low forward-volt-
age drop, ORing Schottky diodes cause excessive
power dissipation at high currents. The MAX5079
allows for the use of low-on-resistance n-channel power
MOSFETs to replace the Schottky diodes. This results
in low power dissipation, smaller size, and elimination
of heatsinks in high-power applications.
♦ 2.75V to 13.2V Input ORing Voltage
♦ 1V to 13.2V Input ORing Voltage with 2.75V Aux
Voltage Present
♦ 2A MOSFET Gate Pulldown Current During Fault
Condition
♦ Ultra-Fast 200ns, MOSFET Turn-Off During Fault
Condition
♦ Supply Undervoltage and Bus Overvoltage
The MAX5079 operates from 2.75V to 13.2V and includes
a charge pump to drive the high-side n-channel MOSFET.
Operation down to 1V is possible if an auxiliary voltage of
at least 2.75V is available. When the controller detects a
positive voltage difference between IN and BUS, the
n-channel MOSFET is turned on. The MOSFET is turned
off as soon as the MAX5079 sees a negative potential at
IN with respect to the BUS voltage, and is automatically
turned back on when the positive potential is restored.
Under fault conditions, the ORing MOSFET’s gate is
pulled down with a 1A current, providing an ultra-fast
200ns turn-off. The reverse voltage turn-off threshold is
externally adjustable to avoid unintentional turn-off of the
ORing MOSFET due to glitches at IN or BUS caused by
hot plugging the power supply.
Detection
♦ Power-Good (PGOOD) and Overvoltage (OVP)
Outputs for Fault Detection
♦ Space-Saving 14-Pin TSSOP Package
♦ -40°C to +85°C Operating Temperature Range
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5079EUD
-40°C to +85°C
14 TSSOP
Typical Operating Circuit
Additional features include an OVP flag to facilitate
shutdown of a failed power supply due to an overvolt-
SUB 75N 03-04
BUS
COMMON
V
BUS
1V TO 13.2V
N1
V
OUT1
age condition, and a PGOOD signal that indicates if V
IN
is in
POWER SUPPLY 1
(PS1)
is either below the undervoltage lockout or V
BUS
V
IN
IN
GATE
U1
BUS
an overvoltage condition. The MAX5079 operates over
the -40°C to +85°C temperature range and is available
in a space-saving 14-pin TSSOP package.
>2.75V
AUXIN
UVLO
PGOOD
OVI
OVP
MAX5079
STH
C+
Applications
C- FTH
GND
C
STH
R
STH
Paralleled DC-DC Converter Modules
N+1 Redundant Power Systems
Servers
R
FTH
C
EXT
SUB 75N 03-04
Base-Station Line Cards
RAID
1V TO 13.2V
V
BUS
N2
V
OUT2
POWER SUPPLY 2
(PS2)
V
IN
Networking Line Cards
IN
GATE
U2
BUS
C
BUS
>2.75V
PGOOD
AUXIN
UVLO
STH
OVI
OVP
MAX5079
FTH
GND
C+
C-
C
STH
R
STH
R
FTH
C
EXT
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
ABSOLUTE MAXIMUM RATINGS
GATE to GND ..............................................-0.3V to (V + 8.5V)
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
IN
All Other Pins to GND.............................................-0.3V to +15V
Continuous Current Into Any Pin ...................................... 50mA
Continuous Power Dissipation (T = +70°C)
A
14-Pin TSSOP (derate 9.1mW/°C above +70°C) ......727.3mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
((V = 2.75V to 13.2V and V
= 0V) or (V = 1V and V
= 2.75V to 13.2V), R
= open, R
= 0, V
= 1V, V
= 0V,
IN
AUXIN
IN
AUXIN
STH
FTH
UVLO
OVI
T = -40°C to +85°C, unless otherwise noted. Typical values are at V = 12V and T = +25°C. See the Typical Operating Circuit.) (Note 1)
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
2.75
1.0
0
13.20
13.2
13.2
V
V
V
IN Input Voltage Range
AUXIN Input Voltage Range
V
IN
V
V
≥ 2.75V
AUXIN
AUXIN
V
AUXIN
(V
AUXIN
- V ) High Threshold
IN
V
AUXIN_
(When GATE Connects Directly
to AUXIN) (Note 2)
rising, I
= 10µA
4.3
4.9
40
5.4
V
GATE
THRESHOLD
(V
AUXIN
- V ) Hysteresis (When
IN
V
AUXIN_
GATE Connects Directly To
AUXIN)
mV
HYSTERESIS
IN Supply Current
I
V
V
= 1V, V > V
IN
4
mA
µA
IN
UVLO
BUS
AUXIN Leakage Current
I
I
= 0V
20
LEAK_AUX
AUXIN
V
V
= 1V, V
= 13.2V, V
≥
UVLO
, V
AUXIN
AUXIN
AUXIN Supply Current
BUS Leakage Current
BUS Supply Current
I
4
1
3
mA
mA
mA
AUXIN
≥ V
BUS
IN AUXIN
V
= 13.2V, V
= 0V
LEAK_BUS
IN
BUS
V
V
= 13.2V, V
> V , V
>
BUS
BUS
IN BUS
I
BUS
AUXIN
IN TO AUXIN SWITCHOVER
Switchover High Threshold
Switchover Low Threshold
V
(V - V
), V
falling
rising
-60
+25
-25
+200
+50
mV
mV
AUXIN_HIGH
IN
AUXIN
AUXIN
V
(V - V
), V
-200
AUXIN_LOW
IN
AUXIN
AUXIN
IN UNDERVOLTAGE LOCKOUT
V
rising, V
= 0V or V
AUXIN AUXIN
IN
Internal UVLO High Threshold
Internal UVLO Hysteresis
V
V
2.0
2.25
30
2.5
V
INTUVLO_HIGH
INTUVLO_HYST
rising, V = 0V
IN
V
falling, V
= 0V or V
AUXIN AUXIN
IN
mV
falling, V = 0V
IN
External UVLO Threshold
External UVLO Hysteresis
External UVLO Input Bias
V
V
falling
UVLO
0.568
0.6
60
0.632
500
V
UVLO
V
mV
nA
UVLO_HYST
I
UVLO
2
_______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
ELECTRICAL CHARACTERISTICS (continued)
((V = 2.75V to 13.2V and V
= 0V) or (V = 1V and V
= 2.75V to 13.2V), R
= open, R
= 0, V
= 1V, V
= 0V,
IN
AUXIN
IN
AUXIN
STH
FTH
UVLO
OVI
T = -40°C to +85°C, unless otherwise noted. Typical values are at V = 12V and T = +25°C. See the Typical Operating Circuit.) (Note 1)
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ORing MOSFET CONTROL
C
= 10nF, C
= 100nF,
GATE
EXT
ORing MOSFET Turn-On Time
t
10
25
20
µs
ON
MOSFET gate threshold = 2V
ORing MOSFET Forward Voltage
Threshold (Fast Comparator)
V
(V - V ) rising
5
12.5
mV
DTH
IN
BUS
R
R
R
= 0
-12
-63
-24
-31
FTH
FTH
FTH
ORing MOSFET Reverse Voltage
Turn-Off Threshold (Fast
V
= 12kΩ
= 27kΩ, V ≥ 3.5V
-104
-204
-150
-300
mV
FTH
FBL
Comparator (V - V
))
BUS
IN
-126
IN
ORing MOSFET Reverse Voltage
Blanking Time (Fast Comparator)
V
V
= 2.8V, R
- V = 0.3V
IN
= 0,
FTH
BUS
BUS
t
50
1
ns
V
Slow-Comparator Output Voltage
Threshold on STH
V
0.95
-0.1
1.05
O_STH
R
STH
R
STH
R
STH
open
-12
-25
-24.0
ORing MOSFET Reverse Voltage
Turn-Off Threshold (Slow
V
mV
mS
ms
= 500kΩ
= 64kΩ
STH
Comparator (V - V
))
BUS
IN
-100
(V - V
) to I
BUS STH
IN
Transconductance (Slow
Comparator)
G
V
= 0V
0.17
M_STH
STH
STH floating
0.5
0.9
5
1.5
5.0
ORing MOSFET Reverse Voltage
Blanking Time (Slow
Comparator)
t
C
C
= 0.047µF
SBL
STH
STH
= 0.22µF
14
ORing MOSFET DRIVER
Gate-Charge Current
I
C
= 100nF
0.7
0.9
2
mA
A
GATE
EXT
V
V
V
V
V
≥ V , V = 5V, V = 5V
BUS
2
GATE
GATE
GATE
IN IN
Gate Discharge Current (Note 3)
I
GATE.DIS_MIN
≥ V , V = 2.75V, V
= 3.5V
1.3
3.2
600
200
IN IN
BUS
≥ V , V = 12V, V
= 13.2V
BUS
IN IN
= 3.5V, C
= 0.1µF
BUS
BUS
GATE
GATE
Gate Fall Time
t
ns
ns
FGATE
= 3.5V, C
= 0.01µF
Gate Discharge Current Delay
Time (Time from V Falling from
IN
V
= 3.5V, V
= 0V,
FTH
BUS
t
70
200
DIS_GATE
C
= 0.1nF
GATE
3.7V to 3V to V
= V )
IN
GATE
Gate to IN Resistance
Gate to IN Clamp Voltage
R
(V
- V ) = 100mV
900
11
Ω
GATE_IN
GATE
IN
V
I
= 10mA, V ≥ V
8.5
V
GATE_IN_CLAMP GATE
IN
BUS
2.7V < V < 13.2V
3.8
6.5
4.5
IN
Gate-Drive Voltage (Measured
with Respect to V
(V
GATE
- V
IN
)
V
V
V
V
= 13.2V
= 2.75V
7
5
7.6
5.5
IN
IN
)
IN
V
Switchover Threshold to
IN
V
7.4
8
8.5
IN_SOTH+
Higher GATE Voltage (Note 4)
_______________________________________________________________________________________
3
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
ELECTRICAL CHARACTERISTICS (continued)
((V = 2.75V to 13.2V and V
= 0V) or (V = 1V and V
= 2.75V to 13.2V), R
= open, R
= 0, V
= 1V, V
= 0V,
IN
AUXIN
IN
AUXIN
STH
FTH
UVLO
OVI
T = -40°C to +85°C, unless otherwise noted. Typical values are at V = 12V and T = +25°C. See the Typical Operating Circuit.) (Note 1)
A
IN
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
Switchover Hysteresis
IN
V
40
mV
IN_SOHYS
(Note 4)
External
70
Charge-Pump Frequency
f
kHz
CP
Internal, V < 5V, V
IN
< 5V
1100
AUXIN
PROTECTION
OVI Input Bias Current
OVI Threshold
I
500
0.632
0.4
1
nA
V
OVI
V
OVI rising
0.568
0.6
0.2
OVI_TH
OVP Output Low Voltage
OVP Leakage Current
PGOOD Leakage Current
PGOOD Output Low Voltage
V
V
V
V
= 1V, I = 10mA
SINK
V
OVP_LOW
OVP_LEAK
OVI
I
= 2.75V, V
= 13.2V
µA
µA
V
IN
PGOOD
OVP
I
= 13.2V
= 2mA
1
PG_LEAK
V
I
0.2
0.4
PG_LOW
SINK
Note 1: All devices are production tested at +25°C. Limits over temperature are guaranteed by design.
Note 2: Threshold is reached when charge pump turns off.
Note 3: Gate discharge current is guaranteed through the testing of gate fall time.
Note 4: V switchover threshold is V at which the gate-drive voltage (V
- V ) goes from 5V to 7V, V rising and (V ≥ V
).
BUS
IN
IN
GATE
IN
IN
IN
Typical Operating Characteristics
(T = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
A
AUXIN SUPPLY CURRENT
SLOW-COMPARATOR REVERSE VOLTAGE
GATE-CHARGE CURRENT vs. V
IN
vs. TEMPERATURE (V = V
= 1V)
THRESHOLD (V
vs. R
)
IN
BUS
STH
STH
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
1
0
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
T
A
= -40°C, T = +25°C,
A
T
= +85°C, T = +125°C
A
A
V
= 10V
AUXIN
V
= 5V
AUXIN
T
= +25°C
A
T
= -40°C
A
T
= +85°C
A
V
= 2.7V
AUXIN
T
= +125°C
A
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
100
(kΩ)
1000
V
(V)
IN
TEMPERATURE (°C)
R
STH
4
_______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
A
SLOW-COMPARATOR BLANKING TIME
vs. C (R = 180kΩ)
FAST-COMPARATOR REVERSE VOLTAGE
THRESHOLD (V vs. R
t
FAST-COMPARATOR RESPONSE TIME
STH
STH STH
)
FTH
FTH
100
90
80
70
60
50
40
30
20
10
0
80
72
64
56
48
40
32
24
16
8
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V
= 1V, V
= 5V
AUXIN
75mV OVERDRIVE
IN
V
= 5V, V
= 0V
AUXIN
IN
T
= +85°C
A
T
= +125°C
A
V
= 12V,
IN
V
= 0V
AUXIN
V
= 2.75V,
= 12V
IN
T
= -40°C
V
A
AUXIN
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
(µF)
0
20
40
60
R
80 100 120 140
TEMPERATURE (°C)
C
STH
(kΩ)
FTH
CHARGE-PUMP FREQUENCY
vs. INPUT VOLTAGE
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
GATE-CHARGE CURRENT vs. C
EXT
MAX5079 toc09
80
78
76
74
72
70
68
66
64
62
60
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
MOSFET REVERSE
CURRENT
5A/div
V
= 12V
IN
T
= +125°C
A
T
= +85°C
A
BUS
5V/div
T
= +25°C
A
T
= -40°C
A
GATE
10V/div
IN
5V/div
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
400ns/div
= 5V,
1
10
(nF)
100
V
V
R
= 5V, V
BUS
IN
V
(V)
IN
C
EXT
= 0V, C = 0,
AUXIN
STH
= OPEN, R = 0,
STH
FTH
UVLO = IN
_______________________________________________________________________________________
5
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
A
FAULT CURRENT WAVEFORM
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
(IN SHORTED TO PGND)
MAX5079 toc10
MAX5079 toc11
MOSFET REVERSE
CURRENT
MOSFET REVERSE
CURRENT
10A/div
10A/div
BUS
2V/div
BUS
10V/div
GATE
GATE
5V/div
20V/div
IN
IN
2V/div
10V/div
1µs/div
400ns/div
= 12V,
V
V
R
= 2.75V, V
AUXIN
STH
= 2.75V,
V
V
R
= 12V, V
BUS
AUXIN
STH
IN
BUS
STH
IN
= 0V, C = 0µF,
= OPEN, R = 0,
= 0V, C = 0µF,
STH
= OPEN, R = 0,
FTH
FTH
UVLO = IN
UVLO = IN
FAULT CURRENT WAVEFORM
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
(IN SHORTED TO PGND)
MAX5079 toc13
MAX5079 toc12
MOSFET REVERSE
CURRENT
10A/div
MOSFET REVERSE
CURRENT
10A/div
BUS
5V/div
BUS
1V/div
GATE
5V/div
GATE
10V/div
IN
1V/div
IN
5V/div
1µs/div
1µs/div
V
V
R
= 5V, V
AUXIN
STH
= 5V,
BUS
STH
V
V
R
= 1V, V
AUXIN
STH
= 1V,
STH
FTH
IN
IN
BUS
= 5V, C = 0µF,
= OPEN, R = 0,
= 5V, C = 0µF,
= OPEN, R = 0,
FTH
UVLO = IN
UVLO = IN
6
_______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted. See the Typical Operating Circuit.)
A
FAULT CURRENT WAVEFORM
(IN SHORTED TO PGND)
POWER-UP WAVEFORM
MAX5079 toc14
MAX5079 toc15
MOSFET REVERSE
CURRENT
10A/div
IN
2V/div
BUS
10V/div
BUS
2V/div
GATE
20V/div
GATE
10V/div
IN
10V/div
CXN
10V/div
1µs/div
= 12V,
40µs/div
= 4.9V,
V
V
R
= 12V, V
BUS
AUXIN
STH
V
I
= 5.2V, V
IN
IN
BUS
= 5V, C = 0,
= 5A
STH
BUS
= OPEN, R = 0,
FTH
UVLO = IN
POWER-UP WAVEFORM
POWER-UP WAVEFORM
MAX5079 toc16
MAX5079 toc17
IN
IN
5V/div
1V/div
BUS
BUS
5V/div
500mV/div
GATE
10V/div
GATE
5V/div
CXN
10V/div
CXN
10V/div
20µs/div
= 11.9V,
20µs/div
V
= 12.2V, V
= 5A
V
V
= 1.2V, V
= 1V,
BUS
IN
BUS
IN
BUS
I
= 5V, I
= 5A
BUS
AUXIN
_______________________________________________________________________________________
7
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Pin Description
PIN
1
NAME
CXN
FUNCTION
Negative Terminal of External Flying Charge-Pump Capacitor
Positive Terminal of External Flying Charge-Pump Capacitor
Open-Drain Active-Low Output. OVP sinks up to 10mA when V
2
CXP
≥ 0.6V and V ≥ V . OVP can be
BUS
OVI
IN
3
4
OVP
used to drive an optodiode. Cycle power or pull UVLO low and then high to reset OVP.
PGOOD
Open-Drain Active-Low Output. PGOOD pulls low when V ≤ 0.6V or V ≥ 0.6V.
UVLO
OVI
ORing MOSFET Slow-Comparator Reverse Voltage Threshold and Blanking Time Setting Input. Connect
a resistor from STH to GND to set the threshold. Connect a capacitor from STH to GND to set the
blanking time. Leave STH floating to set the internal threshold (-12mV) and internal blanking time
(0.9ms).
5
STH
Fast-Comparator Reverse Threshold Setting. Connect a resistor from FTH to GND to set the fast-
comparator reverse voltage threshold from -24mV to -400mV.
6
7
8
FTH
OVI
Overvoltage Comparator Input. Connect OVI to BUS through a resistive divider.
Undervoltage Lockout Comparator Input. Connect UVLO to IN through a resistive divider. The MAX5079
UVLO
remains off until V
rises above 0.66V. When V
rises above 0.664V, V
is raised to V .
GATE IN
UVLO
UVLO
Power Ground. Ground discharge path of the 2A GATE pulldown. Connect to external power ground
plane.
9
PGND
GATE
BUS
GND
IN
10
11
12
13
Gate-Driver Output for n-Channel ORing MOSFET
Bus Voltage-Sense Input. Connect BUS to the drain of the ORing MOSFET to sense the polarity of the
Bus Current. The MAX5079 receives its power from BUS when V and V
IN
are not present.
AUXIN
Signal Ground. Connect to the low-level signal or analog ground.
Source Connection for ORing MOSFET and Supply Input for the MAX5079. Connect IN directly to the
power-supply voltage of 2.75V to 13.2V or 1V to 13.2V with V ≥ 2.75V.
AUXIN
Auxiliary Power-Supply Input. AUXIN supplies power to the IC when 1V ≤ V ≤ 2.75V. Connect AUXIN to
IN
14
AUXIN
2.75V or higher if V is less than 2.75V.
IN
8
_______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Block Diagram
CXP
CXN
GATE
IN
BUS
V
V
SUPPLY
SUPPLY
AUXIN TO GATE
DIRECT CONNECTION
G
M
BUS
STH
FTH
IN/AUXIN/BUS
SWITCHOVER
V
SUPPLY
V
SUPPLY
HYSTERESIS
CONTROL
20µA
CHARGE
PUMP
AUXIN
IN/AUXIN CHARGE-PUMP
SWITCHOVER
0.9ms
DELAY
V
SUPPLY
IN/AUXIN SUPPLY
SWITCHOVER
IN
TOP LOGIC
GATE TARGET SELECTOR
COMPARATOR
CPOFF
V
0.6V
SUPPLY
REFERENCE
UVLO PGOOD OVI
PULLDOWN
REG
INTERNAL
UVLO
2A
PULLDOWN
GND
N
MAX5079
DRIVER
PGOOD
LOGIC
UVLO
OVI
OV
LOGIC
OVP
PGOOD
PGND
Figure 1. Block Diagram
_______________________________________________________________________________________
9
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
V ), by sourcing 2mA into N1’s gate capacitance.
IN
Detailed Description
This results in a less than 10µs turn-on time for the
FDB7045L used in the MAX5079 evaluation kit. The
fast turn-on is needed to assure that N1 is ON
The MAX5079 ORing MOSFET controller drives an
external n-channel MOSFET and replaces ORing
diodes in high-reliability redundant power-management
systems or multiple paralleled power supplies. The
device has an internal charge pump to drive the high-
side n-channel ORing MOSFET. Additional features
include an adjustable undervoltage lockout threshold
(UVLO), output overvoltage detector (OVI/OVP), input
power-good detector (PGOOD), and two programma-
ble reverse voltage detectors to detect both fast and
slow rises in the reverse voltage across the ORing
MOSFET. The input power-supply range is from 2.75V
to 13.2V or down to 1V when an auxiliary supply of at
least 2.75V is available.
before the rising V
reaches its steady-state
OUT1
value. If the MOSFET is not turned on before V
OUT1
reaches its steady state, V
may overshoot due
BUS
to the shorting of the 0.7V (forward drop) of N1’s
body diode. A higher V (U1) can more quickly
IN
charge the charge-pump capacitor to 5V (or 7V),
while a lower V (U1) will take longer. Typically the
IN
MOSFET turns on at V
= 2.5V. Ensure that the
GS
soft-start time of the power supply is large enough
(> 5ms) to avoid V racing ahead and causing
OUT1
V
to overshoot. Care must be taken to avoid the
BUS
overloading of V
by either limiting the source
OUT1
current (using the current-sharing circuit) or delay
the loading of the BUS until all three power supplies
are up and running.
Operational Description
This section describes a detailed startup sequence and
behavior of the MAX5079 under different conditions of
V
and V . The MAX5079 powers up whenever V
IN IN
b. V
turns on and begins increasing the voltage
BUS
OUT2
at IN (U2). V
is equal to or greater than 2.75V and V
the UVLO threshold of 0.66V. Operation with V down
to 1V is possible as long as V
2.75V.
exceeds
(U2) crosses the UVLO thresh-
UVLO
UVLO
old, the MAX5079 (U2) charge pump turns on and
U2 monitors the V to V voltage. When this
IN
≥ 0.6V and V
≥
UVLO
AUXIN
OUT2
BUS
voltage difference becomes positive, GATE (U2)
begins sourcing 2mA into N2’s gate capacitance.
During turn-on, the reverse voltage turn-off circuit
When V
crosses the UVLO threshold, V
rises
UVLO
GATE
to V and the charge pump turns on. The charge
IN
is momentarily disabled. If V
OUT1
is lower than
OUT2
pump delivers 2mA to charge the gate capacitance of
the external MOSFET connected to GATE. The constant
gate-charge current prevents large inrush currents from
the input supply. During turn-on, the MAX5079 will
ignore the reverse voltage at IN with respect to BUS.
This is necessary to avoid the unintentional turn-off of
the ORing MOSFET as the momentary inrush current
V
, the external load-sharing controller circuit
of PS2 will try to increase V
to source current
OUT2
from V
. Assume V
’s rise time is slow
OUT2
OUT2
enough not to cause any overshoot before N2
turns on and starts sharing the current.
c. V
turns on and U3 follows the same sequence
OUT3
as U2. Eventually V
causes V to dip.
IN
, V
, and V
reach
OUT1 OUT2
OUT3
to equilibrium and sharing equal currents.
Figure 2 shows the MAX5079 in an ORing configuration
with three parallel power supplies (PS1, PS2, and PS3)
and three MAX5079s (U1, U2, and U3) provided by out-
2) PS1 and PS2 are on and sharing the load when
PS3 is hot-inserted. PS3 will take the same
course as discussed in 1b above.
puts V
, V
, and V
. The following events
OUT3
OUT1
OUT2
must be carefully considered to ensure proper function-
ality of the MAX5079 ICs.
a. If V
is higher than V
, the BUS voltage will
OUT3
BUS
increase to the new level determined by V
.
OUT3
1) V
is zero with a discharged capacitor (C
).
The external load-sharing controller circuit of PS1
and PS2 will increase V
current sharing.
BUS
BUS
All three power supplies are turned ON simulta-
and V
to force
OUT2
OUT1
neously. V
V
comes up before V
and
OUT2
OUT1
.
OUT3
b. If V
is lower than V
, the load-sharing cir-
to force the sharing
OUT3
OUT3
BUS
OUT3
a. When V
turns on, the bus capacitors (C
)
cuit of PS3 will increase V
of current. This causes V
OUT1
BUS
begin charging from V
through N1’s body
to increases above
OUT1
diode. When V
(U1) rises above the UVLO
V
BUS
. When this voltage difference becomes posi-
UVLO
threshold, the MAX5079 (U1) charge pump turns
on, and U1 monitors the positive potential from
tive, GATE (U3) begins sourcing 2mA into N3’s
gate capacitance. Again, the reverse voltage turn-
off circuit is disabled momentarily, as discussed
before. The load-sharing circuit of PS3’s controller
V
to V
. When V
≥ V
the charge
BUS
OUT1
BUS
OUT1
pump brings GATE (U1) to 5.5V above V (U1) (or
IN
7.5V above V depending on the magnitude of
IN
will adjust V
so as to share the load current.
OUT3
10 ______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
c. During the hot insertion, a voltage spike can occur
at N1 and N2 and cause the (V to V ) or
lockout and keep all ORing MOSFETs off. The average
current sourced by PS1, PS2, or PS3 must be low
enough so as not to exceed the MOSFETs power dissi-
OUT1
BUS
(V
to V
) voltage to go negative. If the
OUT2
BUS
reverse voltage is below the fast-comparator
reverse voltage threshold (V ) but above the
pation (P = V x I
).
D
F
SHORT
FTH
a. Use additional n-channel MOSFETs in series with
N1, N2, and N3 in the reverse direction to isolate
the power supplies from a shorted bus (Figure 3).
programmed slow-comparator reverse voltage
threshold (V ), the spike is ignored for the pro-
STH
grammed blanking time (t
). If the spike is
STH
When power is turned on with a shorted bus, V
IN_
longer than 50ns (the fast-comparator internal
blanking time, t ) and larger than V , then U1
(U1, U2, U3) increases and V
rises above
UVLO
FBL
FTH
the UVLO threshold. The MAX5079’s GATE out-
puts start charging the back-to-back ORing
MOSFET gates. The short-circuit condition at BUS
and U2 will turn off N1 and N2 quickly. If the mag-
nitude of the voltage spike is above V but less
STH
than V
, and longer than the slow-comparator
FTH
collapses V (U1), V (U2), and V (U3) send-
IN
IN
IN
blanking time (t
), U1 and U2 will turn off their
STH
ing the MAX5079s into undervoltage lockout. This
turns off the MAX5079s entirely, including dis-
charging of the charge-pump storage capacitors.
The IN voltages come back up again crossing
UVLO (UVLO has 60mV hysteresis). A new cycle
starts and the time required to charge the charge-
pump capacitor and the turn-on time of the device
serves as a dead time. However, the dead time
may not be enough to reduce the dissipation in
the MOSFETs to an acceptable level. We advise
in keeping the short-circuit current low and pro-
viding hiccup current-limit protection to the power
supplies (PS1, PS2, and PS3).
respective ORing MOSFETs (N1 and N2) by dis-
charging their GATE pins to PGND. The external
load-sharing circuit of PS1 and PS2 will force
V
, V
above V
and N1, N2 will turn
BUS
OUT1
OUT2
back on through the 2mA current sourcing from
the GATE pins of U1 and U2. To avoid this situa-
tion the user can set the slow-comparator thresh-
old and blanking time depending on the
magnitude and duration of the voltage spikes.
d. PS3 fails to start. V
(U3) threshold is not
UVLO
crossed and U3 keeps N3 off.
e. PS3 goes into an overvoltage condition (no feed-
back). This causes V
to go into an overvoltage
b. Any other overload condition that would sustain the
IN voltage above UVLO, will keep the MOSFETs ON
continuously. Ensure the MOSFETs’ current
rating is higher than the maximum short-circuit
source current of the power supplies (PS1, PS2,
and PS3) to avoid damage to the ORing MOSFETs.
BUS
condition increasing the loading on PS3 (provided
PS3 is able to supply all the required BUS cur-
rent). The current-sharing circuit will force the out-
puts of PS1 and PS2 to increase and eventually
saturate at their current-sharing voltage range.
Eventually only PS3 will have a positive voltage at
IN (U3) with respect to BUS. PS1 and PS2 will
4) PS1, PS2, and PS3 are present and PS1 is short-
ed to GND.
have a negative voltage at V
and V
with
OUT2
OUT1
V
V
drops below V
. The negative potential from
BUS
OUT1
respect to BUS. All overvoltage inputs OVI (U1),
OVI (U2), and OVI (U3) sense the overvoltage, but
only OVP (U3) is asserted and latched low. GATE
(U3) is pulled to PGND and remains low as long
(U1) to V
increases above the fast-comparator
IN
BUS
threshold and lasts longer than the 50ns blanking time.
The MAX5079 (U1) takes its power from the voltage at
BUS (U1). Connect BUS close to C
, away from N1
BUS
as V
≥ 0.6V. When V
drops below 0.6V,
OVI
OVI
so that U1 can receive power from BUS for a few
microseconds until N1 isolates BUS from IN. N1 is dis-
charged with 2A pulldown current, turning off N1 and
isolating PS1 from the BUS. The load-sharing circuit of
PS2 and PS3 will increase PS2 and PS3’s load current
until the total bus current requirement is satisfied.
OVP remains low. However, U3 tries to turn on N3
unless V is actively kept below the undervolt-
OUT3
age lockout. Use OVP (U3) to either drive the
cathode of the optocoupler to shutdown PS3 from
the primary side or use OVP (U3) to fire an SCR
connected between V
and PGND.
OUT3
For V (U1) < 2.75V, V
(U1) must come from an
AUXIN
IN
3) PS1, PS2, PS3 are turned on with a shorted BUS.
independent source or remain on for some time (a few
Body diodes of N1, N2, and N3 conduct and short the
outputs of PS1, PS2, and PS3 to PGND. The power
supplies go into current limit (either in foldback or in
hiccup mode). The MAX5079s remain in undervoltage
microseconds) after V (U1) has failed. This minimum
IN
on-time is needed to discharge the gate of the ORing
MOSFET and isolate PS1 from the BUS.
______________________________________________________________________________________ 11
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
5) PS1, PS2, PS3 are present and PS1 goes open.
pump is divided into two stages, a voltage doubler run-
ning at 70kHz using an external charge-pump capaci-
PS1’s output capacitors discharge and V drops
OUT1
tor (C
), and a voltage tripler running at 1MHz using
EXT
below V
. The MAX5079 (U1) senses a negative
BUS
an internal capacitor.
potential from V
to V
. Depending upon how
BUS
OUT1
fast PS1’s output capacitor discharges, N1 is turned off
due to the crossing of the fast- or slow-comparator
reverse voltage threshold. N1’s gate is discharged with
a 2A sink current into GATE (U1), turning off N1 and
isolating PS1 from the BUS. The load-sharing circuit of
PS2 and PS3 will increase PS2 and PS3’s load current
until the total BUS current requirement is satisfied.
Connect an external capacitor (C
) between C+ and
EXT
C-. C
is charged from the higher of V or V
.
EXT
IN
AUXIN
(V
When the rising V becomes greater then V
IN
BUS UVLO
> 0.66V), C
is discharged through GATE into the
EXT
external MOSFET’s gate capacitance. The charge-
pump output is controlled by an internal regulator. The
charge-pump output at GATE sources typically 2mA.
This provides enough current drive to turn on a typical
6) PS1, PS2, PS3 are present and providing BUS
current. PS1 loses its feedback signal and goes
into an overvoltage condition.
ORing MOSFET in less than 10µs. When (V
- V )
IN
GATE
reaches the target value (depending on V ) the charge
IN
pump is switched off (see the Electrical Characteristics
V
increases and PS1 is loaded heavily. The current
BUS
table). Choose C
equal to 10 times the ORing
EXT
share circuit forces V
and V
higher and they
OUT3
OUT2
MOSFET gate capacitance. Too low of a capacitance
will delay the turn-on of the ORing MOSFET, while too
high of a capacitance can cause excessive ripple at
will eventually saturate at their current-sharing voltage
range. Now only PS1 has a positive voltage at IN (U1)
with respect to BUS. All OVI inputs will sense the over-
voltage, but only OVP (U1) will be asserted and latched
low. GATE (U1) is pulled to PGND and remains low as
V . Bypass IN to GND with a 1µF ceramic capacitor to
IN
avoid ripple at IN caused by the charge-pump switch-
ing. A clamp is placed internally between GATE and IN
long as V
≥ 0.6V. When V
drops below 0.6V, OVP
OVI
OVI
to prevent (V
- V ) from exceeding 11V. When V
IN IN
GATE
remains low, however, U1 tries to turn on N1 unless
is actively kept below the undervoltage lockout.
is less than 5V, the charge pump (tripler) will increase
to 3x’s V to further reduce the R of the
V
OUT1
V
GATE
IN
DSON
Use OVP (U1) to either drive the cathode of an opto-
coupler to shutdown PS1 from the primary, or fire an
SCR connected between IN (U1) and PGND.
ORing MOSFET. The internal charge-pump booster
(voltage tripler) section is operational only when V and
IN
V
are low and is turned off when V exceeds 5V.
AUXIN
IN
When an additional supply is connected to AUXIN and
(V - V ) > 5V, both charge pumps are completely
Internal and External
Undervoltage Lockout
AUXIN
IN
disabled. In this case, the charging of the ORing gate
comes entirely from V . In this case, the charge-
The internal undervoltage lockout monitors V and
AUXIN
IN
V
and keeps the MAX5079 off until either voltage
AUXIN
pump flying capacitor can be eliminated and C+, C-
can be left floating.
reaches 2.75V. Once powered and V and/or V
IN
AUXIN
increase above 2.75V, the external UVLO is monitored.
The external undervoltage lockout feature monitors the
UVLO input and keeps the MAX5079 off (GATE shorted
GATE Drive and Gate Pulldown
The MAX5079’s charge pump provides bias to charge
the ORing MOSFET gate above IN (the MOSFET’s
source). GATE source current and the turn-on speed
to PGND) until V
is greater than 0.66V. Connect a
UVLO
resistive divider from IN to UVLO to GND or from
AUXIN to UVLO to GND to set the external undervolt-
age lockout threshold. We advise setting the external
UVLO ≥ 2.75V when AUXIN is not present.
depends upon the value of C
(connected between
EXT
C+ and C-). Typically GATE can source up to 2mA with
= 0.1µF. This enables V to rise to over 2V
C
EXT
GATE
above V in less than 10µs for an ORing MOSFET gate
Charge Pump
IN
capacitance of up to 10nF. With V < 5V, 12V MOSFETs
The MAX5079 has an internal charge pump that pumps
IN
DSON
can be used for better R characteristics. The
the gate-drive voltage (V
) high enough to fully
GATE
MAX5079 automatically selects the gate-drive voltage for
enhance the n-channel ORing MOSFET. The charge
12 ______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
V
= 5V or V = 12V. For V ≤ 8V, the gate drive is 5V
Slow Comparator (STH)
The MAX5079 includes a slow comparator to provide
glitch immunity during the hot insertion or removal of
paralleled power supplies. During the hot insertion,
BUS can see voltage spikes. These spikes can be
interpreted as a reverse voltage across the ORing
MOSFET. The amplitude of the spikes is proportional to
the load step seen by the parallel power supply while
the duration of the spikes depends on the loop
response of the load share and PWM controller.
IN
IN
IN
above V and for V > 8V, the gate drive is 7V above
IN
IN
V . Lower gate drive means faster turn-off during faults,
IN
while higher gatedrive means lower R
.
DSON
A fast and slow comparator monitor the voltage from IN
to BUS. When this voltage crosses the negative fast- or
slow-comparator threshold voltage for the blanking time
duration, GATE is pulled low by an internal 2A current
sink. Both comparators have an adjustable threshold
voltage. GATE is pulled low if any of the following con-
ditions are met.
The slow comparator has a programmable reverse volt-
age threshold (V
) as well as a programmable blank-
STH
1) V
2) V
3) V
< 0.6V.
UVLO
ing time (t
). An internal transconductance amplifier
STH
< 2.25V and V < 2.25V.
AUXIN
IN
converts the IN to BUS differential voltage to a current
and applies it to a parallel combination of resistor and
≥ 0.6V.
OVI
capacitor (R
and C
) from STH to GND. The
STH
STH
4) V ≤ (V
- V
) or V ≤ (V
- V
) and
STH
IN
BUS
FTH
IN
BUS
reverse threshold voltage (V
) for the slow compara-
STH
(V
- V ) ≥ 1.8V.
GATE
IN
tor is adjusted through R
tion to calculate the R
. Use the following equa-
STH
When the above conditions are not true and V
V
≤
IN
for a required V
.
STH
STH
, GATE is shorted to IN. To insure that the external
BUS
MOSFET is quickly turned off, given the above condi-
tions, the GATE pulldown circuitry is powered by either
1V
R
=
STH
V
−12mV x G
(
)
STH
M_STH
V
, V
, or V as long as any one is greater
BUS
IN
AUXIN
then 2.75V.
where G
= 0.17mS.
M_STH
Fast Comparator (FTH)
The internal 500kΩ resistance from the output of the
transconductance to GND can change the actual V
The fast comparator has a 50ns blanking time to avoid
unintentional turn-off of the ORing MOSFET during fast
transients. Additionally, the fast-comparator reverse
STH
if R
is above 50kΩ. In this case, see the Typical
STH
Operating Circuit to select R
the blanking time can be adjusted by C
time is:
. Once R
is chosen,
STH
STH
voltage threshold (V
) is programmable to suit the
FTH
. The delay
STH
need of an individual application. Higher V
thresh-
FTH
old allows for a larger glitch at BUS during a fault, but
improves the noise immunity. Lower V reduces
FTH
V
STH
+ V
t
=R
×C
× −ln 1−
+ t
SBL
glitches at BUS during a fault, however, with lower V
FTH
DELAY
STH
STH
V
STH
DD
spikes at BUS or glitches at IN can be read as faults,
unintentionally turning off the ORing MOSFET. Program
where t
= 0.9ms and is the default blanking time
SBL
V
V
by connecting a resistor from FTH to GND. Adjust
to optimize the system performance using the fol-
FTH
FTH
generated by an internal digital delay. Leaving STH
floating results in a 12mV threshold voltage and a 0.9ms
lowing equation:
blanking time. V
(overdrive) is the difference between
OD
actual reverse voltage (V
- V ) and V
threshold.
BUS
IN
STH
V
− 24mV
6.67µA
FTH
R
=
FTH
Overvoltage Protection Latch (OVI/OVP)
OVI is the negative input to the overvoltage compara-
tor. The positive input of this comparator is connected
to the internal 0.6V reference and an open-drain output
is provided at OVP. The overvoltage sensing for over-
voltage protection is done at either IN or BUS. OVP
V
can be chosen from 24mV to 400mV. Connect
FTH to GND to choose the default 24mV threshold.
FTH
______________________________________________________________________________________ 13
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
latches low and the internal GATE pulldown circuitry is
activated and pulls GATE low only when both of the
conditions are satisfied:
Layout Guidelines
1) Place a 1µF ceramic input bypass capacitor physi-
cally close to IN and PGND. Connect IN as close as
possible to the source of the ORing MOSFET.
1) V
≥ 0.6V.
OVI
2) Sense the V
close to the bulk capacitor, away from
BUS
2) V ≥ V
.
IN
BUS
the drain of the ORing MOSFET. When IN is shorted to
ground during a fault, BUS is also pulled low through
OVP can sink 10mA maximum. Cycle power or pull
UVLO low and then high again to reset the OVP latch.
GATE is pulled to PGND and remains low as long as
the ORing MOSFET. In the absence of V
, the
AUXIN
MAX5079 loses both power inputs V and V
. This
BUS
IN
V
≥ 0.6V. When V
drops below 0.6V, OVP remains
OVI
OVI
can cause a delayed pulldown of the gate. Sensing
the BUS away from the ORing MOSFET drain, close to
the BUS bulk capacitor provides power to the
MAX5079 for a few microseconds, long enough to pull
down the ORing MOSFET gate and isolate BUS from a
shorted IN.
low. However, the MAX5079 tries to turn on the ORing
MOSFET unless V is actively kept below the undervolt-
IN
age lockout. Use OVP to drive the cathode of an opto-
coupler to shut down the respective power supply from
the primary side (see the Typical Application Circuit of
Figure 2) or fire an SCR connected from IN to PGND.
3) Place the charge-pump capacitor (C
) and the
EXT
Power-Good Comparator (PGOOD)
slow-comparator blanking time adjustment capacitor
(C ) as close as possible to the MAX5079.
PGOOD output pulls low when V
OVI
of 2mA.
falls below 0.6V
UVLO
STH
or V
goes above 0.6V. PGOOD can sink a maximum
4) Run a thick trace from the gate of the ORing MOSFET
to GATE.
14 ______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
BUS
COMMON
1V TO 13.2V
1V TO 13.2V
1V TO 13.2V
N1
V
BUS
V
OUT1
V
BUS
POWER SUPPLY 1
(PS1)
V
IN
TO PRIMARY-SIDE
SHUTDOWN
IN
GATE
U1
BUS
>2.75V
AUXIN
UVLO
OVP
STH
OVI
MAX5079
PGOOD
C+
C- FTH
GND
R
STH
C
STH
R
FTH
C
EXT
N2
V
BUS
V
OUT2
V
BUS
POWER SUPPLY 2
(PS2)
V
IN
IN
GATE
U2
BUS
TO PRIMARY-SIDE
SHUTDOWN
C
BUS
>2.75V
AUXIN
UVLO
OVP
STH
OVI
MAX5079
PGOOD
C+
C- FTH
GND
R
STH
C
STH
R
FTH
C
EXT
N3
V
BUS
V
OUT3
V
BUS
POWER SUPPLY 3
(PS3)
V
IN
IN
GATE
U3
BUS
TO PRIMARY-SIDE
SHUTDOWN
>2.75V
AUXIN
UVLO
OVP
STH
OVI
MAX5079
PGOOD
C+
C- FTH
GND
R
STH
C
STH
R
FTH
C
EXT
Figure 2. Typical Application Circuit
______________________________________________________________________________________ 15
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
BUS
COMMON
1V TO 13.2V
V
BUS
V
OUT1
V
BUS
POWER SUPPLY 1
(PS1)
V
IN
TO PRIMARY-SIDE
SHUTDOWN
IN
GATE
U1
BUS
>2.75V
AUXIN
UVLO
OVP
STH
OVI
MAX5079
PGOOD
C+
C- FTH
GND
R
STH
C
STH
R
FTH
C
EXT
1V TO 13.2V
V
BUS
V
OUT2
V
BUS
POWER SUPPLY 2
(PS2)
V
IN
IN
GATE
U2
BUS
TO PRIMARY-SIDE
SHUTDOWN
C
BUS
>2.75V
AUXIN
UVLO
OVP
STH
OVI
MAX5079
PGOOD
C+
C- FTH
GND
R
STH
C
STH
R
FTH
C
EXT
Figure 3. Parallel Supplies with Back-to-Back MOSFET
16 ______________________________________________________________________________________
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Pin Configuration
Chip Information
TRANSISTOR COUNT: 2,911
PROCESS: BiCMOS
TOP VIEW
CXN
CXP
1
2
3
4
5
6
7
14 AUXIN
13 IN
OVP
12 GND
11 BUS
10 GATE
PGOOD
STH
MAX5079
FTH
9
8
PGND
UVLO
OVI
TSSOP
______________________________________________________________________________________ 17
ORing MOSFET Controller with
Ultra-Fast 200ns Turn-Off
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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