MAX5083 [MAXIM]
1.5A, 40V, MAXPower Step-Down DC-DC Converters; 1.5A ， 40V ，牛魔王降压型DC -DC转换器
| 型号： | MAX5083 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1.5A, 40V, MAXPower Step-Down DC-DC Converters |
| 文件： | 总18页 (文件大小：404K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3657; Rev 0; 5/05
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
General Description
Features
The MAX5082/MAX5083 are 250kHz PWM step-down
DC-DC converters with an on-chip, 0.3Ω high-side
switch. The input voltage range is 4.5V to 40V for the
MAX5082 and 7.5V to 40V for the MAX5083. The output
is adjustable from 1.23V to 32V and can deliver up to
1.5A of load current.
♦ 4.5V to 40V (MAX5082) or 7.5V to 40V (MAX5083)
Input Voltage Range
♦ 1.5A Output Current
♦ V
Range From 1.23V to 32V
OUT
♦ Internal High-Side Switch
Both devices utilize a voltage-mode control scheme for
good noise immunity in the high-voltage switching envi-
ronment and offer external compensation allowing for
maximum flexibility with a wide selection of inductor val-
ues and capacitor types. The switching frequency is
internally fixed at 250kHz and can be synchronized to
an external clock signal through the SYNC input. Light
load efficiency is improved by automatically switching
to a pulse-skip mode.
♦ Fixed 250kHz Internal Oscillator
♦ Automatic Switchover to Pulse-Skip Mode at
Light Loads
♦ External Frequency Synchronization
♦ Thermal Shutdown and Short-Circuit Protection
♦ Operates Over the -40°C to +125°C Temperature
All devices include programmable undervoltage lock-
out and soft-start. Protection features include cycle-by-
cycle current limit, hiccup-mode output short-circuit
protection, and thermal shutdown. Both devices are
available in a space-saving, high-power (2.7W), 16-pin
TQFN package and are rated for operation over the
-40°C to +125°C temperature range.
Range
♦ Space-Saving (5mm x 5mm) High-Power 16-Pin
TQFN Package
Ordering Information
PART
TEMP RANGE
-40°C to +125°C
-40°C to +125°C
PIN-PACKAGE
16 TQFN-EP*
16 TQFN-EP*
Applications
MAX5082ATE
MAX5083ATE
FireWire® Power Supplies
Distributed Power
Automotive
Industrial
*EP = Exposed pad.
Pin Configurations appear at end of data sheet.
FireWire is a registered trademark of Apple Computer, Inc.
Typical Operating Circuits
V
IN
C
D1
F
4.5V TO 40V
C
BST
IN
DVREG
C-
C+
BST
L1
R1
LX
FB
V
OUT
C6
REG
C1
R3
R4
C5
D2
MAX5082
R6
ON/OFF
C8
R5
SYNC SGND PGND
SS
COMP
R2
C7
C
C2
SS
PGND
PGND
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
ABSOLUTE MAXIMUM RATINGS
T = +125°C.........................................................................3A
IN, ON/OFF to SGND..............................................-0.3V to +45V
J
T = +150°C.........................................................................2A
LX to SGND .................................................-0.3V to (V + 0.3V)
BST to SGND................................................-0.3V to (V + 12V)
IN
BST to LX................................................................-0.3V to +12V
PGND to SGND .....................................................-0.3V to +0.3V
REG, DVREG, SYNC to SGND ...............................-0.3V to +12V
J
IN
Continuous Power Dissipation* (T = +70°C)
A
16-Pin TQFN (derate 33.3mW/°C above +70°C) ...2666.7mW
16-Pin TQFN (θ )........................................................30°C/W
JA
16-Pin TQFN (θ ).......................................................1.7°C/W
JC
Operating Temperature Range .........................-40oC to +125°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
FB, COMP, SS to SGND...........................-0.3V to (V
+ 0.3V)
REG
C+ to PGND (MAX5082 only)................(V
- 0.3V) to +12V
DVREG
C- to PGND (MAX5082 only)................-0.3V to (V
+ 0.3V)
DVREG
Continuous current through internal power MOSFET (pins 11/12
connected together and pins 13/14 connected together)
*As per JEDEC 51 Standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = V
= 12V, V
= V
, V
= PGND = SGND, T = T = -40°C to +125°C, unless otherwise noted. Typical values
IN
ON/OFF
REG
DVREG SYNC A J
are at T = + 25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
4.5
7.5
3.9
6.8
TYP
MAX
40
UNITS
MAX5082
MAX5083
Input Voltage Range
V
V
IN
40
V
V
rising, MAX5082
4.2
7.3
IN
IN
Undervoltage Lockout Threshold
UVLO
V
V
rising, MAX5083
MAX5082
MAX5083
0.4
0.7
10.5
9.5
84
Undervoltage Lockout Hysteresis UVLO
Switching Supply Current (PWM
HYST
V
V
V
= 0V, MAX5082
= 0V, MAX5083
FB
FB
IN
I
mA
SW
Operation)
= 12V, V
= 3.3V, I
= 1.5A
= 1.5A
OUT
OUT
Efficiency
%
V
= 4.5V, V
= 3.3V, I
OUT OUT
IN
88
(MAX5082)
MAX5082
MAX5083
1.4
1.3
2.5
2.3
300
No-Load Supply Current
(PFM Operation)
mA
µA
Shutdown Current
I
V
V
V
= 0V, V = 40V
IN
200
SHDN
ON/OFF
ON/OFF
ON/OFF
ON/OFF CONTROL
Input Voltage Threshold
Input Voltage Hysteresis
Input Bias Current
V
rising
1.20
-250
1.23
0.12
1.25
V
V
ON/OFF
= 0 to 40V
+250
nA
ERROR AMPLIFIER/SOFT-START
Soft-Start Current
I
8
15
24
µA
V
SS
Reference Voltage (Soft-Start)
FB Regulation Voltage
FB Input Range
V
V
1.215
1.215
0
1.228
1.228
1.240
1.240
1.5
SS
FB
I
I
I
= -500µA to +500µA
= -500µA to +500µA
= -500µA to +500µA
V
COMP
COMP
COMP
V
FB Input Current
-250
0.25
+250
4.50
nA
V
COMP Voltage Range
Open-Loop Gain
80
dB
MHz
mV
Unity-Gain Bandwidth
FB Offset Voltage
1.8
-5
+5
2
_______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
ELECTRICAL CHARACTERISTICS (continued)
(V = V
= 12V, V
= V
, V
= PGND = SGND, T = T = -40°C to +125°C, unless otherwise noted. Typical values
IN
ON/OFF
REG
DVREG SYNC A J
are at T = + 25°C.) (Note 1)
A
PARAMETER
OSCILLATOR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
kHz
%
Frequency
f
V
V
V
V
= 0V
225
87
250
275
SW
SYNC
SYNC
SYNC
SYNC
= 0V, V = 4.5V, MAX5082
IN
Maximum Duty Cycle
D
= 0V, V = 7.5V, MAX5083
87
MAX
IN
= 0V, V ≤ 40V
87
IN
SYNC High-Level Voltage
SYNC Low-Level Voltage
SYNC Frequency Range
PWM Modulator Gain
Ramp Level Shift (Valley)
POWER SWITCH
2.2
V
V
0.8
f
150
350
kHz
V/V
V
SYNC
f
= 150kHz to 350kHz
10
SYNC
0.3
Switch On-Resistance
Switch Gate Charge
V
V
V
V
- V = 6V
0.3
6
0.6
Ω
BST
BST
LX
- V = 6V
nC
µA
µA
LX
Switch Leakage Current
BST Leakage Current
CHARGE PUMP
= 40V, V = V = 0V
BST
10
10
IN
LX
= V = V = 40V
BST
LX
IN
C- Output Voltage Low
MAX5082 only, sinking 10mA
0.1
0.1
V
V
MAX5082 only, relative to DVREG,
sourcing 10mA
C- Output Voltage High
DVREG to C+ On-Resistance
MAX5082 only, sourcing 10mA
Sinking 10mA
10
12
Ω
Ω
LX to PGND On-Resistance
CURRENT-LIMIT COMPARATOR
Pulse-Skip Threshold
I
100
1.9
200
2.7
300
3.5
mA
A
PFM
Cycle-by-Cycle Current Limit
I
ILIM
Number of Consecutive ILIM
Events to Hiccup
4
Clock
periods
Hiccup Timeout
512
INTERNAL VOLTAGE REGULATOR
Output Voltage
MAX5082
MAX5083
4.75
7.6
5
8
5.25
8.4
1
V
V
REG
V
V
= 5.5V to 40V, MAX5082
= 9.0V to 40V, MAX5083
IN
IN
Line Regulation
Load Regulation
Dropout Voltage
mV/V
1
I
= 0 to 20mA
0.25
0.5
0.5
V
V
REG
V
V
= 4.5V, I
= 7.5V, I
= 20mA, MAX5082
= 20mA, MAX5083
IN
IN
REG
REG
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Temperature rising
+160
20
°C
°C
Note 1: 100% production tested at T = +25°C and T = +125°C. Limits at -40°C are guaranteed by design.
A
A
_______________________________________________________________________________________
3
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Typical Operating Characteristics
(V = 12V, see Figure 5 (MAX5082) and Figure 6 (MAX5083), T = +25°C, unless otherwise noted.)
IN
A
UNDERVOLTAGE LOCKOUT HYSTERESIS
vs. TEMPERATURE (MAX5082)
UNDERVOLTAGE LOCKOUT HYSTERESIS
vs. TEMPERATURE (MAX5083)
ON/OFF THRESHOLD HYSTERESIS
vs. TEMPERATURE
1.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40 -15
10
35
60
85 110 135
-40 -15
10
35
60
85 110 135
-40 -15
10
35
60
85 110 135
TEMPERATURE (°C )
TEMPERATURE (°C )
TEMPERATURE (°C )
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5083)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5082)
SHUTDOWN SUPPLY CURRENT
vs. INPUT VOLTAGE (MAX5082)
300
275
250
225
200
175
150
125
100
75
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
250
225
200
175
150
125
100
75
T
= +135°C
A
T
= +85°C
A
T
= +135°C
A
T
= +85°C
A
T
= +135°C
A
T
= +85°C
A
T
= -40°C
A
T
= +25°C
A
T
= -40°C
A
T
= +25°C
A
T
= +25°C
A
T
A
= -40°C
50
50
V
= 0V
V
= 0V
ON/OFF
5
25
ON/OFF
5
25
0
0
0
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
MAXIMUM DUTY CYCLE
vs. INPUT VOLTAGE (MAX5082)
OPERATING FREQUENCY
vs. TEMPERATURE
100
98
96
94
92
90
88
86
84
82
80
260
258
256
254
V
= 4.5V
IN
252
250
248
246
244
242
240
V
= 40V
IN
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
-40 -15
10
35
60
85 110 135
TEMPERATURE (°C)
4
_______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Typical Operating Characteristics (continued)
(V = 12V, see Figure 5 (MAX5082) and Figure 6 (MAX5083), T = +25°C, unless otherwise noted.)
IN
A
MAXIMUM DUTY CYCLE
vs. INPUT VOLTAGE (MAX5083)
OUTPUT CURRENT LIMIT
vs. INPUT VOLTAGE
OPEN-LOOP GAIN/PHASE vs. FREQUENCY
MAX5082 toc10
100
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
MAX5082
= +25°C
T
= -40°C
A
100
80
175
150
125
98
96
94
92
90
88
86
84
82
80
T
A
GAIN
60
T
= +135°C
A
40
20
0
T
= +85°C
A
100
PHASE
75
50
OUTPUT IS
PULSED WITH 3% DUTY CYCLE
-20
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
0
0.001 0.01 0.1
1
10 100 1000 10,000
0
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
FREQUENCY (kHz)
TURN-ON/OFF WAVEFORM
TURN-ON/OFF WAVEFORM
MAX5082/3 toc11b
MAX5082/3 toc11a
I
= 100mA
I
= 1A
LOAD
LOAD
V
ON/OFF
2V/div
V
ON/OFF
2V/div
V
V
OUT
OUT
2V/div
2V/div
2ms/div
2ms/div
OUTPUT VOLTAGE vs. TEMPERATURE
EFFICIENCY vs. LOAD CURRENT
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
100
90
80
70
60
50
40
30
20
0
MAX5082
V
= 4.5V,
= 3.3V
IN
V
OUT
I
= 0A
LOAD
V
V
= 7.5V,
IN
= 3.3V
OUT
V
V
= 12V,
= 3.3V
IN
OUT
I
= 1A
LOAD
V
V
= 24V,
= 3.3V
IN
OUT
V
V
= 40V,
= 3.3V
IN
MAX5082
OUT
-40 -15
10
35
60
85 110 135
0.001
0.01
0.1
1
10
TEMPERATURE (°C)
LOAD CURRENT (A)
_______________________________________________________________________________________
5
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Typical Operating Characteristics (continued)
(V = 12V, see Figure 5 (MAX5082) and Figure 6 (MAX5083), T = +25°C, unless otherwise noted.)
IN
A
EFFICIENCY vs. LOAD CURRENT
LOAD-TRANSIENT RESPONSE
MAX5082/3 toc14
100
90
80
70
60
50
40
30
20
0
V
= 12V, I = 0.5A TO 1.5A
OUT
IN
MAX5082
V
OUT
AC-COUPLED
200m/V/div
V
V
= 7.5V,
IN
= 5V
OUT
V
V
= 12V,
= 5V
IN
OUT
I
LOAD
1A/div
V
V
= 24V,
= 5V
IN
OUT
V
V
= 40V,
OUT
0
IN
= 5V
MAX5083
0.001
0.01
0.1
LOAD CURRENT (A)
1
10
200µs/div
LX VOLTAGE AND INDUCTOR CURRENT
MAX5082/3 toc15
I
= 40mA
LOAD
V
LX
5V/div
INDUCTOR
CURRENT
200mA/div
2µs/div
LX VOLTAGE AND INDUCTOR CURRENT
LX VOLTAGE AND INDUCTOR CURRENT
MAX5082/3 toc17
MAX5082/3 toc16
V
V
LX
LX
5V/div
5V/div
INDUCTOR CURRENT
500mA/div
INDUCTOR CURRENT
100mA/div
0
0
I = 1A
LOAD
I
= 140mA
LOAD
2µs/div
2µs/div
6
_______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Pin Description
PIN
NAME
FUNCTION
MAX5082 MAX5083
1
1
COMP
Error Amplifier Output. Connect COMP to the compensation feedback network.
Feedback Regulation Point. Connect to the center tap of a resistive divider from converter
output to SGND to set the output voltage. The FB voltage regulates to the voltage present at SS
(1.23V).
2
2
FB
ON/OFF and External UVLO Control. The ON/OFF rising threshold is set to approximately 1.23V.
Connect to the center tap of a resistive divider from IN to SGND to set the UVLO (rising)
threshold. Pull ON/OFF to SGND to shut down the device. ON/OFF can be used for power-
supply sequencing. Connect to IN for always-on operation.
3
3
ON/OFF
Soft-Start and Reference Output. Connect a capacitor from SS to SGND to set the soft-start
time. See the Applications Information section to calculate the value of the SS capacitor.
4
5
6
4
5
6
SS
Oscillator Synchronization Input. SYNC can be driven by an external 150kHz to 350kHz clock to
synchronize the MAX5082/MAX5083’s switching frequency. Connect SYNC to SGND when not
used.
SYNC
DVREG
Gate Drive Supply for High-Side MOSFET Driver. Connect externally to REG for MAX5082.
Connect to REG and the anode of the boost diode for MAX5083.
7
8
—
—
C+
C-
Charge-Pump Flying Capacitor Positive Connection
Charge-Pump Flying Capacitor Negative Connection
—
7, 8
N.C.
No Connection. Not internally connected. Can be left floating or connected to SGND.
Power Ground Connection. Connect the input filter capacitor’s negative terminal, the anode of
the freewheeling diode, and the output filter capacitor’s return to PGND. Connect externally to
SGND at a single point near the input capacitor’s return terminal.
9
9
PGND
High-Side Gate Driver Supply. Connect BST to the cathode of the boost diode and to the
positive terminal of the boost capacitor.
10
11, 12
13, 14
15
10
11, 12
13, 14
15
BST
LX
Source Connection of Internal High-Side Switch. Connect the inductor and rectifier diode’s
anode to LX.
Supply Input Connection. Connect to an external voltage source from 4.5V to 40V (MAX5082) or
a 7.5V to 40V (MAX5083).
IN
Internal Regulator Output. 5V output for the MAX5082 and 8V output for the MAX5083. Bypass
to SGND with at least a 1µF ceramic capacitor.
REG
Signal Ground Connection. Solder the exposed pad to a large SGND plane. Connect SGND
and PGND together at one point near the input bypass capacitor return terminal.
16
EP
16
EP
SGND
—
Exposed Pad. Connect exposed pad to SGND.
of L and C filter components. Both devices offer an
Detailed Description
automatic switchover to pulse-skipping (PFM) mode,
providing low quiescent current and high efficiency at
light loads. Under no load, a PFM mode operation
reduces the current consumption to only 1.4mA. In
shutdown, the supply current falls to 200µA. Additional
features include an externally programmable undervolt-
age lockout through the ON/OFF pin, a programmable
soft-start, cycle-by-cycle current limit, hiccup mode
output short-circuit protection, and thermal shutdown.
The MAX5082/MAX5083 are voltage-mode buck con-
verters with internal 0.3Ω power MOSFET switches. The
MAX5082 has a wide input voltage range of 4.5V to
40V. The MAX5083’s input voltage range is 7.5V to 40V.
The internal low R
switch allows for up to 1.5A of
DS_ON
output current. The 250kHz fixed switching frequency,
external compensation, and voltage feed-forward sim-
plify loop compensation design and allow for a variety
_______________________________________________________________________________________
7
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
C-
C+
DVREG
ON/OFF
IN
DVREG
>1.23V ON
<1.11V OFF
LDO
EN
LEVEL
SHIFT
REG
PCLK
SGND
1.23V
1.23V
MAX5082
ILIM
CLK
OVERL
OVERLOAD
MANAGEMENT
THERMAL
SHDN
REF
V
REF
I
SS
EN
REGOK
ILIM
1.23V
SS
FB
REF_ILIM
REF_PFM
SSA
E/A
IN
V
REF
HIGH-SIDE
CURRENT
SENSE
PFM
COMP
BST
LX
LOGIC
IN
RAMP
CPWM
DVREG
EN
OSC
SYNC
PCLK
SCLK
0.3V
CHARGE-PUMP
MANAGEMENT
CLK
PGND
Figure 1. MAX5082 Simplified Block Diagram
Internal Linear Regulator (REG)
REG is the output terminal of a 5V (MAX5082), or 8V
(MAX5083) LDO which is powered from IN and pro-
vides power to the IC. Connect REG externally to
DVREG to provide power for the high-side MOSFET
gate driver. Bypass REG to SGND with a ceramic
capacitor of at least 1µF. Place the capacitor physically
close to the MAX5082/MAX5083 to provide good
bypassing. During normal operation, REG is intended
for powering up only the internal circuitry and should
not be used to supply power to external loads.
grammed at the ON/OFF pin. The external UVLO over-
rides the internal UVLO when the external UVLO is
higher than the internal UVLO. During startup, before
any operation begins, the input voltage and the voltage
at ON/OFF must exceed their respective UVLOs. The
external UVLO has a rising threshold of 1.23V with
0.12V of hysteresis. Program the external UVLO by
connecting a resistive divider from IN to ON/OFF to
SGND. Connect ON/OFF to IN directly to disable the
external UVLO.
Driving ON/OFF to ground places the MAX5082/
MAX5083 in shutdown. When in shutdown, the internal
power MOSFET turns off, all internal circuitry shuts
down and the quiescent supply current reduces to
200µA. Connect an RC network from ON/OFF to SGND
to set a turn-on delay that can be used to sequence the
output voltages of multiple devices.
Internal UVLO/External UVLO
The MAX5082/MAX5083 provides two undervoltage
lockouts (UVLOs). An internal UVLO looks at the input
voltage (V ) and is fixed at 4.1V (MAX5082) or 7.1V
IN
(MAX5083). An external UVLO is sensed and pro-
8
_______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
ON/OFF
IN
>1.23V ON
<1.11V OFF
SGND
LDO
EN
REG
MAX5083
1.23V
1.23V
ILIM
CLK
OVERL
OVERLOAD
MANAGEMENT
THERMAL
SHDN
REF
V
REF
I
SS
EN
REGOK
ILIM
PFM
1.23V
SS
FB
REF_ILIM
SSA
E/A
IN
V
REF
HIGH-SIDE
CURRENT
SENSE
REF_PFM
COMP
BST
LOGIC
IN
RAMP
CPWM
LX
EN
OSC
DVREG
SYNC
PCLK
SCLK
0.3V
BOOTSTRAP
CONTROL
CLK
ILIM
PGND
Figure 2. MAX5083 Simplified Block Diagram
Soft-Start and Reference (SS)
SS is the 1.23V reference bypass connection for the
MAX5082/MAX5083 and also controls the soft-start
Internal Charge Pump (MAX5082)
The MAX5082 features an internal charge pump to
enhance the turn-on of the internal MOSFET, allowing
for operation with input voltages down to 4.5V. Connect
period. At startup, after V is applied and the internal
IN
and external UVLO thresholds are reached, the device
enters soft-start. During soft-start, 15µA is sourced into
a flying capacitor (C ) between C+ and C-, a boost
F
diode from C+ to BST, as well as a bootstrap capacitor
the capacitor (C ) connected from SS to SGND caus-
(C
) between BST and LX to provide the gate-drive
SS
BST
ing the reference voltage to ramp up slowly. When V
voltage for the high-side n-channel DMOS switch.
During the on-time, the flying capacitor is charged to
SS
reaches 1.23V the output becomes fully active. Set the
soft-start time (t ) using the following equation:
V
. During the off-time, the positive terminal of the
SS
DVREG
flying capacitor (C+) is pumped to two times V
DVREG
to provide twice the
and charge is dumped onto C
BST
1.23V × C
15µA
SS
t
=
regulator voltage across the high-side DMOS driver.
Use a ceramic capacitor of at least 0.1µF for C and
SS
BST
C located as close to the device as possible.
F
where t is in seconds and C is in Farads.
SS
SS
For applications that do not require a 4.5V minimum
input, use the MAX5083. In this device, the charge
_______________________________________________________________________________________
9
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
pump is omitted and the input voltage range is from
7.5V to 40V. In this situation, the boost diode and the
boost capacitor are still required (see the MAX5083
Typical Operating Circuit).
During normal operation, the current is monitored at the
drain of the internal power MOSFET. When the current
limit is exceeded, the internal power MOSFET turns off
until the next on-cycle and a counter increments. If the
counter counts four consecutive current-limit events,
the device discharges the soft-start capacitor and
shuts down for 512 clock periods before restarting with
a soft-start sequence. Each time the power MOSFET
turns on and the device does not exceed the current
limit, the counter is reset.
Gate Drive Supply (DVREG)
DVREG is the supply input for the internal high-side
MOSFET driver. The power for DVREG is derived from
the output of the internal regulator (REG). Connect
DVREG to REG externally. We recommend the use of
an RC (1Ω and 0.47µF) filter from REG to DVREG to fil-
ter the noise generated by the switching of the charge
pump. In the MAX5082, the high-side drive supply is
generated using the internal charge pump along with
the bootstrap diode and capacitor. In the MAX5083, the
high-side MOSFET driver supply is generated using
only the bootstrap diode and capacitor.
Thermal-Overload Protection
The MAX5082/MAX5083 feature an integrated thermal-
overload protection. Thermal-overload protection limits
the total power dissipation in the device and protects it
in the event of an extended thermal fault condition.
When the die temperature exceeds +160°C, an internal
thermal sensor shuts down the part, turning off the
power MOSFET and allowing the IC to cool. After the
temperature falls by 20°C, the part will restart with a
soft-start sequence.
Error Amplifier
The output of the internal error amplifier (COMP) is avail-
able for frequency compensation (see the Compensation
Design section). The inverting input is FB, the noninvert-
ing input SS, and the output COMP. The error amplifier
has an 80dB open-loop gain and a 1.8MHz GBW prod-
uct. See the Typical Operating Character-istics for the
Gain and Phase vs. Frequency graph.
Applications Information
Setting the Undervoltage Lockout
When the voltage at ON/OFF rises above 1.23V, the
MAX5082/MAX5083 turns on. Connect a resistive
divider from IN to ON/OFF to SGND to set the UVLO
threshold (see Figure 5). First select the ON/OFF to the
SGND resistor (R2) then calculate the resistor from IN
to ON/OFF (R1) using the following equation:
Oscillator/Synchronization Input (SYNC)
With SYNC tied to SGND, the MAX5082/MAX5083 use
their internal oscillator and switch at a fixed frequency
of 250kHz. For external synchronization, drive SYNC
with an external clock from 150kHz to 350kHz. When
driven with an external clock, the device synchronizes
to the rising edge of SYNC.
⎡
⎢
⎤
V
IN
ON/OFF
R1= R2 ×
− 1
⎥
V
⎢
⎣
⎥
⎦
PWM Comparator/Voltage Feed-Forward
An internal 250kHz ramp generator is compared
against the output of the error amplifier to generate the
PWM signal. The maximum amplitude of the ramp
where V is the input voltage at which the converter
ON/OFF
than 600kΩ.
If the external UVLO divider is not used, connect
ON/OFF to IN directly. In this case, an internal under-
voltage lockout feature monitors the supply voltage at
IN and allows operation to start when IN rises above
4.1V (MAX5082) and 7.1V (MAX5083).
IN
turns on, V
= 1.23V and R2 is chosen to be less
(V
) automatically adjusts to compensate for input
RAMP
voltage and oscillator frequency changes. This causes
the V /V to be a constant 10V/V across the input
IN RAMP
voltage range of 4.5V to 40V (MAX5082) or 7.5V to 40V
(MAX5083) and the SYNC frequency range of 150kHz
to 350kHz.
Setting the Output Voltage
Connect a resistive divider from OUT to FB to SGND to
set the output voltage (see Figure 5). First calculate the
resistor from OUT to FB using the guidelines in the
Compensation Design section. Once R3 is known, cal-
culate R4 using the following equation:
Output Short-Circuit Protection
(Hiccup Mode)
The MAX5082/MAX5083 protects against an output short
circuit by utilizing hiccup-mode protection. In hiccup
mode, a series of sequential cycle-by-cycle current-limit
events will cause the part to shut down and restart with
a soft-start sequence. This allows the device to operate
with a continuous output short circuit.
10 ______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
the input capacitor). The total voltage ripple is the sum
R3
R4 =
of ∆V and ∆V
. Calculate the input capacitance and
Q
ESR
⎡
⎢
⎣
⎤
V
V
OUT
ESR required for a specified ripple using the following
equations:
− 1
⎥
⎦
FB
where V = 1.23V.
FB
∆V
ESR
ESR =
Inductor Selection
∆I
⎛
⎞
-
P P
2
I
+
⎜
⎝
⎟
⎠
OUT_MAX
Three key inductor parameters must be specified for
operation with the MAX5082/MAX5083: inductance
value (L), peak inductor current (I
saturation current (I
), and inductor
PEAK
−
× D(1 D)
I
). The minimum required induc-
SAT
OUT_MAX
C
=
=
IN
tance is a function of operating frequency, input-to-out-
put voltage differential, and the peak-to-peak inductor
∆V × f
Q
SW
current (∆I ). Higher ∆I
allows for a lower inductor
requires a higher inductor
where
P-P
P-P
P-P
value while a lower ∆I
value. A lower inductor value minimizes size and cost
and improves large-signal and transient response, but
reduces efficiency due to higher peak currents and
higher peak-to-peak output voltage ripple for the same
output capacitor. On the other hand, higher inductance
increases efficiency by reducing the ripple current.
Resistive losses due to extra wire turns can exceed the
benefit gained from lower ripple current levels especial-
ly when the inductance is increased without also allow-
ing for larger inductor dimensions. A good compromise
(V − V
IN OUT
) × V
OUT
∆I
and
-
P P
V
× f
× L
IN
SW
V
OUT
D =
V
IN
I
is the maximum output current, D is the duty
OUT_MAX
cycle, and f
is the switching frequency.
SW
The MAX5082/MAX5083 includes internal and external
UVLO hysteresis and soft-start to avoid possible unin-
tentional chattering during turn-on. However, use a bulk
capacitor if the input source impedance is high. Use
enough input capacitance at lower input voltages to
avoid possible undershoot below the undervoltage
lockout threshold during transient loading.
is to choose ∆I
equal to 40% of the full load current.
P-P
Calculate the inductor using the following equation:
V
(V − V )
OUT IN OUT
L =
V
× f
× ∆I
-
SW P P
IN
V
and V
are typical values so that efficiency is opti-
IN
OUT
mum for typical conditions. The switching frequency
Output Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the output capacitance and its ESR. The output
(f ) is fixed at 250kHz or can vary between 150kHz and
SW
350kHz when synchronized to an external clock (see the
Oscillator/Synchronization Input (SYNC) section). The
peak-to-peak inductor current, which reflects the peak-to-
peak output ripple, is worst at the maximum input voltage.
See the Output Capacitor Selection section to verify that
the worst-case output ripple is acceptable. The inductor
ripple is mainly composed of ∆V (caused by the
Q
capacitor discharge) and ∆V
(caused by the volt-
ESR
age drop across the equivalent series resistance of the
output capacitor). The equations for calculating the
peak-to-peak output voltage ripple are:
saturating current (I
) is also important to avoid run-
SAT
away current during continuous output short circuit.
Select an inductor with an I specification higher than
SAT
∆I
P-P
∆V
=
the maximum peak current limit of 3.5A.
Q
16 × C
× f
SW
OUT
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore the
input capacitor must be carefully chosen to keep the
input voltage ripple within design requirements. The
∆V
= ESR × ∆I
-
P P
ESR
Normally, a good approximation of the output voltage
ripple is ∆V
≈ ∆V
+ ∆V . If using ceramic
ESR Q
RIPPLE
input voltage ripple is comprised of ∆V (caused by the
Q
capacitors, assume the contribution to the output volt-
age ripple from ESR and the capacitor discharge to be
capacitor discharge) and ∆V
(caused by the ESR of
ESR
______________________________________________________________________________________ 11
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
equal to 20% and 80%, respectively. ∆I
is the peak-to-
(C
) (C5 in the Typical Application Circuit) and its
OUT
P-P
peak inductor current (see the Input Capacitors Selection
section) and f is the converter’s switching frequency.
equivalent series resistance (ESR). The power modula-
tor incorporates a voltage feed-forward feature, which
automatically adjusts for variations in the input voltage
resulting in a DC gain of 10. The following equations
define the power modulator:
SW
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
V
IN
G
=
= 10
MOD(DC)
greater duty cycle. The response time (t
)
V
RESPONSE
RAMP
depends on the closed-loop bandwidth of the converter
(see the Compensation Design section). The resistive
drop across the output capacitor’s ESR, the drop
1
f
=
LC
across the capacitor’s ESL (∆V ), and the capacitor
ESL
2π L × C
OUT
discharge causes a voltage droop during the load-
step. Use a combination of low-ESR tantalum/aluminum
electrolyte and ceramic capacitors for better transient
load and voltage ripple performance. Nonleaded
capacitors and capacitors in parallel help reduce the
ESL. Keep the maximum output voltage deviation
below the tolerable limits of the electronics being pow-
ered. Use the following equations to calculate the
required ESR, ESL, and capacitance value during a
load step:
1
f
=
ZESR
2π × C
× ESR
OUT
The switching frequency is internally set at 250kHz or
can vary from 150kHz to 350kHz when driven with an
external SYNC signal. The crossover frequency (f ),
C
which is the frequency when the closed-loop gain is
equal to unity, should be set at 15kHz or below therefore:
f
≤ 15kHz
C
∆V
ESR
ESR =
I
STEP
The error amplifier must provide a gain and phase
bump to compensate for the rapid gain and phase loss
from the LC double pole. This is accomplished by utiliz-
ing a type 3 compensator that introduces two zeroes
and 3 poles into the control loop. The error amplifier
I
t
STEP × RESPONSE
C
=
OUT
∆V
Q
has a low-frequency pole (f ) near the origin.
P1
The two zeros are at:
∆V
t
ESL × STEP
ESL =
I
STEP
1
1
f
=
and f
=
Z1
Z2
where I
is the load step, t
is the rise time of the
STEP
STEP
2π × R5 × C7
2π × (R6 + R3) × C6
load step, and t
controller.
is the response time of the
RESPONSE
and the higher frequency poles are at:
Compensation Design
1
1
f
=
and f
=
P2
P3
The MAX5082/MAX5083 use a voltage-mode control
scheme that regulates the output voltage by comparing
the error amplifier output (COMP) with an internal ramp
to produce the required duty cycle. The output lowpass
LC filter creates a double pole at the resonant frequen-
cy, which has a gain drop of -40dB/decade. The error
amplifier must compensate for this gain drop and phase
shift to achieve a stable closed-loop system.
2π × R6 × C6
⎛
⎞
C7 × C8
C7 + C8
2π × R5 ×
⎜
⎟
⎝
⎠
Compensation When f < f
C
ZESR
Figure 3 shows the error amplifier feedback as well as
its gain response for circuits that use low-ESR output
capacitors (ceramic). In this case f
occurs after f .
C
ZESR
f
is set to 0.8 x f
and f is set to f to com-
LC(MOD) Z2 LC
The basic regulator loop consists of a power modulator,
an output feedback divider, and a voltage-error amplifi-
er. The power modulator has a DC gain set by
Z1
pensate for the gain and phase loss due to the double
pole. Choose the inductor (L) and output capacitor
(C
) as described in the Inductor and Output
V /V
, with a double pole and a single zero set by
OUT
IN RAMP
Capacitor Selection section.
the output inductance (L), the output capacitance
12 ______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
1
C8
R6 =
2π × C6 × 0.5 × f
SW
C7
R5
Since R3 >> R6, R3 + R6 can be approximated as R3.
R3 is then calculated as:
C6
R6
R3
1
V
OUT
R3 ≈
2π × f × C6
LC
EA
COMP
R4
REF
f
P3
is set at 5xf . Therefore, C8 is calculated as:
C
C7
C8 =
GAIN
(dB)
(2π × C7 × R5 × f −1)
P3
CLOSED-LOOP
GAIN
EA
GAIN
Compensation When f > f
C
ZESR
For larger ESR capacitors such as tantalum and alu-
minum electrolytic ones, f can occur before f . If
ZESR
C
f
f
< f , then f occurs between f and f . f and
ZESR
Z2
equal to f
C C P2 P3 Z1
remain the same as before however, f is now set
P2
. The output capacitor’s ESR zero fre-
f
f
f
f f
P2 P3
ZESR
Z1 Z2
C
FREQUENCY
quency is higher than f
but lower than the closed-
LC
loop crossover frequency. The equations that define
the error amplifier’s poles and zeroes (f , f , f , f
Figure 3. Error Amplifier Compensation Circuit (Closed-Loop
and Error-Amplifier Gain Plot) for Ceramic Capacitors
,
Z1 Z2 P1 P2
and f ) are the same as before. However, f is now
P3
P2
lower than the closed-loop crossover frequency. Figure
4 shows the error amplifier feedback as well as its gain
response for circuits that use higher-ESR output capac-
itors (tantalum or aluminum electrolytic).
Pick a value for the feedback resistor R5 in Figure 3
(values between 1kΩ and 10kΩ are adequate).
C7 is then calculated as:
Pick a value for the feedback resistor R5 in Figure 4 (val-
ues between 1kΩ and 10kΩ are adequate).
C7 is then calculated as:
1
C7 =
2π × 0.8 × f × R5
LC
f
occurs between f and f . The error-amplifier gain
Z2 P2
C
1
C7 =
(G ) at f is due primarily to C6 and R5. Therefore,
EA
C
2π × 0.8 × f × R5
LC
G
= 2π x f x C6 x R5 and the modulator gain at
EA(fC)
C
f is:
C
The error amplifier gain between f and f is approxi-
P2
P3
mately equal to R5/R6 (given that R6 << R3). R6 can
then be calculated as:
G
MOD(DC)
G
=
MOD(fC)
(2π)2 × L × C
× f
C
2
OUT
2
R5 × 10 × f
LC
R6 ≈
Since G
x G
= 1, C6 is calculated by:
MOD(fC)
2
EA(fC)
f
C
f
× L × C
×2π
OUT
C
C6 is then calculated as:
C6 =
R5 × G
MOD(DC)
C
× ESR
R6
OUT
C6 =
f
is set at one-half the switching frequency (f ). R6
P2
SW
is then calculated by:
______________________________________________________________________________________ 13
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
The power dissipated in the device is the sum of the
C8
power dissipated from supply current (P ), transition
Q
losses due to switching the internal power MOSFET
C7
R5
(P ), and the power dissipated due to the RMS cur-
SW
C6
rent through the internal power MOSFET (P
).
R6
MOSFET
The total power dissipated in the package must be lim-
ited such that the junction temperature does not
exceed its absolute maximum rating of +150°C at maxi-
mum ambient temperature. Calculate the power lost in
the MAX5082/MAX5083 using the following equations:
R3
V
OUT
EA
COMP
R4
REF
The power loss through the switch:
2
P
=I
×R
MOSFET RMS_MOSFET
ON
2
GAIN
(dB)
D
3
CLOSED-LOOP
GAIN
2
I
=
I
+(I × I ) +I
×
PK
DC
RMS_MOSFET
PK DC
[
]
EA
GAIN
∆I
P−P
I
= I
+
−
PK
OUT
2
∆I
P−P
I
= I
OUT
DC
2
f
f
f
f
f
P3
Z1 Z2
P2
C
FREQUENCY
R
is the on-resistance of the internal power MOSFET
ON
(see the Electrical Characteristics).
Figure 4. Error Amplifier Compensation Circuit (Closed-Loop
and Error Amplifier Gain Plot) for Higher ESR Output Capacitors
The power loss due to switching the internal MOSFET:
V
× I
× (t ×t ) × f
IN
OUT R F SW
Since R3 >> R6, R3 + R6 can be approximated as R3.
R3 is then calculated as:
P
=
SW
4
where t and t are the rise and fall times of the internal
R
F
1
power MOSFET measured at LX.
R3 ≈
2π × f × C6
LC
The power loss due to the switching supply current
(I ):
SW
f
P3
is set at 5xf . Therefore, C8 is calculated as:
C
P
Q
= V x I
IN SW
C7
C8 =
The total power dissipated in the device will be:
= P + P + P
(2π × C7 × R5 × f −1)
P3
P
TOTAL
MOSFET
SW
Q
Power Dissipation
The MAX5082/MAX5083 is available in a thermally
enhanced package and can dissipate up to 2.7W at T =
A
+70°C. When the die temperature reaches +160°C, the
part shuts down and is allowed to cool. After the part
cools by 20°C, the device restarts with a soft-start.
Chip Information
TRANSISTOR COUNT: 4300
PROCESS: BiCMOS/DMOS
14 ______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Typical Application Circuits
V
IN
4.5V TO 40V
C10
0.1µF
C3
0.1µF
D1
C4
0.1µF
IN
DVREG
C-
C+
BST
R1
1.4MΩ
LX
FB
V
OUT
L1
47µH
C6
6.8nF
REG
C1
10µF
R3
C5
47µF
D2
6.81kΩ
R6
187Ω
MAX5082
ON/OFF
C8
820pF
R2
549kΩ
SYNC SGND PGND
SS
COMP
R4
4.02kΩ
C9
C2
0.047µF
0.1µF
R5
3.01kΩ
C7
22nF
PGND
PGND
Figure 5. MAX5082 Typical Application Circuit
V
IN
7.5V TO 40V
C10
0.1µF
D1
C4
0.1µF
IN
DVREG
BST
R1
1.4MΩ
LX
FB
V
OUT
L1
47µH
C6
6.8nF
REG
C1
10µF
R3
C5
47µF
D2
6.81kΩ
R6
187Ω
MAX5083
ON/OFF
C8
820pF
R2
301kΩ
SYNC SGND PGND
SS
COMP
R4
4.02kΩ
C9
0.047µF
C2
0.1µF
R5
3.01kΩ
C7
22nF
PGND
PGND
Figure 6. MAX5083 Typical Application Circuit
______________________________________________________________________________________ 15
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Typical Operating Circuits (continued)
V
IN
7.5V TO 40V
D1
C
BST
IN
DVREG
BST
L1
R1
LX
V
OUT
C6
REG
C1
R3
R4
C5
D2
MAX5083
R6
ON/OFF
FB
C8
R5
SYNC SGND PGND
SS
COMP
R2
C7
C
C2
SS
PGND
PGND
Pin Configurations
TOP VIEW
12
11
10
9
12
11
10
9
IN
IN
C-
C+
IN
N.C.
13
8
7
6
5
13
14
15
16
8
7
6
5
IN
REG
N.C.
14
15
16
MAX5082
MAX5083
REG
DVREG
SYNC
DVREG
SYNC
SGND
SGND
1
2
3
4
1
2
3
4
TQFN
TQFN
16 ______________________________________________________________________________________
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
XXXXX
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
C
L
L1
L
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
21-0140
H
-DRAWING NOT TO SCALE-
2
______________________________________________________________________________________ 17
1.5A, 40V, MAXPower Step-Down
DC-DC Converters
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
DOWN
BONDS
ALLOWED
L
PKG.
CODES
MIN. NOM. MAX. MIN. NOM. MAX. ±0.15
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
T1655-1
T1655-2
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
**
**
**
**
A1
A3
b
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
0
0.02 0.05
0.20 REF.
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-2
T2055-3
T2055-4
T2055-5
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
NO
YES
NO
D
E
**
**
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-1
T2855-2
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
NO
NO
L
**
**
**
**
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
40
T2855-3
T2855-4
3.15 3.25 3.35 3.15 3.25 3.35
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
N
ND
NE
16
20
28
32
4
4
5
5
7
7
8
8
10
10
T2855-5
T2855-6
T2855-7
T2855-8
**
**
**
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
NO
YES
2.80
3.35
3.35
3.20
2.60 2.70
3.15 3.25
2.60 2.70 2.80
3.15 3.25 3.35
3.15 3.25 3.35
3.00 3.10 3.20
0.40
YES
NO
NO
NOTES:
T2855N-1 3.15 3.25
**
**
**
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255-2
T3255-3
T3255-4
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
NO
**
**
**
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
NO
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3, AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
H
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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