MAX5096_07 [MAXIM]
40V, 600mA Buck Converters with Low-Quiescent-Current Linear Regulator Mode; 40V ， 600mA buck转换器具有低静态电流线性稳压模式
| 型号： | MAX5096_07 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 40V, 600mA Buck Converters with Low-Quiescent-Current Linear Regulator Mode |
| 文件： | 总20页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0603; Rev 1; 6/07
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
General Description
Features
♦ High-Efficiency Switcher Mode (Buck Mode) or
The MAX5096/MAX5097 easy-to-use, Dual Mode™,
DC-DC converters operate as LDO (low dropout) or
switch-mode buck converters. At a high output load,
the converters operate as high-efficiency pulse-width-
modulated (PWM) switch-mode converters and reduce
the power dissipation. The devices switch to a low-qui-
Low-Quiescent-Current Linear Regulator
(LDO Mode) Operation
♦ Wide Operating Input Voltage Range
+5V to +40V Buck Mode
+4V to +40V LDO Mode
♦ Fixed 3.3V or 5V and Adjustable (1.24V to 11V)
escent-current (I ) LDO mode of operation at light load.
Q
Output Voltage Versions
During the key-off condition, the system’s microcon-
troller drives the LDO/BUCK input on the fly and forces
the MAX5096/MAX5097 into LDO Mode, thereby reduc-
ing the quiescent current significantly.
♦ 6µA (typ) Shutdown Current
♦ Fixed 135kHz or 330kHz Switching Frequency
♦ External Frequency Synchronization
♦ Programmable Soft-Start
In Buck Mode, the MAX5096/MAX5097 operate from a 5V
to 40V input voltage range and deliver up to 600mA of
load current with excellent load and line regulation. The
fixed-switching frequency versions of 135kHz and
330kHz are available. The MAX5096/MAX5097 DC-DC
internal oscillator can be synchronized to an external
clock. External compensation and a current-mode control
scheme make it easy to design with.
♦ Integrated Microprocessor Reset (RESET) Circuit
with Programmable Timeout Period
♦ Thermal and Short-Circuit Protection
♦ -40°C to +125°C Automotive Temperature Range
♦ Thermally-Enhanced Package Dissipates
2.6W at T = +70°C (16-Pin TQFN)
A
1.7W at T = +70°C (20-Pin TSSOP)
A
Ordering Information
In LDO Mode, the MAX5096/MAX5097 operate from a
4V to 40V input voltage. The LDO Mode operation is
intended for a lower output load current of up to
100mA. The quiescent current at 100µA load in LDO
Mode is only 41µA (typ).
PKG
CODE
PART
TEMP RANGE PIN-PACKAGE
MAX5096AATE+* -40°C to +125°C 16 TQFN-EP** T1655-2
MAX5096BATE+ -40°C to +125°C 16 TQFN-EP** T1655-2
MAX5096AAUP+* -40°C to +125°C 20 TSSOP-EP** U20E-4
MAX5096BAUP+* -40°C to +125°C 20 TSSOP-EP** U20E-4
MAX5097AATE+ -40°C to +125°C 16 TQFN-EP** T1655-2
MAX5097BATE+* -40°C to +125°C 16 TQFN-EP** T1655-2
MAX5097AAUP+* -40°C to +125°C 20 TSSOP-EP** U20E-4
MAX5097BAUP+* -40°C to +125°C 20 TSSOP-EP** U20E-4
The MAX5096/MAX5097 feature an enable input that
shuts down the device, reducing the current consump-
tion to 6µA (typ). Additional features include a power-on
reset output with a capacitor-adjustable timeout period,
programmable soft-start, output tracking, output over-
load, short-circuit and thermal shutdown protections.
The MAX5096/MAX5097 operate over the -40°C to
+125°C automotive temperature range and are avail-
able in thermally enhanced 20-pin TSSOP or 16-pin
TQFN packages.
*Future product—contact factory for availability.
+Denotes lead-free package.
**EP = Exposed pad.
Applications
Pin Configurations
TOP VIEW
TOP VIEW
Automotive
Industrial
+
16
15
14
13
+
IN
IN
1
2
3
4
5
6
7
8
9
20 LX
19 LX
PGND
SGND
RESET
BP
EN
1
2
3
4
12
11
10
9
IN
18 N.C.
17 EN
OUT
PGND
SGND
RESET
BP
MAX5096
MAX5097
MAX5096
MAX5097
16 OUT
15 ADJ
14 N.C.
ADJ
LDO/BUCK
LDO/BUCK
N.C.
SYNC
13
5
6
7
8
12 COMP
11 CT
SS 10
Dual Mode is a trademark of Maxim Integrated Products, Inc.
TQFN
TSSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to PGND, unless otherwise noted.)
IN (transient, 1ms)..................................................-0.3V to +45V
SGND ....................................................................-0.3V to +0.3V
Thermal Resistance:
(θ , 16-Pin TQFN)* ...................................................30.0°C/W
JA
(θ , 16-Pin TQFN).......................................................1.7°C/W
JC
LX....................................................................-1V to (V + 0.3V)
(θ , 20-Pin TSSOP)* .................................................46.0°C/W
JA
IN
LX Current................................................................................2A
(θ , 20-Pin TSSOP)........................................................2°C/W
JC
EN................................................................-0.3V to (V + 0.3V)
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
IN
BP, SYNC, LDO/BUCK, RESET to SGND...............-0.3V to +12V
BP, RESET Output Current..................................................25mA
CT, SS, ADJ, COMP to SGND ....................-0.3V to (V + 0.3V)
BP
OUT ........................................................................-0.3V to +11V
OUT Short-Circuit Duration ........................................Continuous
Continuous Power Dissipation (T = +70°C)*
A
16-Pin TQFN (derate 33.3mW/°C above +70°C) ........2666mW
20-Pin TSSOP (derate 21.7mW/°C above +70°C) ......1739mW
*As per JEDEC 51 Standard—Multilayer Board.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +14V, I
= 1mA, C = 100µF, C
= 22µF, L = 22µH, C = 1µF, V = +2.4V (Figure 2), SGND = PGND = 0V, T = T =
OUT BP EN A J
IN
OUT
IN
-40°C to +125°C, unless otherwise noted. Typical values are at T = T = +25°C.) (Note 1)
A
J
PARAMETER
SYSTEM INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Range (LDO Mode)
V
LDO/BUCK = high
LDO/BUCK = low
4
5
40
40
V
V
IN_LDO
Input Voltage Range (Buck
Mode)
V
IN_BUCK
Internal Input Undervoltage
Lockout
V
V
V
rising
falling
3.5
3.65
0.2
3.9
V
V
UVLO
BP
BP
Internal Input Undervoltage
Lockout Hysteresis
V
UVLO_HYS
BP (Internal Regulator) Output
Voltage
V
V
= +4.5V, I = 100µA
3.75
4
4.20
70
V
BP
IN
BP
LDO/BUCK = high,
measured at input supply
return, V
T
= -40°C to
A
I
38
Q
= 5V,
+125°C
OUT
I
= 100µA
OUT
Quiescent Supply Current
(LDO Mode)
µA
LDO/BUCK = high,
measured at input supply
T
= -40°C to
A
I
44
100
Q
return, V
= 5V,
+125°C
OUT
I
= 100mA
OUT
Buck Converter No-Load Supply
Current
I
V
= 14V, V
= 5V, I
OUT
= 0
680
6
µA
µA
Q_BUCK
IN
OUT
T
= -40°C to
A
19
12
+125°C
V
= 0V, measured
EN
Shutdown Supply Current
I
SHDN
from V
T
= -40°C to
IN
A
6
+85°C
2
_______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
ELECTRICAL CHARACTERISTICS (continued)
(V = +14V, I
= 1mA, C = 100µF, C
= 22µF, L = 22µH, C = 1µF, V = +2.4V (Figure 2), SGND = PGND = 0V, T = T =
OUT BP EN A J
IN
OUT
IN
-40°C to +125°C, unless otherwise noted. Typical values are at T = T = +25°C.) (Note 1)
A
J
PARAMETER
BUCK MODE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LDO/BUCK = low,
= 1.4V, MAX5096,
no switching
Supply Current
(Buck Converter On)
135kHz
version
V
I
693
720
980
µA
ADJ
S
LDO/BUCK = low,
Supply Current
(Buck Converter On)
330kHz
Version
I
S
V
= 1.4V, MAX5097,
ADJ
1000
µA
V
no switching
5V version, 5.5V ≤ V ≤ 40V, no load
4.85
3.196
1.21
5
3.3
1.235
5
5.12
3.391
1.27
100
IN
Fixed Output Voltage
V
OUT
3.3V version, 5.5V ≤ V ≤ 40V, no load
IN
ADJ Set Point
V
50% duty cycle, no load
V
FB
ADJ Input Bias Current
I
V
= 1.5V
nA
FB
ADJ
V
V
ADJ rising
ADJ falling
125
62
ADJTH_R
ADJTH_F
Dual Mode ADJ Threshold
mV
Maximum Duty Cycle
D
V
V
= 0.5V
100
136
%
µS
V
MAX
ADJ
Error Amplifier Transconductance
Adjustable Output Voltage Range
Minimum Output Current
Switch Current Limit
Gm
= V , I =
ADJ COMP
10µA
55
210
EA
ADJ
COMP
V
1.235
11.000
I
V
V
V
V
V
V
= 6.5V to 40V
= 6V to 40V
600
1.5
0.9
0.05
85
mA
A
OUT
IN
IN
IN
EN
IN
IN
I
1.15
1.90
2.1
3
SW_LIM
Internal Switch On-Resistance
Switch Leakage Current
R
= 14V, I = 100mA
DRAIN
Ω
DS(ON)
I
= 0V
µA
SW_L
= 14V, V
= 14V, V
= 5V, I
= 400mA
OUT
OUT
OUT
Efficiency
η
%
= 3.3V, I
= 400mA
81
OUT
MAX5096
MAX5097
MAX5096
MAX5097
120
300
120
300
2.0
135
330
148
350
500
500
kHz
kHz
kHz
kHz
V
Switching Frequency
Synchronization SYNC Input
f
SW
f
SYNC
SYNC Input High Threshold
SYNC Input Low Threshold
V
V
V
= 4V
= 4V
SYNCH
BP
BP
V
0.8
1
V
SYNCL
SYNC Input Minimum High Pulse
Width
250
ns
SYNC Input Leakage
LDO MODE
V
=11V
µA
SYNC
Guaranteed Output Current
I
(Note 2)
100
mA
OUT
_______________________________________________________________________________________
3
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
ELECTRICAL CHARACTERISTICS (continued)
(V = +14V, I
= 1mA, C = 100µF, C
= 22µF, L = 22µH, C = 1µF, V = +2.4V (Figure 2), SGND = PGND = 0V, T = T =
OUT BP EN A J
IN
OUT
IN
-40°C to +125°C, unless otherwise noted. Typical values are at T = T = +25°C.) (Note 1)
A
J
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5V version, MAX5096B/MAX5097B,
4.89
5
5.09
V
5.5V ≤ V ≤ 40V, I
= 10mA
IN
OUT
Output Voltage
V
OUT
3.3V version, MAX5096A/MAX5097A,
4V ≤ V ≤ 40V, I = 10mA
89
3.3
3.378
V
IN
OUT
ADJ Set Point
V
V
I
= 10mA
= 4V
1.21
1.2375
0.5
1.26
100
V
nA
V
ADJ
OUT
ADJ Input Bias Current
Adjustable Output Voltage Range
I
V
FB
ADJ
OUT
I
= 10mA
1.237
11.000
ADJ
I
V
= 100mA,
= 0.98 x V (5V version
OUT(NOMINAL)
OUT
Dropout Voltage
∆V
0.37
V
DO
OUT
only), MAX5096B/MAX5097B
Rising edge of EN to
V
= 10% V
,
OUT
OUT(NOMINAL)
Startup Response Time
300
µs
R = 500Ω, V
= SGND,
ADJ
L
LDO/BUCK = 4V, C = 2nF
SS
5V version,
0.125
0.093
+5.5V ≤ V ≤ +40V, I
= 100mA
IN
OUT
∆V
∆V
/
/
OUT
Line Regulation
Load Regulation
mV/V
∆V
IN
3.3V version,
+4V ≤ V ≤ +40V, I
= 100mA
IN
OUT
5V version,
T = +25°C
0.242
0.242
0.164
0.164
0.374
1
J
I
= 100µA to
OUT
T = -40°C to +125°C
J
100mA, V = +14V
IN
OUT
mV/mA
∆I
OUT
3.3V version,
T = +25°C
J
0.237
1
I
= 100µA to
OUT
T = -40°C to +125°C
J
100mA, V = +14V
IN
I
V
= 10mA, f = 100Hz, 500mV
,
OUT
P-P
Power-Supply Rejection Ratio
Short-Circuit Current
PSRR
60
dB
= +5V, V = +14V
IN
OUT
I
V
= 6V
IN
150
330
500
mA
SC
BUCK MODE (LDO MODE TRANSITION)
LDO/BUCK High Threshold
2.0
V
V
LDO/BUCK Low Threshold
0.8
1
LDO/BUCK Input Leakage
LDO/BUCK = 11V
µA
Transition Timing from LDO Mode
to Buck Mode
Falling edge of LDO/BUCK to buck
converter on
Clock
Periods
32
Transition Timing from Buck
Mode to LDO Mode
Rising edge of LDO/BUCK to LDO
operation
100
µs
SOFT-START, ENABLE (EN) AND RESET
Soft-Start Charge Current
Soft-Start Reference Voltage
EN High-Voltage Threshold
I
V
V
= 0.1V
3
5
7
µA
V
SS
SS
V
= V - 20%
OUT(NOMINAL)
0.9
1.4
0.99
1.1
SS-REF
OUT
V
EN = high, regulator on
V
ENH
4
_______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
ELECTRICAL CHARACTERISTICS (continued)
(V = +14V, I
= 1mA, C = 100µF, C
= 22µF, L = 22µH, C = 1µF, V = +2.4V (Figure 2), SGND = PGND = 0V, T = T =
OUT BP EN A J
IN
OUT
IN
-40°C to +125°C, unless otherwise noted. Typical values are at T = T = +25°C.) (Note 1)
A
J
PARAMETER
EN Low-Voltage Threshold
EN Input Pulldown
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Regulator off
0.4
ENL
V
V
V
= 2V, LDO/BUCK = 4V
0.5
92
90
µA
EN
RESET Voltage Threshold High
RESET Voltage Threshold Low
RESET Output-Low Voltage
V
rising
falling
= 1mA
89
87
94
92
% V
% V
RESET_H
OUT
OUT
SINK
OUT
OUT
V
RESET_L
V
I
0.2
V
RL
RESET Output-High Leakage
Current
I
V
= 5V, V = 1.5V
ADJ
1
µA
µs
RH
RESET
RESET Output Minimum Timeout
Period
C
= 0
25
CT
V
to RESET Delay
V
V
falling 10mV/µs, C = 0
6
µs
V
OUT
OUT
CT
Delay Comparator Threshold
V
rising
1.18
0.74
1.2374
1.29
1.20
CT_TH
CT
Delay Comparator Threshold
Hysteresis
100
mV
CT Charge Current
I
1
µA
CH
CT Discharge Current
I
V
= 1V
13.8
mA
DISCH
CT
THERMAL SHUTDOWN
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
Temperature rising
+165
20
°C
°C
J(SHDN)
∆T
J(SHDN)
Note 1: Limits to -40°C are guaranteed by design.
Note 2: The continuous maximum output current from LDO is limited by package power dissipation.
_______________________________________________________________________________________
5
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Typical Operating Characteristics
(V = +14V, V = +2.4V, MAX5097AATE+, Figures 2 and 4, T = +25°C, unless otherwise specified.)
IN
EN
A
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(LDO MODE)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(BUCK MODE)
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE (LDO MODE)
4.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
80
70
60
50
40
30
20
10
0
V
V
= 14V
IN
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
= 3.3V
OUT
I
= 100mA
OUT
I
= 0
OUT
I
= 100µA
OUT
I
= 600mA
I
= 50mA
OUT
OUT
1
10
100
1
10
100
-40 -25 -10
5
20 35 50 65 80 95 110 125
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
NO-LOAD SUPPLY CURRENT
vs. TEMPERATURE (BUCK MODE)
SHUTDOWN CURRENT
vs. TEMPERATURE
OUTPUT VOLTAGE vs. TEMPERATURE
(LDO MODE)
710
700
690
680
670
660
650
640
14
12
10
8
3.5
3.4
3.3
3.2
3.1
3.0
V
V
= 14V
V
V
= 0V
= 14V
V
= 3.3V
IN
EN
IN
OUT
= 3.3V
OUT
I
= 100µA
OUT
I
= 10mA
OUT
6
I
= 10mA
OUT
4
2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
DROPOUT VOLTAGE
vs. OUTPUT CURRENT (LDO MODE)
OUTPUT VOLTAGE
vs. TEMPERATURE (BUCK MODE)
EFFICIENCY vs. LOAD CURRENT
(V = 3.3V)
OUT
100
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
V
= 3.3V
OUT
f
= 330kHz
V
= 5V
SW
OUT
90
80
70
60
50
40
30
20
10
0
I
= 100µA
OUT
V
= 24V
IN
V
= 5V
IN
V
= 40V
I
= 600mA
IN
OUT
I
= 100mA
OUT
V
= 14V
IN
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
20
40
60
80
100
0.01
0.1
LOAD CURRENT (A)
1
TEMPERATURE (°C)
OUTPUT CURRENT (mA)
6
_______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Typical Operating Characteristics (continued)
(V = +14V, V = +2.4V, MAX5097AATE+, Figures 2 and 4, T = +25°C, unless otherwise specified.)
IN
EN
A
LOAD-TRANSIENT RESPONSE
(BUCK MODE)
EFFICIENCY vs. LOAD CURRENT
LOAD-TRANSIENT RESPONSE
(LDO MODE)
(V
OUT
= 5V)
MAX5096 toc12
MAX5096 toc11
100
V
= 14V
= 100µA to 50mA
IN
90
80
70
60
50
40
30
20
10
0
I
OUT
I
I
OUT
OUT
200mA/div
50mA/div
V
= 14V
IN
V
= 24V
IN
V
= 5.5V
IN
V
V
V
= 40V
OUT
OUT
IN
AC-COUPLED
100mV/div
50mV/div
V
= 14V
IN
I
= 300mA to 600mA
STEP
1ms/div
0.01
0.1
LOAD CURRENT (A)
1
2ms/div
V
IN
STARTUP RESPONSE
(LDO MODE)
ENABLE STARTUP RESPONSE
(LDO MODE)
V
IN
STARTUP RESPONSE
(BUCK MODE)
MAX5096 toc15
MAX5096 toc13
MAX5096 toc14
V
I
C
= 14V
= 0A
IN
OUT
V
V
V
IN
IN
IN
V
I
C
= 14V
= 0A
V
I
C
= 14V
IN
OUT
IN
10V/div
10V/div
10V/div
= 0.047µF
CT
= 100mA
OUT
= 0.047µF
= 0.047µF
CT
CT
V
EN
V
V
EN
5V/div
EN
10V/div
5V/div
V
V
V
OUT
OUT
OUT
2V/div
2V/div
2V/div
RESET
5V/div
RESET
5V/div
RESET
5V/div
10ms/div
10ms/div
10ms/div
ENABLE STARTUP RESPONSE
(BUCK MODE)
SHUTDOWN RESPONSE THROUGH
SHUTDOWN RESPONSE THROUGH
V
IN
(LDO MODE)
V (BUCK MODE)
IN
MAX5096 toc16
MAX5096 toc17
MAX5096 toc18
I
= 50mA
I
= 50mA
OUT
OUT
V
V
V
IN
IN
IN
V
= 14V
= 600mA
IN
10V/div
10V/div
10V/div
I
OUT
C
= 0.047µF
CT
V
V
V
EN
EN
EN
5V/div
10V/div
10V/div
V
V
V
OUT
OUT
OUT
2V/div
2V/div
2V/div
RESET
5V/div
RESET
5V/div
RESET
5V/div
10ms/div
100ms/div
100ms/div
_______________________________________________________________________________________
7
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Typical Operating Characteristics (continued)
(V = +14V, V = +2.4V, MAX5097AATE+, Figures 2 and 4, T = +25°C, unless otherwise specified.)
IN
EN
A
LX VOLTAGE, SYNC INPUT,
AND INDUCTOR CURRENT
LX VOLTAGE AND INDUCTOR CURRENT
LX VOLTAGE AND INDUCTOR CURRENT
MAX5096 toc20
MAX5096 toc19
MAX5096 toc21
I
= 600mA
I
= 0A
OUT
OUT
V
LX
10V/div
V
LX
10V/div
V
LX
5V/div
SYNC INPUT
5V/div
INDUCTOR
CURRENT
500mA/div
INDUCTOR
CURRENT
200mA/div
INDUCTOR
CURRENT
500mA/div
1µs/div
2µs/div
1µs/div
TRANSITION FROM BUCK
MODE TO LDO MODE
TRANSITION FROM LDO MODE
TO BUCK MODE
MAX5096 toc22
MAX5096 toc23
LDO/BUCK
5V/div
LDO/BUCK
3V/div
V
OUT
V
AC-COUPLED
200mV/div
OUT
AC-COUPLED
200mV/div
I
I
OUT
OUT
100mA/div
100mA/div
V
= 14V
V
= 14V
IN
IN
I
= 100mA
I
= 100mA
OUT
OUT
400µs/div
100µs/div
8
_______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Pin Description
PIN
NAME
FUNCTION
TQFN
TSSOP
Power Ground. Return path for p-channel power MOSFET driver. Connect the input
capacitor return, freewheeling diode anode, and output capacitor return terminals to
PGND.
1
2
4
5
PGND
SGND
Signal Ground. Connect SGND to PGND near the input bypass capacitor return terminal.
Open-Drain, Active-Low Reset Output. RESET asserts low when OUT drops below the
reset threshold. When output rises above 92% of the programmed level, RESET
becomes high impedance after the reset timeout period. Connect a pullup resistor from
RESET to the converter output to create a logic output.
3
6
RESET
4V Internal Regulator Output. Bypass BP to SGND with a 1µF or greater ceramic
capacitor.
4
5
6
7
7
9
BP
SYNC
SS
Synchronization Input. Connect SYNC to an external clock for synchronization. Connect
SYNC to SGND when not used.
Soft-Start Timer Input. Connect an external capacitor from SS to SGND to adjust the soft-
start timeout period (see the Soft-Start (SS) section).
10
11
Reset Timeout Period. Connect a capacitor from CT to SGND to set the reset timeout
period (see the Power-On Reset Output RESET section).
CT
Buck Converter (Buck Mode) Control Loop Compensation. See the Compensation
Network section for compensation network design. LDO mode does not need external
compensation.
8
9
12
13
COMP
LDO Mode/Buck Mode Select. Drive LDO/BUCK low to select the Buck Mode. The Buck
Mode activates after 32 internal/external clock cycles. Force the LDO/BUCK high (> 2V),
to select LDO Mode. The Buck Mode stops and LDO Mode is activated with a 100µs
delay.
LDO/BUCK
Regulator Output Feedback Point. Connect ADJ to SGND for a fixed 3.3V
10
11
15
16
ADJ
OUT
(MAX5096A/MAX5097A) or 5V (MAX5096B/MAX5097B). For adjustable output voltage,
use an external resistive divider to set V . V
OUT ADJ
regulating set point is 1.237V.
Converter Output. OUT must always be connected to the regulator output. Connect at
least a 22µF low-ESR (equivalent series resistance) capacitor from OUT to PGND for
stable operation.
Enable Input. EN is internally pulled to ground. Drive EN high to turn on the regulator.
Force EN low or leave unconnected to place the device in shutdown mode.
12
13, 14
15, 16
—
17
19, 20
1, 2, 3
8, 14, 18
EP
EN
LX
Drain Connection of Internal p-Channel High-Side Switch
Regulator Input. Bypass IN to PGND with a parallel combination of low-ESR ceramic and
aluminum capacitor to handle the input ripple current.
IN
N. C.
EP
No Connection. Not internally connected.
Exposed Pad. Connect externally to a large ground plane (SGND) for improved heat
dissipation. Do not use EP as an electrical ground connection.
EP
_______________________________________________________________________________________
9
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
IN
C
IN
BP
INTERNAL
4V LDO
V
OUT
CURRENT
SENSE
C
BP
OSCILLATOR
AND RAMP
GENERATOR
- +
DC
CURRENT
LIMITER
V
IN
DC-DC ENABLE
PWM
0.9Ω
GATE
DRIVER
MUX
L
V
LX
OUT
PWM
COMPARATOR
+
FB
+
-
-
C
OUT
gm
SS
V
R
1
REF
BUCK MODE GM
AMPLIFIER
COMP
SYNC
ADJ
OUT
-
FB
+
-
-
R
C
+
SS
V
SYNCRO
R
2
0.12V
REF
FEEDBACK
SELECTOR
LDO MODE
AMPLIFIER
C
C
C
P
LDO/BUCK
SELECTOR
LDO/BUCK
MODE
SELECTOR
R
PU
EN
SS
RESET
BIAS SOFT-
START
INTERNAL
BANDGAP
UVLO
RESET
THERMAL
PROTECTION
C
SS
MAX5096
MAX5097
SGND
PGND
CT
C
CT
Figure 1. Simplified Diagram
10 ______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
turned on and off while in both Buck and LDO Modes.
Detailed Description
The MAX5096/MAX5097 are easy-to-use, high-efficien-
Each time the EN is toggled, the output rises with a pro-
grammed soft-start period.
cy, PWM current-mode, step-down switching convert-
ers in normal operation. The MAX5096/MAX5097 have
an internal high-side p-channel 0.9Ω switch and use a
low forward-drop freewheeling diode for rectification. In
Buck Mode, the p-channel switches at the 135kHz or
330kHz frequency. Buck Mode uses a current-mode
control architecture that offers excellent line-transient
response, easier frequency compensation, and cycle-
by-cycle current limiting. The buck converter is com-
pensated externally for a selected value/type of output
inductor and capacitor.
Internal Regulator (BP)/
Undervoltage Lockout
The MAX5096/MAX5097 include an internal 4V auxiliary
regulator to power internal circuitry. Bypass the auxil-
iary regulator output (BP) to SGND with a 1µF ceramic
capacitor physically located close to the device. The
regulator is not intended to supply the external circuit
other than pulling up the LDO/BUCK input or RESET.
Do not load BP externally by more than 2mA. The regu-
lator output is regulated to 4V with 7% accuracy during
steady state. During turn-on, the BP voltage stabilizes
after 250µs with a 1µF capacitor at BP. Drive EN high to
turn on the internal regulator. The internal UVLO with
hysteresis ensures stable operation, resulting in the
monotonic rise of the output voltage. The UVLO circuit
monitors the output of the regulator. The rising UVLO
threshold is internally set to 3.65V (BP rising) with a
185mV hysteresis (BP falling). The 3.65V UVLO at the
The internal p-channel switch acts as a pass element
when operating in the low-quiescent-current LDO
Mode.
The LDO Mode can be selected on the fly through the
LDO/BUCK input. During the key-off condition, the sys-
tem’s microcontroller drives the LDO/BUCK input high
and forces the MAX5096/MAX5097 into LDO Mode,
reducing the quiescent current to 1µA (typ). When in
LDO Mode, the device is capable of delivering up to
100mA, which may be limited by the device power dis-
sipation. The LDO and switcher share the same pass
element and the reference; however, the error ampli-
fiers are different with their own compensation
schemes.
no-load BP output guarantees operation at V lower
IN
than 4V.
Soft-Start (SS)
Soft-start provides for the monotonic, glitch-free turn-on
of the converter. Soft-start limits the input inrush current
which may cause a glitch, especially if the source
impedance is high. The soft-start period required also
depends on the output capacitance and the closed-
loop bandwidth of converter. The soft-start period for
the MAX5096/MAX5097 is externally programmable
The MAX5096/MAX5097 include an integrated micro-
processor reset circuit with an adjustable reset timeout
period. The internal reset circuit monitors the regulator
output voltage and asserts RESET low when the regula-
tor output falls below the reset threshold voltage. Other
features include an enable input, externally program-
mable soft-start, optimized current-limit protection in
both LDO and Buck Modes, and thermal shutdown.
using a single capacitor (C ). The soft-start is
SS
achieved by the controlled ramping up of the error
amplifier reference input. At startup, after V is applied
IN
and the UVLO threshold is reached, the device enters
soft-start. During soft-start, 5µA is sourced into the
Enable Input (EN)
EN is a logic-level enable input that turns the device on
or off. The logic-high and logic-low voltages for the EN
input are 1.4V and 0.4V, respectively. Drive EN high to
turn on the device, and drive it low to place the device
in shutdown. Leaving EN unconnected disables the
device since the EN is internally pulled low with a 0.5µA
current, however, a forced pulldown of EN improves the
noise immunity. The MAX5096/MAX5097 draw 6µA
(typ) of supply current when in shutdown. EN with-
stands up to +40V, allowing EN to be connected direct-
ly to IN for always-on operation. The converter may be
capacitor (C ) connected from SS to SGND (Figure 2)
SS
causing the reference voltage to ramp up slowly. When
V
reaches 1.237V, the output becomes fully active.
SS
Set the soft-start time (t ) using following equation:
SS
V
SS
t
=
×C
SS
SS
I
SS
where V is 1.237V, I is 5µA, t is in seconds, and
SS
SS
SS
C
is in Farads.
SS
Pulling EN low quickly discharges the C
capacitor,
SS
making it ready for the next soft-start period.
______________________________________________________________________________________ 11
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
V
IN
V
IN
BP
1.0µF
C
IN
EN
100µF
22µH
LDO/BUCK
SYNC
V
OUT
LX
+
D1*
B260/
MURS105
C
OUT
22µF
(CER.)
MAX5096
MAX5097
COMP
R
C
ADJ
OUT
100kΩ
C
P
C
C
1.2nF
22pF
100kΩ
SS
CT
RESET
RESET
C
SS
GND
PGND
0.047µF
*USE MURS105 IN APPLICATIONS
WHERE LDO MODE QUIESCENT
CURRENT IS CRITICAL.
C
CT
0.01µF
Figure 2. Fixed Output Voltage Configuration
a high-impedance state after the active timeout period
Output Voltage Tracking/Sequencing
The output voltages of multiple MAX5096/MAX5097
converters can be made to track by using the SS pin
during turn-on and turn-off (see Figure 3). SS is pulled
up using a 5µA current source and connecting SS of
multiple MAX5096/MAX5097s, raising the references
with the same slope. Tracking the converters reduces
the differential voltages between the core and I/O volt-
ages during turn-on, turn-off, and brownout. If any one
converter output drops due to shutdown or an overload
fault situation, the SS drops, pulling down all the con-
verters simultaneously. The rate of fall of output volt-
ages, however, depends on the output capacitance
and load of the individual converter.
(t ). The active timeout period is externally program-
RP
mable using a single capacitor from CT to ground. Use
the following equation to calculate the required timeout
period for the power-on reset:
V
CT−TH
t
=
×C
CT
RP
I
CH
where V
is 1.237V, I
is 1µA, t is in seconds,
RP
CT-TH
and C is in Farads.
CH
CT
To obtain a logic-voltage output, connect a pullup
resistor from RESET to a logic-supply voltage. The
internal open-drain MOSFET can sink 1mA while provid-
ing a TTL logic-low signal. If unused, ground RESET or
leave it unconnected.
Multiple voltage sequencing can be done by daisy-
chaining several MAX5096/MAX5097s. The RESET of
the first converter can be connected to EN of the sec-
ond converter. This allows the first converter to come
up first every time the system is powered up.
The power-on reset behavior is the same in both the
LDO and Buck Modes of operation.
Oscillator/Synchronization Input (SYNC)
The MAX5096/MAX5097 internal oscillator generates a
factory-preset frequency of either 135kHz (MAX5096)
or 330kHz (MAX5097). The 135kHz version keeps the
maximum fundamental frequency below 150kHz, which
keeps the third harmonic below 450kHz and under the
Power-On Reset Output (RESET)
A supervisor circuit is integrated in the MAX5096/
MAX5097. RESET is an open-drain output. RESET pulls
low as soon as V
drops below 90% of its nominal
OUT
regulation voltage. Once the output voltage rises above
92% of the set output voltage, the RESET output enters
12 ______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Applications Information
V
OUT3
Output Voltage Selection
The MAX5096/MAX5097 can be configured as either a
preset fixed output voltage or an adjustable output volt-
age device. Connect ADJ to ground to select the facto-
ry-preset output voltage option (Figure 2). The
MAX5096A/MAX5097A and MAX5096B/MAX5097B
provide a fixed output voltage equal to 3.3V and 5V,
respectively (see the Selector Guide). The MAX5096/
MAX5097 become an adjustable version as soon as the
devices detect about 125mV at the ADJ pin. The resis-
tor-divider at ADJ increases the ADJ voltage above
125mV and also adjusts the output voltage depending
upon the resistor values. In adjustable mode, select an
output between +1.273V and +11V using two external
resistors connected as a voltage-divider to ADJ (Figure
4). Set the output voltage using the following equation:
V
OUT2
OUT1
V
SOFT-START
STOP
RATIOMETRIC TRACKING OUTPUTS
V
OUT1
V
OUT2
V
OUT3
STOP
R1
R2
⎛
⎞
V
= V
× 1 +
⎜
ADJ
⎟
⎠
OUT
SOFT-START
SEQUENCED OUTPUTS
⎝
where V
= 1.273V and R2 is chosen to be approxi-
ADJ
mately 100kΩ.
Figure 3. Output Voltage Tracking/Sequencing
Connect ADJ to GND if adjustable mode is not used.
lower end of the AM band. The MAX5096 is suitable for
noise-sensitive applications like AM radio power sup-
ply. For an application where size is more important,
use the MAX5097, which runs at 330kHz frequency.
The high-frequency operation reduces the size and
cost of the external inductor and capacitor. The
MAX5096/MAX5097 can be synchronized using an
external signal. The MAX5096 can be synchronized
from 120kHz to 500kHz, while the MAX5097 is capable
of synchronizing from 300kHz to 500kHz. The external
synchronization feature makes frequency hopping pos-
sible depending on the selected AM channel. Connect
SYNC to ground, if not used.
Inductor Selection
Three key inductor parameters must be specified for
proper operation with the MAX5096/MAX5097: induc-
tance value (L), peak inductor current (I
), and
PEAK
). The minimum
inductor saturation current (I
SAT
required inductance is a function of operating frequen-
cy, input-to-output voltage differential, and the peak-to-
peak inductor current (∆I ). Higher ∆I
allows for a
requires a
P-P
P-P
P-P
lower inductor value, while a lower ∆I
higher inductor value. A lower inductor value minimizes
size and cost and improves large-signal and transient
response, but reduces efficiency due to higher peak
currents and higher peak-to-peak output voltage ripple
for the same output capacitor. On the other hand, high-
er inductance increases efficiency by reducing the rip-
ple current. Resistive losses due to extra wire turns can
exceed the benefit gained from lower ripple current lev-
els, especially when the inductance is increased while
keeping the dimension of the inductor constant. A good
Thermal Protection
When the junction temperature exceeds T = +165°C,
J
an internal thermal sensor signals the shutdown logic,
which turns off the regulator (both in Buck Mode and
LDO Mode), and discharges the soft-start capacitor
allowing the IC to cool. The thermal sensor turns the
regulator on again after the IC’s junction temperature
cools by 20°C, resulting in a cycled output during con-
tinuous thermal-overload conditions. The thermal hys-
teresis and a soft-start period limit the average power
dissipation into the device during continuous fault con-
dition. During operation, do not exceed the absolute
compromise is to choose ∆I
equal to 40% of the full
P-P
load current. Calculate the inductor value using the fol-
lowing equation:
V
V
(V − V
)
OUT IN
OUT
L =
× f × ∆I
P−P
IN SW
maximum junction temperature rating of T = +150°C.
J
______________________________________________________________________________________ 13
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
5V TO 40V
V
IN
V
IN
BP
1.0µF
C
IN
EN
100µF
22µH
LDO/BUCK
SYNC
V
OUT
LX
D1*
+
C
22µF
OUT
B260/
MURS105
MAX5096
MAX5097
COMP
R1
R
C
ADJ
OUT
R2
C
C
C
P
R
PU
SS
CT
RESET
RESET
*USE MURS105 IN APPLICATIONS
WHERE LDO MODE QUIESCENT
CURRENT IS CRITICAL.
GND
PGND
C
SS
C
CT
Figure 4. Adjustable Output Voltage Configuration
use typical values of V and f
so that efficiency is opti-
IN
SW
Table 1. Inductor/Output Capacitor
Selection
mum for typical conditions. The switching frequency (f
)
SW
is fixed at 135kHz (MAX5096) and 330kHz (MAX5097).
can also be varied from 120kHz to 500kHz
f
SW
INDUCTOR
OUTPUT CAPACITOR (C
)
OUT
(MAX5096) and from 300kHz to 500kHz (MAX5097) when
synchronized to an external clock (see the Oscillator/
Synchronization Input (SYNC) section). The peak-to-peak
inductor current, which reflects the peak-to-peak output
ripple, is worst at the maximum input voltage. See the
Output Capacitor Selection section to verify that the
worst-case output ripple is acceptable. The inductor satu-
22µF, ESR = 5mΩ to 20mΩ (ceramic)
47µF, ESR = 40mΩ to 150mΩ
100µF, ESR = 30mΩ to 100mΩ
470µF / ESR = 60Ω to 400mΩ
22µF, ESR = 5mΩ to 20mΩ (ceramic)
47µF / ESR = 40mΩ to 150mΩ
100µF / ESR = 30mΩ to 100mΩ
470µF / ESR = 60mΩ to 400mΩ
22µF, ESR = 5mΩ to 20mΩ (ceramic)
47µF / ESR = 40mΩ to 150mΩ
100µF / ESR = 30mΩ to 100mΩ
470µF / ESR = 60mΩ to 400mΩ
22µH
rating current (I
) is also important to avoid runaway
SAT
47µH
current during continuous output short circuit. Select an
inductor with an I
specification higher than the maxi-
SAT
mum peak current limit of 1.9A.
The Buck Mode operation determines the inductor and
output capacitor values. However, the values of the
inductor, its DCR, and the output capacitance/ESR
affect the closed-loop transfer function both in Buck
and LDO Modes. The internal compensation of the
MAX5096/MAX5097 in LDO Mode limits the values of
these external components. Make sure that the combi-
nation of output inductor, capacitor, and ESR falls with-
in the range specified in following Table 1.
100µH
Output Capacitor Selection
The allowable output voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the output capacitance and its ESR. The output
14 ______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
ripple is mainly composed of ∆V (caused by the
where I
is the load step, t
is the rise time of the
STEP
Q
STEP
load step, and t
capacitor discharge) and ∆V
(caused by the volt-
is the response time of the
RESPONSE
ESR
age drop across the ESR of the output capacitor).
Normally, a good approximation of the output voltage
controller. The response time of the converter is
approximately one third of the inverse of its closed-loop
bandwidth and also depends on the phase margin.
ripple is ∆V
≈ ∆V
+ ∆V . If using ceramic
ESR Q
RIPPLE
capacitors, assume the contribution to the output volt-
age ripple from the ESR and the capacitor discharge to
be equal to 20% and 80%, respectively. If using alu-
minum electrolyte capacitors, assume the contribution
to the output voltage ripple from the ESR and the
capacitor discharge to be equal to 90% and 10%,
respectively.
Rectifier Selection
The MAX5096/MAX5097 require an external Schottky/
fast-recovery diode rectifier as a freewheeling diode.
Connect this rectifier close to the device using short
leads and short PC board traces. Choose a rectifier
with a continuous current rating greater than the high-
est output current-limit threshold (1.9A) and with a volt-
age rating greater than the maximum expected input
Use the following equations for calculating the output
capacitance and its ESR for required peak-to-peak out-
put voltage ripple.
voltage, V . Use a low forward-voltage-drop Schottky
IN
rectifier to limit the negative voltage at LX. Avoid higher
than necessary reverse-voltage Schottky rectifiers that
have higher forward-voltage drops. Use a 60V (max)
Schottky rectifier with a 2A current rating. The Schottky
rectifier leakage current at high temperature significant-
ly increases the quiescent current in LDO Mode. In
applications where LDO Mode quiescent current is
important, use an ultra-fast switching diode to limit the
leakage current. In this type of application, use
MURS105, MURS120 for their fast-switching and low-
leakage features.
∆I
P−P
C
=
OUT
16× ∆V × f
Q
SW
∆V
ESR
ESR=
∆I
P−P
∆I
is the peak-to-peak inductor current and f
is
SW
P-P
the converter’s switching frequency.
The allowable deviation of the output voltage during
fast load transients also determines the output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
Input Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents and therefore, the
input capacitor must be carefully chosen to keep the
input voltage ripple within design requirements. The
greater duty cycle. The response time (t
)
RESPONSE
depends on the closed-loop bandwidth of the converter
(see the Compensation Network section). The resistive
drop across the output capacitor’s ESR, the drop
across the capacitor’s ESL, and the capacitor dis-
charge, causes a voltage drop during the load step.
Use a combination of low-ESR tantalum/aluminum elec-
trolytic and ceramic capacitors for better transient load
and voltage ripple performance. Non-leaded capaci-
tors and/or multiple parallel capacitors help reduce the
ESL. Keep the maximum output voltage deviation
below the tolerable limits of the electronics being pow-
ered. Use the following equations to calculate the
required ESR, ESL, and capacitance value during a
load step:
input voltage ripple is comprised of ∆V (caused by
Q
the capacitor discharge) and ∆V
(caused by the
ESR
ESR of the input capacitor). The total voltage ripple is
the sum of ∆V and ∆V . Calculate the input capaci-
Q
ESR
tance and ESR required for a specified ripple using the
following equations (continuous mode):
∆V
ESR
ESR=
∆I
⎛
⎞
P−P
2
I
+
⎜
⎝
⎟
⎠
OUT_MAX
I
×D(1−D)
OUT_MAX
C
=
IN
∆V × f
Q
SW
where
∆V
ESR
ESR=
(V − V
)× V
OUT
× f ×L
IN
OUT
∆I
STEP
∆I
=
and
P−P
V
IN SW
I
× t
∆V
STEP RESPONSE
C
=
OUT
V
V
OUT
Q
D =
IN
∆V
× t
ESL STEP
ESL =
I
I
is the maximum output current and D is the
OUT_MAX
duty cycle.
STEP
______________________________________________________________________________________ 15
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Compensation Network
The MAX5096/MAX5097 in LDO Mode are compensat-
ed internally with a compensation network around the
LDO error amplifier. When in Buck Mode, the DC-DC
Switching Between LDO Mode
and Buck Mode
The MAX5096/MAX5097 switch between the Buck
Mode and LDO Mode on the fly. However, care must
be taken to reduce output glitch or overshoot during
the switching.
g
amplifier must be externally compensated using a
M
network connected from COMP to ground. The current-
mode control architecture reduces the compensation
network to a single pole-zero. The RC and C network,
connected from the internal transconductance amplifier
output to SGND, can provide a single pole-zero pair.
Choose all the power components like the inductor,
output capacitor, and ESR first and design the com-
pensation network around them. Choose the closed-
Buck Mode to LDO Mode
The LDO Mode is intended for the low 100mA output
current while the buck converter delivers up to 600mA
output current. It is important to first reduce the output
load below 100mA before switching to the LDO Mode.
If the output load is higher than 100mA, the
MAX5096/MAX5097 may go into the current limit and
the output will drop significantly. Whenever the mode is
changed, output is expected to glitch because the loop
dynamics change due to different error amplifiers when
operating in the LDO and Buck Modes. The output volt-
age undershoot can be minimized by reducing the out-
put load during switching and using larger output
capacitance.
loop bandwidth (f ) to be approximately 1/10 of the
C
switching frequency. See the following equations to cal-
culate the compensation values for the low-ESR output
capacitor with ESR zero frequency, approximately a
decade higher than f .
C
Calculate the dominant pole due to the output capaci-
tor (C
) and the load (R
):
OUT
OUT
1
f
=
PO
LDO Mode to Buck Mode
When switching from the LDO Mode to Buck Mode, a
fixed amount of delay (32 cycles) is applied so that the
buck converter control loop and oscillator reach their
steady-state conditions. The 32-cycle delay translates
to approximately 250µs and 100µs for 150kHz and
330kHz switching frequency versions, respectively. It is
recommended that the output load of 600mA must be
delayed by at least this much time to allow the
MAX5096/MAX5097 to switch to high-current Buck
Mode. This ensures that the output does not drop due
to the LDO current-limit protection mechanism.
2× π ×C
×R
OUT
OUT
where R
= V
/ I
.
OUT
OUT LOAD
Calculate the R using following equation:
C
V
× f
C
O
R
=
C
g
×R
×g × V × f
ADJ PO
MC
OUT
m
where g
is the control to output gain of the
MC
MAX5096/MAX5097 buck converter and is equal to
1.06. V
is the feedback set point equal to 1.237V
ADJ
and g (transconductance amplifier gain) is equal to
m
PC Board Layout Guidelines
136µS. See Figure 2.
1) Proper PC board layout is essential. Minimize
ground noise by connecting the anode of the free-
wheeling rectifier, the input bypass capacitor
ground lead, and the output filter capacitor ground
lead to a large PGND plane.
Place a zero (f ) at 0.9 x f
:
PO
Z
1
C
=
C
2× π ×R
× f
CFPO PO
2) Minimize lead lengths to reduce stray capacitance,
trace resistance, and radiated noise. In particular,
place the Schottky/fast recovery rectifier diode right
next to the device.
Finally, place a high-frequency pole at the frequency
equal to half of the converter switching frequency (f ).
SW
1
C =
P
π ×R × f
C
SW
Place the compensation network physically close to the
MAX5096/MAX5097.
16 ______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
3) Connect the exposed pad of the IC to the SGND
Chip Information
plane. Do not make a direct connection between the
exposed pad plane and SGND (pin 2) under the IC.
Connect the exposed pad and pin 2 to the SGND
plane separately. Connect the ground connection of
the feedback resistive divider, the soft-start capaci-
tor, the adjustable reset timeout capacitor, and the
compensation network to the SGND plane. Connect
the SGND plane and PGND plane at one point near
PROCESS: BiCMOS
the input bypass capacitor at V .
IN
4) Use the large SGND plane as a heatsink for the
MAX5096/MAX5097. Use large PGND and LX
planes as heatsinks for the rectifier diode and the
inductor.
Selector Guide
OUTPUT
VOLTAGE
(V)
SWITCHING
FREQUENCY
(kHz)
PART
MAX5096A_ _ _
MAX5096B_ _ _
MAX5097A_ _ _
MAX5097B_ _ _
+3.3/Adjustable
+5.0/Adjustable
+3.3/Adjustable
+5.0/Adjustable
135
135
330
330
______________________________________________________________________________________ 17
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
K
21-0140
2
18 ______________________________________________________________________________________
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
K
21-0140
2
______________________________________________________________________________________ 19
40V, 600mA Buck Converters with Low-
Quiescent-Current Linear Regulator Mode
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
XX XX
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY,
EXPOSED PAD
1
E
21-0108
1
Revision History
Pages changed at Rev 1: 1, 2, 3, 5, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
Boblet
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