MAX509BCPP_技术文档

19-0155; Rev 2; 1/96

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

♦ Single +5V or Dual ±5V Supply Operation

The MAX509/MAX510 are quad, serial-input, 8-bit volt-

age-output digital-to-analog converters (DACs). They

operate with a single +5V supply or dual ±5V supplies.

Internal, precision buffers swing rail-to-rail. The refer-

ence input range includes both supply rails.

♦ Output Buffer Amplifiers Swing Rail-to-Rail

♦ Reference Input Range Includes Both Supply Rails

♦ Calibrated Offset, Gain, and Linearity (1LSB TUE)

♦ 10MHz Serial Interface, Compatible with SPI, QSPI

The MAX509 has four separate reference inputs, allow-

ing each DAC's full-scale range to be set independently.

20-pin DIP, SSOP, and SO packages are available. The

MAX510 is identical to the MAX509 except it has two ref-

erence inputs, each shared by two DACs. The MAX510

is housed in space-saving 16-pin DIP and SO packages.

(CPOL = CPHA = 0) and Microwire

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy-Chaining

♦ Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

The serial interface is double-buffered: A 12-bit input

shift register is followed by four 8-bit buffer registers and

four 8-bit DAC registers. A 12-bit serial word is used to

load data into each register. Both input and DAC regis-

ters can be updated independently or simultaneously

with single software commands. Two additional asyn-

chronous control pins provide simultaneous updating

(LDAC) or clearing (CLR) of input and DAC registers.

______________Ord e rin g In fo rm a t io n

TUE

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

MAX509ACPP

MAX509BCPP

MAX509ACWP

MAX509BCWP

MAX509ACAP

MAX509BCAP

MAX509BC/D

0°C to +70°C

20 Plastic DIP

20 Wide SO

20 SSOP

±1

±1 1/2

±1

The interface is compatible with Microwire^TMand SPI/

QSPI^TM

. All digital inputs and outputs are TTL/CMOS

±1 1/2

±1

compatible. A buffered data output provides for read-

back or daisy-chaining of serial devices.

20 SSOP

±1 1/2

Dice*

Ordering Information continued on last page.

* Dice are specified at +25°C, DC parameters only.

_______________Fu n c t io n a l Dia g ra m s

**Contact factory for availability and processing to MIL-STD-883.

CLR

LDAC

DGND

AGND

V

SS

DOUT

V

DD

REFB REFA

_________________P in Co n fig u ra t io n s

MAX509

DECODE

CONTROL

TOP VIEW

OUTA

INPUT

REG A

DAC

REG A

DAC A

DAC B

DAC C

DAC D

OUTB

OUTA

OUTC

OUTD

V

1

2

20

19

OUTB

OUTC

OUTD

V

SS

3

18 DD

12-BIT

SHIFT

REGISTER

INPUT

REG B

DAC

REG B

REFB

REFC

4

MAX509

17

16

15

14

13

12

11

REFA

AGND

N.C.

REFD

CS

5

INPUT

REG C

6

DAC

REG C

N.C.

SCLK

DIN

7

DGND

LDAC

8

INPUT

REG D

DAC

REG D

SR

CONTROL

9

DOUT

CLR

10

REFD

DIP/SO/SSOP

SCLK

REFC

CS DIN

Pin Configurations continued at end of data sheet.

Microwire is a trademark of National Semiconductor. SPI and QSPI are trademarks of Motorola.

________________________________________________________________ Maxim Integrated Products

Functional Diagrams continued at end of data sheet.

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

ABSOLUTE MAXIMUM RATINGS

V

DD

to DGND ..............................................................-0.3V, +6V

to AGND...............................................................-0.3V, +6V

to DGND...............................................................-6V, +0.3V

to AGND ...............................................................-6V, +0.3V

20-Pin Plastic DIP (derate 11.11mW/°C above +70°C)....889mW

20-Pin Wide SO (derate 10.00mW/°C above +70°C) .......800mW

20-Pin SSOP (derate 10.00mW/°C above +70°C)............800mW

20-Pin CERDIP (derate 11.11mW/°C above +70°C) ........889mW

Operating Temperature Ranges:

V

DD

V

SS

V

SS

V

DD

to V .................................................................-0.3V, +12V

SS

Digital Input Voltage to DGND ......................-0.3V, (V + 0.3V)

MAX5_ _ _C_ _.....................................................0°C to +70°C

MAX5_ _ _E_ _ ..................................................-40°C to +85°C

MAX5_ _ _MJ_ ................................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

DD

REF_....................................................(V - 0.3V), (V + 0.3V)

SS

DD

OUT_..............................................................................V , V

DD SS

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (T = +70°C)

A

16-Pin Plastic DIP (derate 10.53mW/°C above +70°C)....842mW

16-Pin Wide SO (derate 9.52mW/°C above +70°C) .........762mW

16-Pin CERDIP (derate 10.00mW/°C above +70°C) ........800mW

Note: The outputs may be shorted to V , V , or AGND if the package power dissipation is not exceeded. Typical short-circuitcurrent

DD SS

to AGND is 50mA. Do not bias AGND more than +1V above DGND, or more than 2.5V below DGND.

9/MAX510

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

= +5V ±10%, V = 0V to -5.5V, V

= 4V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T

to T ,

MAX

DD

SS

REF

L

A

MIN

unless otherwise noted.)

PARAMETER

STATIC ACCURACY

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

8

Bits

MAX5_ _A

MAX5_ _B

MAX5_ _A

MAX5_ _B

±1

VREF = +4V,

= 0V or -5V ±10%

V

SS

VREF = -4V,

= -5V ±10%

±1.5

LSB

±1

Total Unadjusted Error

Differential Nonlinearity

TUE

DNL

V

SS

±1.5

Guaranteed monotonic

±1

14

16

LSB

MAX5_ _C

MAX5_ _E

Code = 00 hex,

V

= 0V

SS

MAX5_ _M

MAX5_ _C

MAX5_ _E

20

Zero-Code Error

ZCE

mV

±14

±16

Code = 00 hex,

= -5V ±10%

V

SS

MAX5_ _M

±20

Code = 00 hex, V = 5V ±10%,

DD

Zero-Code-Error Supply Rejection

1

2

mV

V

= 0V or -5V ±10%

SS

Zero-Code

Temperature Coefficient

Code = 00 hex

±10

µV/°C

mV

Full-Scale Error

Code = FF hex

Code = FF hex,

±14

4

MAX5_ _C

MAX5_ _E

MAX5_ _M

1

8

Full-Scale-Error Supply Rejection

V

DD

= +5V ±10%,

mV

V

SS

= 0V or -5V ±10%

12

Full-Scale-Error

Temperature Coefficient

Code = FF hex

±10

µV/°C

2

_______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

ELECTRICAL CHARACTERISTICS (continued)

(V

= +5V ±10%, V = 0V to -5.5V, V

= 4V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T

to T ,

MAX

DD

SS

REF

L

A

MIN

unless otherwise noted.)

PARAMETER

REFERENCE INPUTS

Input Voltage Range

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

V

SS

V

DD

MAX509

MAX510

MAX509

MAX510

16

24

12

Input Resistance (Note 1)

Input Capacitance (Note 2)

Code = 55 hex

kΩ

8

15

Code = 00 hex

pF

30

Channel-to-Channel Isolation

AC Feedthrough

(Note 3)

(Note 4)

-60

-70

dB

DAC OUTPUTS

Full-Scale Output Voltage

V

SS

V

DD

V

VREF = 4V, load regulation ≤ 1/4LSB

2

VREF = -4V, V = -5V ±10%,

SS

load regulation ≤ 1/4LSB

2

Resistive Load

kΩ

VREF = V MAX5_ _C/E,

DD

load regulation ≤ 1LSB

10

VREF = V MAX5_ _M,

DD

load regulation ≤ 2LSB

10

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Current

V

2.4

V

IH

V

IL

0.8

1.0

10

I

IN

V

= 0V or V

µA

pF

IN

DD

Input Capacitance

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

DYNAMIC PERFORMANCE

C

(Note 5)

IN

V

OH

I

= 0.2mA

V - 0.5

DD

V

SOURCE

V

OL

I

= 1.6mA

0.4

SINK

MAX5_ _C

MAX5_ _E

MAX5_ _M

1.0

0.7

0.5

Voltage-Output Slew Rate

Positive and negative

V/µs

Output Settling Time (Note 6)

Digital Feedthrough

To 1/2LSB, 10kΩ II 100pF load

6

5

µs

Code = 00 hex, all digital inputs

nV-s

from 0V to V

DD

Code 128➝127

Digital-to-Analog Glitch Impulse

12

87

VREF = 4V at 1kHz, V = 5V,

p-p

DD

code = FF hex

Signal-to-Noise + Distortion Ratio

SINAD

dB

VREF = 4V at 20kHz, V = -5V ±10%

74

1

p-p

SS

Multiplying Bandwidth

VREF = 0.5V , 3dB bandwidth

MHz

p-p

Wideband Amplifier Noise

60

µV

RMS

_______________________________________________________________________________________

3

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

ELECTRICAL CHARACTERISTICS (continued)

(V

= +5V ±10%, V = 0V to -5.5V, V

= 4V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T

to T ,

MAX

DD

SS

REF

L

A

MIN

unless otherwise noted.)

PARAMETER

POWER SUPPLIES

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

Positive Supply Voltage

Negative Supply Voltage

V

For specified performance

4.5

5.5

0

V

DD

V

SS

-5.5

MAX5_ _C/E

MAX5_ _M

5

10

12

Outputs unloaded, all

digital inputs = 0V or V

Positive Supply Current

I

DD

mA

DD

V

= -5V ±10%, outputs

SS

MAX5_ _C/E

MAX5_ _M

5

10

12

Negative Supply Current

I

SS

unloaded, all digital

inputs = 0V or V

mA

DD

Note 1: Input resistance is code dependent. The lowest input resistance occurs at code = 55 hex.

Note 2: Input capacitance is code dependent. The highest input capacitance occurs at code = 00 hex.

Note 3: VREF = 4V , 10kHz. Channel-to-channel isolation is measured by setting the code of one DAC to FF hex and setting the

p-p

9/MAX510

code of all other DACs to 00 hex.

Note 4: VREF = 4V , 10kHz. DAC code = 00 hex.

p-p

Note 5: Guaranteed by design.

Note 6: Output settling time is measured by taking the code from 00 hex to FF hex, and from FF hex to 00 hex.

TIMING CHARACTERISTICS

(V

= +5V ±10%, V = 0V to -5V, V

= 4V, AGND = DGND = 0V, C = 50pF, T = T

to T , unless otherwise noted.)

MAX

DD

SS

REF

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

40

50

0

TYP

20

MAX UNITS

MAX5_ _C/E

MAX5_ _M

(Notes 7, 8)

MAX5_ _C/E

MAX5_ _M

t

ns

LDAC Pulse Width Low

LDW

25

t

CS Rise to LDAC Fall Setup Time

CLR Pulse Width Low

CLL

40

50

20

25

t

CLW

SERIAL INTERFACE TIMING

CS Fall to SCLK Setup Time

MAX5_ _C/E

MAX5_ _M

40

50

0

t

ns

CSS

t

ns

SCLK Fall to CS Rise Hold Time

SCLK Rise to CS Rise Hold Time

SCLK Fall to CS Fall Hold Time

CSH2

t

(Note 9)

40

0

CSH1

t

(Note 7)

CSH0

MAX5_ _C/E

MAX5_ _M

40

50

0

DIN to SCLK Rise Setup Time

DIN to SCLK Rise Hold Time

SCLK Clock Frequency

t

ns

DS

t

ns

DH

MAX5_ _C/E

MAX5_ _M

MAX5_ _C/E

MAX5_ _M

MAX5_ _C/E

MAX5_ _M

MAX5_ _C/E

MAX5_ _M

20

12.5

MHz

10

f

CLK

40

50

40

50

10

SCLK Pulse Width High

SCLK Pulse Width Low

t

ns

CH

t

CL

100

ns

SCLK to DOUT Valid

t

DO

100

Note 7: Guaranteed by design.

Note 8: If LDAC is activated prior to CS's rising edge, it must stay low for t

Note 9: Minimum delay from 12th clock cycle to CS rise.

or longer after CS goes high.

LDW

4

_______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(T = +25°C, unless otherwise noted.)

A

SUPPLY CURRENT

vs. TEMPERATURE

OUTPUT SOURCE CURRENT

vs. OUTPUT VOLTAGE

OUTPUT SINK CURRENT

vs. (V - V

)

OUT SS

-25

-20

7

6

12

10

V

= VREF = +5V

= GND

DD

V

SS

DIGITAL INPUT = FF HEX

5

4

3

2

1

0

I

8

6

4

2

0

DD

-15

-10

-5

I

SS

V

SS

= +5.5V

= -5.5V

DD

V

= VREF = +5V

= GND = 0V

DD

VREF = -4.75

ALL DIGITAL INPUTS = +5V

V

SS

ALL DIGITAL INPUTS = 00 HEX

0

3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

-60 -40 -20

0

20 40 60 80 100 120 140

0

0.2

0.4

0.6

0.8

1.0

1.2

V

OUT

(V)

TEMPERATURE (°C)

V

OUT

- V (V)

SS

THD + NOISE AT DAC OUTPUT

vs. REFERENCE FREQUENCY

SUPPLY CURRENT

vs. REFERENCE VOLTAGE

THD + NOISE AT DAC OUTPUT

vs. REFERENCE AMPLITUDE

-20

-30

-40

-50

-60

10%

1%

6

5

-40

1%

V

SS

= +5V

= -5V

DD

V

= +5V

= -5V

DD

-45

-50

SS

V

SS

= 0V

INPUT CODE = FF HEX

FREQ = SWEPT

INPUT CODE = FF HEX

V

= -5V

SS

4

3

2

1

0

-55

-60

-65

-70

-75

-80

-85

-90

0.1%

VREF = 8Vp-p

0.1%

0.01%

FREQ = 20kHz

-70

-80

-90

VREF = 1Vp-p

FREQ = 1kHz

V

DD

= +5V

ALL LOGIC

INPUTS = +5V

0.01%

VREF = 4Vp-p

1k

10

100

10k

100k

-5 -4 -3 -2 -1

0

1

2

3

4

5

0

2

4

6

8

10

REFERENCE FREQUENCY (Hz)

VREF VOLTAGE (V)

REFERENCE AMPLITUDE (Vp-p)

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

0

-10

-20

-30

-20

-30

-20

-30

V

DD

= +5V

V

DD

= +5V

V

= +5V

= -5V

DD

V

= AGND

V

= AGND

SS

V

SS

VREF = 2.5VDC + 0.5Vp-p SINE WAVE

VREF = 2.5VDC + 0.05Vp-p SINE WAVE

-40

VREF = 2.5VDC + 4Vp-p SINE WAVE

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

1k

10k

100k

1M

10M

FREQUENCY (Hz)

_______________________________________________________________________________________

5

Qu a d , S e ria l 8 -DACs

w it h Ra il-t o -Ra il Ou t p u t s

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T = +25°C, unless otherwise noted.)

A

ZERO-CODE ERROR

vs. NEGATIVE SUPPLY VOLTAGE

5.0

REFERENCE FEEDTHROUGH AT 40kHz

WORST-CASE 1LSB DIGITAL STEP CHANGE

2V

20mV

V

= +5V

DD

VREF = +4V

4.8

4.6

4.4

4.2

4.0

3.8

3.6

3.4

A

B

200nS

9/MAX510

A = REFA, 10V

p-p

A = CS, 2V/div

B = OUTA, 20mV ˜

TIMEBASE = 200ns/div

0

-1

-2

-3

(V)

-4

-5

-6

B = OUTA, 100µV/div, UNLOADED

TIMEBASE = 10µs/div

= +5V, V = -5V

DD SS

CODE = ALL 0s

V

SS

V

REFERENCE FEEDTHROUGH AT 10kHz

REFERENCE FEEDTHROUGH AT 4kHz

50µV

REFERENCE FEEDTHROUGH AT 400Hz

5V

A

B

10

100µS

A = REFA, 10V

p-p

A = REFA, 10V

p-p

A = REFA, 10V

p-p

B = OUTA, 50µV/div, UNLOADED

TIMEBASE = 50µs/div

B = OUTA, 50µV/div, UNLOADED

TIMEBASE = 100µs/div

B = OUTA, 50µV/div, UNLOADED

TIMEBASE = 1ms/div

6

_______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T = +25°C, unless otherwise noted.)

A

POSITIVE SETTLING TIME

(V = AGND OR -5V)

SS

CLOCK FEEDTHROUGH

5V

100mV

A

B

A

B

1µS

A = DIGITAL INPUT, 5V/div

B = OUT_ , 2V/div

TIMEBASE = 1µs/div

A = SCLK, 333kHz

B = OUT_, 10mV/div

TIMEBASE = 2µs/div

V

DD

= +5V

REF_ = +4V

ALL BITS OFF TO ALL BITS ON

R = 10kΩ, C = 100pF

L

NEGATIVE SETTLING TIME

(V = -5V)

(V = AGND)

SS

5V

100mV

5V

100mV

A

B

1µS

A = DIGITAL INPUT, 5V/div

B = OUT_ , 2V/div

A = DIGITAL INPUT, 5V/div

B = OUT_ , 2V/div

TIMEBASE = 1µs/div

V

DD

= +5V

V = +5V

DD

REF_ = +4V

ALL BITS ON TO ALL BITS OFF

R = 10kΩ, C = 100pF

L

R = 10kΩ, C = 100pF

L L

_______________________________________________________________________________________

7

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

MAX509 MAX510

OUTB

OUTA

DAC B Voltage Output

DAC A Voltage Output

1

2

3

–

4

–

5

–

6

2

3

V

SS

Negative Power Supply, 0V to -5V ±10%. Connect to AGND for single-supply operation.

Reference Voltage Input for DAC B

Reference Voltage Input for DACs A and B

Reference Voltage Input for DAC A

Analog Ground

4

REFB

REFAB

REFA

AGND

N.C.

–

5

6

9/MAX510

7, 14

8

Not Internally Connected

DGND

Digital Ground

Load DAC Input (active low). Driving this asynchronous input low (level sensitive)

transfers the contents of each input latch to its respective DAC latch.

9

7

8

9

LDAC

Serial Data Output. Can sink and source current. Data at DOUT is adjustable to be

clocked out on rising or falling edge of SCLK.

10

11

DOUT

Clear DAC input (active low). Driving CLR low causes an asynchronous clear of input

and DAC registers and sets all DAC outputs to zero.

CLR

DIN

Serial Data Input. TTL/CMOS-compatible input. Data is clocked into DIN on the

rising edge of SCLK. CS must be low for data to be clocked in.

12

13

15

10

11

12

Serial Clock Input. Data is clocked in on the rising edge and clocked out on either the

rising (default) or the falling edge.

SCLK

CS

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming

commands are executed when CS rises.

16

–

REFD

REFCD

REFC

Reference Voltage Input for DAC D

Reference Voltage Input for DACs C and D

Reference Voltage Input for DAC C

Positive Power Supply, +5V ±10%

DAC D Output Voltage

13

–

17

18

19

20

14

15

16

V

DD

OUTD

OUTC

DAC C Output Voltage

8

_______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

b e twe e n up d a te s . DOUT d oe s not g o into a hig h-

impedance state if the clock or CS is high.

_______________De t a ile d De s c rip t io n

S e ria l In t e rfa c e

At p owe r-on, the s e ria l inte rfa c e a nd a ll DACs a re

cleared and set to code zero. The serial data output

(DOUT) is set to transition on SCLK's rising edge.

Serial data is clocked into the data registers in MSB-

first format, with the address and configuration infor-

ma tion p re c e d ing the a c tua l DAC d a ta . Da ta is

clocked in on SCLK's rising edge while CS is low. Data

at DOUT is clocked out 12 clock cycles later, either at

SCLK's rising edge (default or mode 1) or falling edge

(mode 0).

The MAX509/MAX510 communicate with microproces-

sors through a synchronous, full-duplex, 3-wire inter-

face (Figure 1). Data is sent MSB first and can be

transmitted in one 4-bit and one 8-bit (byte) packet or

in one 12-bit word. If a 16-bit control word is used, the

first four bits are ignored. A 4-wire interface adds a line

for LDAC and allows asynchronous updating. The serial

clock (SCLK) synchronizes the data transfer. Data is

transmitted and received simultaneously.

Chip select (CS) must be low to enable the DAC. If CS

is high, the interface is disabled and DOUT remains

unchanged. CS must go low at least 40ns before the

first rising edge of the clock pulse to properly clock in

the firs t b it. With CS low, d a ta is c loc ke d into the

MAX509/MAX510's internal shift register on the rising

edge of the external serial clock. SCLK can be driven

at rates up to 12.5MHz.

Fig ure 2 s hows a d e ta ile d s e ria l inte rfa c e timing .

Please note that the clock should be low if it is stopped

INSTRUCTION

EXECUTED

CS

• • •

SCLK

DIN

• • •

A1

C1

A1

C0

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

A1 A0 C1 C0

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

A0

DACA

DACD

DOUT

MODE 1

(DEFAULT)

• • •

A1

A0 C1 C0 D7

D0

D6 D5 D4 D3 D2 D1

A1 A0 C1 C0 D7

D6 D5 D4 D3 D2 D1 D0

A1

DATA FROM PREVIOUS DATA INPUT

DOUT

MODE 0

• • •

D0

A1 A0 C1 C0 D7

D6 D5 D4 D3 D2 D1 D0

A1 A0 C1 C0 D7

D6 D5 D4 D3 D2 D1

A1

Figure 1. MAX509/MAX510 3-Wire Interface Timing

_______________________________________________________________________________________

9

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

t

CLL

CS

t

CSH2

• • •

t

CH

CSS

t

CSH0

• • •

SCLK

DIN

t

CL

t

DS

t

CSH1

t

DH

• • •

9/MAX510

t

DO

• • •

DOUT

LDAC

• • •

NOTE: TIMING SPECIFICATION t IS RECOMMENDED TO MINIMIZE OUTPUT GLITCH, BUT IS NOT MANDATORY.

CLL

t

LDW

Figure 2. Detailed Serial Interface Timing (Mode 0 Shown)

Table 1. Serial-Interface Programming Commands

12-Bit Serial Word

LDAC

Function

A1

A0

C1

C0

D7 . . . . . . . . D0

0

1

0

1

0

1

0

1

8-Bit DAC Data

1

Load DAC A input register, DAC output unchanged.

Load DAC B input register, DAC output unchanged.

Load DAC C input register, DAC output unchanged.

Load DAC D input register, DAC output unchanged.

0

1

0

1

0

1

8-Bit DAC Data

1

Load input and DAC register A.

Load input and DAC register B.

Load input and DAC register C.

Load input and DAC register D.

X

0

1

0

8-Bit DAC Data

X X X X X X X X

X

Update all DACs from shift register.

No Operation (NOP), shifts data in shift register.

“LDAC” Command, all DACs updated from respective

input registers.

0

1

X

1

0

X X X X X X X X

X

Mode 1, DOUT clocked out on rising edge of SCLK

(default). All DACs updated from respective input

registers.

1

Mode 0, DOUT clocked out on falling edge of SCLK.

All DACs updated from input registers.

0

10 ______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

Serial Input Data Format and Control Codes

The 12-bit serial input format shown in Figure 3 com-

prises two DAC address bits (A1, A0), two control bits

(C1, C0) and eight bits of data (D0...D7).

Update All DACs from Shift Registers

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

x

0

8-Bit DAC Data

(LDAC = x)

The 4-bit address/control code configures the DAC as

shown in Table 1.

All four DAC registers are updated with shift-register

data. This command allows all DACs to be set to any

analog value within the reference range. This command

can be used to substitute CLR if code 00 hex is pro-

grammed, which clears all DACs.

This is the first bit shifted in

MSB

LSB

● ● ●

A1

A0

C1 C0

D7 D1D6 D0

DOUT

DIN

No Operation (NOP)

Control and

Address bits

8-bit DAC data

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

x

1

0

x

Figure 3. Serial Input Format

(LDAC = x)

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

The NOP command (no operation) allows data to be shift-

ed through the MAX509/MAX510 shift register without

affecting the input or DAC registers. This is useful in daisy

chaining (also see the Daisy-Chaining Devices section).

For this command, the data bits are "Don't Cares." As an

example, three MAX509/MAX510s are daisy-chained (A, B

and C), and DAC A and DAC C need to be updated. The

36-bit-wide command would consist of one 12-bit word for

device C, followed by an NOP instruction for device B and

a third 12-bit word with data for device A. At CS's rising

edge, only device B is not updated.

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

Address

0

1

8-Bit Data

(LDAC = H)

When performing a single update operation, A1 and A0

select the respective input register. At the rising edge

of CS, the selected input register is loaded with the cur-

re nt s hift-re g is te r d a ta . All DAC outp uts re ma in

unchanged. This preloads individual data in the input

register without changing the DAC outputs.

“LDAC” Command (Software)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

Load Input and DAC Registers

0

x

1

0

x

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

(LDAC = x)

Address

1

8-Bit Data

All DAC registers are updated with the contents of their

respective input registers at CS's rising edge. With the

exception of using CS to execute, this performs the

same function as the asynchronous LDAC.

(LDAC = H)

This command directly loads the selected DAC register

at CS's rising edge. A1 and A0 set the DAC address.

Current shift-register data is placed in the selected

input and DAC registers.

Set DOUT Phase – SCLK Rising (Mode 1, Default)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

For example, to load all four DAC registers simultaneously

with individual settings (DAC A = 1V, DAC B = 2V, DAC

C = 3V and DAC D = 4V), five commands are required.

First, perform four single input register update opera-

tions. Next, perform an “LDAC” command as a fifth

command. All DACs will be updated from their respec-

tive input registers at the rising edge of CS.

1

0

x

(LDAC = x)

Mode 1 resets the serial output DOUT to transition at

SCLK's ris ing e d g e . This is the MAX509/MAX510’s

d e fa ult s e tting a fte r the s up p ly volta g e ha s b e e n

applied.

The command also loads all DAC registers with the con-

tents of their respective input registers, and is identical to

the “LDAC” command.

______________________________________________________________________________________ 11

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

Set DOUT Phase – SCLK Falling (Mode 0)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

SCLK

DIN

SK

SO

1

0

1

0

x

MAX509

MAX510

(LDAC = x)

MICROWIRE

PORT

DOUT

CS

SI

This command resets DOUT to transition at SCLK's falling

edge. Once this command is issued, the phase of DOUT is

latched and will not change except on power-up or if the

specific command is issued that sets the phase to rising

edge.

I/0

THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE

MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.

The same command also updates all DAC registers with

the contents of their respective input registers, identical to

the “LDAC” command.

Figure 4. Connections for Microwire

LDAC Operation (Hardware)

LDAC is typically used in 4-wire interfaces (Figure 7).

LDAC allows asynchronous hardware control of the DAC

outputs and is level-sensitive. With LDAC low, the DAC reg-

isters are transparent and any time an input register is

updated, the DAC output immediately follows.

9/MAX510

DOUT

DIN

MISO

MOSI

MAX509

MAX510

SPI

PORT

Clear DACs with CLR

Strobing the CLR pin low causes an asynchronous clear of

input and DAC registers and sets all DAC outputs to zero.

Similar to the LDAC pin, CLR can be invoked at any time,

typically when the device is not selected (CS = H). When

the DAC data is all zeros, this function is equivalent to the

"Update all DACs from Shift Registers" command.

SCLK

CS

SCK

I/0

CPOL = 0, CPHA = 0

THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE

MAX509/MAX510, BUT MAY BE USED FOR READ-BACK PURPOSES.

Digital Inputs and Outputs

Digital inputs and outputs are compatible with both TTL and

Figure 5. Connections for SPI

5V CMOS logic. The power-supply current (I ) depends

DD

The MAX509/MAX510 c a n inte rfa c e with Inte l's

80C5X/80C3X family in mode 0 if the SCLK clock polarity is

inverted. More universally, if a serial port is not available,

three lines from one of the parallel ports can be used for bit

manipulation.

on the input logic levels. Using CMOS logic to drive CS,

SCLK, DIN, CLR and LDAC turns off the internal level trans-

lators and minimizes supply currents.

Serial Data Output

DOUT is the output of the internal shift register. DOUT can be

programmed to clock out data on SCLK's falling edge (mode

0) or rising edge (mode 1). In mode 0, output data lags the

input data by 12.5 clock cycles, maintaining compatibility with

Microwire, SPI, and QSPI. In mode 1, output data lags the input

by 12 clock cycles. On power-up, DOUT defaults to mode 1

timing. DOUT never three-states; it always actively drives either

high or low and remains unchanged whenCS is high.

Digital feedthrough at the voltage outputs is greatly mini-

mized by operating the serial clock only to update the regis-

ters. Also see the Clock Feedthrough photo in the Typical

Operating Characteristics section. The clock idle state is low.

Daisy-Chaining Devices

Any number of MAX509/MAX510s can be daisy-chained by

connecting the DOUT pin of one device to the DIN pin of the

following device in the chain. The NOP instruction (Table 1)

allows data to be passed from DIN to DOUT without chang-

ing the input or DAC registers of the passing device. A three-

wire inte rfa c e up d a te s d a is y-c ha ine d or ind ivid ua l

MAX509/MAX510s simultaneously by bringing CS high.

Interfacing to the Microprocessor

The MAX509/MAX510 are Microwire, SPI, and QSPI compati-

ble. For SPI and QSPI, clear the CPOL and CPHA configura-

tion bits (CPOL = CPHA = 0). The SPI/QSPI CPOL = CPHA

= 1 configuration can also be used if the DOUT output is

ignored.

12 ______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

MAX509

MAX510

MAX509

MAX510

MAX509

MAX510

SCLK

DIN

CS

SCLK

DIN

CS

SCLK

DIN

CS

SCLK

DIN

CS

DOUT

TO OTHER

SERIAL DEVICES

MAX509

MAX510

SCLK

DIN

CS

SCLK

DIN

CS

Figure 6. Daisy-chained or individual MAX509/MAX510s are simultaneously updated by bringing CS high. Only three wires are

required.

DIN

SCLK

LDAC

CS1

TO OTHER

SERIAL

DEVICES

CS2

CS3

CS

MAX509

MAX510

MAX509

MAX510

MAX509

MAX510

LDAC

SCLK

DIN

SCLK

DIN

SCLK

DIN

Figure 7. Multiple MAX509/MAX510 DACs sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by

enabling individual CS.

______________________________________________________________________________________ 13

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

dependent: 15pF typical for the MAX509 and 30pF

typical for the MAX510.

The output voltage for any DAC can be represented by

a digitally programmable voltage source as:

R

OUT_

VOUT = (NB x VREF) / 256

where NB is the numerical value of the DAC's binary

input code.

2R

D0

2R

D5

2R

D6

2R

D7

Output Buffer Amplifiers

All MAX509/MAX510 volta g e outp uts a re inte rna lly

buffered by precision unity-gain followers that slew at

REF_

AGND

up to 1V/µs. The outputs can swing from V to V

.

SS

DD

With a 0V to +4V (or +4V to 0V) output transition, the

amplifier outputs will settle to 1/2LSB in typically 6µs

when loaded with 10kΩ in parallel with 100pF.

SHOWN FOR ALL 1 ON DAC

Figure 8. DAC Simplified Circuit Diagram

9/MAX510

The buffer amplifiers are stable with any combination of

resistive loads ≥ 2kΩ and capacitive loads ≤ 300pF.

If multiple devices share a common DIN line, Figure 7's

configuration provides simultaneous update by strob-

ing LDAC low. CS1, CS2, CS3... are driven separately,

thus controlling which data are written to devices 1, 2, 3....

__________Ap p lic a t io n s In fo rm a t io n

P o w e r S u p p ly a n d

Re fe re n c e Op e ra t in g Ra n g e s

The MAX509/MAX510 are fully specified to operate with

An a lo g S e c t io n

DAC Operation

The MAX509/MAX510 contain four matched voltage-

output DACs. The DACs are inverted R-2R ladder net-

works that convert 8-bit digital words into equivalent

analog output voltages in proportion to the applied ref-

erence voltages. Each DAC in the MAX509 has a sepa-

rate reference input, while the two reference inputs in

the MAX510 each share a pair of DACs. The two refer-

ence inputs permit different full-scale output voltage

ranges for each pair of DACs. A simplified diagram of

one of the four DACs is shown in Figure 8.

V

= 5V ±10% and V = 0V to -5.5V. 8-bit perfor-

DD

SS

mance is guaranteed for both single- and dual-supply

operation. The zero-code output error is less than 14mV

when operating from a single +5V supply.

The DACs work well with reference voltages from V

to V . The reference voltage is referred to AGND.

SS

DD

The preferred power-up sequence is to apply V and

then V , but bringing up both supplies at the same

time is also acceptable. In either case, the voltage

applied to REF should not exceed V

SS

DD

during power-

DD

up or at any other time. If proper power sequencing is

not p os s ib le , c onne c t a n e xte rna l Sc hottky d iod e

Reference Input

The MAX509/MAX510 c a n b e us e d for multip lying

applications. The reference accepts both DC and AC

signals. The voltage at each REF input sets the full-

scale output voltage for its respective DAC(s). If the ref-

e re nc e volta g e is p os itive , b oth the MAX509 a nd

MAX510 can be operated from a single supply. If dual

supplies are used, the reference input can vary from

between V and AGND to ensure compliance with the

SS

Absolute Maximum Ratings. Do not apply signals to

the digital inputs before the device is fully powered up.

P o w e r-S u p p ly Byp a s s in g

a n d Gro u n d Ma n a g e m e n t

In single-supply operation (AGND = DGND = V

=

SS

V

SS

to V , but is always referred to AGND. The input

0V), AGND, DGND a nd V

s hould b e c onne c te d

DD

SS

impedance at REF is code dependent, with the lowest

value (16kΩ for the MAX509 and 8kΩ for the MAX510)

occurring when the input code is 55 hex or 0101 0101.

The maximum value, practically infinity, occurs when

the input code is 00 hex. Since the REF input imped-

ance is code dependent, the DAC's reference sources

must have a low output impedance (no more than 32Ω

for the MAX509 and 16Ω for the MAX510) to maintain

output linearity. The REF input capacitance is also code

together in a "star" ground at the chip. This ground

should then return to the highest quality ground avail-

able. Bypass V

with a 0.1µF capacitor, located as

DD

close to V

and DGND as possible. In dual-supply

DD

operation, bypass V to AGND with 0.1µF.

SS

Careful PC board layout minimizes crosstalk among

DAC outp uts , re fe re nc e inp uts , a nd d ig ita l inp uts .

Figures 9 and 10 show suggested circuit board layouts

to minimize crosstalk.

14 ______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

SYSTEM GND

OUTC

OUTD

OUTB

OUTA

OUTC

OUTD

OUTB

OUTA

V

DD

V

SS

V

REFC

REFD

REFB

REFA

AGND

V

SS

DD

REFCD

REFAB

AGND

Figure 9. Suggested MAX509 PC Board Layout for Minimizing

Crosstalk (Bottom View)

Figure 10. Suggested MAX510 PC Board Layout for Minimizing

Crosstalk (Bottom View)

Un ip o la r-Ou t p u t , 2 -Qu a d ra n t Mu lt ip lic a t io n

In unipolar operation, the output voltages and the refer-

ence input(s) are the same polarity. Figures 11 and 12

show the MAX509/MAX510 unipolar configurations.

Both devices can be operated from a single supply if

the reference inputs are positive. If dual supplies are

Bip o la r-Ou t p u t , 2 -Qu a d ra n t Mu lt ip lic a t io n

Bipolar-output, 2-quadrant multiplication is achieved by

offsetting AGND positively or negatively. Table 3 shows

the bipolar code.

AGND can be biased above DGND to provide an arbi-

trary nonzero output voltage for a 0 input code, as

shown in Figure 13. The output voltage at OUTA is:

used, the reference input can vary from V to V

.

SS

DD

Table 2 shows the unipolar code.

V

OUTA

= V

+ (NB/256)(V ),

IN

BIAS

Table 3. Bipolar Code Table

Table 2. Unipolar Code Table

DAC CONTENTS

ANALOG

OUTPUT

ANALOG

OUTPUT

MSB

LSB

MSB

LSB

127

255

256

1 1 1 1

+V

REF

(

––––

128

)

1 1 1 1

+V

(

––––

)

REF

1

128

129

1 0 0 0

0 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

+V

(

––––

1 0 0 0

0 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

+V

––––

REF

256

0V

V

REF

128

––––

2

+V

(

––––

)

= +

REF

256

1

-V

(

––––)

128

REF

127

+V

(

––––

256

)

REF

127

0 0 0 0

0 0 0 1

0 0 0 0

-V

(

––––

)

REF

128

1

0 0 0 0

0 0 0 1

0 0 0 0

-8

+V

(

––––

REF

256

128

-V

(

––––

)

= -V

REF

0V

1

Note: 1LSB = (V ) (2 ) = +V_REF(––––)

REF

256

______________________________________________________________________________________ 15

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

REFERENCE INPUTS (V TO V

)

DD

+5V

18

V

DD

SS

16

+5V

18

V

DD

5

4

17

5

REFA REFB REFC REFD

REFA

2

OUTA

DAC A

2

OUTA

DAC A

V

IN

6

1

AGND

OUTB

OUTC

OUTD

DAC B

DAC C

DAC D

MAX509

SERIAL

INTERFACE

NOT SHOWN

V

BIAS

V

SS

DGND

8

3

20

-5V (OR GND)

+5V

9/MAX510

14

V

DD

4

REFAB

19

2

DGND

8

V

AGND

6

SS

OUTA

DAC A

3

V

IN

-5V (OR GND)

5

MAX509

AGND

MAX510

Figure 11. MAX509 Unipolar Output Circuit

V

DGND

6

V

BIAS

SS

3

-5V (OR GND)

SERIAL INTERFACE NOT SHOWN

REFERENCE INPUTS (V TO V

SS

)

DD

+5V

14

4

V

DD

REFAB

Figure 13. MAX509/MAX510 AGND Bias Circuits (Positive

Offset)

2

OUTA

DAC A

whe re NB re p re s e nts the d ig ita l inp ut word . Sinc e

AGND is common to all four DACs, all outputs will be

1

offset by V

in the same manner. Do not bias AGND

BIAS

OUTB

OUTC

OUTD

DAC B

DAC C

DAC D

more than +1V above DGND, or more than 2.5V below

DGND.

SERIAL

INTERFACE

NOT SHOWN

Figures 14 and 15 illustrate the generation of negative

offsets with bipolar outputs. In these circuits, AGND is

biased negatively (up to -2.5V with respect to DGND) to

provide an arbitrary negative output voltage for a 0

input code. The output voltage at OUTA is:

16

15

OUTA = -(R2/R1)(2.5V) + (NB/256)(2.5V)(R2/R1+1)

whe re NB re p re s e nts the d ig ita l inp ut word . Sinc e

AGND is common to all four DACs, all outputs will be

DGND

6

V

REFCD

AGND

5

SS

offs e t b y V

in the s a me ma nne r. Ta b le 3, with

3

13

BIAS

V

= 2.5V, shows the digital code vs. output voltage

REF

-5V (OR GND)

for Fig ure 14 a nd 15's c irc uits with R1 = R2. The

ICL7612 op amp is chosen because its common-mode

range extends to both supply rails.

MAX510

Figure 12. MAX510 Unipolar Output Circuit

16 ______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

REFERENCE INPUTS

+5V

0.1µF

5

4

17

16

18

V

DD

+5V

SERIAL

INTERFACE

NOT SHOWN

MAX509

0.1µF

2

1

OUTA

OUTB

DAC A

R1

330k

0.1%

R2

330k

0.1%

MAX873

DAC B

DAC C

DAC D

+2.5V

+5V

20

19

0.1µF

OUTC

OUTD

7

2

6

3

8

1

ICL7611A

DGND

8

V

AGND

6

SS

3

-5V

0.1µF

-5V

Figure 14. MAX509 AGND Bias Circuit (Negative Offset)

4 -Qu a d ra n t Mu lt ip lic a t io n

Each DAC output may be configured for 4-quadrant

multiplication using Figure 16 and 17's circuit. One op

amp and two resistors are required per channel. With

R1 = R2:

V_OUT= V_REF[2(NB/256)-1]

where NB represents the digital word in DAC register A.

The recommended value for resistors R1 and R2 is

330kΩ (±0.1%). Table 3 shows the digital code vs. out-

put voltage for Figure 16 and 17's circuit.

______________________________________________________________________________________ 17

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

+5V

14

REFERENCE INPUTS

13

4

+5V

0.1µF

V

DD

SERIAL

INTERFACE

MAX510

0.1µF

2

1

NOT SHOWN

OUTA

DAC A

2

R1

330k

0.1%

R2

330k

0.1%

6

MAX873

4

OUTB

DAC B

DAC C

DAC D

+2.5V

+5V

16

15

0.1µF

OUTC

OUTD

7

2

3

6

8

9/MAX510

1

ICL7611A

V

AGND

5

DGND

6

SS

3

-5V

0.1µF

-5V

Figure 15. MAX510 AGND Bias Circuit (Negative Offset)

REFERENCE INPUTS (V TO V

)

DD

SS

+5V

0.1µF

+5V

18

V

DD

5

4

17 16

R2

R1

0.1µF

MAX509

ICL7612A*

+5V

V

OUT

2

DAC A

OUTA

0.1µF

-5V

1

SERIAL

INTERFACE

NOT SHOWN

DAC B

DAC C

DAC D

OUTB

0.1µF

R2

20

OUTC

R1

ICL7612A*

V

OUT

19

OUTD

0.1µF

V

AGND

6

DGND

SS

-5V

3

8

0.1µF

*CONNECT ICL7612A PIN 8 TO AGND

AGND OR -5V

Figure 16. MAX509 Bipolar Output Circuit

18 ______________________________________________________________________________________

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

9/MAX510

REFERENCE INPUTS

+5V

14

V

4

13

0.1µF

DD

R1

MAX510

R2

ICL7612A*

V

OUT

2

DAC A

OUTA

0.1µF

-5V

+5V

1

SERIAL

INTERFACE

NOT SHOWN

DAC B

DAC C

DAC D

OUTB

16

R1

OUTC

R2

ICL7612A*

V

OUT

15

OUTD

0.1µF

V

DGND

6

SS

AGND

5

-5V

3

0.1µF

*CONNECT ICL7612A PIN 8 TO AGND

AGND OR -5V

Figure 17. MAX510 Bipolar Output Circuit

____P in Co n fig u ra t io n s (c o n t in u e d )

__Fu n c t io n a l Dia g ra m s (c o n t in u e d )

CLR

DOUT LDAC

DGND

AGND

V

SS

V

DD

REFB REFA

TOP VIEW

MAX509

DECODE

CONTROL

OUTA

OUTB

OUTA

OUTC

OUTD

V

1

2

3

4

5

6

7

8

16

15

INPUT

REG A

DAC

REG A

DAC A

DAC B

DAC C

DAC D

V

SS

14 DD

OUTB

OUTC

OUTD

REFAB

REFCD

MAX510

13

12

11

10

9

12-BIT

SHIFT

REGISTER

INPUT

REG B

DAC

REG B

AGND

DGND

LDAC

DOUT

CS

SCLK

DIN

CLR

INPUT

REG C

DAC

REG C

DIP/Wide SO

INPUT

REG D

DAC

REG D

SR

CONTROL

REFD

SCLK

REFC

CS DIN

______________________________________________________________________________________ 19

Qu a d , S e ria l 8 -Bit DACs

w it h Ra il-t o -Ra il Ou t p u t s

_Ord e rin g In fo rm a t io n (c o n t in u e d )

___________________Ch ip To p o g ra p h y

MAX509/MAX510

TUE

PART

TEMP. RANGE PIN-PACKAGE

OUTB

OUTD

V

SS

(LSB)

OUTA

OUTC

V

DD

MAX509AEPP

MAX509BEPP

MAX509AEWP

MAX509BEWP

MAX509AEAP

MAX509BEAP

MAX509AMJP

MAX509BMJP

MAX510ACPE

MAX510BCPE

MAX510ACWE

MAX510BCWE

MAX510AEPE

MAX510BEPE

MAX510AEWE

MAX510BEWE

MAX510AMJE

MAX510BMJE

-40°C to +85°C

20 Plastic DIP

20 Wide SO

20 SSOP

±1

REFC

(REFCD)

±1 1/2

±1

REFB

(REFAB)

REFD

(REFCD)

±1 1/2

±1

CS

REFA

(REFAB)

20 SSOP

±1 1/2

±1

0. 121"

(3. 07mm)

-55°C to +125°C 20 CERDIP**

AGND

±1 1/2

±1

0°C to +70°C

-40°C to +85°C

16 Plastic DIP

16 Wide SO

16 Plastic DIP

16 Wide SO

±1 1/2

±1

9/MAX510

DGND

SCLK

±1 1/2

±1

LDAC DOUT

CLR DIN

0. 128"

(3. 25mm)

±1 1/2

±1

±1 1/2

±1

NOTE: LABELS IN ( ) ARE FOR MAX510 ONLY.

-55°C to +125°C 16 CERDIP**

TRANSISTOR COUNT: 2235;

SUBSTRATE CONNECTED TO V

±1 1/2

.

DD

**Contact factory for availability and processing to MIL-STD-883.

________________________________________________________P a c k a g e In fo rm a t io n

INCHES

MILLIMETERS

DIM

MIN

0.068

MAX

0.078

0.008

0.015

0.009

0.289

0.212

MIN

1.73

0.05

0.25

0.13

7.07

5.20

MAX

1.99

0.21

0.38

0.22

7.33

5.38

A

e

A1 0.002

B

C

D

E

e

0.010

0.005

0.278

0.205

E

H

0.0256 BSC

0.65 BSC

H

L

0.301

0.311

0.037

8˚

7.65

0.55

0˚

7.90

0.95

0.022

0˚

α

8˚

21-0003A

D

α

A

0.127mm

0.004in.

20-PIN PLASTIC

SHRINK

SMALL-OUTLINE

PACKAGE

A1

B

C

L

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

20 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX509BCPP
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Quad, Serial 8-Bit DACs with Rail-to-Rail Outputs 四，串行8位DAC，具有轨至轨输出
文件：	总20页 (文件大小：235K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX509BCPP [MAXIM]

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