MAX5104EEE+T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 15us Settling Time, PDSO16, QSOP-16;
| 型号： | MAX5104EEE+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 15us Settling Time, PDSO16, QSOP-16 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1587; Rev 0; 11/99
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
MAX5104
Ge n e ra l De s c rip t io n
The MAX5104 low-power, serial, voltage-output, dual
12-bit digital-to-analog converter (DAC) consumes only
500µA from a single +5V supply. This device features
____________________________Fe a t u re s
♦ 12-Bit Dual DAC with Internal Gain of +2V/V
♦ Rail-to-Rail Output Swing
®
Rail-to-Rail output swing and is available in a space-
♦ 12µs Settling Time
saving 16-pin QSOP package. To maximize the dynamic
range, the DAC output amplifiers are configured with an
internal gain of +2V/V.
♦ +5V Single-Supply Operation
♦ Low Quiescent Current
500µA (normal operation)
2µA (power-down mode)
The 3-wire serial interface is SPI™/QSPI™/MICROWIRE™
compatible. Each DAC has a double-buffered input
organized as an input register followed by a DAC register,
which allows the input and DAC registers to be updated
independently or simultaneously with a 16-bit serial
word. Additional features include programmable power-
down (2µA), hardware power-down lockout (PDL), a
separate reference voltage input for each DAC that
accepts AC and DC signals, and an active-low clear
input (CL) that resets all registers and DACs to zero.
These devices provide a programmable logic pin for
added functionality, and a serial-data output pin for
daisy chaining.
♦ SPI/QSPI/MICROWIRE Compatible
♦ Space-Saving 16-Pin QSOP Package
♦ Power-On Reset Clears Registers and DACs to Zero
♦ Adjustable Output Offset
Ord e rin g In fo rm a t io n
PIN-
PACKAGE
INL
(LSB)
PART
TEMP. RANGE
________________________Ap p lic a t io n s
Industrial Process Control
MAX5104CEE
MAX5104EEE
0°C to +70°C
16 QSOP
16 QSOP
±4
±4
-40°C to +85°C
Remote Industrial Controls
Pin Configuration appears at end of data sheet.
Digital Offset and Gain Adjustment
Microprocessor-Controlled Systems
Motion Control
Automatic Test Equipment (ATE)
Fu n c t io n a l Dia g ra m
V
DD
CL
PDL
DGND
DOUT
AGND
REFA
OSA
R
DECODE
CONTROL
R
OUTA
OSB
DAC
REG A
INPUT
REG A
DAC A
16-BIT
SHIFT
R
REGISTER
MAX5104
R
SR
CONTROL
OUTB
DAC
REG B
INPUT
REG B
DAC B
REFB
LOGIC
OUTPUT
UPOH
CS
DIN
SCLK
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
to AGND............................................................-0.3V to +6V
to DGND ...........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.30mW/°C above +70°C).......667mW
Operating Temperature Ranges
MAX5104CEE ...................................................0°C to +70°C
MAX5104EEE.................................................-40C° to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
V
DD
AGND to DGND..................................................................±0.3V
OSA, OSB to AGND.......................(V - 4V) to (V + 0.3V)
REF_, OUT_ to AGND.................................-0.3V to (V + 0.3V)
AGND
DD
DD
Digital Inputs (SCLK, DIN, CS,
CL, PDL) to DGND...........................................(-0.3V to +6V)
Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V + 0.3V)
DD
Maximum Current into Any Pin .........................................±20mA
MAX5104
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +5V ±10%, V
= V
= +2.048V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values
MAX
DD
REFA
REFB
L
L
A
MIN
are at T = +25°C (OS_ connected to AGND for a gain of +2V/V).)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
(Note 1)
±4
±1
DNL
Guaranteed monotonic
Code = 10
LSB
V
OS
±10
mV
Offset Tempco
TCV
Normalized to 2.048V
4
-0.2
4
ppm/°C
LSB
OS
Gain Error
±8
Gain-Error Tempco
Normalized to 2.048V
ppm/°C
V
Power-Supply
DD
PSRR
REF
4.5V ≤ V ≤ 5.5V
20
600
µV/V
DD
Rejection Ratio
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
0
V
- 1.4
V
DD
R
Minimum with code 1554 hex
Input code = 1FFE hex,
14
20
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
300
-82
75
kHz
dB
V
REF_
= 0.67Vp-p at 2.5V
DC
Input code = 0000 hex,
= (V - 1.4Vp-p), f = 1kHz
Reference Feedthrough
V
REF_
DD
Signal-to-Noise plus
SINAD
Input code = 1FFE hex,
V = 1Vp-p at 1.25V , f = 25kHz
REF_
dB
Distortion Ratio
DC
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
3
V
V
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
= 0 to V
IN DD
C
IN
2
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
MAX5104
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V ±10%, V
= V
= +2.048V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values
MAX
DD
REFA
REFB
L
L
A
MIN
are at T = +25°C (OS_ connected to AGND for a gain of +2V/V).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DOUT, UPO)
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.40
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.75
15
V/µs
µs
To 1/2LSB of full-scale, V
= 4V
SCLK
STEP
Output Voltage Swing
OSA or OSB Input Resistance
Time Required to Exit Shutdown
Digital Feedthrough
Rail-to-rail (Note 2)
0 to V
V
DD
R
24
34
25
5
kΩ
µs
OS_
nVs
nVs
CS = V , SCLK = 100kHz, V
= 5Vp-p
DD
Digital Crosstalk
5
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
Power-Supply Current
V
4.5
5.5
V
DD
I
DD
(Note 3)
(Note 3)
0.5
2
0.65
mA
I
10
±1
µA
µA
DD(SHDN)
in Shutdown
Reference Current in Shutdown
TIMING CHARACTERISTICS
SCLK Clock Period
0
t
CP
(Note 4)
100
40
ns
ns
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise
Setup Time
t
40
0
ns
ns
CSS
SCLK Rise to CS Rise
Hold Time
t
CSH
SDI Setup Time
SDI Hold Time
t
40
0
ns
ns
DS
t
DH
SCLK Rise to DOUT
Valid Propagation Delay
t
t
C
C
= 200pF
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT
Valid Propagation Delay
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
CS0
CS1
t
t
100
CSW
Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for V greater than 6mV and less than V - 50mV. Guaranteed by PSRR test at the
OUT_
DD
end points.
Note 3: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.
DD
L
Note 4: SCLK minimum clock period includes the rise and fall times.
_______________________________________________________________________________________
3
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, R = 10kΩ, C = 100pF, OS_ pins connected to AGND, T = +25°C, unless otherwise noted.)
DD
L
L
A
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
0
700
650
600
550
500
450
400
-30
V
= +1Vp-p AT 2.5V
DC
-2
-4
REF
CODE = 1FFE (HEX)
CODE = 1FFE (HEX)
-40
-50
-60
-70
MAX5104
-6
-8
-10
-12
-14
-16
-18
-20
CODE = 0000 (HEX)
V
= +0.67Vp-p AT 2.5V
DC
REF
CODE = 1FFE (HEX)
V
REF
= +2.048V
R = ∞
L
-80
1
370
740
1110
1480
1850
-55 -35 -15
5
25 45 65 85 105 125
1
10
FREQUENCY (kHz)
100
FREQUENCY (kHz)
TEMPERATURE (°C)
FULL-SCALE ERROR vs. RESISTIVE LOAD
REFERENCE FEEDTHROUGH AT 1kHz
-50
0.50
0.25
0
V
REF
= +2.048V
V
= +3.6Vp-p AT 1.88V
DC
REF
CODE = 0000 (HEX)
-60
-70
-80
-0.25
-90
-0.50
-0.75
-1.00
-1.25
-1.50
-100
-110
-120
-130
-140
-150
0.1
1
10
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz)
R (kΩ)
L
SHUTDOWN CURRENT
vs. TEMPERATURE
OUTPUT FFT PLOT
0
6
5
4
3
2
1
0
V
= +1V
V
= +2.45Vp-p AT 1.225V
REF
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
REF DC
f = 1kHz
CODE = 1FFE (HEX)
NOTE: RELATIVE TO FULL SCALE
0.5
1.6
2.7
3.8
4.9
6.0
-55 -35 -15
5
25 45 65 85 105 125
TEMPERATURE (°C)
FREQUENCY (kHz)
4
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
MAX5104
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, R = 10kΩ, C = 100pF, OS_ pins connected to AGND, T = +25°C, unless otherwise noted.)
DD
L
L
A
DYNAMIC RESPONSE RISE TIME
DYNAMIC RESPONSE FALL TIME
CS
CS
5V/div
5V/div
OUT_
1V/div
OUT_
1V/div
2µs/div
2µs/div
V
REF
= +2.048V
V
REF
= +2.048V
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAJOR-CARRY TRANSITION
0.60
0.55
CODE = 1FFE (HEX)
CS
2V/div
0.50
0.45
0.40
CODE = OOOO (HEX)
OUT_
50mV/div
AC-COUPLED
4.50
4.75
5.00
5.25
5.50
5µs/div
SUPPLY VOLTAGE (V)
TRANSITION FROM 1000 (HEX) TO 0FFE (HEX)
ANALOG CROSSTALK
DIGITAL FEEDTHROUGH
SCLK
5V/div
OUTA
5V/div
OUTA
500µV/div
AC-COUPLED
OUTB
200µV/div
AC-COUPLED
250µs/div
2.5µs/div
V
REF
= +2.048V, GAIN = +2V/V, CODE = 1FFE HEX
_______________________________________________________________________________________
5
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
_____________________P in De s c rip t io n
OS_
R
R
PIN
1
NAME
AGND
OUTA
OSA
FUNCTION
Analog Ground
2
DAC A Output Voltage
DAC A Offset Adjustment
Reference for DAC A
OUT_
R
R
R
3
4
REFA
2R
2R
D0
2R
D10
2R
D11
2R
D12
MAX5104
Active-Low Clear Input. Resets all reg-
isters to zero. DAC outputs go to 0V.
5
CL
6
7
Chip-Select Input
Serial-Data Input
CS
REF_
DIN
AGND
8
SCLK
DGND
DOUT
UPO
Serial-Clock Input
Digital Ground
Figure 1. Simplified DAC Circuit Diagram
9
10
11
Serial-Data Output
User-Programmable Output
V
OUT
= (V
· NB / 4096) · 2
REF
where NB is the numeric value of the DAC’s binary input
code (0 to 4095) and V is the reference voltage.
REF
Power-Down Lockout. The device can-
not be powered down when PDL is low.
12
PDL
The reference input impedance ranges from 14kΩ (1554
hex) to several gigohms (with an input code of 0000
hex). The reference input capacitance is code depen-
dent and typically ranges from 15pF with an input code
of all zeros to 50pF with a full-scale input code.
13
14
15
16
REFB
OSB
Reference for DAC B
DAC B Offset Adjustment
DAC B Output Voltage
Positive Power Supply
OUTB
Ou t p u t Am p lifie r
The MAX5104’s output amplifiers have internal resistors
that provide for a gain of +2V/V when OS_ is connected
to AGND. These resistors are trimmed to minimize gain
error. The output amplifiers have a typical slew rate of
0.75V/µs and settle to 1/2LSB within 15µs, with a load
of 10kΩ in parallel with 100pF. Loads less than 2kΩ
degrade performance.
V
DD
_______________De t a ile d De s c rip t io n
The MAX5104 dual, 12-bit, voltage-output DAC is easily
configured with a 3-wire serial interface. The device
includes a 16-bit data-in/data-out shift register, and
each DAC has a double-buffered input composed of an
inp ut re g is te r a nd a DAC re g is te r (s e e Func tiona l
Diagram). In addition, trimmed internal resistors produce
an internal gain of +2V/V that maximizes output voltage
swing. The amplifier’s offset-adjust pin allows for a DC
shift in the DAC’s output.
The OS_ pin can be used to produce an adjustable off-
set voltage at the output. For instance, to achieve a 1V
offset, apply -1V to the OS_ pin to produce an output
range from 1V to (1V + V
· 2). Note that the DAC’s
REF
output range is still limited by the maximum output voltage
specification.
Both DACs use an inverted R-2R ladder network that
produces a weighted voltage proportional to the input
voltage value. Each DAC has its own reference input to
facilitate independent full-scale values. Figure 1 depicts
a simplified circuit diagram of one of the two DACs.
P o w e r-Do w n Mo d e
The MAX5104 features a software-programmable shut-
down mode that reduces the typical supply current to
2µA. The two DACs can be powered down indepen-
dently, or simultaneously using the appropriate pro-
g ra mming c omma nd . Ente r p owe r-d own mod e b y
writing the appropriate input-control word (Table 1). In
power-down mode, the reference inputs and amplifier
outputs become high impedance, and the serial inter-
face remains active. Data in the input registers is saved,
Re fe re n c e In p u t s
The reference inputs accept both AC and DC values
with a voltage range extending from 0 to (V - 1.4V).
DD
Determine the output voltage using the following equa-
tion (OS_ = AGND):
6
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
MAX5104
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
D11.......................D0
A0 C1
C0
S0
(MSB)
(LSB)
0
1
0
1
0
0
1
1
1
1
0
0
12-bit DAC data
0
0
0
0
Load input register A; DAC registers are unchanged.
Load input register B; DAC registers are unchanged.
Load input register A; all DAC registers are updated.
Load input register B; all DAC registers are updated.
12-bit DAC data
12-bit DAC data
12-bit DAC data
Load all DAC registers from the shift register
(start up both DACs with new data).
0
1
1
12-bit DAC data
0
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
1
1
0
0
1
0
0
1
0
XXXXXXXXXXXX
XXXXXXXXXXXX
0
0
0
Shut down both DACs (provided PDL = 1).
Update DAC register A from input register A
(start up DAC A with data previously stored in input register A).
0 0 1 X XXXXXXXX
Update DAC register B from input register B
(start up DAC B with data previously stored in input register B).
0
0
0
1 0 1 X XXXXXXXX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 0 X XXXXXXXX
1 1 1 X XXXXXXXX
0 1 0 X XXXXXXXX
0 1 1 X XXXXXXXX
1 0 0 1 XXXXXXXX
1 0 0 0 XXXXXXXX
0 0 0 X XXXXXXXX
0
0
0
0
0
0
0
Power Down DAC A (provided PDL = 1).
Power Down DAC B (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
No operation (NOP).
X = Don’t care
Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub-bit, always zero.
allowing the MAX5104 to recall the output state prior to
entering power-down when returning to normal mode.
Exit power-down by recalling the previous condition or
b y up d a ting the DAC with ne w informa tion. Whe n
SCLK
SK
returning to normal operation (exiting power-down),
wait 20µs for output stabilization.
MICROWIRE
PORT
MAX5104
DIN
CS
SO
I/O
S e ria l In t e rfa c e
The MAX5104’s 3-wire serial interface is compatible
with both MICROWIRE (Figure 2) and SPI/QSPI (Figure 3)
serial-interface standards. The 16-bit serial input word
consists of 1 address bit, 2 control bits, 12 bits of data
(MSB to LSB), and 1 sub-bit as shown in Figure 4. The
address and control bits determine the MAX5104’s
response, as outlined in Table 1.
Figure 2. Connections for MICROWIRE
_______________________________________________________________________________________
7
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
The MAX5104’s d ig ita l inp uts a re d oub le buffe re d,
which allows any of the following: loading the input reg-
+5V
ister(s) without updating the DAC register(s), updating
the DAC register(s) from the input register(s), or updating
the input and DAC registers concurrently. The address
and control bits allow the DACs to act independently.
SS
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, MICROWIRE), with CS low during
DIN
MOSI
SCK
this period. The address and control bits determine
which register will be updated, and the state of the reg-
isters when exiting power-down. The 3-bit address/con-
trol determines the following:
MAX5104
SPI/QSPI
PORT
MAX5104
SCLK
• Registers to be updated
CS
I/O
• Clock edge on which data is to be clocked out via the
serial-data output (DOUT)
CPOL = 0, CPHA = 0
• State of the user-programmable logic output
• Configuration of the device after power-down
Figure 3. Connections for SPI/QSPI
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data; otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maximum
clock frequency guaranteed for proper operation is
10MHz. Figure 6 shows a more detailed timing diagram
of the serial interface.
MSB...................................................................................LSB
16 Bits of Serial Data
Sub
Bit
Address Bits
A0
Control Bits
MSB...Data Bits...LSB
C1, C0
D11.......................D0
12 Data Bits
S0
0
1 Address/2 Control Bits
Figure 4. Serial-Data Format
CS
COMMAND
EXECUTED
SCLK
1
8
9
16
S0
C1
DIN
A0
C0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 5. Serial-Interface Timing Diagram
8
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
MAX5104
t
CSW
CS
t
CP
t
CSH
t
t
CH
CSS
t
t
CL
CSO
t
CS1
SCLK
DIN
t
DS
t
DH
Figure 6. Detailed Serial-Interface Timing Diagram
SCLK
SCLK
SCLK
MAX5104
MAX5104
MAX5104
DIN
CS
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 7. Daisy Chaining MAX5104s
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX5104
MAX5104
MAX5104
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 8. Multiple MAX5104s Sharing a Common DIN Line
_______________________________________________________________________________________
9
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
S e ria l-Da t a Ou t p u t
OS_
+5V/+3V
The serial-data output, DOUT, is the internal shift register’s
output. DOUT allows for daisy chaining of devices and
data readback. The MAX5104 can be programmed to
shift data out of DOUT on SCLK’s falling edge (Mode 0)
or on the rising edge (Mode 1). Mode 0 provides a lag
of 16 clock cycles, which maintains compatibility with
SPI/QSPI and MICROWIRE interfaces. In Mode 1, the
output data lags 15.5 clock cycles. On power-up, the
device defaults to Mode 0.
REF_
V
DD
R
R
MAX5104
DAC_
OUT_
MAX5104
AGND
DGND
Us e r-P ro g ra m m a b le Lo g ic Ou t p u t
User-programmable logic output (UPO) allows an external
device to be controlled through the serial interface
(Table 1), thereby reducing the number of microcontroller
I/O pins required. On power-up, UPO is low.
GAIN = +2V/V
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
P o w e r-Do w n Lo c k o u t In p u t
The power-down lockout (PDL) pin disables software
shutdown when low. When in power-down, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to power-down. PDL can also be
used to asynchronously wake up the device.
OS_
+5V/+3V
REF_
V
OS
V
DD
R
R
MAX5104
Da is y-Ch a in in g De vic e s
Any number of MAX5104s can be daisy-chained by
connecting the DOUT pin of one device to the DIN pin
of the following device in the chain (Figure 7).
DAC _
OUT_
AGND
DGND
Since the MAX5104’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines the
time required to discharge/charge a capacitive load.
See the digital output V and V specifications in the
Electrical Characteristics.
OH
OL
Figure 10. Setting OS_ for Output Offset
Table 2. Unipolar Code Table (Gain = +2)
Figure 8 shows an alternate method of connecting several
MAX5104s. In this configuration, the data bus is common
to all devices; data is not shifted through a daisy chain.
More I/O lines are required in this configuration because
a dedicated chip-select input (CS) is required for each IC.
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
4095
4096
1 1 1 1 1 1 1 1 11 1 1 (0 )
1 0 0 0 0 0 0 0 00 0 1 (0 )
1 0 0 0 0 0 0 0 00 0 0 (0 )
0 1 1 1 1 1 1 1 11 1 1 (0 )
0 0 0 0 0 0 0 0 0 0 0 1 (0 )
+V
REF
2
2
__________Ap p lic a t io n s In fo rm a t io n
2049
4096
Un ip o la r Ou t p u t
Figure 9 shows the MAX5104 configured for unipolar,
rail-to-rail operation with a gain of +2V/V. The MAX5104
can produce a 0 to 4.096V output with a 2.048V reference
(Figure 9). Table 2 lists the unipolar output codes. An
offset to the output can be achieved by connecting a
voltage to OS_, as shown in Figure 10. By applying
+V
REF
2048
4096
+V
REF
2 = V
REF
2047
+V
REF
2
2
4096
V
OS_
= -1V, the output values will range between 1V
and (1V + V
· 2).
REF
1
+V
REF
4096
Bip o la r Ou t p u t
The MAX5104 can be configured for a bipolar output
(Figure 11). The output voltage is given by the equation
(OS_ = AGND):
0 0 0 0 0 0 0 0 00 0 0 (0 )
0V
Note: ( ) are for the sub-bit.
10 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
MAX5104
V
= V
[((2 · NB) / 4096) - 1]
Ha rm o n ic Dis t o rt io n a n d No is e
The total harmonic distortion plus noise (THD+N) is typ-
ically less than -78dB at full scale with a 1Vp-p input
swing at 5kHz.
OUT
REF
where NB represents the numeric value of the DAC’s
binary input code. Table 3 shows digital codes and the
corresponding output voltage for Figure 11’s circuit.
Dig it a l Ca lib ra t io n a n d
Th re s h o ld S e le c t io n
Us in g a n AC Re fe re n c e
In applications where the reference has an AC signal
component, the MAX5104 has multiplying capabilities
within the reference input voltage range specifications.
Figure 12 shows a technique for applying a sinusoidal
input to REF_, where the AC signal is offset before
being applied to the reference input.
Figure 13 shows the MAX5104 in a digital calibration
application. With a bright-light value applied to the pho-
todiode (on), the DAC is digitally ramped until it trips
the comparator. The microprocessor (µP) stores this
“high” calibration value. Repeat the process with a dim
light (off) to obtain the dark current calibration.
Table 3. Bipolar Code Table
+5V/
+3V
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
+5V/+3V
26k
AC
MAX495
2047
2048
REFERENCE
INPUT
+V
1 1 1 1 1 1 1 1 1 1 1 1 (0 )
REF
1
1 0 0 0 0 0 0 0 0 0 0 1 (0 )
1 0 0 0 0 0 0 0 0 0 0 0 (0 )
0 1 1 1 1 1 1 1 1 1 1 1 (0 )
+V
REF
10k
V
DD
REF
2048
R
500mVp-p
OS_
0V
R
DGND
V+
1
-V
REF
OUT_
2048
DAC_
2047
4096
0 0 0 0 0 0 0 0 0 0 0 1 (0 )
+V
REF
2
MAX5104
AGND
2048
2048
-V
= - V
REF
0 0 0 0 0 0 0 0 0 0 0 0 (0 )
REF
Figure 12. AC Reference Input Circuit
Note: ( ) are for the sub-bit.
+5V/+3V
REF_
10k
10k
V+
PHOTODIODE
REF_
+5V/+3V
OS_
OS_
V
DD
V
DD
R
R
R
R
V+
MAX5104
MAX5104
V
OUT
10k
V
OUT
OUT_
µP
DAC _
AGND
DAC _
OUT_
V-
DIN
10k
DGND
V-
R
DGND
AGND
PULLDOWN
Figure 13. Digital Calibration
______________________________________________________________________________________ 11
Figure 11. Bipolar Output Circuit
Lo w -P o w e r, Du a l, Vo lt a g e -Ou t p u t , 1 2 -Bit DAC
w it h S e ria l In t e rfa c e
V
DD
OSA
R
R
MAX5104
REFA
V
IN
R1
R3
OUTA
OUTB
CS
INPUT
REG A
DAC
REG A
DACA
DACB
R2
SHIFT
REGISTER
SCLK
1
INPUT
REG B
DAC
REG B
V
OUT
DIN
R4
REFB
R
R
V
REF
V
OUT
=
GAIN
–
OFFSET
[ ] [
]
OSB
2NA
R2
R4
1+
)(R1+R2)( ) ( 2NB )(R4 )
=
V
V
REF
IN
(
[
R3 ] [
]
4096
4096 R3
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
AGND
DGND
Figure 14. Digital Control of Gain and Offset
The µP then programs the DAC to set an output voltage
at the midpoint of the two calibrated values. Applications
include tachometers, motion sensing, automatic readers,
and liquid-clarity analysis.
P in Co n fig u ra t io n
TOP VIEW
AGND
OUTA
OSA
REFA
CL
1
2
3
4
5
6
7
8
16 V
DD
Dig it a l Co n t ro l o f Ga in a n d Offs e t
The two DACs can be used to control the offset and gain
for curve-fitting nonlinear functions, such as transducer
linearization or analog compression/expansion applica-
tions. The input signal is used as the reference for the
gain-adjust DAC, whose output is summed with the output
from the offset-adjust DAC. The relative weight of each
DAC output is adjusted by R1, R2, R3, and R4 (Figure 14).
15 OUTB
14 OSB
13 REFB
12 PDL
11 UPO
10 DOUT
MAX5104
CS
DIN
P o w e r-S u p p ly Co n s id e ra t io n s
SCLK
9 DGND
On power-up, the input and DAC registers clear (set to
zero code). For rated performance, V
should be at
QSOP
REF_
least 1.4V below V . Bypass the power supply with a
DD
4.7µF capacitor in parallel with a 0.1µF capacitor to
AGND. Minimize lead lengths to reduce lead inductance.
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 3053
SUBSTRATE CONNECTED TO AGND
Gro u n d in g a n d La yo u t Co n s id e ra t io n s
Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance ground
plane. Carefully lay out the traces between channels to
reduce AC cross-coupling and crosstalk. Wire-wrapped
boards and sockets are not recommended. If noise
becomes an issue, shielding may be required.
P a c k a g e In fo rm a t io n
Package information is available on Maxim’s website:
www.maxim-ic.com.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX5105EEP-T
D/A Converter, 1 Func, Serial Input Loading, 6us Settling Time, PDSO20, 0.150 INCH, 0.025 INCH PITCH, QSOP-20
MAXIM
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