MAX5133AEEE+T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16;
| 型号： | MAX5133AEEE+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 20us Settling Time, PDSO16, 0.150 INCH, 0.025 INCH PITCH, QSOP-16 光电二极管 转换器 |
| 文件： | 总20页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1441; Rev 0; 3/99
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX5132/MAX5133 low-power, 13-bit, voltage-out-
put digital-to-analog converters (DACs) feature an inter-
nal precision bandgap reference and output amplifier.
♦ Single-Supply Operation
+5V (MAX5132)
+3V (MAX5133)
The MAX5132 operates on a single +5V supply with an
internal reference of +2.5V and offers a configurable out-
put amplifier. If necessary, the user can override the on-
chip, <10ppm/°C voltage reference with an external
reference. The MAX5133 has the same features as the
MAX5132 but operates from a single +3V supply and
has an internal +1.25V precision reference. The user-
accessible inverting input and output of the amplifier
allows specific gain configurations, remote sensing, and
hig h outp ut d rive c a p a b ility for a wid e ra ng e of
force/sense applications. Both devices draw only 500µA
of supply current, which reduces to 3µA in power-down
mode. In addition, their power-up reset feature allows for
a user-selectable initial output state of either 0V or mid-
scale and reduces output glitches during power-up.
♦ Built-In 10ppm/°C max Precision Bandgap Reference
+2.5V (MAX5132)
+1.25V (MAX5133)
♦ SPI/QSPI/MICROWIRE-Compatible, 3-Wire Serial
Interface
♦ Pin-Programmable Shutdown-Mode and Power-
Up Reset (0V or Midscale Output Voltage)
♦ Buffered Output Capable of Driving 5kΩ 100pF
or 4–20mA Loads
♦ Space-Saving 16-Pin QSOP Package
♦ Pin-Compatible Upgrades for the 12-Bit
MAX5122/MAX5123
The serial interface is compatible with SPI™, QSPI™,
a nd MICROWIRE™, whic h ma ke s the MAX5132/
MAX5133 suitable for cascading multiple devices. Each
DAC has a double-buffered input organized as an input
register followed by a DAC register. A 16-bit shift register
loads data into the input register. The DAC register may
be updated independently or simultaneously with the
input register.
♦ Pin-Compatible 14-Bit Upgrades Available
(MAX5171/MAX5173)
Ord e rin g In fo rm a t io n
PIN-
PACKAGE
INL
(LSB)
PART
TEMP. RANGE
Both devices are available in a 16-pin QSOP package
and are specified for the extended-industrial (-40°C to
+85°C) operating temperature range. For pin-compati-
ble 14-bit upgrades, see the MAX5171/MAX5173 data
s he e t; for p in-c omp a tib le 12-b it ve rs ions , s e e the
MAX5122/MAX5123 data sheet.
MAX5132AEEE
MAX5132BEEE
MAX5133AEEE
MAX5133BEEE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 QSOP
16 QSOP
16 QSOP
16 QSOP
±0.5
±1
±1
±2
Ap p lic a t io n s
Industrial Process Control
P in Co n fig u ra t io n
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Motion Control
TOP VIEW
FB
1
2
3
4
5
6
7
8
16 V
DD
OUT
15 REFADJ
14 REF
RSTVAL
PDL
Microprocessor-Controlled Systems
MAX5132
MAX5133
13 AGND
12 PD
CLR
CS
11 UPO
10 DOUT
DIN
SCLK
9 DGND
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND, DGND...............................................-0.3V to +6V
Maximum Current into Any Pin............................................50mA
AGND to DGND.....................................................-0.3V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
16-Pin QSOP (derate 8.00mW/°C above +70°C)..........667mW
Operating Temperature Range ..........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Digital Outputs (DOUT, UPO) to DGND.....-0.3V to (V + 0.3V)
DD
FB, OUT to AGND ......................................-0.3V to (V + 0.3V)
DD
REF, REFADJ to AGND ..............................-0.3V to (V + 0.3V)
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5132 (+5V)
(V = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connect-
DD
L
L
ed in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2/MAX513
N
13
-0.5
-1
Bits
MAX5132A
MAX5132B
0.5
1
Integral Nonlinearity (Note 1)
INL
LSB
Differential Nonlinearity
Offset Error (Note 2)
Gain Error
DNL
-1
1
LSB
mV
mV
V
OS
-10
-3
10
3
GE
-0.2
3
MAX5132A
MAX5132B
10
30
250
Full-Scale Temperature
Coefficient (Note 3)
TCV
ppm/°C
µV/V
FS
10
20
Power-Supply Rejection Ratio
REFERENCE
PSRR
4.5V ≤ V ≤ 5.5V
DD
Output Voltage
V
T
= +25°C
2.475
2.5
3
2.525
V
REF
A
MAX5132A
MAX5132B
Output Voltage Temperature
Coefficient
TCV
ppm/°C
REF
10
Reference External Load Regulation
Reference Short-Circuit Current
REFADJ Current
V
/I
0 ≤ I
≤ 100µA (sourcing)
50
7
µV/µA
mA
OUT OUT
OUT
4
REFADJ = V
3.3
µA
DD
DIGITAL INPUT
Input High Voltage
V
3
V
V
IH
Input Low Voltage
V
IL
0.8
1
Input Hysteresis
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
IN
= 0 or V
-1
DD
C
IN
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
2
_______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
ELECTRICAL CHARACTERISTICS—MAX5132 (+5V) (continued)
(V = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connect-
DD
L
L
ed in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.6
20
V/µs
µs
To ±0.5LSB, V
= 2.5V
STEP
Output Voltage Swing (Note 4)
Current into FB
0 to V
V
DD
-0.1
4.5
0
2
0.1
µA
ms
Time Required to Exit Shutdown
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-s
V
SCLK
= 5Vp-p
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
Power-Supply Current in Shutdown
V
5.5
600
20
V
DD
I
DD
500
3
µA
µA
I
SHDN
ELECTRICAL CHARACTERISTICS—MAX5133 (+3V)
(V
DD
= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier
L L
connected in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
13
-1
Bits
MAX5133A
MAX5133B
1
2
Integral Nonlinearity (Note 1)
INL
LSB
-2
Differential Nonlinearity
Offset Error (Note 2)
Gain Error
DNL
-1
1
LSB
mV
mV
V
OS
-10
-5
10
5
GE
-0.2
3
MAX5133A
MAX5133B
10
30
250
Full-Scale Temperature
Coefficient (Note 3)
TCV
ppm/°C
µV/V
FS
10
20
Power-Supply Rejection Ratio
REFERENCE
PSRR
2.7V ≤ V ≤ 3.3V
DD
Output Voltage
V
T
= +25°C
1.237
1.25
3
1.263
V
REF
A
MAX5133A
MAX5133B
Output Voltage Temperature
Coefficient
TCV
ppm/°C
REF
10
0.1
4
Reference External Load Regulation
Reference Short-Circuit Current
REFADJ Current
V
/I
0 ≤ I
≤ 100µA (sourcing)
1
7
µV/µA
mA
OUT OUT
OUT
REFADJ = V
3.3
µA
DD
DIGITAL INPUT
Input High Voltage
V
2.2
V
V
IH
Input Low Voltage
V
IL
0.8
Input Hysteresis
V
HYS
200
mV
_______________________________________________________________________________________
3
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
ELECTRICAL CHARACTERISTICS—MAX5133 (+3V) (continued)
(V
DD
= +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier
L L
connected in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
Input Leakage Current
Input Capacitance
SYMBOL
CONDITIONS
MIN
TYP
0.001
8
MAX
UNITS
µA
I
IN
V
IN
= 0 or V
-1
1
DD
C
pF
IN
DIGITAL OUTPUTS
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.4
0.1
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.6
20
V/µs
µs
To ±0.5LSB, V
= 1.25V
STEP
Output Voltage Swing (Note 4)
Current into FB
0 to V
V
DD
-0.1
0
2
µA
ms
Time Required to Exit Shutdown
2/MAX513
CS = V , f
= 100kHz,
DD SCLK
Digital Feedthrough
5
nV-s
V
SCLK
= 3Vp-p
POWER REQUIREMENTS
Power-Supply Voltage (Note 5)
Power-Supply Current (Note 5)
V
2.7
3.6
600
20
V
DD
I
DD
500
3
µA
µA
Power-Supply Current in Shutdown
I
SHDN
TIMING CHARACTERISTICS—MAX5132 (+5V)
(V = +5V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connect-
DD
L
L
ed in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SCLK Clock Period
SYMBOL
CONDITIONS
MIN
100
40
40
40
0
TYP
MAX
UNITS
ns
t
CP
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
CH
t
ns
CL
t
ns
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
CSS
CSH
t
ns
t
DS
40
0
ns
SDI Hold Time
t
ns
DH
SCLK Rise to DOUT Valid
Propagation Delay Time
t
C
C
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay Time
t
= 200pF
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
100
CSW
4
_______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
TIMING CHARACTERISTICS—MAX5133 (+3V)
(V = +3V ±10%, AGND = DGND, 33nF capacitor at REFADJ, internal reference, R = 5kΩ, C = 100pF, output amplifier connect-
DD
L
L
ed in unity-gain, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
PARAMETER
SCLK Clock Period
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
CP
150
75
75
60
0
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
CH
t
ns
CL
t
ns
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
CSS
CSH
t
ns
t
DS
60
0
ns
SDI Hold Time
t
ns
DH
SCLK Rise to DOUT Valid
Propagation-Delay Time
t
C
C
= 200pF
200
200
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation-Delay Time
t
= 200pF
t
10
75
ns
ns
ns
SCLK Rise to CS Fall Delay Time
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
t
CS1
t
150
CSW
Note 1: Accuracy is guaranteed by following the table:
Accuracy Guaranteed
From Code: To Code:
32 8191
65 8191
V
DD
(V)
5
3
Note 2: Offset is measured at the code closest to 10mV.
Note 3: The temperature coefficient is determined by the “box” method in which the maximum ∆V
over the temperature range is
OUT
divided by ∆T and the typical reference voltage.
Note 4: Accuracy is better than 1.0LSB for V = 10mV to V - 180mV. Guaranteed by PSR test on end points.
OUT
DD
Note 5: R
= ∞ and digital inputs are at either V or DGND.
DD
LOAD
_______________________________________________________________________________________
5
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, output amplifier connected in unity-gain configuration, unless other-
DD
L
L
A
wise noted.)
MAX5132
MAX5132
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
MAX5132
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
REFERENCE VOLTAGE vs. TEMPERATURE
2.510
2.505
2.500
2.495
2.490
0.20
0.15
0.10
0.05
0
0.20
0.15
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.05
-0.10
-0.15
-0.20
0
2/MAX513
-60 -40 -20
0
20 40 60 80 100
0
2,000
4,000
6,000
8,000 10,000
2,000
4,000
6,000
8,000 10,000
TEMPERATURE (°C)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
MAX5132
MAX5132
MAX5132
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
(CODE = 1555 HEX)
500
450
400
350
300
250
200
3.0
2.5
2.0
1.5
1.0
0.5
0
500
450
400
350
300
250
(CODE = 1555 HEX)
(CODE = 0000 HEX)
(CODE = 0000 HEX)
-60 -40 -20
0
20 40 60 80 100
4
4.5
5
5.5
6
-60 -40 -20
0
20 40 60 80 100
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
MAX5132
MAX5132
MAX5132
DYNAMIC-RESPONSE RISE TIME
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE
FULL-SCALE OUTPUT ERROR
vs. RESISTIVE LOAD
MAX5132/33-09
2.510
2.505
2.500
R = 5kΩ
L
0.25
-0.50
-1.25
-2.00
-2.75
C = 100pF
L
CS
5V/div
OUT
1V/div
2.495
2.490
-3.50
-60 -40 -20
0
20 40 60 80 100
2µs/div
0.1
1
10
100
TEMPERATURE (°C)
R (kΩ)
L
6
_______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, output amplifier connected in unity-gain configuration,unless other-
DD
L
L
A
wise noted.)
MAX5132
MAX5132
MAX5132
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAJOR CARRY TRANSITION
DYNAMIC-RESPONSE FALL TIME
MAX5132/33-11
MAX5132/33-12
MAX5132/33-10
SCLK
2V/div
CS
2V/div
CS
5V/div
OUT
1mV/div
AC-COUPLED
OUT
100mV/div
AC-COUPLED
OUT
1V/div
2µs/div
5µs/div
2µs/div
MAX5133
MAX5133
DIFFERENTIAL NONLINEARITY vs.
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY vs.
DIGITAL INPUT CODE
MAX5133
REFERENCE VOLTAGE vs. TEMPERATURE
0.25
0.20
0.15
0.15
0.10
0.05
0
1.260
1.255
1.250
1.245
1.240
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.05
-0.10
-0.15
-0.20
0
2,000
4,000
6,000
8,000 10,000
0
2,000
4,000
6,000
8,000 10,000
-60 -40 -20
0
20 40 60 80 100
DIGITAL INPUT CODE
DIGITAL INPUT CODE
TEMPERATURE (°C)
MAX5133
MAX5133
MAX5133
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
0.5
0.4
400
350
300
250
400
350
300
(CODE = 1555 HEX)
(CODE = 1555 HEX)
0.3
0.2
0.1
(CODE = 0000 HEX)
(CODE = 0000 HEX)
250
200
200
2.5
2.75
3.0
3.25
3.5
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, R = 5kΩ, C = 100pF, OS = AGND, T = +25°C, output amplifier connected in unity-gain configuration,unless other-
DD
L
L
A
wise noted.)
MAX5133
FULL-SCALE OUTPUT VOLTAGE
vs. TEMPERATURE
MAX5133
FULL-SCALE OUTPUT ERROR
vs. RESISTIVE LOAD
MAX5133
DYNAMIC-RESPONSE RISE TIME
MAX5132/33-21
1.260
1.255
1.250
0
-1
-2
CS
2V/div
OUT
400mV/div
1.245
1.240
-3
-4
2/MAX513
1µs/div
-60 -40 -20
0
20 40 60 80 100
0.1
10
100
1000
TEMPERATURE (°C)
R (kΩ)
L
MAX5133
MAJOR CARRY TRANSITION
MAX5133
DIGITAL FEEDTHROUGH (SCLK, OUT)
MAX5132
DYNAMIC-RESPONSE FALL TIME
MAX5132/33-24
MAX5132/33-22
MAX5132/33-23
SCLK
2V/div
CS
2V/div
CS
2V/div
OUT
100mV/div
AC-COUPLED
OUT
500mV/div
AC-COUPLED
OUT
400mV/div
5µsV/div
1µs/div
2µs/div
8
_______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
P in De s c rip t io n
PIN
1
NAME
FUNCTION
FB
Amplifier Inverting Sense Input (Analog Input)
2
OUT
Analog Output Voltage. High impedance if part is in shutdown.
Reset Value Input (Digital Input)
3
RSTVAL
1: Connect to VDD to select midscale as the output reset value.
0: Connect to DGND to select 0V as the output reset value.
Power-Down Lockout (Digital Input).
1: Normal operation.
0: Disallows shutdown (device cannot be powered down).
4
5
PDL
CLR
Reset DAC Input (Digital Input). Clears the DAC to its predetermined (RSTVAL) output state. Clearing the
DAC will cause it to exit a software shutdown state.
6
7
Active-Low Chip-Select Input (Digital Input)
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Serial Clock Input
CS
DIN
8
SCLK
DGND
DOUT
UPO
9
Digital Ground
10
11
Serial Data Output
User-Programmable Output (Digital Output)
Power-Down Input (Digital Input). Pulling PD high when PDL = V places the IC into shutdown with a
DD
maximum shutdown current of 20µA.
12
13
PD
AGND
Analog Ground
Buffered Reference Output/Input. In internal reference mode, the reference buffer provides a +2.5V
(MAX5132) or +1.25V (MAX5133) nominal output, externally adjustable at REFADJ. In external reference
14
REF
mode, disable the internal reference by pulling REFADJ to V and applying the external reference to REF.
DD
Analog Reference Adjust Input. Bypass with a 33nF capacitor to AGND. Connect to V when using an
DD
external reference.
15
16
REFADJ
V
DD
Positive Power Supply. Bypass with a 0.1µF capacitor in parallel with a 4.7µF capacitor to AGND.
_______________________________________________________________________________________
9
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
V
DD
AGND DGND
CS DIN SCLK
PDL
PD
SR
CONTROL
16-BIT
SHIFT REGISTER
DOUT
UPO
LOGIC
OUTPUT
RSTVAL
CLR
DECODE
CONTROL
FB
13
INPUT
REGISTER
DAC
REGISTER
MAX5132
MAX5133
OUT
DAC
2/MAX513
2X
(X1)
2.5V (1.25V)
BANDGAP 1.25V
REFERENCE
4k
REFERENCE
BUFFER
REFADJ
REF
( ) FOR MAX5133 ONLY.
Figure 1. Simplified Functional Diagram
_______________De t a ile d De s c rip t io n
The MAX5132/MAX5133 13-bit, force/sense DACs are
easily configured with a 3-wire serial interface. They
include a 16-bit data-in/data-out shift register and have a
double-buffered digital input consisting of an input regis-
te r a nd a DAC re g is te r. In a d d ition, the s e d e vic e s
employ precision bandgap references, as well as an out-
put amplifier with accessible feedback and output pins
that can be used for setting the gain externally (Figure 1)
or for forcing and sensing applications. These DACs
are designed with an inverted R-2R ladder network
(Figure 2) that produces a weighted voltage proportion-
al to the digital input code.
FB
OUT
R
R
R
2R
D0
2R
D10
2R
D11
2R
2R
D12
REF*
AGND
In t e rn a l Re fe re n c e
Both devices use an on-board precision bandgap ref-
e re nc e with a low te mp e ra ture c oe ffic ie nt of only
10ppm/°C (max) to generate an output voltage of +2.5V
(MAX5132) or +1.25V (MAX5133). The REF pin can
source up to 100µA and may become unstable with
capacitive loads exceeding 100pF. REFADJ can be
used for minor adjustments to the reference voltage.
The circuits in Figures 3a and 3b achieve a nominal ref-
e re nc e a d jus tme nt ra ng e of ± 1%. Conne c t a 33nF
capacitor from REFADJ to AGND to establish low-noise
SHOWN FOR ALL 1s ON DAC
*INTERNAL REFERENCE: 2.5V (MAX5132),
1.25V (MAX5133); OR EXTERNAL REFERENCE
Figure 2. Simplified Inverted R-2R DAC Structure
10 ______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
operation of the DAC. Larger capacitor values may be
used but will result in increased start-up delay. The
unity gain and loaded with 5kΩ 100pF. Loads less
than 1kΩ may result in degraded performance.
time constant τ for the start-up delay is determined by
P o w e r-Do w n Mo d e
The MAX5132/MAX5133 feature software- and hard-
ware-programmable (PD pin) shutdown modes that
reduce the typical supply current to 3µA. To enter soft-
ware shutdown mode, program the control sequence
for the DAC as shown in Table 1.
the REFADJ input impedance of 4kΩ and C
:
REFADJ
τ = 4kΩ · C
REFADJ
Ex t e rn a l Re fe re n c e
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
V
. This allows an external reference signal (AC- or
In s hutd own mod e , the a mp lifie r outp ut b e c ome s
high impedance and the serial interface remains active.
Da ta in the inp ut re g is te rs is s a ve d , a llowing the
MAX5132/MAX5133 to recall the output state prior to
entering shutdown when returning to normal operation.
To exit shutdown mode, load both input and DAC regis-
ters simultaneously or update the DAC register from the
input register. When returning from shutdown to normal
operation, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
DD
DC-based) to be fed into the REF pin. For proper oper-
ation, do not exceed the input voltage range limits of
0V to (V - 1.4V) for V
.
REF
DD
Determine the output voltage using the following equa-
tion (REFADJ = V ):
DD
V
OUT
= V (NB / 8192)G
REF
whe re NB is the nume ric va lue of the MAX5132/
MAX5133 input code (0 to 8191), V is the external
re fe re nc e volta g e , a nd G is the g a in of the outp ut
amplifier, set by an external resistor-divider. The REF
pin has a minimum input resistance of 40kΩ and is
code dependent.
REF
Power-Down Lockout Input (PDL)
The power-down lockout (PDL) pin disables shutdown
when low. When in shutdown mode, a high-to-low tran-
sition on PDL will wake up the DAC with its output still
set to the state prior to power-down. PDL can also be
used to wake up the device asynchronously.
Ou t p u t Am p lifie r
The MAX5132/MAX5133’s DAC outp ut is inte rna lly
buffered by a precision amplifier with a typical slew rate
of 0.6V/µs. Access to the output amplifier’s inverting
inp ut (FB) p rovid e s the us e r g re a te r fle xib ility with
a mp lifie r g a in s e tting a nd s ig na l c ond itioning (s e e
Applications Information).
Power-Down Input (PD)
Pulling PD high places the MAX5132/MAX5133 in shut-
d own. Pulling PD low will not re turn the MAX5132/
MAX5133 to normal operation. A high-to-low transition
on PDL or appropriate commands (Table 1) via the ser-
ial interface are required to exit power-down.
The output amplifier typically settles to ±0.5LSB from a
full-scale transition within 20µs when it is connected in
+3V
+5V
15k
MAX5133
90k
MAX5132
400k
400k
100k
100k
REFADJ
REFADJ
33nF
33nF
Figure 3a. MAX5132 Reference Adjust Circuit
Figure 3b. MAX5133 Reference Adjust Circuit
______________________________________________________________________________________ 11
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
C2
C1
C0
D12 ............... D0
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
0
1
1
XXXXXXXXXXXXX
13-Bit DAC Data
13-Bit DAC Data
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
XXXXXXXXXXXXX
1XXXXXXXXXXXX
00XXXXXXXXXXX
No operation.
Load input register; DAC register unchanged.
Simultaneously load input and DAC registers; exit shutdown.
Update DAC register from input register; exit shutdown.
Shutdown DAC (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1: DOUT clocked out on SCLK’s rising edge.
Mode 0: DOUT clocked out on SCLK’s falling edge (default).
X = Don’t care
2/MAX513
S e ria l-In t e rfa c e Co n fig u ra t io n
V
DD
(S P I/QS P I/MICROWIRE/P IC1 6 /P IC1 7 )
The MAX5132/MAX5133 3-wire serial interface is com-
patible with SPI, QSPI, PIC16/PIC17 (Figure 4) and
MICROWIRE (Figure 5) interface standards. The 2-
byte-long serial input word contains three control bits
and 13 data bits in MSB-first format (Table 2).
SS
DIN
MOSI
SCK
The MAX5132/MAX5133’s digital inputs are double
buffered, which allows the user to:
SPI/QSPI
PORT
(PIC16/PIC17)
MAX5132
MAX5133
SCLK
•
•
•
load the input register without updating the DAC
register,
update the DAC register with data from the input
register,
CS
I/O
update the input and DAC registers concurrently.
( ) PIC16/PIC17 ONLY
CPOL = 0, CPHA = 0
The 16-bit input word may be sent in two 1-byte pack-
ets (SPI-, MICROWIRE- and PIC16/PIC17-compatible),
with CS low during this period. The control bits C2, C1,
and C0 (Table 1) determine:
(CKE = 1, CKP = 0, SMP = 0,
SSPM3 - SSPMO = 0001)
Figure 4. SPI/QSPI Interface Connections (PIC16/PIC17)
•
•
•
the clock edge on which DOUT transitions,
the state of the user-programmable logic output,
the configuration of the device after shutdown.
SK
SO
I/O
SCLK
DIN
CS
The general timing diagram in Figure 6 illustrates how
data is acquired. CS must be low for the part to receive
data. With CS low, data at DIN is clocked into the regis-
ter on the rising edge of SCLK. When CS transitions
high, data is latched into the input and/or DAC registers,
depending on the setting of the three control bits C2,
C1, and C0. The maximum serial-clock frequency guar-
anteed for proper operation is 10MHz for the MAX5132
and 6.6MHz for the MAX5133. Figure 7 depicts a more
detailed timing diagram of the serial interface.
MICROWIRE
PORT
MAX5132
MAX5133
Figure 5. MICROWIRE Interface Connections
12 ______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
PIC16 with SSP Module
and PIC17 Interface
the three control bits (C2, C1, C0) and the first five data
bits (D12–D8). The second 8-bit data stream contains
the remaining bits, D7–D0.
The MAX5132/MAX5133 a re c omp a tib le with a
PIC16/PIC17 microcontroller (µC), using the synchro-
nous serial port (SSP) module. To establish SPI com-
munication, connect the controller as shown in Figure 4
and configure the PIC16/PIC17 as system master by
initializing its synchronous serial-port control register
(SSPCON) and synchronous serial-port status register
(SSPSTAT) to the bit patterns shown in Tables 3 and 4.
S e ria l Da t a Ou t p u t
The contents of the internal shift-register are output seri-
ally on DOUT, which allows for daisy-chaining (see
Applications Information) of multiple devices as well as
data readback. The MAX5132/MAX5133 may be pro-
grammed to shift data out of DOUT on the serial clock’s
rising edge (Mode 1) or on the falling edge (Mode 0).
The latter is the default during power-up and provides a
la g of 16 c loc k c yc le s , ma inta ining SPI, QSPI,
MICROWIRE, and PIC16/PIC17 compatibility. In Mode
1, the outp ut d a ta la g s DIN b y 15.5 c loc k c yc le s .
During power-down, DOUT retains its last digital state
prior to shutdown.
In SPI mode, the PIC16/PIC17 µCs allow eight bits of
data to be synchronously transmitted and received
simultaneously. Two consecutive 8-bit writings (Figure
6) are necessary to feed the DAC with three control bits
and 13 data bits. DIN data transitions on the serial
clock’s falling edge and is clocked into the DAC on
SCLK’s rising edge. The first eight bits of DIN contain
Us e r-P ro g ra m m a b le Ou t p u t (UP O)
The UPO feature allows an external device to be con-
trolled through the serial-interface setup (Table 1),
thereby reducing the number of microcontroller I/O
ports required. During power-down, this output will
retain the last digital state before shutdown. With CLR
pulled low, UPO will reset to the default state after
wake-up.
Table 2. Serial Data Format
MSB ........................................... LSB
16 BITS OF SERIAL DATA
Control Bits
C2, C1, C0
MSB ..... Data Bits ..... LSB
D12................................D0
CS
COMMAND
EXECUTED
SCLK
DIN
1
8
9
16
D6 D5 D4 D3 D2 D1 D0
C1
C0
D11 D10
D9 D8
C2
D12
D7
Figure 6. Serial-Interface Timing
t
CSW
CS
t
CSH
t
t
CSS
CS0
t
CS1
SCLK
t
CH
t
CL
t
CP
DIN
t
DS
t
DH
t
t
DO1
DO2
DOUT
Figure 7. Detailed Serial-Interface Timing
______________________________________________________________________________________ 13
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
Table 3. Detailed SSPCON Register Contents
MAX5132/MAX5133
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER
(SSPCON)
CONTROL BIT
WCOL
BIT7
BIT6
X
X
Write-Collision Detection Bit
SSPOV
Receive-Overflow Detection Bit
Synchronous Serial Port Enable Bit
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI as seri-
al-port pins.
SSPEN
BIT5
1
CKP
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
1
Clock-Polarity Select Bit. CKP = 0 for SPI master-mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode
and selects f
= f
/ 16.
CLK
OSC
X = Don’t care
2/MAX513
Table 4. Detailed SSPSTAT Register Contents
MAX5132/MAX5133
SYNCHRONOUS SERIAL-PORT STATUS REGISTER
(SSPSTAT)
CONTROL BIT
SETTINGS
SPI Data-Input Sample Phase. Input data is sampled at the mid-
dle of the data-output time.
SMP
CKE
BIT7
BIT6
0
1
SPI Clock-Edge Select Bit. Data will be transmitted on the rising
edge of the serial clock.
D/A
P
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
X
X
X
X
X
X
Data-Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full-Status Bit
X = Don’t care
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 8b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than or equal to
1LSB, the DAC guarantees no missing codes and is
monotonic.
__________Ap p lic a t io n s In fo rm a t io n
De fin it io n s
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 8a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve) or
a line drawn between the endpoints of the transfer func-
tion, once offset and gain errors have been nullified. For
a DAC, the deviations are measured at every single
step.
Offset Error
The offset error (Figure 8c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
14 ______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
Gain Error
Gain error (Figure 8d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
a lte rs the s lop e of the tra ns fe r func tion a nd c orre -
sponds to the same percentage error in each step.
Un ip o la r Ou t p u t
Fig ure 9 s hows the MAX5132/MAX5133 s e tup for
unipolar, Rail-to-Rail™ operation with a closed-loop
gain of 2V/V. With its internal reference of +2.5V, the
MAX5132 provides a convenient unipolar output range
of 0 to +4.99939V, while the MAX5133 offers an output
range of 0 to +2.499695V with its on-board +1.25V ref-
erence. Table 5 lists example codes for unipolar output
voltages.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
Bip o la r Ou t p u t
The MAX5132/MAX5133 can be configured for unity-
gain bipolar operation (FB = OUT) using the circuit
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
la yout a nd g round ing will s ig nific a ntly re d uc e this
nois e , b ut the re will a lwa ys b e s ome fe e d throug h
caused by the DAC itself.
shown in Figure 10. The output voltage V
is then
OUT
given by the following equation:
V
OUT
= V
[G (NB / 8192) - 1]
REF
7
6
ACTUAL
DIAGRAM
3
5
2
1
0
4
IDEAL DIAGRAM
AT STEP
011 (1/2 LSB )
3
2
1
0
OFFSET ERROR
(+1 1/4 LSB)
AT STEP
001 (1/4 LSB )
ACTUAL
OFFSET POINT
IDEAL OFFSET
POINT
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
DIGITAL INPUT CODE
Figure 8a. Integral Nonlinearity
Figure 8c. Offset Error
IDEAL FULL-SCALE OUTPUT
GAIN ERROR
6
5
4
7
1 LSB
(-1 1/4 LSB)
6
5
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
IDEAL DIAGRAM
3
ACTUAL
FULL-SCALE
OUTPUT
1 LSB
2
1
0
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
4
0
000
001
010
011
100
101
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 8b. Differential Nonlinearity
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
Figure 8d. Gain Error
______________________________________________________________________________________ 15
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
where NB is the numeric value of the DAC’s binary
input code, V
is the voltage of the internal (or exter-
REF
+5V/+3V
nal) precision reference, and G is the overall gain. The
application circuit in Figure 10 uses a low-cost op amp
(MAX4162) e xte rna l to the MAX5132/MAX5133.
Together with the MAX5132/MAX5133, this circuit offers
an overall gain of 2V/V. Table 6 lists example codes for
bipolar output voltages.
REF
V
DD
50k
50k
MAX5132
MAX5133
FB
OUT
DAC
Re s e t (RS TVAL) a n d
CLR
Cle a r (
) Fu n c t io n s
AGND
DGND
The MAX5132/MAX5133 DACs fe a ture a c le a r p in
(CLR), whic h re s e ts the outp ut to a c e rta in va lue ,
depending upon how RSTVAL is set. RSTVAL = DGND
GAIN = 2 V/V
selects an output of 0, and RSTVAL = V
selects a
DD
midscale output when CLR is pulled low.
Figure 9. Unipolar Output Circuit Using Internal (+1.25V/+2.5V)
or External Reference. With external reference, pull REFADJ
The CLR pin has a minimum input resistance of 40kΩ in
series with a diode to the supply voltage (V ). If the
to V
.
DD
DD
digital voltage is higher than the supply voltage for the
part, a small input current may flow, but this current will
2/MAX513
+5V/+3V
50k
50k
V+
be limited to (V
- V - 0.5V) / 40kΩ.
CLR
DD
REF
Note: Clearing the DAC will also cause the part to exit
software shutdown (PD = 0).
V
DD
FB
MAX5132
MAX5133
Da is y-Ch a in in g De vic e s
Any number of MAX5132/MAX5133s may be daisy-
chained simply by connecting the serial data output pin
(DOUT) of one device to the serial data input pin (DIN)
of the following device in the chain (Figure 11).
V
OUT
DAC
OUT
MAX4162
V-
DGND
AGND
Anothe r c onfig ura tion (Fig ure 12) a llows s e ve ra l
MAX5132/MAX5133 DACs to share one common DIN
signal line. In this configuration, the data bus is com-
mon to all devices; data is not shifted through a daisy
chain. However, more I/O lines are required in this con-
figuration because each IC needs a dedicated CS line.
Figure 10. Unity-Gain Bipolar Output Circuit Using Internal
(+1.25V/+2.5V) or External Reference. With external reference,
pull REFADJ to V
.
DD
SCLK
SCLK
SCLK
I
II
III
MAX5132
MAX5133
MAX5132
MAX5133
MAX5132
MAX5133
DIN
CS
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 11. Daisy-Chaining Multiple Devices with the Digital I/Os DIN/DOUT
16 ______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
Table 5. Unipolar Code Table (Gain = +2V/V)
DAC CONTENTS
ANALOG OUTPUT
INTERNAL REFERENCE
MAX5132 MAX5133
EXTERNAL REFERENCE
MAX5132/MAX5133
MSB
LSB
1 1111 1111 1111
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
4.99939V
2.50061V
2.5V
2.49969V
1.25031V
1.25V
V
(8191 / 8192) 2
(4097 / 8192) 2
(4096 / 8192) 2
(4095 / 8192) 2
REF
V
REF
V
REF
2.49939V
610.35µV
0V
1.24969V
305.18µV
0V
V
REF
V
(1 / 8192) 2
0V
REF
Table 6. Bipolar Code Table for Figure 10
DAC CONTENTS
ANALOG OUTPUT
INTERNAL REFERENCE
MAX5132
MAX5133
EXTERNAL REFERENCE
MAX5132/MAX5133
MSB
LSB
1 1111 1111 1111
2.49939V
610.35µV
0V
1.24969V
305.18µV
0V
V
[2 (8191 / 8192) - 1]
[2 (4097 / 8192) - 1]
[2 (4096 / 8192) - 1]
[2 (4095 / 8192) - 1]
REF
1 1000 0000 0001
1 1000 0000 0000
0 1111 1111 1111
0 0000 0000 0001
0 0000 0000 0000
V
REF
V
REF
-610.35µV
-2.49939V
-2.5V
-305.18µV
-1.24969V
-1.25V
V
REF
V
[ 2 (1 / 8192) - 1]
REF
-V
REF
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
I
II
III
CS
CS
CS
MAX5132
MAX5133
MAX5132
MAX5133
MAX5132
MAX5133
SCLK
SCLK
SCLK
DIN
DIN
DIN
Figure 12. Multiple Devices Share One Common Digital Input (DIN)
______________________________________________________________________________________ 17
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
capacitor in parallel with a 0.1µF capacitor to AGND.
Minimize lead lengths to reduce lead inductance.
Us in g a n Ex t e rn a l Re fe re n c e
w it h AC Co m p o n e n t s
The MAX5132/MAX5133 have multiplying capabilities
within the reference input voltage range specifications.
Figure 13 shows a technique for applying a sinusoidal
input to REF, where the AC signal is offset before being
applied to the reference input.
La yo u t Co n s id e ra t io n s
Digital and AC signals coupling to AGND can create
noise at the output. Connect AGND to the highest quali-
ty ground available. Use proper grounding techniques,
s uc h a s a multila ye r b oa rd with a low-ind uc ta nc e
ground plane. Wire-wrapped boards and sockets are
not recommended. If noise becomes an issue, shield-
ing may be required.
P o w e r-S u p p ly a n d Byp a s s in g
Co n s id e ra t io n s
On power-up, the input and DAC registers are cleared
to either zero (RSTVAL = DGND) or midscale (RSTVAL
= V ). Bypass the power supply (V ) with a 4.7µF
DD
DD
+5V/
+3V
+5V/+3V
26k
AC
MAX495
REFERENCE
INPUT
2/MAX513
10k
500mVp-p
V
DD
REF
FB
OUT
DAC
MAX5132
MAX5133
AGND
DGND
Figure 13. External Reference with AC Components
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 3308
SUBSTRATE CONNECTED TO AGND.
18 ______________________________________________________________________________________
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
2/MAX513
________________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 19
+5 V/+3 V, 1 3 -Bit , S e ria l, Fo rc e /S e n s e DACs
w it h 1 0 p p m /°C In t e rn a l Re fe re n c e
NOTES
2/MAX513
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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