MAX513MJD_技术文档

19-0252; Rev 2; 5/96

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

The MAX512/MAX513 contain three 8-bit, voltage-output

digital-to-analog converters (DAC A, DAC B, and DAC C).

Output buffer amplifiers for DACs A and B provide voltage

outputs while reducing external component count. The

output buffer for DAC A can source or sink 5mA to within

♦ Operate from a Single +5V (MAX512) or

+3V (MAX513) Supply, or from Bipolar Supplies

♦ Low Power Consumption

1mA Operating Current

<1µA Shutdown Current

0.5V of V or V . The buffer for DAC B can source or

DD

SS

s ink 0.5mA to within 0.5V of V

unbuffered, providing a third voltage output with increased

a c c ura c y. The MAX512 op e ra te s with s ing le

or V . DAC C is

DD

SS

♦ Unipolar or Bipolar Outputs

♦ 5MHz, 3-Wire Serial Interface

a

♦ SPI, QSPI, and Microwire Compatible

♦ Two Buffered, Bipolar-Output DACs (DACs A/B)

♦ Independently Programmable Shutdown Mode

♦ Space-Saving 14-Pin SO/DIP Packages

♦ Pin and Software Reset

+5V ±10% supply, and the MAX513 operates with a

+2.7V to +3.6V supply. Both devices can also operate

with split supplies.

The 3-wire serial interface has a maximum operating fre-

quency of 5MHz and is compatible with SPI™, QSPI™,

and Microwire™. The serial input shift register is 16 bits

long and consists of 8 bits of DAC input data and 8 bits

for DAC selection and shutdown. DAC registers can be

______________Ord e rin g In fo rm a t io n

loaded independently or in parallel at the positive edge

–—–

of CS. A latched logic output is also available for auxil-

PART

TEMP. RANGE

0°C to +70°C

PIN-PACKAGE

14 Plastic DIP

14 SO

iary control.

MAX512CPD

MAX512CSD

MAX512C/D

Ultra -low p owe r c ons ump tion a nd s ma ll p a c ka g e s

(14-pin DIP/SO) make the MAX512/MAX513 ideal for

portable and battery-powered applications. Supply cur-

rent is only 1mA, dropping to less than 1µA in shutdown.

Any of the three DACs can be independently shut down.

In shutdown mode, the DAC's R-2R ladder network is

disconnected from the reference input, minimizing sys-

tem power consumption.

Dice*

Ordering Information continued at end of data sheet.

* Contact factory for dice specifications.

________________Fu n c t io n a l Dia g ra m

________________________Ap p lic a t io n s

DIN

1

CS

2

REFAB REFC

12 11

Digital Gain and Offset Adjustment

Programmable Attenuators

Programmable Current Sources

Programmable Voltage Sources

RF Digitally Adjustable Bias Circuits

VCO Tuning

SCLK

3

OUTA

8

DAC

DAC A

LATCH

A

OUTB

9

DAC

LATCH

B

DAC B

DAC C

__________________P in Co n fig u ra t io n

TOP VIEW

DIN

CS

DAC

LATCH

C

1

2

3

4

5

6

7

14

13

12

LOUT

I.C.

OUTC

10

MAX512

MAX513

SCLK

RESET

REFAB

MAX512

MAX513

11 REFC

V

DD

10

9

OUTC

OUTB

OUTA

LOUT

14

LATCH

GND

V

SS

8

4

5

7

6

V

DD

V

SS

GND

RESET

DIP/SO

Microwire is a trademark of National Semiconductor Corp. SPI and QSPI are trademarks of Motorola Inc.

________________________________________________________________ Maxim Integrated Products

1

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Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

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ABSOLUTE MAXIMUM RATINGS

V_DDto GND ................................................................ -0.3V, +6V

V_SSto GND................................................................. -6V, +0.3V

V_DDto V_SS................................................................ -0.3V, +12V

Digital Inputs and Outputs to GND............... -0.3V, (V_DD+ 0.3V)

REFAB ................................................ (V_SS- 0.3V), (V_DD+ 0.3V)

OUTA, OUTB (Note 1)....................................................V_SS, V_DD

OUTC.............................................................-0.3V, (V_DD+ 0.3V)

REFC..............................................................-0.3V, (V_DD+ 0.3V)

Continuous Power Dissipation (T_A= +70°C)

Plastic DIP (derate 10.00mW/°C above +70°C) ............800mW

SO (derate 8.33mW/°C above +70°C)...........................667mW

CERDIP (derate 9.09mW/°C above +70°C)...................727mW

Operating Temperature Ranges

MAX51_C_ _ .........................................................0°C to +70°C

MAX51_E_ _.......................................................-40°C to +85°C

MAX51_MJD....................................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +165°C

Lead Temperature (soldering, 10sec) .............................+300°C

Note 1: The outputs may be shorted to V_DD, V_SS, or GND if the package power dissipation is not exceeded. Typical short-circuit cur-

rent to GND is 50mA.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V_DD= + 4.5V to + 5.5V for MAX512, V_DD= + 2.7V to + 3.6V for MAX513, V_SS= GND = 0V, REFAB = REFC = V_DD

T_A= T_MINto T_MAX, unless otherwise noted. Typical values are at T_A= +25°C.)

2/MAX513

,

PARAMETER

STATIC PERFORMANCE

Resolution

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

N

8

Bits

Differential Nonlinearity

DNL

Guaranteed monotonic

±1

±1.5

±1

LSB

DAC A/B (Note 2)

DAC C

Integral Nonlinearity

INL

LSB

Total Unadjusted Error

TUE

(Note 2)

±1

100

5

LSB

DAC A/B

DAC C

Zero-Code Temperature

Coefficient

µV/°C

MAX512, 4.5V ≤ V ≤ 5.5V,

REFAB = REFC = 4.096V

DD

0.01

Power-Supply Rejection Ratio

PSRR

%/%

MAX513, 2.7V ≤ V ≤ 3.6V,

REFAB = REFC = 2.4V

DD

0.015

REFERENCE INPUTS

REFAB

REFC

V

DD

SS

Reference Input Voltage Range

Reference Input Capacitance

Reference Input Resistance

V

GND

V

DD

25

2

pF

kΩ

REFAB (Note 3)

REFC (Note 3)

8

R_REF

12

Reference Input Resistance

(shutdown mode)

REFAB, REFC

MΩ

2

_______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

ELECTRICAL CHARACTERISTICS (continued)

(V_DD= + 4.5V to + 5.5V for MAX512, V_DD= + 2.7V to + 3.6V for MAX513, V_SS= GND = 0V, REFAB = REFC = V_DD

T_A= T_MINto T_MAX, unless otherwise noted. Typical values are at T_A= +25°C.)

,

PARAMETER

DAC OUTPUTS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Output Voltage Range

0

REF_

V

DAC A

DAC B

DAC C

DAC A

DAC B

DAC C

0.10

0.01

0

Capacitive Load

µF

0.050

0.500

24

Output Resistance

kΩ

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

V

(0.7)(V )

DD

V

IH

V

IL

(0.3)(V

)

DD

Input Current

I

V

= 0V or V

DD

0.1

±10

µA

pF

IN

Input Capacitance

DIGITAL OUTPUT

Output High Voltage

Output Low Voltage

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

C

(Notes 4, 5)

10

IN

V

OH

I

≤ 1.6mA

V - 0.4

DD

V

SOURCE

V

OL

I

≤ 1.6mA

0.4

SINK

SR

C

= 0.1µF (DAC A), C = 0.01µF (DAC B)

0.1

70

35

10

V/µs

µs

L

C

= 0.1µF (DAC A)

= 0.01µF (DAC B)

= 0.1nF (DAC C)

L

1

Voltage-Output Settling Time

To ± ⁄ LSB

2

Digital Feedthrough and Crosstalk

All 0s to all 1s

nV-s

POWER SUPPLIES

MAX512

MAX513

MAX512

MAX513

4.5

5.5

3.6

Positive Supply Voltage Range

V

DD

2.7

-5.5

-3.6

-4.5

-2.7

2.8

Negative Supply Voltage Range

(Note 6)

V

SS

MAX512 (V = 5.5V)

1.3

0.9

-1.3

0.1

DD

Positive Supply Current

I

DD

All inputs = 0V

mA

MAX513 (V = 3.6V)

2.5

DD

Negative Supply Current

Shutdown Supply Current

I

SS

All inputs = 0V, V = -5.5V

mA

µA

SS

Note 2: Digital code from 24 through 232 are due to swing limitations of output amplifiers on DAC A and DAC B. See Typical

Operating Characteristics.

Note 3: Reference input resistance is code dependent. The lowest input resistance occurs at code 55hex. Refer to the reference

input section in the Detailed Description.

Note 4: Guaranteed by design. Not production tested.

Note 5: Input capacitance is code dependent. The highest capacitance occurs at code 00hex.

Note 6: For single-supply mode, tie V to GND.

SS

_______________________________________________________________________________________

3

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TIMING CHARACTERISTICS (Note 4)

(V_DD= +4.5V to +5.5V for MAX512, V_DD= +2.7V to +3.6V for MAX513, V_SS= GND = 0V, T_A= T_MINto T_MAX, unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

SERIAL INTERFACE TIMING

–—–

CS Fall to SCLK Rise Setup Time

t

150

50

ns

CSS

–—–

SCLK Rise to CS Rise Setup Time

t

CSH

DIN to SCLK Rise Setup Time

DIN to SCLK Rise Hold Time

SCLK Pulse Width High

SCLK Pulse Width Low

Output Delay LOUT

t

DS

DH

CH

t

50

100

t

CL

t

C

= 100pF

L

150

ns

OD

–—–

CS Pulse Width High

t

200

CSPWH

Note 4: Guaranteed by design. Not production tested.

2/MAX513

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(T = +25°C, unless otherwise noted.)

A

OUTPUT VOLTAGE vs.

OUTPUT SOURCE CURRENT (V = 3V)

DD

OUTPUT SOURCE CURRENT (V = 5V)

DD

OUTPUT SINK CURRENT

5.2

5.0

4.8

4.6

4.4

4.2

3.5

900

800

700

600

500

400

300

V

= 3V, V = GND = 0V

SS

DD

DAC A

DAC B

REFAB = V

DD

CODE = ALL 1s

3

DAC A

2.5

DAC B

2

DAC B

1.5

1

V

= 3V, V = GND = 0V

SS

V

= 5V, V = GND = 0V

SS

DD

200

REFAB = V

DD

CODE = ALL 1s

REFAB = V

DD

CODE = ALL 1s

4.0

3.8

0.5

0

100

0

0.0001 0.001 0.01

0.1

1

10

100

0.0001 0.001 0.01

0.1

1

10

100

0.0001 0.001 0.01

0.1

1

10

100

OUTPUT SOURCE CURRENT (mA)

OUTPUT SINK CURRENT (mA)

TOTAL UNADJUSTED ERROR

vs. DIGITAL CODE (Single Supply)

TOTAL UNADJUSTED ERROR

vs. DIGITAL CODE (Dual Supplies)

POSITIVE SUPPLY CURRENT

vs. SUPPLY VOLTAGE

0

-5

1.5

1.4

12

REFAB = REFC = V

ALL LOGIC INPUTS GROUNDED

V

= +3V, V = -3V

DD

SS

DAC A LOADED WITH 5mA

DAC B LOADED WITH 0.5mA

REFAB = V , REFC = V

CODE = ALL 1s

SS

DD

10

8

1.3

1.2

-10

-15

1.1

1.0

0.9

0.8

6

4

2

DAC A LOADED WITH 5mA

-20

DAC B LOADED WITH 0.5mA

-25

-30

-35

DAC A NO LOAD

DAC B NO LOAD

0.7

0.6

0

V

= 3V, V = GND = 0V

DD SS

REFAB = 3V

DAC C NO LOAD

0.5

-2

2.5

3.0

3.5

4.0

(V)

4.5

5.0

5.5

0

32 64 96 128 160 192 224 255

DIGITAL CODE

0

32 64 96 128 160 192 224 255

DIGITAL CODE

V

DD

4

_______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T = +25°C, unless otherwise noted.)

A

POSITIVE SUPPLY CURRENT

vs. TEMPERATURE

SHUTDOWN SUPPLY CURRENT

vs. TEMPERATURE

SUPPLY CURRENT

vs. REFERENCE VOLTAGE

1.5

1.370

4.5

4.0

V

= +5V, V = GND = 0V

SS

DD

REFAB = REFC = V

DD

I

, V = 5V, V = -5V

DD DD SS

1.365

1.360

ALL LOGIC INPUTS = +5V

1.0

0.5

3.5

3.0

I

, V = 3V, V = -3V

DD DD SS

2.5

2.0

1.5

1.0

REFC GROUNDED FOR REF_ < 0

CODE = ALL 1s

1.355

1.350

0

I

, V = 3V, V = -3V

SS DD SS

-0.5

V

= +5V, V = GND = 0V

SS

DD

REFAB = REFC = V

ALL LOGIC INPUTS = +5V

ALL DACs SET TO ALL 1s

DD

1.345

1.340

-1.0

-1.5

I

, V = 5V, V = -5V

SS DD

SS

0.5

0

-60 -40 -20

0

20 40 60 80 100 120 140

-60 -40 -20

0

20 40 60 80 100 120 140

-5 -4 -3 -2 -1

0

1

2

3

4

TEMPERATURE (°C)

REFAB = REFC (V)

REFERENCE FEEDTHROUGH

vs. FREQUENCY

REFERENCE LARGE-SIGNAL

FREQUENCY RESPONSE

REFERENCE SMALL-SIGNAL

FREQUENCY RESPONSE

0

5

0

V

DD

= 3V, V = GND = 0V

SS

REF_ FROM 0V TO 2.9V

-20 NO LOAD

CODE = ALL 0s

0

DAC A

DAC C

-20

-40

-5

-40

DAC B

DAC C

-10

-60

-15

-80

DAC A, B

-60

-80

V

= 3V, V = GND = 0V

SS

DD

V

= 3V, V = GND = 0V

-20

-25

-100

-120

DD SS

REFAB, REFC

SINE WAVE 0V TO V

REFAB, REFC

SINE WAVE ±40mV

DD

0.01

0.1

1

10

100

1000

0.001 0.01 0.1

1

10

100 1000

0.1k

1k

10k

100k 1M

10M

FREQUENCY (kHz)

FREQUENCY (Hz)

_______________________________________________________________________________________

5

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e Ou t p u t DACs

w it h S e ria l In t e rfa c e

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T = +25°C, unless otherwise noted.)

A

LINE-TRANSIENT RESPONSE (OUTC)

LINE-TRANSIENT RESPONSE (OUTA)

3.14V

2.86V

A

B

A

2.86V

B

2/MAX513

20µs/div

REFC = 2.56V, NO LOAD, CODE = ALL 1s

REFAB = 2.56V, NO LOAD, CODE = ALL 1s

A : V , 100mV/div

DD

A : V 100mV/div

DD,

B : OUTA, 500µV/div

B : OUTC, 2mV/div

CLOCK FEEDTHROUGH (OUTA)

CLOCK FEEDTHROUGH (OUTC)

A

B

A

B

1µs/div

V = 0V, CS = HIGH

SS

V

SS

= 0V, CS = HIGH

A: SCLK, 333kHz, 0V TO 2.9V, 2V/div

B: OUTC, 2mV/div

A: SCLK, 333kHz, 0V TO 2.9V, 2V/div

B: OUTA, 2mV/div

6

_______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T = +25°C, unless otherwise noted.)

A

POSITIVE SETTLING TIME (DAC A)

POSITIVE SETTLING TIME (DAC B)

A

B

A

B

20µs/div

V

DD

= 3V, V = 0V, REFAB = V R = 1Ωk , C = 0.1µF

V

DD

= 3V, V = 0V, REFAB = V R = 10Ωk , C = 0.01µF

SS

DD,

L

SS

DD,

L

ALL BITS OFF TO ALL BITS ON

A: CS, 2V/div

B: OUTA, 20mV/div

B: OUTB, 20mV/div

POSITIVE SETTLING TIME (DAC C)

POSITIVE SETTLING TIME WITH DUAL SUPPLIES

A

B

10µs/div

V

DD

= 3V, V = 0V, REFC = V R = ∞, C = 122pF

SS DD, L L

V

DD

= 5V, V = -5V, REFAB = 2.56V, R = 1Ωk , C = 0.1µF

SS L L

ALL BITS OFF TO ALL BITS ON

A: CS, 2V/div

A: CS, 5V/div

B: OUTC, 20mV/div

B: OUTA, 10mV/div

_______________________________________________________________________________________

7

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T_A= +25°C, unless otherwise noted.)

TIME EXITING SHUTDOWN MODE

OUTPUT VOLTAGE NOISE DC TO 1MHz

A

B

OUTA,

200µV/div

2/MAX513

20µs/div

2ms/div

V

DD

= 3V, V = 0V, REFAB = V R = 1Ωk , C = 0.1µF

DIGITAL CODE = 80, REFAB = V NO LOAD

DD,

SS

DD,

L

DAC LOADED WITH ALL 1s

A: CS, 2V/div

B: OUTA, 1V/div

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

DIN

Serial Data Input of the 16-bit shift register. Data is clocked into the register on the rising edge of SCLK.

1

Chip Select (active low). Enables data to be shifted into the 16-bit shift register. Programming commands

are executed at the rising edge of CS.

–—–

CS

2

3

4

–—–

SCLK

Serial Clock Input. Data is clocked in on the rising edge of SCLK.

Asynchronous reset input (active low). Clears all registers to their default state (FFhex for DAC A and

DAC B registers); all other registers are reset to 0 (including the input shift register).

–————–

RES ET

5

6

V

Positive Power Supply (2.7V to 5.5V). Bypass with 0.22µF to GND.

Ground

DD

GND

Negative Power Supply 0V or (-1.5V to -5.5V). Tie to GND for single supply operation. If a negative supply

is applied, bypass with 0.22µF to GND.

7

V

SS

8

OUTA

OUTB

OUTC

REFC

REFAB

I.C.

DAC A Output Voltage (Buffered). Resets to full scale. Connect 0.1µF capacitor or greater to GND.

DAC B Output Voltage (Buffered). Resets to full scale. Connect 0.01µF capacitor or greater to GND.

DAC C Output Voltage (Unbuffered). Resets to zero.

DAC C Reference Voltage

9

10

11

12

13

14

DAC A/B Reference Voltage

Internally connected. Do not make connections to this pin.

Logic Output (latched)

LOUT

8

_______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

_______________De t a ile d De s c rip t io n

An a lo g S e c t io n

The MAX512/MAX513 contain three 8-bit, voltage-out-

R

OUT

put, digital-to-analog converters (DACs). The DACs are

“inverted” R-2R ladder networks using complementary

switches that convert 8-bit digital inputs into equivalent

analog output voltages in proportion to the applied ref-

erence voltages.

2R

The MAX512/MAX513 have two reference inputs: one is

shared by DAC A and DAC B and the other is used by

DAC C. These inputs allow different full-scale output

voltages and different output voltage polarities for the

DAC pair A/B and DAC C.

REF

GND

SHOWN FOR ALL 1s ON DAC; DAC C IS NOT BUFFERED

The MAX512/MAX513 include output buffer amplifiers

for DACs A and B and input logic for simple micro-

processor (µP) and CMOS interfaces.

Figure 1. DAC Simplified Circuit Diagram

The MAX512/MAX513 operate in either single-supply or

Output Buffer Amplifiers (DAC A / DAC B)

DAC A a nd DAC B volta g e outp uts a re inte rna lly

b uffe re d . The b uffe r a mp lifie rs ha ve a ra il-to-ra il

(V to V ) output voltage range.

SS DD

dual-supply mode, as determined by V . If V is with-

SS

in approximately -0.5V of GND, single-supply mode is

assumed. If V is below -1.5V, the devices are in dual-

SS

supply mode.

In single-supply mode, the DAC outputs A and B are

internally divided by two and the buffer is set to a gain

of two, eliminating the need for a buffer input voltage

range to the positive supply rail.

Reference Inputs and DAC Output Range

The voltage at REF_ sets the full-scale output of the

DACs. The input impedance of the REF_ inputs is code

dependent. The lowest value, approximately 12kΩ for

REFC (8kΩ for REFAB), occurs when the input code is

01010101 (55he x). The ma ximum va lue of infinity

occurs when the input code is zero.

In dual-supply mode, the DAC outputs are not attenuat-

ed and the buffer is set to unity gain.

Although only necessary for negative output voltages,

the dual-supply mode may be used even if the desired

DAC output voltage is positive. Possible errors associ-

ated with the divide-by-two attenuator and gain-of-two

buffers in single-supply mode are eliminated in dual-

supply mode. In this case, do not use reference volt-

In shutdown mode, the selected DAC output is set to

zero while the value stored in the DAC register remains

unchanged. This removes the load from the reference

input to save power. Bringing the MAX512/MAX513 out

of shutdown mode restores the DAC output voltage.

Because the input resistance at REF_ is code depen-

dent, the DAC’s reference sources should have an out-

put impedance of no more than 5Ω. The input capaci-

tance at the REF_ pins is also code dependent and

typically does not exceed 25pF.

ages higher than (V - 1.5V).

DD

DAC A’s output amplifier can source and sink up to 5mA

of c urre nt (0.5mA for DAC B b uffe r). Se e the Tota l

Unadjusted Error vs. Digital Code graph in the Typical

Operating Characteristics for dual and single supplies.

The amplifier is unity-gain stable with a capacitive load of

0.05µF (0.01µF for DAC B buffer) or greater. The slew

rate is limited by the load capacitor and is typically

0.1V/µs with a 0.1µF load (0.01µF for DAC B buffer).

The reference voltage on REFAB can range anywhere

between the supply rails. In dual-supply mode, a posi-

tive reference input voltage on REFAB should be less

than (V - 1.5V) to avoid saturating the buffer ampli-

DD

Unbuffered Output (DAC C)

The output of DAC C is unbuffered and has a typical out-

put impedance of 24kΩ. It can be used to drive a high-

impedance load, such as an op amp or comparator, and

has 35µs typical settling time to 1/2LSB with a single 3V

supply. Use DAC C if a quick dynamic response is

required.

fiers. The reference voltage includes the negative sup-

ply rail. See the Output Buffer Amplifier section for more

information. The REFC input accepts positive voltages

up to V and should not be forced below ground.

DD

The absolute difference between any reference voltage

and GND should not exceed 6V.

_______________________________________________________________________________________

9

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

Shutdown Mode

When programmed to shutdown mode, the outputs of

Table 1. Input Shift Register

B0*

DAC Data Bit 0 (LSB)

DAC A and B go into a high-impedance state. Virtually

no current flows into or out of the buffer amplifiers in

that state. The output of DAC C goes to 0V when shut

down. In shutdown mode, the REF_ inputs are high

impedance (2MΩ typ) to conserve current drain from

the system reference; therefore, the system reference

does not have to be powered down. The logic output

LOUT remains active in shutdown.

B1

DAC Data Bit 1

B2

DAC Data Bit 2

B3

DAC Data Bit 3

B4

DAC Data Bit 4

B5

DAC Data Bit 5

B6

DAC Data Bit 6

Coming out of shutdown, the DAC outputs return to the

values kept in the registers. The recovery time is equiv-

alent to the DAC settling time.

B7

DAC Data Bit 7 (MSB)

Load Reg DAC A, Active High

Load Reg DAC B, Active High

Load Reg DAC C, Active High

Shut Down DAC A, Active High

Shut Down DAC B, Active High

Shut Down DAC C, Active High

Logic Output

LA

LB

LC

SA

SB

SC

Q1

Q2**

Reset

–————–

The RESET input is active low. When asserted (RESET

= 0), DACs A and B are set to full scale (FFhex) and

active, while DAC C is set to zero code (00hex) and

active. The 16-bit serial register is cleared to 0000hex.

LOUT is reset to zero.

2/MAX513

S e ria l In t e rfa c e

An active-low chip select (CS) enables the shift register

Uncommitted Bit

–—–

**Clocked in last.

**Clocked in first.

to re c e ive d a ta from the s e ria l d a ta inp ut. Da ta is

clocked into the shift register on every rising edge of

the serial clock signal (SCLK). The clock frequency can

be as high as 5MHz.

–—–

the input shift register, the rising edge of CS updates

the DAC outputs, the shutdown status, and the status of

the logic output. Because of their single buffered struc-

ture, DACs cannot be simultaneously updated to differ-

ent digital values.

Data is sent MSB first and can be transmitted in one

16-bit word. The write cycle can be interrupted at any

–—–

time when CS is kept active (low) to allow, for example,

two 8-bit-wide transfers. After clocking all 16 bits into

CS

INSTRUCTION

EXECUTED

SCLK

OPTIONAL

SDIN

Q2 Q1 SC SB SA LC LB LA

(CONTROL BYTE)

D7 D6 D5 D4 D3 D2 D1 D0

(DATA BYTE)

Figure 2. MAX512/MAX513 3-Wire Serial-Interface Timing Diagram

10 ______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

Table 2. Serial-Interface Programming Commands

CONTROL

DATA

FUNCTION

MSB

LSB

Q2 Q1 SC SB SA LC LB LA B7 B6 B5 B4 B3 B2 B1 B0

*

0

1

*

0

1

0

1

*

0

1

0

1

*

0

1

*

X

No Operation to DAC Registers

Load Register to DAC C

Load Register to DAC B

Load Register to DAC A

Load All DAC Registers

All DACs Active

*

0

1

0

1

*

8-Bit DAC Data

*

X

*

0

1

0

1

0

1

*

X

Shut Down DAC C

Shut Down DAC B

Shut Down DAC A

Shut Down All DACs

Reset LOUT

Set LOUT

X

*

Don’t care.

Not shown for clarity. The functions of loading and shutting down the DACs and programming the logic can be combined in a single command.

Serial-Input Data Format and Control Codes

Digital Inputs

The digital inputs are compatible with CMOS logic.

Supply current increases slightly when toggling the

log ic inp uts throug h the tra ns ition zone b e twe e n

Table 2 lists the serial-input data format. The 16-bit

input word consists of an 8-bit control byte and an 8-bit

data byte. The 8-bit control byte is not decoded inter-

nally. Every control bit performs one function. Data is

clocked in starting with Q2 (uncommitted bit), followed

by the remaining control bits and the data byte. The

LSB of the data byte (B0) is the last bit clocked into the

shift register (Figure 2).

(0.3)(V ) and (0.7)(V ).

DD

Digital Output

The latched digital output (LOUT) has a 1.6mA source

capability while maintaining a (V - 0.4V) output level.

DD

With a 1.6mA sink current, the output voltage is guaran-

teed to be no more than 0.4V. The output can be used

for digital auxiliary control. Please note that the digital

output remains fully active during shutdown mode.

Example of a 16-bit input word:

Loaded

in First

Loaded

in Last

Q2 Q1 SC SB SA LC LB LA B7 B6 B5 B4 B3 B2 B1 B0

Microprocessor Interfacing

The MAX512/MAX513 serial interface is compatible with

Microwire, SPI, and QSPI. For SPI and QSPI, clear the

CPOL a nd CPHA b its (CPOL = 0 a nd CPHA = 0).

CPOL = 0 sets the inactive state of clock to zero and

CPHA = 0 changes data at the falling edge of SCLK.

This setting allows both SPI and QSPI to run at full clock

speeds (0.5MHz and 4MHz, respectively). If a serial port

is not available on your µP, three bits of a parallel port

can be used to emulate a serial port by bit manipulation.

Minimize digital feedthrough at the voltage outputs by

operating the serial clock only when necessary.

X

0

1

0

1

0

The example above performs the following functions:

• 80hex (128 decimal) loaded into DAC registers

A and B.

• Content of the DAC C register remains unchanged.

• DAC A and DAC B are active.

• DAC C is shut down.

• LOUT is reset to 0.

______________________________________________________________________________________ 11

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

CS

t

CSPWH

t

CSH

CSS

t

CH

SCLK

t

CL

t

DS

t

DH

DIN

2/MAX513

t

OD

LOUT

Figure 3. MAX512/MAX513 Detailed Serial-Interface Timing Diagram

P o w e r-S u p p ly Byp a s s in g a n d

Gro u n d Ma n a g e m e n t

_____________ Ap p lic a t io n s In fo rm a t io n

P o w e r-S u p p ly a n d Re fe re n c e

Op e ra t in g Ra n g e s

The MAX512 is fully s p e c ifie d to op e ra te with

In single-supply operation (V = GND), GND and V

SS

should be connected to the highest quality ground

available. Bypass V with a 0.1µF to 0.22µF capacitor

DD

V

= 5V ±10% and V = GND = 0V. The MAX513 is

to GND. For dual-supply operation, bypass V with a

DD

SS

specified for single-supply operation with V ranging from

0.1µF to 0.22µF capacitor to GND. Reference inputs

can be used without bypassing. For optimum line/load-

transient response and noise performance, bypass the

reference inputs with 0.1µF to 4.7µF to GND. Careful

PC board layout minimizes crosstalk among DAC out-

puts, reference inputs, and digital inputs. Separate ana-

log lines with ground traces between them. Make sure

that high-frequency digital lines are not routed in paral-

lel to analog lines.

DD

2.7V to 3.6V, covering all commonly used supply voltages

in 3V systems. The MAX512/MAX513 can also be used

with a negative supply ranging from -1.5V to -5.5V. Using a

negative supply typically improves zero-code error and

s e ttling time (a s s hown in the Typ ic a l Op e ra ting

Characteristics graphs).

The two separate reference inputs for the DAC pair A/B

and the unbuffered output C allow different full-scale out-

put voltages and, if a negative supply is used, also allow

different polarity. In dual-supply mode, REFAB can vary

from V to (V - 1.5V). In single-supply mode, the

Un ip o la r Ou t p u t

With unipolar output, the output voltage and the refer-

e nc e volta g e a re the s a me p ola rity. The MAX512/

MAX513 can be used with a single supply if the refer-

ence voltages are positive. With a negative supply,

SS

DD

specified range for REFAB is 0V to V . REFC can range

DD

from GND to V . Do not force REFC below ground.

DD

th e REFAB volta g e c a n va ry from

V

to

Power-supply sequencing is not critical. If a negative sup-

SS

approximately (V - 1.5V), allowing two-quadrant mul-

ply is used, make sure V is never more than 0.3V above

DD

SS

tiplication.

ground. Do not apply signals to the digital inputs until the

device is powered-up. If this is not possible, add current-

limiting resistors to the digital inputs.

12 ______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

Table 3. Unipolar Code Table

Table 4. Bipolar Code Table

DAC CONTENTS

ANALOG

OUTPUT

ANALOG

OUTPUT

B7 B6 B5 B4 B3 B2 B1 B0

255

256

127

128

+REF_ ×

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

129

256

1

+REF_ ×

0V

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

128

REF_

2

=

+

256

1

−REF_ ×

128

127

256

127

128

−REF_ ×

0

1

0

1

0

1

0

256

128

=

− REF_

128

0V

Note :

1LSB

Note :

1LSB

1

−(8 - 1)

−8

=

REF_ × 2

= REF_ ×

=

REF_ × 2

= REF_ ×

128

256

D

ANALOG OUTPUT = REF_ ×

−1

ANALOG OUTPUT = REF_ ×

128

256

Bip o la r Ou t p u t

RF Ap p lic a t io n s

Using Figure 4’s circuit, the MAX512/MAX13 can be con-

figured for bipolar outputs. Table 4 lists the bipolar codes

and corresponding output voltages. There are two ways to

a c hie ve ra il-to-ra il outp uts : 1) Op e ra te the

MAX512/MAX513 with a single supply and positive refer-

ence voltages or 2) Use dual supplies with a positive or

negative voltage at REFAB and a positive voltage at REFC.

In either case, the op amps need dual supplies. When

using the dual-supply mode, possible errors associated

with the divide-by-two attenuator and gain-of-two buffer are

eliminated (see the Output Buffer Amplifier section). For

maximum output swing of all outputs in dual-supply mode,

Both the MAX512 and MAX513 can bias GaAs FETs,

where the gate of the FETs must be negatively biased

to ensure that there is no drain current. In a typical

application, power to the RF amplifiers should not be

turned on until the bias voltages provided by DAC A

and DAC B are fully established; likewise, the supply

should be turned off before the bias voltage is switched

off. Figure 5 shows how DAC B supplies the negative

bias V

negative bias V

for the driver stage and DAC A provides the

GG1

for the output stage [1].

GG2

The DAC A and DAC B outputs are also ideal for con-

trolling VCOs in mobile radios or cellular phones. Other

applications include varactor and PIN diode circuits.

connect REFAB to V and REFC to V . In single-supply

SS

DD

mode, connect REFAB, REFC, and V together.

DD

The unbuffered DAC C provides a span within GND

and V and is individually set at REF C. DAC C typi-

cally adjusts offset and gain in the system.

With dual supplies, DACs A and B can perform four-

quadrant multiplication. Please note that in dual-supply

DD

mod e , the REFAB inp ut ra ng e s from V to (V

-

SS

DD

1.5V). Because REFC accepts only positive inputs,

DAC C performs two-quadrant multiplication.

Figure 4 shows Maxim’s ICL7612A with rail-to-rail input

common-mode range and rail-to-rail output voltage

swing—ideal for a high output voltage swing from low

supply voltages.

1 [John Wachsmann. “A High-Efficiency GaAs MMIC Power Amplifier for

1.9GHz PCS Applications,” Proceedings of the First Annual Wireless

Symposium, pp. 375, Penton Publishing, Jan. 1993.]

______________________________________________________________________________________ 13

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

REFAB

V

DD

REFC

11

R*

DIN

1

CS

R*

0.1µF

12

2

SCLK

3

V

OUT

8

ICL7612A**

DAC

OUTA

DAC A

LATCH

A

0.05µF

0.1µF

V

SS

R*

9

DAC

LATCH

B

OUTB

DAC B

DAC C

V

DD

R*

0.1µF

DAC

LATCH

C

10

OUTC

V

OUT

ICL7612A**

2/MAX513

MAX512

MAX513

14

LATCH

LOUT

V

SS

V

7

RESET

4

DD

SS

GND

6

5

* R IN 10kΩ RANGE

** CONNECT PIN 8 TO GND

0.22µF

V

DD

V

SS

Figure 4. Bipolar Output Circuit

V

DD1

V

DD2

RF

IN

RF

OUT

REFAB = -4.2V

MAX512

V

GG1

V

GG2

MAX513

OUTB

DAC B

0.01µF

0.05µF

OUTA

DAC A

Figure 5. RF Bias Circuit

14 ______________________________________________________________________________________

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

2/MAX513

_Ord e rin g In fo rm a t io n (c o n t in u e d )

___________________Ch ip To p o g ra p h y

PART

TEMP. RANGE

-40°C to +85°C

-55°C to +125°C

0°C to +70°C

PIN-PACKAGE

14 Plastic DIP

14 SO

OUTC OUTB OUTA

V

SS

GND

MAX512EPD

MAX512ESD

MAX512MJD

MAX513CPD

MAX513CSD

MAX513C/D

MAX513EPD

MAX513ESD

MAX513MJD

V

DD

14 CERDIP

14 Plastic DIP

14 SO

REFC

0°C to +70°C

REFAB

0°C to +70°C

Dice*

-40°C to +85°C

-55°C to +125°C

14 Plastic DIP

14 SO

0. 122"

14 CERDIP

(3. 099mm)

* Contact factory for dice specifications.

RESET

SCLK

LOUT

DIN CS

0. 081"

(2. 057mm)

TRANSISTOR COUNT: 1910

SUBSTRATE CONNECTED TO V

DD

______________________________________________________________________________________ 15

Lo w -Co s t , Trip le , 8 -Bit Vo lt a g e -Ou t p u t DACs

w it h S e ria l In t e rfa c e

________________________________________________________P a c k a g e In fo rm a t io n

INCHES

MILLIMETERS

DIM

D1

MIN

MAX

0.200

–

MIN

–

MAX

5.08

–

A

–

A1 0.015

A2 0.125

A3 0.055

0.38

3.18

1.40

0.41

1.27

0.20

18.67

1.27

7.62

6.10

0.150

0.080

0.022

0.065

0.012

0.765

0.080

0.325

0.280

3.81

2.03

0.56

1.65

0.30

19.43

2.03

8.26

7.11

B

0.016

B1 0.050

C

D

0.008

0.735

E

D1 0.050

0.300

E1 0.240

E

E1

D

e

0.100 BSC

0.300 BSC

2.54 BSC

7.62 BSC

A3

e

A

B

2/MAX513

A2

A1

A

L

e

–

0.115

0˚

0.400

0.150

15˚

–

10.16

3.81

L

2.92

0˚

α

15˚

21-330A

α

14-PIN PLASTIC

DUAL-IN-LINE

PACKAGE

C

e

B1

e

A

B

INCHES

MILLIMETERS

DIM

MIN

0.053

MAX

0.069

0.010

0.019

0.010

0.344

0.157

MIN

1.35

0.10

0.35

0.19

8.55

3.80

MAX

1.75

0.25

0.49

0.25

8.75

4.00

A

A1 0.004

B

C

D

E

e

0.014

0.007

0.337

0.150

E

H

0.050 BSC

1.27 BSC

H

h

0.228

0.010

0.016

0˚

0.244

0.020

0.050

8˚

5.80

0.25

0.40

0˚

6.20

0.50

1.27

L

α

8˚

21-331A

h x 45˚

D

α

A

0.127mm

0.004in.

14-PIN PLASTIC

SMALL-OUTLINE

PACKAGE

e

A1

C

B

L

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX513MJD
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	Low-Cost, Triple, 8-Bit Voltage-Output DACs with Serial Interface 低成本，三路， 8位电压输出DAC，串行接口
文件：	总16页 (文件大小：180K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX513MJD [MAXIM]

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