MAX5155BEEE [MAXIM]
Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface; 低功耗,双通道, 12位电压输出DAC,串行接口型号: | MAX5155BEEE |
厂家: | MAXIM INTEGRATED PRODUCTS |
描述: | Low-Power, Dual, 12-Bit Voltage-Output DACs with Serial Interface |
文件: | 总16页 (文件大小:185K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
19-1316; Rev 1; 12/97
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 12-Bit Dual DAC with Internal Gain of +2V/V
♦ Rail-to-Rail Output Swing
The MAX5154/MAX5155 low-power, serial, voltage-out-
put, dual 12-bit digital-to-analog converters (DACs)
consume only 500µA from a single +5V (MAX5154) or
+3V (MAX5155) supply. These devices feature Rail-to-
Rail® output swing and are available in a space-saving
16-p in QSOP p a c ka g e . To ma ximize the d yna mic
range, the DAC output amplifiers are configured with an
internal gain of +2V/V.
♦ 12µs Settling Time
♦ Single-Supply Operation: +5V (MAX5154)
+3V (MAX5155)
♦ Low Quiescent Current: 500µA (normal operation)
2µA (shutdown mode)
♦ SPI/QSPI and Microwire Compatible
The 3-wire s e ria l inte rfa c e is SPI™/QSPI™ a nd
Mic rowire ™ c omp a tib le . Ea c h DAC ha s a d oub le -
buffered input organized as an input register followed
by a DAC register, which allows the input and DAC reg-
isters to be updated independently or simultaneously
with a 16-bit serial word. Additional features include
programmable shutdown (2µA), hardware-shutdown
lockout (PDL), a separate reference voltage input for
each DAC that accepts AC and DC signals, and an
active-low clear input (CL) that resets all registers and
DACs to zero. These devices provide a programmable
logic pin for added functionality, and a serial-data out-
put pin for daisy chaining.
♦ Available in Space-Saving 16-Pin QSOP Package
♦ Power-On Reset Clears Registers and DACs
to Zero
♦ Adjustable Output Offset
______________Ord e rin g In fo rm a t io n
INL
PART
TEMP. RANGE
PIN-PACKAGE
(LSB)
±1/2
±1
MAX5154ACPE
MAX5154BCPE
MAX5154ACEE
MAX5154BCEE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
±1/2
±1
________________________Ap p lic a t io n s
16 QSOP
Industrial Process Control Remote Industrial Controls
Ordering Information continued at end of data sheet.
Pin Configuration appears at end of data sheet.
Digital Offset and Gain
Adjustment
Microprocessor-
Controlled Systems
Motion Control
Automatic Test
Equipment (ATE)
_________________________________________________________Fu n c t io n a l Dia g ra m
V
DD
CL
PDL
DGND
DOUT
REFA
AGND
OSA
DECODE
CONTROL
R
R
OUTA
OSB
DAC
REG A
INPUT
REG A
DAC A
16-BIT
SHIFT
REGISTER
R
R
MAX5154
MAX5155
SR
CONTROL
OUTB
DAC
REG B
INPUT
REG B
DAC B
LOGIC
OUTPUT
UPO
REFB
CS
DIN
SCLK
Rail-to-Rail is a registered trademark of Nippon Motorola Ltd.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
to AGND............................................................-0.3V to +6V
to DGND ...........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
V
Plastic DIP (derate 10.5mW/°C above +70°C) ...........842mW
QSOP (derate 8.30mW/°C above +70°C)...................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
DD
AGND to DGND..................................................................±0.3V
OSA, OSB to AGND........................(AGND - 4V) to (V + 0.3V)
REF_, OUT_ to AGND.................................-0.3V to (V + 0.3V)
DD
DD
Digital Inputs (SCLK, DIN, CS, CL, PDL)
to DGND............................................................(-0.3V to +6V)
Digital Outputs (DOUT, UPO)
MAX515_ _C_ E .................................................0°C to +70°C
MAX515_ _E_ E ..............................................-40C° to +85°C
MAX515_ _MJE.............................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
to DGND................................................-0.3V to (V + 0.3V)
DD
Maximum Current into Any Pin .........................................±20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5154
(V = +5V ±10%, V
= V
= 2.048V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values are
MAX
DD
REFA
REFB
L
L
A
MIN
at T = +25°C (OS_ tied to AGND for a gain of +2V/V).)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4/MAX15
12
Bits
MAX5154A
MAX5154B
±1/2
±1
Integral Nonlinearity
INL
(Note 1)
LSB
Differential Nonlinearity
Offset Error
DNL
Guaranteed monotonic
Code = 6
±1
LSB
mV
V
os
±6
Offset Tempco
Gain Error
TCV
Normalized to 2.048V
4
-0.2
4
ppm/°C
LSB
os
±3
Gain-Error Tempco
Normalized to 2.048V
ppm/°C
V
Power-Supply
DD
PSRR
REF
4.5V ≤ V ≤ 5.5V
20
260
µV/V
DD
Rejection Ratio
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
0
V
- 1.4
V
DD
R
Minimum with code 1554 hex
Input code = 1FFE hex,
14
20
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
300
-82
75
kHz
dB
V
REF_
= 0.67Vp-p at 2.5V
DC
Input code = 0000 hex,
= (V - 1.4Vp-p) at 1kHz
Reference Feedthrough
Signal-to-Noise plus
V
REF_
DD
Input code = 1FFE hex,
V = 1Vp-p at 1.25V , f = 25kHz
REF_
SINAD
dB
Distortion Ratio
DC
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
3
V
V
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
= 0V to V
IN DD
C
IN
2
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
ELECTRICAL CHARACTERISTICS—MAX5154 (continued)
(V = +5V ±10%, V
= V
= 2.048V, R = 10kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical values are
DD
REFA
REFB
L
L
A
MIN
MAX
at T = +25°C (OS_ tied to AGND for a gain of +2V/V).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DOUT, UPO)
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.40
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.75
15
V/µs
µs
To 1/2LSB of full-scale, V
= 4V
STEP
Output Voltage Swing
OSA or OSB Input Resistance
Time Required to Exit Shutdown
Digital Feedthrough
Rail-to-rail (Note 2)
0 to V
V
DD
R
24
34
25
5
kΩ
µs
OS_
nV-s
nV-s
CS = V , f
= 100kHz, V
= 5Vp-p
DD DIN
SCLK
Digital Crosstalk
5
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
Power-Supply Current
V
4.5
5.5
V
DD
I
DD
(Note 3)
(Note 3)
0.5
2
0.65
mA
I
10
±1
µA
µA
DD(SHDN)
in Shutdown
Reference Current in Shutdown
TIMING CHARACTERISTICS
SCLK Clock Period
0
t
CP
(Note 4)
100
40
ns
ns
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise
Setup Time
t
40
0
ns
ns
CSS
SCLK Rise to CS Rise
Hold Time
t
CSH
SDI Setup Time
SDI Hold Time
t
40
0
ns
ns
DS
t
DH
SCLK Rise to DOUT
Valid Propagation Delay
t
C
C
= 200pF
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT
Valid Propagation Delay
t
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
CS0
t
CS1
t
100
CSW
Note 1: Accuracy is specified from code 6 to code 4095.
Note 2: Accuracy is better than 1LSB for V _ greater than 6mV and less than V - 50mV. Guaranteed by PSRR test at the end
OUT
DD
points.
Note 3: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.
DD
L
Note 4: SCLK minimum clock period includes the rise and fall times.
_______________________________________________________________________________________
3
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS—MAX5155
(V = +2.7V to +3.6V, V
= V
= 1.25V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values
MAX
DD
REFA
REFB
L
L
A
MIN
are at T = +25°C (OS_ pins tied to AGND for a gain of +2V/V).)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
MAX5155A
MAX5155B
±1
±2
±1
±6
Integral Nonlinearity
INL
(Note 5)
LSB
Differential Nonlinearity
Offset Error
DNL
Guaranteed monotonic
Code = 10
LSB
mV
V
os
Offset Tempco
Gain Error
TCV
Normalized to 1.25V
6.5
-0.2
6.5
ppm/°C
LSB
os
±4
Gain-Error Tempco
Normalized to 1.25V
ppm/°C
V
Power-Supply
DD
PSRR
REF
2.7V ≤ V ≤ 3.6V
40
320
µV/V
DD
Rejection Ratio
4/MAX15
REFERENCE INPUT (VREF)
Reference Input Range
0
V
- 1.4
V
DD
Reference Input Resistance
R
Minimum with code 1554 hex
Input code = 1FFE hex,
14
20
kΩ
REF
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
300
-82
73
kHz
dB
V
REF_
= 0.67Vp-p at 0.75V
DC
Input code = 0000 hex,
= (V - 1.4)Vp-p at 1kHz
Reference Feedthrough
V
REF_
DD
Signal-to-Noise plus
SINAD
Input code = 1FFE hex,
V = 1Vp-p at 1V , f = 15kHz
REF_
dB
Distortion Ratio
DC
DIGITAL INPUTS
Input High Voltage
V
2.2
V
V
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
IH
Input Low Voltage
V
IL
0.8
±1
Input Hysteresis
V
HYS
200
0
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
= 0V to V
IN DD
8
C
IN
DIGITAL OUTPUTS (DOUT, UPO)
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.4
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.75
15
V/µs
µs
To 1/2LSB of full-scale, V
= 2.5V
STEP
Output Voltage Swing
OSA or OSB Input Resistance
Rail-to-rail (Note 6)
0 to V
V
DD
R
24
34
kΩ
OS_
Time Required for Valid
Operation after Shutdown
25
µs
Digital Feedthrough
Digital Crosstalk
5
5
nV-s
nV-s
CS = V , f
= 100kHz, V
= 3Vp-p
SCLK
DD DIN
4
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
ELECTRICAL CHARACTERISTICS—MAX5155 (continued)
(V = +2.7V to +3.6V, V
= V
= 1.25V, R = 10kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical values
MAX
DD
REFA
REFB
L
L
A
MIN
are at T = +25°C (OS_ pins tied to AGND for a gain of +2V/V).)
A
PARAMETER
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
2.7
3.6
0.6
V
I
DD
(Note 7)
(Note 7)
0.45
mA
Power-Supply Current
in Shutdown
I
1
0
8
µA
µA
DD (SHDN)
Reference Current in Shutdown
TIMING CHARACTERISTICS
SCLK Clock Period
±1
t
(Note 4)
100
40
ns
ns
ns
CP
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise
Setup Time
t
40
ns
CSS
t
0
50
0
ns
ns
ns
SCLK Rise to CS Rise Hold Time
SDI Setup Time
CSH
t
DS
SDI Hold Time
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
C
C
= 200pF
= 200pF
120
120
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay
t
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
CS0
t
CS1
t
100
CSW
Note 5: Accuracy is specified from code 10 to code 4095.
Note 6: Accuracy is better than 1LSB for V greater than 6mV and less than V - 80mV. Guaranteed by PSRR test at the end
OUT
DD
points.
Note 7: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.
DD
L
_______________________________________________________________________________________
5
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, R = 10kΩ, C = 100pF, OS_ pins tied to AGND, T = +25°C, unless otherwise noted.)
A
DD
L
L
MAX5154
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
SUPPLY CURRENT vs. TEMPERATURE
0
-30
700
650
600
550
500
450
400
V
REF
= 1Vp-p @ 2.5V
DC
-2
-4
CODE = 1FFE (HEX)
CODE = 1FFE (HEX)
CODE = 0000 (HEX)
-40
-50
-60
-70
-6
-8
-10
-12
-14
-16
-18
-20
V
= 0.67Vp-p @ 2.5V
DC
REF
V
REF
= 2.048V
CODE = 1FFE (HEX)
R = ∞
L
-80
4/MAX15
1
10
100
-55 -35 -15
5
25 45 65 85 105 125
1
370
740
1110
1480
1850
FREQUENCY (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
SHUTDOWN CURRENT
vs. TEMPERATURE
REFERENCE FEEDTHROUGH AT 1kHz
FULL-SCALE ERROR vs. RESISTIVE LOAD
-50
-60
0.50
0.25
0
6
5
4
3
2
1
0
V
REF
= 3.6Vp-p @ 1.88V
DC
V
= 2.048V
V
REF
= 1V
REF
CODE = 0000 (HEX)
-70
-80
-0.25
-90
-100
-110
-120
-130
-140
-150
-0.50
-0.75
-1.00
-1.25
-1.50
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz)
-55 -35 -15
5
25 45 65 85 105 125
0.1
1
10
100
TEMPERATURE (°C)
R (kΩ)
L
OUTPUT FFT PLOT
DYNAMIC RESPONSE RISE TIME
DYNAMIC RESPONSE FALL TIME
MAX5154/5155 toc08
MAX5154/5155 toc09
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= 2.45Vp-p @ 1.225V
DC
REF
f = 1kHz
CODE = 1FFE (HEX)
CS
5V/div
CS
5V/div
NOTE: RELATIVE TO FULL-SCALE
OUT_
1V/div
OUT_
1V/div
0.5
1.6
2.7
3.8
4.9
6.0
2µs/div
2µs/div
V
REF
= 2.048V
V
REF
= 2.048V
FREQUENCY (kHz)
6
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, R = 10kΩ, C = 100pF, OS_pins tied to AGND, T = +25°C, unless otherwise noted.)
DD
L
L
A
MAX5155
SUPPLY CURRENT vs. TEMPERATURE
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
0
560
540
520
500
480
460
440
420
400
-30
V
R = ∞
L
= 1V
V
= 1Vp-p @ 1V
REF
REF DC
-2
-4
CODE = 1FFE (HEX)
CODE = 1FFE (HEX)
-40
-50
-60
-70
-6
-8
-10
-12
-14
-16
-18
-20
CODE = 0000 (HEX)
V
= 0.67Vp-p @ 0.75V
DC
REF
CODE = 1FFE
-80
-55 -35 -15
5
25 45 65 85 105 125
1
10
100
1
320
640
960
1280
1600
TEMPERATURE (°C)
FREQUENCY (kHz)
FREQUENCY (kHz)
SHUTDOWN CURRENT
vs. TEMPERATURE
REFERENCE FEEDTHROUGH AT 1kHz
FULL-SCALE ERROR vs. RESISTIVE LOAD
-50
-60
3.0
2.8
2.6
2.4
2.2
2.0
1.8
0.25
0
V
R = ∞
L
= 1V
REF
V
= 1.6Vp-p @ 0.88V
DC
REF
V
REF
= 1.25V
CODE = 0000 (HEX)
-70
-80
-0.25
-90
-100
-110
-120
-130
-140
-150
-0.50
-0.75
1.6
1.4
1.2
1.0
-1.00
-1.25
-55 -35 -15
5
25 45 65 85 105 125
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz)
0.1
1
10
100
TEMPERATURE (°C)
R (kΩ)
L
DYNAMIC RESPONSE RISE TIME
OUTPUT FFT PLOT
DYNAMIC RESPONSE FALL TIME
MAX5154/5155 toc17
MAX5154/5155 toc18
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CS
2V/div
CS
2V/div
V
= 1.4Vp-p @ 0.75V
DC
REF
f = 1kHz
CODE = 1FFE (HEX)
OUT_
500mV/div
OUT_
500mV/div
2µs/div
0.5
1.6
2.7
3.8
4.9
6.0
2µs/div
FREQUENCY (kHz)
V
REF
= 1.25V
V
REF
= 1.25V
_______________________________________________________________________________________
7
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V (MAX5154), V = +3V (MAX5155), R = 10kΩ, C = 100pF, OS_ pins tied to AGND, unless otherwise noted.)
L
L
DD
DD
MAX5154/MAX5155
MAX5154
MAX5155
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.60
0.55
0.60
0.55
CODE = 1FFE (HEX)
CODE = 1FFE (HEX)
0.50
0.45
0.40
0.50
0.45
0.40
CODE = OOOO (HEX)
CODE = OOOO (HEX)
4/MAX15
4.50
4.75
5.00
5.25
5.50
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
MAX5154
MAJOR-CARRY TRANSITION
CS
2V/div
OUT_
50mV/div
AC COUPLED
5µs/div
TRANSITION FROM 1000 (HEX) TO 0FFE (HEX)
MAX5154
MAX5154
ANALOG CROSSTALK
DIGITAL FEEDTHROUGH
SCLK
5V/div
OUTA
5V/div
OUTA
500µV/div
AC COUPLED
OUTB
200µV/div
AC COUPLED
250µs/div
2.5µs/div
V
REF
= 2.048V, GAIN = +2V/V, CODE = 1FFE HEX
8
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
_____________________P in De s c rip t io n
OS_
R
PIN
1
NAME
AGND
OUTA
OSA
FUNCTION
Analog Ground
R
OUT_
2
DAC A Output Voltage
DAC A Offset Adjustment
Reference for DAC A
R
R
R
3
2R
D0
2R
D9
2R
D10
2R
D11
2R
4
REFA
Active-Low Clear Input. Resets all reg-
isters to zero. DAC outputs go to 0V.
5
CL
REF_
6
7
Chip-Select Input
Serial-Data Input
CS
AGND
DIN
SHOWN FOR ALL 1s ON DAC
8
SCLK
DGND
DOUT
UPO
Serial Clock Input
Digital Ground
Figure 1. Simplified DAC Circuit Diagram
9
10
11
Serial-Data Output
User-Programmable Output
V
OUT
= (V
x NB / 4096) x 2
REF
where NB is the numeric value of the DAC’s binary input
code (0 to 4095) and V is the reference voltage.
REF
Power-Down Lockout. The device can-
not be powered down when PDL is low.
12
PDL
The reference input impedance ranges from 14kΩ (1554
hex) to several giga ohms (with an input code of 0000
hex). The reference input capacitance is code dependent
and typically ranges from 15pF with an input code of all
zeros to 50pF with a full-scale input code.
13
14
15
16
REFB
OSB
Reference for DAC B
DAC B Offset Adjustment
DAC B Output Voltage
Positive Power Supply
OUTB
Ou t p u t Am p lifie r
The output amplifiers on the MAX5154/MAX5155 have
internal resistors that provide for a gain of +2V/V when
OS_ is c onne c te d to AGND. The s e re s is tors a re
trimmed to minimize gain error. The output amplifiers
ha ve a typ ic a l s le w ra te of 0.75V/µs a nd s e ttle to
1/2LSB within 15µs, with a load of 10kΩ in parallel with
100pF. Loads less than 2kΩ degrade performance.
V
DD
_______________De t a ile d De s c rip t io n
The MAX5154/MAX5155 dual, 12-bit, voltage-output
DACs are easily configured with a 3-wire serial inter-
face. These devices include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see Functional Diagram). In addition, trimmed internal
resistors produce an internal gain of +2V/V that maxi-
mizes output voltage swing. The amplifier’s offset-adjust
pin allows for a DC shift in the DAC’s output.
The OS_ pin can be used to produce an adjustable off-
set voltage at the output. For instance, to achieve a 1V
offset, apply -1V to the OS_ pin to produce an output
range from 1V to (1V + V
output range is still limited by the maximum output volt-
age specification.
x 2). Note that the DAC’s
REF
Both DACs use an inverted R-2R ladder network that pro-
duces a weighted voltage proportional to the input volt-
age value. Each DAC has its own reference input to
facilitate independent full-scale values. Figure 1 depicts a
simplified circuit diagram of one of the two DACs.
P o w e r-Do w n Mo d e
The MAX5154/MAX5155 feature a software-program-
mable shutdown mode that reduces the typical supply
current to 2µA. The two DACs can be shutdown inde-
pendently, or simultaneously using the appropriate pro-
gramming command. Enter shutdown mode by writing
the appropriate input-control word (Table 1). In shut-
down mode, the reference inputs and amplifier out-
p uts b e c ome hig h imp e d a nc e , a nd the s e ria l
interface remains active. Data in the input registers is
Re fe re n c e In p u t s
The reference inputs accept both AC and DC values
with a voltage range extending from 0V to (V - 1.4V).
Determine the output voltage using the following equa-
tion (OS_ = AGND):
DD
_______________________________________________________________________________________
9
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
Table 1. Serial-Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
D11.......................D0
A0 C1
C0
S0
(MSB)
(LSB)
0
1
0
1
0
0
1
1
1
1
0
0
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
0
0
0
0
Load input register A; DAC registers are unchanged.
Load input register B; DAC registers are unchanged.
Load input register A; all DAC registers are updated.
Load input register B; all DAC registers are updated.
Load all DAC registers from the shift register
(start up both DACs with new data.).
0
1
1
12-bit DAC data
0
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
1
1
0
0
1
0
0
1
0
xxxxxxxxxxxx
xxxxxxxxxxxx
0
0
0
Shut down both DACs (provided PDL = 1).
4/MAX15
Update DAC register A from input register A
(start up DAC A with data previously stored in input register A).
0 0 1 x xxxxxxxx
Update DAC register B from input register B
(start up DAC B with data previously stored in input register B).
0
0
0
1 0 1 x xxxxxxxx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 0 x xxxxxxxx
1 1 1 x xxxxxxxx
0 1 0 x xxxxxxxx
0 1 1 x xxxxxxxx
1 0 0 1 xxxxxxxx
1 0 0 0 xxxxxxxx
0 0 0 x xxxxxxxx
0
0
0
0
0
0
0
Shut down DAC A (provided PDL = 1).
Shut down DAC B (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
No operation (NOP).
x = Don’t care
Note: D11, D10, D9, and D8 become control bits when A0, C1, and C0 = 0. S0 is a sub bit, always zero.
saved, allowing the MAX5154/MAX5155 to recall the
output state prior to entering shutdown when returning
to normal mode. Exit shutdown by recalling the previ-
ous condition or by updating the DAC with new infor-
mation. When returning to normal operation (exiting
shutdown), wait 20µs for output stabilization.
SCLK
SK
MICROWIRE
PORT
MAX5154
MAX5155
DIN
CS
SO
I/O
S e ria l In t e rfa c e
The MAX5154/MAX5155 3-wire serial interface is com-
patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits,
12 bits of data (MSB to LSB), and one sub bit as shown
in Figure 4. The address and control bits determine the
MAX5154/ MAX5155’s response, as outlined in Table 1.
Figure 2. Connections for Microwire
10 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
The MAX5154/MAX5155’s digital inputs are double
buffered, which allows any of the following: loading the
+5V
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
SS
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
DIN
MOSI
SCK
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated, and the state of the registers
when exiting shutdown. The 3-bit address/control deter-
mines the following:
SPI/QSPI
PORT
MAX5154
MAX5155
SCLK
CS
I/O
•
•
registers to be updated
clock edge on which data is to be clocked out via
the serial-data output (DOUT)
CPOL = 0, CPHA = 0
•
•
state of the user-programmable logic output
configuration of the device after shutdown.
Figure 3. Connections for SPI/QSPI
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
MSB...................................................................................LSB
16 Bits of Serial Data
SUB
BIT
Address Bits
A0
Control Bits
MSB...DataBits...LSB
C1, C0
D11.......................D0
12 Data Bits
S0
0
1 Address/2 Control Bits
Figure 4. Serial-Data Format
CS
COMMAND
EXECUTED
SCLK
1
8
9
16
D5 D4 D3 D2 D1 D0 S0
C1
DIN
A0
C0 D11 D10 D9 D8 D7
D6
Figure 5. Serial-Interface Timing Diagram
______________________________________________________________________________________ 11
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
t
CSW
CS
t
CP
t
CSH
t
t
CH
CSS
t
t
CL
CSO
t
CS1
SCLK
DIN
t
DS
t
DH
Figure 6. Detailed Serial-Interface Timing Diagram
SCLK
SCLK
SCLK
MAX5154
MAX5155
MAX5154
MAX5155
MAX5154
MAX5155
4/MAX15
DIN
CS
DOUT
DIN
DOUT
DIN
CS
DOUT
CS
TO OTHER
SERIAL DEVICES
Figure 7. Daisy Chaining MAX5154/MAX5155s
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX5154
MAX5155
SCLK
MAX5154
MAX5155
SCLK
MAX5154
MAX5155
SCLK
DIN
DIN
DIN
Figure 8. Multiple MAX5154/MAX5155s Sharing a Common DIN Line
12 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
Serial-Data Output
OS_
+5V/+3V
The serial-data output, DOUT, is the internal shift regis-
ter’s output. DOUT allows for daisy chaining of devices
and data readback. The MAX5154/MAX5155 can be
p rog ra mme d to s hift d a ta out of DOUT on SCLK’s
falling edge (Mode 0) or on the rising edge (Mode 1).
Mode 0 provides a lag of 16 clock cycles, which main-
tains compatibility with SPI/QSPI and Microwire inter-
fa c e s . In Mod e 1, the outp ut d a ta la g s 15.5 c loc k
cycles. On power-up, the device defaults to Mode 0.
REF_
V
DD
R
R
MAX5154
MAX5155
DAC_
OUT_
AGND
DGND
User-Programmable Logic Output (UPO)
UPO allows an external device to be controlled through
the serial interface (Table 1), thereby reducing the
number of microcontroller I/O pins required. On power-
up, UPO is low.
GAIN = +2V/V
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL can also be
used to asynchronously wake up the device.
OS_
+5V/+3V
REF_
V
OS
V
DD
R
R
MAX5154
MAX5155
Daisy Chaining Devices
Any numb e r of MAX5154/MAX5155s c a n b e d a is y
chained by connecting the DOUT pin of one device to
the DIN pin of the following device in the chain (Figure 7).
DAC _
OUT_
AGND
DGND
Since the MAX5154/MAX5155’s DOUT pin has an inter-
nal active pull-up, the DOUT sink/source capability
determines the time required to discharge/charge a
Figure 10. Setting OS_ for Output Offset
capacitive load. Refer to the digital output V and V
OH
OL
specifications in the Electrical Characteristics.
Table 2. Unipolar Code Table (Gain = +2)
Figure 8 shows an alternate method of connecting sev-
eral MAX5154/MAX5155s. In this configuration, the
data bus is common to all devices; data is not shifted
through a daisy chain. More I/O lines are required in
this configuration because a dedicated chip-select
input (CS) is required for each IC.
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
4095
4096
1 1 1 1 1 1 1 1 11 1 1 (0 )
1 0 0 0 0 0 0 0 00 0 1 (0 )
1 0 0 0 0 0 0 0 00 0 0 (0 )
0 1 1 1 1 1 1 1 11 1 1 (0 )
0 0 0 0 0 0 0 0 0 0 0 1 (0 )
+V
REF
x 2
x 2
=
__________Ap p lic a t io n s In fo rm a t io n
2049
4096
+V
REF
Un ip o la r Ou t p u t
Figure 9 shows the MAX5154/MAX5155 configured for
unipolar, rail-to-rail operation with a gain of +2V/V. The
MAX5154 c a n p rod uc e a 0V to 4.096V outp ut with
2.048V reference (Figure 9), while the MAX5155 can
produce a range of 0V to 2.5V with a 1.25V reference.
Table 2 lists the unipolar output codes. An offset to the
output can be achieved by connecting a voltage to
2048
4096
+V
REF
x 2
V
REF
2047
4096
+V
REF
x 2
1
+V
REF
x 2
OS_, as shown in Figure 10. By applying V _ = -1V,
OS
4096
the output values will range between 1V and (1V +
0 0 0 0 0 0 0 0 00 0 0 (0 )
0V
V
x 2).
REF
Note: ( ) are for the sub bit.
______________________________________________________________________________________ 13
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
Table 3. Bipolar Code Table
+5V/
+3V
+5V/+3V
DAC CONTENTS
ANALOG OUTPUT
26k
AC
MSB
LSB
MAX495
REFERENCE
INPUT
2047
+V
1 1 1 1 1 1 1 1 1 1 1 1 (0 )
REF
2048
10k
V
DD
REF
R
500mVp-p
1
OS_
1 0 0 0 0 0 0 0 0 0 0 1 (0 )
1 0 0 0 0 0 0 0 0 0 0 0 (0 )
0 1 1 1 1 1 1 1 1 1 1 1 (0 )
+V
REF
2048
R
DGND
V+
0V
OUT_
DAC_
1
-V
REF
2048
MAX5154
MAX5155
2047
0 0 0 0 0 0 0 0 0 0 0 1 (0 )
-V
REF
AGND
2048
2048
-V
= - V
REF
0 0 0 0 0 0 0 0 0 0 0 0 (0 )
REF
4/MAX15
2048
Figure 12. AC Reference Input Circuit
Note: ( ) are for the sub bit.
+5V/+3V
REF_
PHOTODIODE
REF_
+5V/+3V
10k
10k
V+
OS_
V
DD
OS_
V
DD
R
R
V+
MAX5154
MAX5155
R
R
MAX5154
MAX5155
V
OUT
OUT_
10k
V
OUT
DAC _
AGND
µP
DAC _
V-
OUT_
DIN
DGND
10k
R
PULLDOWN
V-
DGND
AGND
Figure 13. Digital Calibration
Figure 11. Bipolar Output Circuit
ing a sinusoidal input to REF_, where the AC signal is
offset before being applied to the reference input.
Bip o la r Ou t p u t
The MAX5154/MAX5155 can be configured for a bipo-
lar output, as shown in Figure 11. The output voltage is
given by the equation (OS_ = AGND):
Ha rm o n ic Dis t o rt io n a n d No is e
The total harmonic distortion plus noise (THD+N) is typ-
ically less than -78dB at full scale with a 1Vp-p input
swing at 5kHz. The typical -3dB frequency is 300kHz
for both devices, as shown in the Typical Operating
Characteristics.
V
OUT
= V
[((2 x NB) / 4096) - 1]
REF
where NB represents the numeric value of the DAC’s
binary input code. Table 3 shows digital codes and the
corresponding output voltage for Figure 11’s circuit.
Us in g a n AC Re fe re n c e
In applications where the reference has an AC signal
component, the MAX5154/MAX5155 have multiplying
capabilities within the reference input voltage range
specifications. Figure 12 shows a technique for apply-
Dig it a l Ca lib ra t io n a n d
Th re s h o ld S e le c t io n
Figure 13 shows the MAX5154/MAX5155 in a digital
calibration application. With a bright light value applied
to the photodiode (on), the DAC is digitally ramped until
14 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
4/MAX15
V
DD
OSA
R
R
MAX5154
MAX5155
REFA
V
IN
R1
R3
OUTA
OUTB
CS
INPUT
REG A
DAC
REG A
DACA
DACB
R2
SHIFT
REGISTER
SCLK
INPUT
REG B
DAC
REG B
V
OUT
DIN
R4
REFB
R
R
V
REF
V
OUT
= GAIN
–
OFFSET
[ ] [
]
OSB
2NA
R2
R4
1+
)( )( ) ( 2NB )(R4 )
=
V
V
REF
IN
(
[
R3 ] [
]
4096 R1+R2
4096 R3
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
AGND
DGND
Figure 14. Digital Control of Gain and Offset
it trips the comparator. The microprocessor (µP) stores
this “high” calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration.
The µP then programs the DAC to set an output voltage
a t the mid p oint of the two c a lib ra te d va lue s .
Ap p lic a tions inc lud e ta c home te rs , motion s e ns ing ,
automatic readers, and liquid clarity analysis.
P o w e r-S u p p ly Co n s id e ra t io n s
On power-up, the input and DAC registers clear (set to
zero code). For rated performance, V should be at
REF_
least 1.4V below V . Bypass the power supply with a
DD
4.7µF capacitor in parallel with a 0.1µF capacitor to
AGND. Minimize lead lengths to reduce lead inductance.
Gro u n d in g a n d La yo u t Co n s id e ra t io n s
Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance ground
plane. Carefully lay out the traces between channels to
reduce AC cross-coupling and crosstalk. Wire-wrapped
boards and sockets are not recommended. If noise
becomes an issue, shielding may be required.
Dig it a l Co n t ro l o f Ga in a n d Offs e t
The two DACs can be used to control the offset and
gain for curve-fitting nonlinear functions, such as trans-
ducer linearization or analog compression/expansion
applications. The input signal is used as the reference
for the gain-adjust DAC, whose output is summed with
the output from the offset-adjust DAC. The relative
weight of each DAC output is adjusted by R1, R2, R3,
and R4 (Figure 14).
______________________________________________________________________________________ 15
Lo w -P o w e r, Du a l, 1 2 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
__________________P in Co n fig u ra t io n
_Ord e rin g In fo rm a t io n (c o n t in u e d )
INL
TOP VIEW
PART
TEMP. RANGE
PIN-PACKAGE
(LSB)
±1/2
±1
AGND
OUTA
OSA
REFA
CL
1
2
3
4
5
6
7
8
16 V
DD
MAX5154AEPE -40°C to +85°C
MAX5154BEPE -40°C to +85°C
MAX5154AEEE -40°C to +85°C
MAX5154BEEE -40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
15 OUTB
14 OSB
13 REFB
12 PDL
11 UPO
10 DOUT
±1/2
±1
MAX5154
MAX5155
16 QSOP
MAX5154BMJE -55°C to +125°C 16 CERDIP*
±1
MAX5155ACPE
MAX5155BCPE
MAX5155ACEE
MAX5155BCEE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
±1
CS
±2
DIN
±1
SCLK
9 DGND
16 QSOP
±2
MAX5155AEPE -40°C to +85°C
MAX5155BEPE -40°C to +85°C
MAX5155AEEE -40°C to +85°C
MAX5155BEEE -40°C to +85°C
16 Plastic DIP
16 Plastic DIP
16 QSOP
±1
DIP/QSOP
±2
±1
16 QSOP
±2
4/MAX15
___________________Ch ip In fo rm a t io n
MAX5155BMJE -55°C to +125°C 16 CERDIP*
*Contact factory for availability.
±2
TRANSISTOR COUNT: 3053
SUBSTRATE CONNECTED TO AGND
________________________________________________________P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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