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MAX5159CEE+T 数据手册
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PDF下载19-1315; Rev 1; 12/97
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ 10-Bit Dual DAC with Internal Gain of +2V/V
♦ Rail-to-Rail Output Swing
The MAX5158/MAX5159 low-power, serial, voltage-
output, dual, 10-bit digital-to-analog converters (DACs)
consume only 500µA from a single +5V (MAX5158) or
+3V (MAX5159) supply. These devices feature Rail-to-
♦ 8µs Settling Time
®
Rail output swing and are available in a space-saving
♦ Single-Supply Operation: +5V (MAX5158)
16-pin QSOP package. To maximize dynamic range, the
DAC output amplifiers are configured with an internal gain
of +2V/V.
+3V (MAX5159)
♦ Low Quiescent Current: 500µA (normal operation)
The 3-wire s e ria l inte rfa c e is SPI™/QSPI™ a nd
Mic rowire ™ c omp a tib le . Ea c h DAC ha s a d oub le -
buffered input organized as an input register followed by
a DAC register, which allows the input and DAC registers
to be updated independently or simultaneously with a
16-bit serial word. Additional features include a 2µA pro-
grammable shutdown, hardware-shutdown lockout, a
separate reference-voltage input for each DAC that
accepts AC and DC signals, and an active-low clear input
(CL) that resets all registers and DACs to zero. The
MAX5158/MAX5159 provide a programmable logic pin
for added functionality and a serial-data output pin for
daisy chaining.
2µA (shutdown mode)
♦ SPI/QSPI and Microwire Compatible
♦ Available in Space-Saving 16-Pin QSOP Package
♦
Power-On Reset Clears Registers and DACs to Zero
♦ Adjustable Output Offset
______________Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 QSOP
MAX5158CPE
MAX5158CEE
MAX5158EPE
MAX5158EEE
MAX5158MJE
0°C to +70°C
________________________Ap p lic a t io n s
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 QSOP
Digital Offset and Gain Adjustment
µP-Controlled Systems
Motion Control
16 CERDIP*
Ordering Information continued at end of data sheet.
*Contact factory for availability.
Remote Industrial Controls
_________________________________________________________Fu n c t io n a l Dia g ra m
V
DD
CL
PDL
DGND
DOUT
REFA
AGND
OSA
DECODE
CONTROL
R
R
OUTA
OSB
DAC
REG A
INPUT
REG A
DAC A
16-BIT
SHIFT
REGISTER
R
R
MAX5158
MAX5159
SR
CONTROL
OUTB
DAC
REG B
INPUT
REG B
DAC B
LOGIC
OUTPUT
UPO
REFB
CS
DIN
SCLK
Rail-to-Rail is a registered trademark of Nippon Motorola Ltd. Microwire is a trademark of National Semiconductor Corp.
SPI and QSPI are trademarks of Motorola, Inc.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 408-737-7600 ext. 3468.
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
to AGND............................................................-0.3V to +6V
to DGND ...........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
V
Plastic DIP (derate 10.5mW/°C above +70°C) ...........842mW
QSOP (derate 8.30mW/°C above +70°C)...................667mW
CERDIP (derate 10.00mW/°C above +70°C)..............800mW
Operating Temperature Ranges
DD
AGND to DGND..................................................................±0.3V
OSA, OSB to AGND........................(AGND - 4V) to (V + 0.3V)
REF_, OUT_ to AGND.................................-0.3V to (V + 0.3V)
DD
DD
Digital Inputs (SCLK, DIN, CS, CL, PDL)
to DGND............................................................(-0.3V to +6V)
Digital Outputs (DOUT, UPO)
MAX515_ _C_ E .................................................0°C to +70°C
MAX515_ _E_ E ..............................................-40C° to +85°C
MAX515_ _MJE.............................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10sec) .............................+300°C
to DGND................................................-0.3V to (V + 0.3V)
DD
Maximum Current into Any Pin .........................................±20mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5158
(V = +5V ±10%, V
= V
= 2.048V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values are
MAX
DD
REFA
REFB
L
L
A
MIN
at T = +25°C (OS_ tied to AGND for a gain of +2V/V).)
A
8/MAX159
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
(Note 1)
±1
±1
±6
DNL
Guaranteed monotonic
Code = 2
LSB
V
OS_
mV
Offset Tempco
TCV
Normalized to 2.048V
4
-0.1
4
ppm/°C
LSB
OS
Gain Error
1
Gain-Error Tempco
Normalized to 2.048V
ppm/°C
V
Power-Supply
DD
PSRR
REF
2.7V ≤
≤ 5.5V
20
260
µV/V
VDD
Rejection Ratio
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
0
V
- 1.4
V
DD
kΩ
R
Minimum with code 1558 hex
Input code = 1FF8 hex,
18
25
REF
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
300
-82
75
kHz
dB
V
REF_
= 0.67Vp-p at 0.75V
DC
Input code = 0000 hex,
= (V - 1.4 Vp-p) at 1kHz
Reference Feedthrough
V
DD
REF_
Signal-to-Noise plus
SINAD
Input code = 1FF8 hex,
V = 1Vp-p at 1.25V , f = 25kHz
REF_
dB
Distortion Ratio
DC
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
3
V
V
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
IH
V
IL
0.8
±1
V
HYS
200
0.001
8
mV
µA
pF
Input Leakage Current
Input Capacitance
I
IN
V
= 0V to V
IN DD
C
IN
2
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
ELECTRICAL CHARACTERISTICS—MAX5158 (continued)
(V = +5V ±10%, V
= V
= 2.048V, R = 10kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical values are
DD
REFA
REFB
L
L
A
MIN
MAX
at T = +25°C (OS_ tied to AGND for a gain of +2V/V).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL OUTPUTS (DOUT, UPO)
Output High Voltage
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
Output Low Voltage
V
OL
I
= 2mA
0.13
0.4
SINK
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
SR
0.75
8
V/µs
µs
To 1/2LSB of full-scale, V
= 4V
STEP
Output Voltage Swing
Rail-to-rail (Note 2)
0 to V
V
DD
OSA or OSB Input Resistance
Time Required to Exit Shutdown
Digital Feedthrough
R
24
34
25
5
kΩ
µs
OS_
nV-s
nV-s
CS = V , f
= 100kHz, V
= 5Vp-p
DD DIN
SCLK
Digital Crosstalk
5
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
V
4.5
5.5
V
DD
I
DD
(Note 3)
(Note 3)
0.5
2
0.65
mA
Power-Supply Current
in Shutdown
I
10
±1
µA
µA
DD(SHDN)
Reference Current in Shutdown
0
TIMING CHARACTERISTICS
SCLK Clock Period
t
(Note 4)
100
40
40
40
0
ns
ns
ns
ns
ns
ns
ns
CP
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
CL
t
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SDI Setup Time
CSS
CSH
t
t
40
0
DS
SDI Hold Time
t
DH
SCLK Rise to DOUT
Valid Propagation Delay
t
t
C
C
= 200pF
= 200pF
80
80
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT
Valid Propagation Delay
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
CS0
CS1
t
t
100
CSW
Note 1: Accuracy is specified from code 2 to code 1023.
Note 2: Accuracy is better than 1LSB for V _ greater than 6mV and less than V - 50mV. Guaranteed by PSRR test at the
OUT
DD
end points.
Note 3: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.
DD
L
Note 4: SCLK minimum clock period includes rise and fall times.
_______________________________________________________________________________________
3
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS—MAX5159
(V = +2.7V to +3.6V, V
= V
= 1.25V, R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted. Typical values
MAX
DD
REFA
REFB
L
L
A
MIN
are at T = +25°C (OS_ pins tied to AGND for a gain of +2V/V).)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
(Note 5)
±1
±1
±6
DNL
Guaranteed monotonic
Code = 3
LSB
V
OS
mV
Offset Tempco
TCV
Normalized to 1.25V
6.5
-0.1
6.5
ppm/°C
LSB
OS
Gain Error
±1
Gain-Error Tempco
Normalized to 1.25V
ppm/°C
V
Power-Supply
DD
PSRR
REF
2.7V ≤
≤ 3.6V
40
320
µV/V
VDD
Rejection Ratio
REFERENCE INPUT (VREF)
Reference Input Range
Reference Input Resistance
8/MAX159
0
V
- 1.4
V
DD
kΩ
R
Minimum with code 1558 hex
Input code = 1FF8 hex,
18
25
REF
MULTIPLYING-MODE PERFORMANCE
Reference 3dB Bandwidth
300
-82
73
kHz
dB
V
REF_
= 0.67Vp-p at 0.75V
DC
Input code = 0000 hex,
= (V - 1.4)Vp-p at 1kHz
Reference Feedthrough
V
DD
REF_
Signal-to-Noise plus
SINAD
Input code = 1FF8 hex,
V = 1Vp-p at 1V , f = 15kHz
REF_
dB
Distortion Ratio
DC
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.2
V
V
CL, PDL, CS, DIN, SCLK
CL, PDL, CS, DIN, SCLK
IH
V
IL
0.8
±1
V
HYS
200
0
mV
µA
pF
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
I
IN
V
= 0V to V
IN DD
C
8
IN
V
OH
I
= 2mA
V
- 0.5
V
V
DD
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
DYNAMIC PERFORMANCE (DOUT, UPO)
Voltage Output Slew Rate
Output Settling Time
SR
0.75
8
V/µs
µs
To 1/2LSB of full-scale, V
= 2.5V
STEP
Output Voltage Swing
Rail-to-rail (Note 6)
0 to V
V
DD
kΩ
OSA or OSB Input Resistance
R
24
34
OS_
Time Required for Valid
Operation after Shutdown
25
µs
Digital Feedthrough
Digital Crosstalk
5
5
nV-s
nV-s
CS = V , f
= 100kHz, V
= 3Vp-p
SCLK
DD DIN
4
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
ELECTRICAL CHARACTERISTICS—MAX5159 (continued)
(V = +2.7V to +3.6V, V
= V
= 1.25V, R = 10kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical values
MAX
DD
REFA
REFB
L
L
A
MIN
are at T = +25°C (OS_ pins tied to AGND for a gain of +2V/V).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Positive Supply Voltage
Power-Supply Current
V
2.7
3.6
0.6
V
DD
I
DD
(Note 7)
(Note 7)
0.5
1
mA
Power-Supply Current
in Shutdown
I
8
µA
µA
DD(SHDN)
Reference Current in
Shutdown
±1
TIMING CHARACTERISTICS
SCLK Clock Period
t
(Note 4)
100
40
ns
ns
ns
CP
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
CS Fall to SCLK Rise
Setup Time
t
40
0
ns
ns
CSS
SCLK Rise to CS Rise
Hold Time
t
CSH
SDI Setup Time
SDI Hold Time
t
50
0
ns
ns
DS
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
C
C
= 200pF
= 200pF
120
120
ns
ns
DO1
DO2
LOAD
LOAD
SCLK Fall to DOUT Valid
Propagation Delay
t
t
10
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
CS0
t
CS1
t
100
CSW
Note 5: Accuracy is specified from code 3 to code 1023.
Note 6: Accuracy is better than 1LSB for V greater than 6mV and less than V - 80mV. Guaranteed by PSRR test at the end
OUT
DD
points.
Note 7: Digital inputs are set to either V or DGND, code = 0000 hex, R = ∞.
DD
L
_______________________________________________________________________________________
5
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, R = 10kΩ, C = 100pF, OS_ pins tied to AGND, T = +25°C, unless otherwise noted.)
A
DD
L
L
MAX5158
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
0
700
650
600
550
500
450
400
-30
V
REF
= 1Vp-p @ 2.5V
DC
-2
-4
CODE = 1FF8 (HEX)
CODE = 1FF8 (HEX)
CODE = 0000 (HEX)
-40
-50
-60
-70
-6
-8
-10
-12
-14
-16
-18
-20
V
= 0.67Vp-p @ 2.5V
DC
REF
V
REF
= 2.048V
CODE = 1FF8 (HEX)
R = ∞
L
-80
8/MAX159
1
370
740
1110
1480
1850
-55 -35 -15
5
25 45 65 85 105 125
1
10
100
FREQUENCY (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
SHUTDOWN CURRENT
vs. TEMPERATURE
REFERENCE FEEDTHROUGH AT 1kHz
FULL-SCALE ERROR vs. RESISTIVE LOAD
-50
-60
6
5
4
3
2
1
0
0.50
0.25
V
REF
= 3.6Vp-p @ 1.88V
V
REF
= 1V
DC
CODE = 0000 (HEX)
-70
-80
0
-0.25
-0.5
-90
-100
-110
-120
-130
-140
-150
-0.75
-1.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz)
-55 -35 -15
5
25 45 65 85 105 125
0.1
1
10
100
TEMPERATURE (°C)
R (kΩ)
L
DYNAMIC RESPONSE FALL TIME
DYNAMIC RESPONSE RISE TIME
OUTPUT FFT PLOT
MAX5158/5159 toc09
MAX5158/5159 toc08
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
= 2.45Vp-p @ 1.225V
DC
REF
f = 1kHz
CODE = 1FF8 (HEX)
CS
5V/div
CS
5V/div
NOTE: RELATIVE TO FULL-SCALE
OUT_
1V/div
OUT_
1V/div
2µs/div
2µs/div
0.5
1.6
2.7
3.8
4.9
6.0
V = 2.048V
REF
V
REF
= 2.048V
FREQUENCY (kHz)
6
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +3V, R = 10kΩ, C = 100pF, OS_ pins tied to AGND, T = +25°C, unless otherwise noted.)
A
DD
L
L
MAX5159
SUPPLY CURRENT vs. TEMPERATURE
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
TOTAL HARMONIC DISTORTION
PLUS NOISE vs. FREQUENCY
0
560
540
520
500
480
460
440
420
400
-30
V
R = ∞
L
= 1V
V
= 1Vp-p @ 1V
REF
REF DC
-2
-4
CODE = 1FF8 (HEX)
CODE = 1FF8 (HEX)
-40
-50
-60
-70
-6
-8
-10
-12
-14
-16
-18
-20
CODE = 0000 (HEX)
V
= 0.67Vp-p @ 0.75V
DC
REF
CODE = 1FF8
-80
1
320
640
960
1280
1600
-55 -35 -15
5
25 45 65 85 105 125
1
10
100
FREQUENCY (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
SHUTDOWN CURRENT
vs. TEMPERATURE
REFERENCE FEEDTHROUGH AT 1kHz
FULL-SCALE ERROR vs. RESISTIVE LOAD
-50
-60
3.0
2.8
2.6
2.4
2.2
2.0
1.8
0.50
0.25
0
V
R = ∞
L
= 1V
REF
V
REF
= 1.6Vp-p @ 0.88V
DC
CODE = 0000 (HEX)
-70
-80
-90
-100
-110
-120
-130
-140
-150
-0.25
-0.50
1.6
1.4
1.2
1.0
-0.75
-1.00
-55 -35 -15
5
25 45 65 85 105 125
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
FREQUENCY (kHz)
0.1
1
10
100
TEMPERATURE (°C)
R (kΩ)
L
DYNAMIC RESPONSE RISE TIME
OUTPUT FFT PLOT
DYNAMIC RESPONSE FALL TIME
MAX5158/5159 toc17
MAX5158/5159 toc18
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
CS
2V/div
CS
2V/div
V
REF
= 1.4Vp-p @ 0.75V
DC
f = 1kHz
CODE = 1FF8 (HEX)
OUT_
500mV/div
OUT_
500mV/div
2µs/div
0.5
1.6
2.7
3.8
4.9
6.0
2µs/div
FREQUENCY (kHz)
V
REF
= 1.25V
V
REF
= 1.25V
_______________________________________________________________________________________
7
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V (MAX5158), V = +3V (MAX5159), R = 10kΩ, C = 100pF, OS_ pins tied to AGND, unless otherwise noted.)
L
L
DD
DD
MAX5158/MAX5159
MAX5158
MAX5159
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.60
0.60
0.55
CODE = 1FF8 (HEX)
CODE = 0000 (HEX)
CODE = 1FF8 (HEX)
0.55
0.50
0.50
CODE = 0000 (HEX)
0.45
0.40
0.45
0.40
8/MAX159
4.50
4.75
5.00
5.25
5.50
2.7
3.0
3.3
3.6
MAX5158
MAJOR-CARRY TRANSITION
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
CS
2V/div
OUT_
50mV/div
AC COUPLED
5µs/div
TRANSITION FROM 1000 (HEX) TO 0FF8 (HEX)
MAX5158
MAX5158
ANALOG CROSSTALK
DIGITAL FEEDTHROUGH
SCLK
5V/div
OUTA
5V/div
OUTA
500µV/div
AC COUPLED
OUTB
200µV/div
AC COUPLED
250µs/div
2.5µs/div
V
REF
= 2.048V, GAIN = +2V/V, CODE = 1FF8 HEX
8
_______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
OS_
_____________________P in De s c rip t io n
R
PIN
1
NAME
AGND
OUTA
OSA
FUNCTION
Analog Ground
R
OUT_
2
DAC A Output Voltage
DAC A Offset Adjustment
Reference for DAC A
R
R
R
3
2R
D0
2R
D7
2R
D8
2R
D9
2R
4
REFA
Active-Low Clear Input. Resets all reg-
isters to zero. DAC outputs go to 0V.
5
CL
REF_
6
7
Chip-Select Input
Serial-Data Input
CS
AGND
DIN
SHOWN FOR ALL 1s ON DAC
8
SCLK
DGND
DOUT
UPO
Serial Clock Input
Digital Ground
Figure 1. Simplified DAC Circuit Diagram
9
10
11
Serial-Data Output
User-Programmable Output
V
OUT
= (V
x NB / 1024) x 2
REF
where NB is the numeric value of the DAC’s binary input
code (0 to 1023) and V is the reference voltage.
REF
Power-Down Lockout. The device can-
not be powered down when PDL is low.
12
PDL
The re fe re nc e inp ut imp e d a nc e ra ng e s from 18kΩ
(1558 hex) to several giga ohms (with an input code of
0000 hex). The reference input capacitance is code
dependent and typically ranges from 15pF with an
input code of all zeros to 50pF with a full-scale input
code.
13
14
15
16
REFB
OSB
Reference for DAC B
DAC B Offset Adjustment
DAC B Output Voltage
Positive Power Supply
OUTB
V
DD
Ou t p u t Am p lifie r
The output amplifiers on the MAX5158/MAX5159 have
internal resistors that provide for a gain of +2V/V when
OS_ is c onne c te d to AGND. The s e re s is tors a re
trimmed to minimize gain error. The output amplifiers
ha ve a typ ic a l s le w ra te of 0.75V/µs a nd s e ttle to
1/2LSB within 8µs, with a load of 10kΩ in parallel with
100pF. Loads less than 2kΩ degrade performance.
_______________De t a ile d De s c rip t io n
The MAX5158/MAX5159 dual, 10-bit, voltage-output
DACs are easily configured with a 3-wire serial inter-
face. These devices include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see Functional Diagram). In addition, trimmed internal
resistors produce an internal gain of +2V/V that maxi-
mizes output voltage swing. The amplifier’s offset-adjust
pin allows for a DC shift in the DAC’s output.
The OS_ pin can be used to produce an adjustable off-
set voltage at the output. For instance, to achieve a 1V
offset, apply -1V to the OS_ pin to produce an output
range from 1V to (1V + V
x 2). Note that the DAC’s
REF
output range is still limited by the maximum output volt-
age specification.
Both DACs use an inverted R-2R ladder network that
produces a weighted voltage proportional to the input
voltage value. Each DAC has its own reference input to
fa c ilita te ind e p e nd e nt full-s c a le va lue s . Fig ure 1
depicts a simplified circuit diagram of one of the two
DACs.
P o w e r-Do w n Mo d e
The MAX5158/MAX5159 feature a software-program-
mable shutdown mode that reduces the typical supply
current to 2µA. The two DACs can be shutdown inde-
pendently, or simultaneously using the appropriate pro-
gramming command. Enter shutdown mode by writing
the appropriate input-control word (Table 1). In shut-
down mode, the reference inputs and amplifier out-
puts become high impedance, and the serial interface
Re fe re n c e In p u t s
The reference inputs accept both AC and DC values
with a voltage range extending from 0V to (V - 1.4V).
DD
Determine the output voltage using the following equa-
tion (OS_ = AGND):
_______________________________________________________________________________________
9
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
remains active. Data in the input registers is saved,
allowing the MAX5158/MAX5159 to recall the output
state prior to entering shutdown when returning to nor-
mal mode. Exit shutdown by recalling the previous con-
SCLK
SK
dition or by updating the DAC with new information.
When returning to normal operation (exiting shutdown),
wait 20µs for output stabilization.
MICROWIRE
PORT
MAX5158
MAX5159
DIN
CS
SO
I/O
S e ria l In t e rfa c e
The MAX5158/MAX5159 3-wire serial interface is com-
patible with both Microwire (Figure 2) and SPI/QSPI
(Figure 3) serial-interface standards. The 16-bit serial
input word consists of an address bit, two control bits, 10
bits of data (MSB to LSB), and 3 sub-bits as shown in
Figure 4. The address and control bits determine the
MAX5158/MAX5159’s response, as outlined in Table 1.
Figure 2. Connections for Microwire
Table 1. Serial-Interface Programming Command
16-BIT SERIAL WORD
8/MAX159
FUNCTION
D9..........................D0
A0 C1 C0
S2–S0
(MSB)
(LSB)
0
1
0
1
0
0
1
1
1
1
0
0
10-bit DAC data
0 0 0
0 0 0
0 0 0
0 0 0
Load input register A; DAC registers are unchanged.
Load input register B; DAC registers are unchanged.
Load input register A; all DAC registers are updated.
Load input register B; all DAC registers are updated.
10-bit DAC data
10-bit DAC data
10-bit DAC data
Load all DAC registers from the shift register
(start up both DACs with new data.).
0
1
1
10-bit DAC data
0 0 0
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input registers).
1
1
0
0
1
0
0
1
0
xxxxxxxxxx
xxxxxxxxxx
0 0 0
0 0 0
0 0 0
Shut down both DACs (provided PDL = 1).
Update DAC register A from input register A
(start up DAC A with data previously stored in input register A).
0 0 1 x xxxxxx
Update DAC register B from input register B
(start up DAC B with data previously stored in input register B).
0
0
0
1 0 1 x xxxxxx
0 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 0 x xxxxxx
1 1 1 x xxxxxx
0 1 0 x xxxxxx
0 1 1 x xxxxxx
1 0 0 1 xxxxxx
1 0 0 0 xxxxxx
0 0 0 x xxxxxx
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
Shut down DAC A (provided PDL = 1).
Shut down DAC B (provided PDL = 1).
UPO goes low (default).
UPO goes high.
Mode 1, DOUT clocked out on SCLK’s rising edge.
Mode 0, DOUT clocked out on SCLK’s falling edge (default).
No operation (NOP).
x = Don’t care
Note: When A0, C1, and C0 = 0, then D9, D8, D7, and D6 become control bits. S2–S0 are sub bits, always zero.
10 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
The MAX5158/MAX5159’s digital inputs are double
buffered, which allows any of the following: loading the
+5V
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
SS
Send the 16-bit data as one 16-bit word (QSPI) or two
DIN
MOSI
SCK
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated and the state of the registers
when exiting shutdown. The 3-bit address/control deter-
mines the following:
SPI/QSPI
PORT
MAX5158
MAX5159
SCLK
CS
I/O
•
•
registers to be updated
clock edge on which data is to be clocked out via
the serial-data output (DOUT)
CPOL = 0, CPHA = 0
•
•
state of the user-programmable logic output
configuration of the device after shutdown.
Figure 3. Connections for SPI/QSPI
The general timing diagram of Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
MSB ..................................................................................LSB
16 Bits of Serial Data
Address Bits Control Bits MSB....DataBits...LSB Sub Bits
D9.................. ......D0
10 Data Bits
A0
C1, C0
S2–S0
000
1 Address/
2 Control Bits
Figure 4. Serial-Data Format
CS
COMMAND
EXECUTED
SCLK
1
8
9
16
D3 D2 D1 D0 S2 S1 S0
C1
DIN
A0
C0 D9 D8 D7 D6 D5
D4
Figure 5. Serial-Interface Timing Diagram
______________________________________________________________________________________ 11
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
t
CSW
CS
t
CP
t
CSH
t
t
CH
CSS
t
t
CL
CSO
t
CS1
SCLK
DIN
t
DS
t
DH
Figure 6. Detailed Serial-Interface Timing Diagram
SCLK
SCLK
SCLK
MAX5158
MAX5159
MAX5158
MAX5159
MAX5158
MAX5159
8/MAX159
DIN
CS
DOUT
DIN
CS
DOUT
DIN
CS
DOUT
TO OTHER
SERIAL DEVICES
Figure 7. Daisy Chaining MAX5158/MAX5159s
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX5158
MAX5159
SCLK
MAX5158
MAX5159
SCLK
MAX5158
MAX5159
SCLK
DIN
DIN
DIN
Figure 8. Multiple MAX5158/MAX5159s Sharing a Common DIN Line
12 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
Table 2. Unipolar Code Table (Gain = +2)
OS_
+5V/+3V
DAC CONTENTS
MSB LSB
ANALOG OUTPUT
REF_
V
DD
1023
1 1 1 1 1 1 1 1 1 1 (0 0 0 )
1 0 0 0 0 0 0 0 0 1 (0 0 0 )
1 0 0 0 0 0 0 0 0 0 (0 0 0 )
0 1 1 1 1 1 1 1 1 1 (0 0 0 )
0 0 0 0 0 0 0 0 0 1 (0 0 0 )
+V
x 2
R
R
REF
MAX5158
MAX5159
1024
513
+V
x 2
REF
1024
DAC_
OUT_
512
1024
+V
x 2
=
V
REF
REF
AGND
DGND
GAIN = +2V/V
511
+V
x 2
REF
1024
1
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
+V
REF
1024
0 0 0 0 0 0 0 0 0 0 (0 0 0 )
0V
Note: ( ) are for the sub bits.
OS_
+5V/+3V
REF_
Serial-Data Output
V
OS
V
DD
The serial-data output, DOUT, is the internal shift regis-
ter’s output. DOUT allows for daisy chaining of devices
and data readback. The MAX5158/MAX5159 can be
p rog ra mme d to s hift d a ta out of DOUT on SCLK’s
falling edge (Mode 0) or on the rising edge (Mode 1).
Mode 0 provides a lag of 16 clock cycles, which main-
tains compatibility with SPI/QSPI and Microwire inter-
fa c e s . In Mod e 1, the outp ut d a ta la g s 15.5 c loc k
cycles. On power-up, the device defaults to Mode 0.
R
R
MAX5158
MAX5159
DAC _
OUT_
AGND
DGND
User-Programmable Logic Output (UPO)
UPO allows an external device to be controlled through
the serial interface (Table 1), thereby reducing the num-
ber of microcontroller I/O pins required. On power-up,
UPO is low.
Figure 10. Setting OS_ for Output Offset
load. Refer to the digital output V
and V specifica-
OL
OH
tions in the Electrical Characteristics.
Power-Down Lockout Input (PDL)
The power-down lockout pin (PDL) disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL can also be
used to asynchronously wake up the device.
Figure 8 shows an alternate method of connecting sev-
eral MAX5158/MAX5159s. In this configuration, the
data bus is common to all devices; data is not shifted
through a daisy chain. More I/O lines are required in
this configuration because a dedicated chip-select
input (CS) is required for each IC.
Daisy Chaining Devices
Any numb e r of MAX5158/MAX5159s c a n b e d a is y
chained by connecting the DOUT pin of one device to
the DIN pin of the following device in the chain (Figure 7).
__________Ap p lic a t io n s In fo rm a t io n
Un ip o la r Ou t p u t
Figure 9 shows the MAX5158/MAX5159 configured for
unipolar, rail-to-rail operation with a gain of +2V/V. The
MAX5158 can produce a 0V to 4.096V output with a
2.048V reference (Figure 9), while the MAX5159 can
Since the MAX5158/MAX5159’s DOUT pin has an internal
active pull-up, the DOUT sink/source capability deter-
mines the time required to discharge/charge a capacitive
______________________________________________________________________________________ 13
Lo w -P o w e r, Du a l, 1 0 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
Table 3. Bipolar Code Table
+5V/
+3V
+5V/+3V
DAC CONTENTS
MSB LSB
ANALOG OUTPUT
26k
AC
MAX495
REFERENCE
INPUT
511
1 1 1 1 1 1 1 1 1 1 (0 0 0 )
+V
REF
512
10k
500mVp-p
1
V
DD
REF
1 0 0 0 0 0 0 0 0 1 (0 0 0 )
1 0 0 0 0 0 0 0 0 0 (0 0 0 )
0 1 1 1 1 1 1 1 1 1 (0 0 0 )
R
+V
REF
512
OS_
0V
R
1
OUT_
-V
DAC_
REF
512
511
MAX5158
MAX5159
0 0 0 0 0 0 0 0 0 1 (0 0 0 )
-V
REF
512
AGND
DGND
V+
512
0 0 0 0 0 0 0 0 0 0 (0 0 0 )
-V
= - V
REF
REF
8/MAX159
512
Figure 12. AC Reference Input Circuit
Note: ( ) are for the sub bits.
+5V/+3V
REF_
PHOTODIODE
V+
10k
10k
REF_
+5V/+3V
OS_
OS_
V
DD
V
DD
R
R
R
R
V+
V-
MAX5158
MAX5159
MAX5158
MAX5159
V
OUT
OUT_
10k
V
OUT
DAC _
AGND
µP
DAC _
OUT_
DIN
V-
DGND
10k
DGND
AGND
R
PULLDOWN
Figure 13. Digital Calibration
Figure 11. Bipolar Output Circuit
produce a range of 0V to 2.5V with a 1.25V reference.
Table 2 lists the unipolar output codes. An offset to the
output can be achieved by connecting a voltage to
Us in g a n AC Re fe re n c e
In applications where the reference has an AC signal
component, the MAX5158/MAX5159 have multiplying
capabilities within the reference input voltage range
specifications. Figure 12 shows a technique for apply-
ing a sinusoidal input to REF_, where the AC signal is
offset before being applied to the reference input.
OS_, as shown in Figure 10. By applying V _ = -1V,
OS
the output values will range between 1V and (1V +
V
REF
x 2).
Bip o la r Ou t p u t
The MAX5158/MAX5159 can be configured for a bipo-
lar output, as shown in Figure 11. The output voltage is
given by the equation (OS_ = AGND):
Ha rm o n ic Dis t o rt io n a n d No is e
The total harmonic distortion plus noise (THD+N) is typ-
ically less than -78dB at full scale with a 1Vp-p input
swing at 5kHz. The typical -3dB frequency is 300kHz
for both devices, as shown in the Typical Operating
Characteristics.
V
OUT
= V
[((2 x NB) / 1024) - 1]
REF
where NB represents the numeric value of the DAC’s
binary input code. Table 3 shows digital codes and the
corresponding output voltage for Figure 11’s circuit.
14 ______________________________________________________________________________________
Lo w -P o w e r, Du a l, 1 0 -Bit , Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
8/MAX159
V
DD
OSA
R
R
MAX5158
MAX5159
REFA
V
IN
R1
R3
OUTA
OUTB
CS
INPUT
REG A
DAC
REG A
DACA
DACB
R2
SHIFT
REGISTER
SCLK
INPUT
REG B
DAC
REG B
V
OUT
DIN
R4
REFB
R
R
V
REF
V
OUT
= GAIN
–
OFFSET
[ ] [
]
OSB
)( )( ) ( 2NB )(R4 )
R3 ] [
2NA
R2
R1+R2
R4
=
V
1+
V
REF
IN
(
[
]
1024
1024
R3
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
AGND
DGND
Figure 14. Digital Control of Gain and Offset
P o w e r-S u p p ly Co n s id e ra t io n s
Dig it a l Ca lib ra t io n a n d
Th re s h o ld S e le c t io n
On power-up, the input and DAC registers clear (set to
zero code). For rated performance, V should be at
REF_
Figure 13 shows the MAX5158/MAX5159 in a digital
calibration application. With a bright light value applied
to the photodiode (on), the DAC is digitally ramped until
it trips the comparator. The microprocessor (µP) stores
this “high” calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration. The
µP then programs the DAC to set an output voltage at
the midpoint of the two calibrated values. Applications
include tachometers, motion sensing, automatic read-
ers, and liquid clarity analysis.
least 1.4V below V . Bypass the power supply with a
DD
4.7µF c a p a c itor in p a ra lle l with a 0.1µF c a p a c itor
to AGND. Minimize le a d le ng ths to re d uc e le a d
inductance.
Gro u n d in g a n d La yo u t Co n s id e ra t io n s
Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance ground
plane. Carefully lay out the traces between channels to
reduce AC cross-coupling and crosstalk. Wire-wrapped
boards and sockets are not recommended. If noise
becomes an issue, shielding may be required.
Dig it a l Co n t ro l o f Ga in a n d Offs e t
The two DACs can be used to control the offset and
gain for curve-fitting nonlinear functions, such as trans-
ducer linearization or analog compression/expansion
applications. The input signal is used as the reference
for the gain-adjust DAC, whose output is summed with
the output from the offset-adjust DAC. The relative
weight of each DAC output is adjusted by R1, R2, R3,
and R4 (Figure 14).
______________________________________________________________________________________ 15
Lo w -P o w e r, Du a l, 1 3 -Bit Vo lt a g e -Ou t p u t DACs
w it h S e ria l In t e rfa c e
__________________P in Co n fig u ra t io n
_Ord e rin g In fo rm a t io n (c o n t in u e d )
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
16 Plastic DIP
16 QSOP
TOP VIEW
MAX5159CPE
MAX5159CEE
MAX5159EPE
MAX5159EEE
MAX5159MJE
AGND
OUTA
OSA
REFA
CL
1
2
3
4
5
6
7
8
16 V
DD
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
16 Plastic DIP
16 QSOP
15 OUTB
14 OSB
13 REFB
12 PDL
11 UPO
10 DOUT
16 CERDIP*
MAX5158
MAX5159
*Contact factory for availability.
CS
DIN
SCLK
9 DGND
___________________Ch ip In fo rm a t io n
DIP/QSOP
TRANSISTOR COUNT: 3053
SUBSTRATE CONNECTED TO AGND
8/MAX159
________________________________________________________P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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