MAX5167LECM+ [MAXIM]
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48;
| 型号： | MAX5167LECM+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48 二极管 放大器 |
| 文件： | 总12页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1675; Rev 0; 4/00
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
General Description
Features
The MAX5167 contains 32 sample-and-hold amplifiers
driven by a single multiplexed input. The control logic
addressing the outputs is a simple 5-wire input to the
multiplexer. Additional logic allows two devices to function
as a single 64-channel unit. Clamping diodes on each
output allows clamping between two external
reference voltages. The MAX5167 is available with an
output impedance of 50Ω, 500Ω, or 1kΩ.
o 32-Channel Sample/Hold
o Output Clamps on Each Channel
o 0.01% Accuracy of Acquired Signal
o 0.01% Linearity Error
o Fast Acquisition Time: 2.5µs
o Low Droop Rate: 1mV/s
The MAX5167 operates with +10V and -5V supplies,
and a separate +5V digital logic supply. Manufactured
with a proprietary BiCMOS process, it provides high
accuracy, fast acquisition time, low droop rate, and a
low hold step. The MAX5167 has a typical linearity error
of less than 0.01% and can accurately acquire an 8V
step input signal to 0.01% accuracy in 2.5µs within the
+7V to -4V input signal range. Transitions from sample
mode to hold mode result in only a 0.5mV error. While
in hold mode, the output voltage slowly droops at a rate
of 1mV/s.
o Low Hold Step: 0.25mV
o Wide Output Voltage Range: +7V to -4V
Ordering Information
PIN-
PACKAGE
PART
TEMP. RANGE
R
(Ω)
OUT
MAX5167LCCM
MAX5167MCCM
MAX5167NCCM
0°C to +70°C
0°C to +70°C
0°C to +70°C
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
48 TQFP
50
The MAX5167 is available in a 48-pin TQFP package and
is specified for both the commercial (0°C to +70°C) and
extended-industrial (-40°C to +85°C) temperature ranges.
500
1k
MAX5167LECM -40°C to +85°C
MAX5167MECM -40°C to +85°C
MAX5167NECM -40°C to +85°C
50
500
1k
Pin Configuration
________________________Applications
Automatic Test Systems (ATE)
Industrial Process Controls
Arbitrary Function Generators
Avionics Equipment
TOP VIEW
ADDR2
ADDR3
ADDR4
SELECT
S/H
1
2
3
4
5
6
7
8
9
36 OUT21
35 OUT20
34 OUT19
33 OUT18
32 OUT17
31 OUT16
CONFIG
MAX5167
V
L
30
V
DD
DGND
29 OUT15
28 OUT14
27 OUT13
26 OUT12
25 OUT11
V
SS
AGND 10
IN 11
CH 12
TQFP
________________________________________________________________ Maxim Integrated Products
1
For free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
ABSOLUTE MAXIMUM RATINGS
V
V
V
to AGND.......................................................-0.3V to +11.0V
to AGND .........................................................-6.0V to +0.3V
Maximum Current into Out_............................................. 10mA
Maximum Current into Logic Inputs ................................ 20mA
DD
SS
DD
to V ......................................................................+15.75V
Continuous Power Dissipation (T = +70°C)
SS
A
V to DGND...........................................................-0.3V to +6.0V
V to AGND ...........................................................-0.3V to +6.0V
L
48-Pin TQFP (derate 12.5mW/°C above +70°C)........1000mW
Operating Temperature ꢀanges
L
MAX5167_CCM ..................................................0°C to +70°C
MAX5167_ECM................................................-40°C to +85°C
Storage Temperature ꢀange.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Maximum Current into C and C .................................. 80mA
L
H
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +10.0V, V = -5.0V, V = +5.0V 5%, AGND = DGND = 0, ꢀ = 5kΩ, C = 50pF, T = T
to T
, unless otherwise noted.
MAX
DD
SS
L
L
L
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
ANALOG SECTION
Linearity Error
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
-4.0V < VIN < +7V ꢀL = ∞
0.01
0.25
1
0.08
1.00
40
%
mV
Hold Step
V
V
IN = AGND
IN = AGND
IN = AGND
HS
Droop ꢀate
T
T
= +25°C
= +25°C
mV/s
mV
A
-30
-5
+30
40
A
Offset Voltage
OS
+15°C ≤ T ≤ +65°C (Note 1)
20
µV/°C
A
V
0.75
+
V
2.4
-
SS
DD
Output Voltage ꢀange
V
OUT_
ꢀL = ∞
V
C = 250pF for
MAX5167L
L
-72
-72
-76
-76
8V step with 500ns
rising edge (Note 1)
Analog Crosstalk
dB
C = 10nF for
L
MAX5167M/67N
Input Capacitance
C
(Note 1)
10
50
20
65
pF
IN
MAX5167L
MAX5167M
MAX5167N
35
350
700
2
ꢀ = ∞,
L
DC Output Impedance
ꢀ
OUT_
500
1000
650
Ω
C = 250pF
L
1300
Output Source Current
Output Sink Current
Output Clamp High
Output Clamp Low
I
V
V
= 0, sample mode
= 0, sample mode
mA
mA
V
SOUꢀCE
IN
I
2
SINK
IN
V
CH
V
SS
V
SS
V
V
DD
V
CL
V
DD
TIMING PERFORMANCE
8V step to 0.08%,
ꢀ = ∞, Figure 2
L
T
T
= +25°C
= +25°C
2.5
4
2
A
Acquisition Time
t
µs
AQ
100mV step to 1mV,
ꢀ = ∞, Figure 2
L
1
1
A
Hold Mode Settling Time
Aperture Delay
t
To 1mV of final value Figure 2 (Note1)
Figure 2 (Note1)
µs
ns
H
t
AP
200
2
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
ELECTRICAL CHARACTERISTICS (continued)
(V
= +10.0V, V = -5.0V, V = +5.0V 5%, AGND = DGND = 0, ꢀ = 5kΩ, C = 50pF, T = T
to T , unless otherwise noted.
MAX
DD
SS
L
L
L
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
S/H Pulse Width
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
t
Figure 2 (Note1)
Figure 2 (Note1)
Figure 2 (Note1)
200
50
PW
Data Setup Time
t
ns
DS
DH
Data Hold Time
t
150
ns
DIGITAL INPUTS
Input Voltage High
V
2.0
-1
V
V
IH
Input Voltage Low
V
0.8
+1
IL
Input Current
I
IN = DGND or V
µA
I
CC
POWER SUPPLIES
Positive Analog Supply
Negative Analog Supply
Digital Logic Supply
Positive Analog Supply Current
Negative Analog Supply Current
V
(Note 2)
(Note 2)
9.5
10
-5
5
10.5
-5.45
5.25
36
V
V
DD
V
-4.75
4.75
SS
V
V
L
I
ꢀ = ∞
L
mA
mA
DD
I
SS
ꢀ = ∞
L
36
ADDꢀ_ = DGND or V , S/H =
L
0.5
5
mA
mA
dB
DGND or V
L
Digital Logic Supply Current
I
L
ADDꢀ_ = +0.8V or +2.0V, S/H =
+0.8V or +2.0V
For V
and V , sample mode,
SS
DD
Power-Supply ꢀejection ꢀatio
PSꢀꢀ
-60
-75
IN = AGND
Note 1: Guaranteed by design.
Note 2: Do not exceed the absolute maximum rating for V
to V of +15.75V (see Absolute Maximum Ratings).
SS
DD
_______________________________________________________________________________________
3
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
Typical Operating Characteristics
(V
= +10V, V = -5V, V = +5V, V = +5V, ꢀ = ∞, C = 0, AGND = DGND = 0, V
= V , V = V , T = +25°C, unless
DD
SS
L
IN
L
L
CH DD CL SS A
otherwise noted.)
DROOP RATE vs. INPUT VOLTAGE
PSRR SAMPLE MODE
DROOP RATE vs. TEMPERATURE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
50
-120
-100
-80
-60
-40
-20
0
NEGATIVE SUPPLY (V
)
SS
40
30
20
10
0
POSITIVE SUPPLY (V
)
DD
-4 -3 -2 -1
0
1
2
3
4
5
6
7
0.1
1
10
100
1000 10,000
-40
-15
10
35
60
85
INPUT VOLTAGE (V)
FREQUENCY (kHz)
TEMPERATURE (°C)
PSRR HOLD MODE
HOLD STEP vs. INPUT VOLTAGE
HOLD STEP vs. TEMPERATURE
-120
-100
-80
-60
-40
-20
0
120
115
110
105
100
95
-160
-140
-120
-100
-80
-60
-40
-20
0
POSITIVE SUPPLY (V
)
DD
NEGATIVE SUPPLY (V
)
SS
90
85
80
0.1
1
10
100
1000 10,000
-4 -3 -2 -1
0
1
2
3
4
5
6
7
-55 -35 -15
5
25
45
65
85
FREQUENCY (kHz)
INPUT VOLTAGE (V)
TEMPERATURE (°C)
OFFSET VOLTAGE vs. INPUT VOLTAGE
OFFSET VOLTAGE vs. TEMPERATURE
-3.0
-3.2
-3.4
0
-1
-2
-3
-4
-5
-6
-3.6
-3.8
-4.0
-4.2
-4.4
-4.6
-4.8
-5.0
-7
-4 -3 -2 -1
0
1
2
3
4
5
6
7
-40
-15
10
35
60
85
INPUT VOLTAGE (V)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
Pin Description
PIN
1
NAME
ADDꢀ2
ADDꢀ3
ADDꢀ4
FUNCTION
Bit 2 of the Address Decoder
2
Bit 3 of the Address Decoder
Bit 4 of the Address Decoder
3
Enables the S/H pin. The polarity of SELECT is determined by the state of the CONFIG pin. If CONFIG
is low, then SELECT is active-high. If CONFIG is high, then SELECT is active-low. When SELECT is not
in its active state, all 32 channels are in hold mode independent of the S/H pin.
4
SELECT
5
6
Puts the selected channel into sample mode when low. Places all channels into hold mode when high.
S/H
CONFIG
Sets the polarity of the SELECT pin.
+5V Logic Supply
Digital GND
7
V
L
8
DGND
9
V
-5V Analog Supply
Analog GND
SS
10
11
12
13
14–29
30
AGND
IN
CH
Input Pin
Clamp High Pin
CL
Clamp Low Pin
OUT0–OUT15
Output 0–15 Pin
V
DD
+10V Analog Supply
Output 16–31 Pin
31–46 OUT16–OUT31
47
48
ADDꢀ0
ADDꢀ1
Bit 0 of the Address Decoder
Bit 1 of the Address Decoder
_______________________________________________________________________________________
5
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
ADDR0–ADDR4
CH
S/H
SELECT
CONFIG
CS
SW1 SW2
SW30 SW31
MAX5167
OUT0
OUT1
IN
OUT30
OUT31
CL
Figure 1. Functional Diagram
The SELECT and CONFIG pins allow the design of a
virtual 64-channel device using two of the MAX5167s.
See the Applications Information section for more infor-
mation about the 64 output addressing scheme.
Detailed Description
Digital Interface
The MAX5167 has three logic control inputs and five
address lines. The address lines are inputs to a demul-
tiplexer that selects one of the 32 outputs in a standard
addressing scheme (Table 1). The analog input is con-
nected to the addressed sample/hold when directed by
the control logic (Table 2).
Sample/Hold
The MAX5167 contains 32 buffered sample/hold circuits
with internal hold capacitors. Internal hold capacitors
minimize leakage current, dielectric absorption,
feedthrough, and required board space. The value of
the hold capacitor affects acquisition time and droop
rate. Smaller capacitance allows faster acquisition times
but increases the droop rate. Larger values increase
hold acquisition time. The hold capacitor used in the
MAX5167 provides fast 2.5µs (typ) acquisition time while
maintaining a relatively low 1mV/s (typ) droop rate, mak-
ing the sample/hold ideal for high-speed sampling.
The three logic control lines determine the state of the
addressed sample/hold. The normal circuit connection
for this device is to hardwire CONFIG and SELECT to
opposing logic voltages. When SELECT and CONFIG
are in opposite states (one high and the other low), the
five address lines select one of the sample/holds. Use
the S/H line to place the selected channel into sample
or hold mode. The other 31 channels will remain in hold
mode.
Sample Mode
When SELECT and CONFIG are in opposing logic states,
the S/H line controls the mode of operation. Sample mode
is entered when S/H is low. During sample mode, the
selected multiplexer channel connects to IN, allowing the
If an active-high sampling mode is desired, tie S/H and
CONFIG low. In this case, SELECT controls the
addressed channel with a high state putting that chan-
nel into sample mode.
6
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
Table 1. Channel/Output Selection
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
OUTPUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VOUT0 is selected
VOUT1 is selected
VOUT2 is selected
VOUT3 is selected
VOUT4 is selected
VOUT5 is selected
VOUT6 is selected
VOUT7 is selected
VOUT8 is selected
VOUT9 is selected
VOUT10 is selected
VOUT11 is selected
VOUT12 is selected
VOUT13 is selected
VOUT14 is selected
VOUT15 is selected
VOUT16 is selected
VOUT17 is selected
VOUT18 is selected
VOUT19 is selected
VOUT20 is selected
VOUT21 is selected
VOUT22 is selected
VOUT23 is selected
VOUT24 is selected
VOUT25 is selected
VOUT26 is selected
VOUT27 is selected
VOUT28 is selected
VOUT29 is selected
VOUT30 is selected
VOUT31 is selected
Table 2. Logic Table for CONFIG, SELECT, and S/H
CONFIG
SELECT
CHANNEL FUNCTION
S/H (SAMPLE/HOLD)
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Hold
Sampling
Sampling
Hold
Hold
_______________________________________________________________________________________
7
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
hold capacitor to acquire the input signal. To guarantee
an accurate sample, maintain sample mode for at least
4µs. The output of the sample/hold amplifier tracks the
input after 4µs. Only the addressed channel on the
selected multiplexer samples the input; all other channels
remain in hold mode.
(V + 0.75V) ≤ V
≤ (V
- 2.4V)
SS
OUT
DD
Output Clamp
The MAX5167 clamps the output between two externally
applied reference voltages. Internal diodes connect all
outputs to the clamping voltages, restricting the output
voltage to:
Hold Mode
No matter what the condition of the other control lines,
S/H = high places the MAX5167 into an all-channel
hold mode. Hold mode disables the multiplexer and
disconnects all 32 sample/holds from the input. When a
channel is disconnected, the hold capacitor maintains
the sampled voltage at the output with a 1mV/s typical
(V
+ 0.7V) ≤ V
≤ (V - 0.7V)
CH
OUT_ CL
When the clamping voltage exceeds the maximum output
voltage, the maximum output voltage will be the limiting
factor. To disable output clamping, connect CH to V
and CL to V to set the clamping voltages beyond the
maximum output voltage range. The clamping diodes
allow the MAX5167 to be used with other devices
requiring restricted input voltages.
DD
SS
droop rate (towards V ).
DD
Hold Step
When switching between sample mode and hold mode,
the voltage of the hold capacitor changes due to
charge injection from stray capacitance. This voltage
change, called hold step, is minimized by limiting the
amount of stray capacitance seen by the hold capacitor.
The MAX5167 limits the hold step to 0.25mV (typ). An
output capacitor to ground can be used to filter out this
small hold-step error.
Timing Definitions
Acquisition time (t ) is the time the MAX5167 must
AQ
remain in sample mode for the hold capacitor to
acquire an accurate sample. The hold-mode settling
time (t ) is the time necessary for the output voltage to
H
settle to its final value. Aperture delay (t ) is the time
AP
interval required to disconnect the input from the hold
capacitor. The hold pulse width (t ) is the time the
PW
MAX5167 must remain in hold mode while the address
Output
The MAX5167 contains an output buffer for each multi-
plexer channel (32 total), so the hold capacitor sees a
high-impedance input that reduces the droop rate. The
capacitor droops at 1mV/s (typ) while in hold mode. The
buffer also provides a low output impedance; however,
the device contains output resistors in series with the
buffer output (Figure 1) for selected output filtering. To
provide greater design flexibility, the MAX5167 is avail-
able with an output impedance of 50Ω, 500Ω, or 1kΩ.
is changed. Data setup time (t ) is the time an
DS
address must be maintained at the digital input pins
before the address becomes valid. Data hold time (t
)
DH
is the time an address must be maintained after the
device is placed in hold mode (Figure 2).
Applications Information
Multiplexing a DAC
Figure 3 shows a typical demultiplexer application.
Different digital codes are converted by the digital-to-
analog converter (DAC) and then stored on 32 different
channels of the MAX5167. The 40mV/s (max) droop
rate requires refreshing the hold capacitors every
250ms before the voltage droops by 1/2LSB for an 8-bit
DAC with a 5V full-scale voltage.
Output loads increase the analog supply current (I
DD
and I ). Excessive loading of the output(s) drastically
SS
increases power dissipation. Do not exceed the maximum
power dissipation specified in the Absolute Maximum
Ratings.
The resistor-divider formed by the output resistor (ꢀ )
O
and load impedance (ꢀ ) scales the sampled voltage
L
Virtual 64 Output Sample and Hold
Two MAX5167s can be configured to operate as a single
64 output sample and hold. The upper and lower
addressed devices are identified by CONFIG’s logic
level. Connect the CONFIG pin of the upper device low,
making its SELECT pin active-high. Connect the CONFIG
pin of the lower device high to make the SELECT pin
active-low. Figure 4 shows how to configure the devices.
(V ). Determine the output voltage (V ) as follows:
SAMP OUT_
Voltage Gain = A = ꢀ / (ꢀ + ꢀ )
V
L
L
O
✕
V
OUT_
= V
A
V
SAMP
The maximum output voltage range depends on the ana-
log supply voltages available and the scaling factor used:
✕
✕
(V + 0.75V) A ≤ V
≤ (V
- 2.4V)
A
V
The devices now use only six address lines and a single
S/H control to decode 64 outputs. Address lines A0–A4
from the control logic connect to ADDꢀ0–ADDꢀ4 on
SS
V
OUT_
DD
when ꢀL = ∞, then A = 1, and this equation becomes:
V
8
_______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
t
PW
S/H
t
DS
t
DH
ADDR_
SELECT, CONFIG
t
H
HOLD STEP
OUT_
IN
t
AQ
t
AP
(CHANNEL x FROM HOLD TO SAMPLE)
(CHANNEL x FROM SAMPLE TO HOLD)
Figure 2. Timing Diagram
V
L
SELECT
ADDRESS BUS
ADDR0–ADDR4
CS
MAX5167
SWITCHES 0–31
S/H
OUT0
OUT1
IN
DATA BUS
DAC
OUT30
OUT31
CONFIG
Figure 3. Multiplexing a DAC
_______________________________________________________________________________________
9
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
V
L
OUT0
OUT1
CONFIG
A0–A4
A5
ADDR0–ADDR4
MAX5167
SELECT
S/H
WR
INPUT
IN
OUT30
OUT31
OUT32
OUT33
ADDR0–ADDR4
SELECT
S/H
MAX5167
IN
CONFIG
OUT62
OUT63
Figure 4. 64 Output Sample-and-Hold Circuit
both of the 32-channel devices. The A5 line toggles the
SELECT pins of both devices to select the active one.
The device that has CONFIG tied high responds to the
lower 32 addresses (000000 through 011111). The
device that has CONFIG grounded responds to the
upper 32 addresses (100000 through 111111).
I
BIAS
10µA, I = LOW
NH
Input Drive Requirements
The input of the MAX5167 feeds the inputs of 32 high-
impedance buffers. These buffers are what charge the
sample/hold capacitor through the multiplexer switch
resistance. The bias current of a selected buffer is
10µA, and this feeds into the 10pF input capacitance.
Figure 5 shows an equivalent input circuit. The bias cur-
rents of the other 31 sample and holds are very small in
comparison to the bias current of the selected channel.
C
IN
10pF
Figure 5. Input Equivalent Circuit
Chip Information
Powering the MAX5167
The MAX5167 does not require a special power-up
sequence to avoid latchup. The device requires three
separate supply voltages for operation. However, when
one or two of the voltages are not available, DC-DC
charge-pump (switched-capacitor) converters provide
a simple, efficient solution. The MAX860 provides volt-
age doubling or inversion, ideal for conversions from
+5V to +10V or from +5V to -5V.
TꢀANSISTOꢀ COUNT: 6961
10 ______________________________________________________________________________________
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
Package Information
______________________________________________________________________________________ 11
32-Channel Sample/Hold Amplifier
with Output Clamping Diodes
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2000 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX5167LECM-T
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
MAX5167MCCM+
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
MAX5167MCCM-T
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
MAX5167MECM+
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
MAX5167NCCM+
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
MAX5167NCCM+T
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
MAX5167NECM+
Sample and Hold Circuit, 1 Func, Sample, 2.5us Acquisition Time, BICMOS, PQFP48, 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
MAXIM
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