MAX5184BEEG [MAXIM]
10-Bit, 40MHz, Current/Voltage-Output DACs; 10位， 40MHz的，电流/电压输出DAC
| 型号： | MAX5184BEEG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10-Bit, 40MHz, Current/Voltage-Output DACs |
| 文件： | 总16页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1579; Rev 0; 12/99
10-Bit, 40MHz, Current/Voltage-Output DACs
General Description
Features
The MAX5181 is a 10-bit, current-output digital-to-ana-
log converter (DAC) designed for superior performance
in signal reconstruction or arbitrary waveform genera-
tion applications requiring analog signal reconstruction
with low distortion and low-power operation. The
MAX5184 provides equal specifications, with on-chip
precision resistors for voltage-output operation. The
MAX5181/MAX5184 are designed for a 10pVs glitch
operation to minimize unwanted spurious signal com-
ponents at the output. An on-board +1.2V bandgap cir-
cuit provides a well-regulated, low-noise reference that
can be disabled for external reference operation.
ꢀ +2.7V to +3.3V Single-Supply Operation
ꢀ Wide Spurious-Free Dynamic Range: 70dB
at f = 2.2MHz
OUT
ꢀ Fully Differential Output
ꢀ Low-Current Standby or Full Shutdown Modes
ꢀ Internal +1.2V, Low-Noise Bandgap Reference
ꢀ Small 24-Pin QSOP Package
The devices are designed to provide a high level of sig-
nal integrity for the least amount of power dissipation.
They operate from a single +2.7V to +3.3V supply.
Additionally, these DACs have three modes of opera-
tion: normal, low-power standby, and full shutdown,
which provides the lowest possible power dissipation
with a 1µA max shutdown current. A fast wake-up time
(0.5µs) from standby mode to full DAC operation facili-
tates power conservation by activating the DAC only
when required.
Ordering Information
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 QSOP
MAX5181BEEG
MAX5184BEEG
24 QSOP
The MAX5181/MAX5184 are available in 24-pin QSOP
packages and are specified for the extended (-40°C to
+85°C) temperature range. For lower resolution, 8-bit
versions, refer to the MAX5187/MAX5190 data sheet.
Pin Configuration
TOP VIEW
Applications
Signal Reconstruction
CREF
1
2
3
4
5
6
7
8
9
24 REFO
23 REFR
22 DGND
OUTP
OUTN
AGND
Arbitrary Waveform Generators (AWGs)
Direct Digital Synthesis
21 DV
20 D9
19 D8
18 D7
17 D6
16 D5
15 D4
14 D3
13 D2
DD
Imaging Applications
MAX5181
MAX5184
AV
DD
DACEN
PD
CS
CLK
REN 10
DO 11
D1 12
QSOP
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
10-Bit, 40MHz, Current/Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
AV , DV
to AGꢁD, DGꢁD .................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DD
Digital Inputs to DGꢁD.............................................-0.3V to +6V
OUTP, OUTꢁ, CREF to AGꢁD .................................-0.3V to +6V
24-Pin QSOP (derate 9.50mW/°C above +70°C) ........762mW
Operating Temperature Range
MAX518_BEEG................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
V
to AGꢁD ..........................................................-0.3V to +6V
AGꢁD to DGꢁD.....................................................-0.3V to +0.3V
AV to DV .................................................................... 3.3V
REF
DD
DD
Maximum Current into Any Pin............................................50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ꢁ
10
-2
Bits
LSB
LSB
Integral ꢁonlinearity
Differential ꢁonlinearity
IꢁL
DꢁL
0.5
0.5
+2
1
Guaranteed monotonic
-1
MAX5181
MAX5184
(ꢁote 1)
-2
+2
+8
+40
Zero-Scale Error
LSB
LSB
-8
Full-Scale Error
-40
15
DYNAMIC PERFORMANCE
Output Settling Time
Glitch Impulse
To 0.5LSB error band
25
10
72
70
-70
-68
61
59
50
10
ns
pVs
f
= 550kHz
= 2.2MHz
= 550kHz
= 2.2MHz
= 550kHz
= 2.2MHz
OUT
Spurious-Free Dynamic Range
to ꢁyquist
SFDR
THD
SꢁR
f
f
f
= 40MHz
= 40MHz
= 40MHz
dBc
dB
CLK
CLK
CLK
f
57
56
OUT
f
OUT
OUT
OUT
OUT
Total Harmonic Distortion
to ꢁyquist
f
f
f
-63
Signal-to-ꢁoise Ratio to ꢁyquist
dB
Clock and Data Feedthrough
Output ꢁoise
All 0s to all 1s
nVs
pA/√Hz
ANALOG OUTPUT
Full-Scale Output Voltage
Voltage Compliance of Output
Output Leakage Current
Full-Scale Output Current
V
400
mV
V
FS
-0.3
-1
0.8
1
DACEꢁ = 0, MAX5181 only
MAX5181 only
µA
mA
I
FS
0.5
1
1.5
DAC External Output Resistor
Load
R
L
MAX5181 only
400
Ω
2
_______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
REFERENCE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Range
V
1.12
1.2
50
1.28
V
REF
Output Voltage Temperature
Drift
TCV
ppm/°C
REF
Reference Output Drive
Capability
I
10
µA
REFOUT
Reference Supply Rejection
0.5
8
mV/V
Current Gain (I / I
)
mA/mA
FS REF
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
Digital Supply Current
AV
2.7
2.7
3.3
4.0
3.3
5.0
1.5
V
DD
I
PD = 0, DACEꢁ = 1, digital inputs at 0 or DV
1.7
mA
V
AVDD
DD
DV
DD
I
PD = 0, DACEꢁ = 1, digital inputs at 0 or DV
PD = 0, DACEꢁ = 0, digital inputs at 0 or DV
PD = 1, DACEꢁ = X,
4.2
1.0
mA
mA
DVDD
DD
Standby Current
I
STAꢁDBY
DD
Shutdown Current
I
0.5
1
µA
SHDꢁ
digital inputs at 0 or DV (X = don’t care)
DD
LOGIC INPUTS AND OUTPUTS
Digital Input Voltage High
Digital Input Voltage Low
Digital Input Current
V
2
V
V
IH
V
0.8
1
IL
I
Iꢁ
V
Iꢁ
= 0 or DV
DD
µA
pF
Digital Input Capacitance
TIMING CHARACTERISTICS
C
10
Iꢁ
DAC DATA to CLK Rise Setup
Time
t
10
0
ns
ns
DS
DAC CLK Rise to DATA Hold
Time
t
DH
5
5
ns
ns
µs
µs
ns
ns
ns
CS Fall to CLK Rise Time
CS Fall to CLK Fall Time
DACEꢁ Rise Time to V
0.5
50
OUT
PD Fall Time to V
OUT
Clock Period
t
25
10
10
CLK
Clock High Time
Clock Low Time
t
CH
t
CL
Note 1: Excludes reference and reference resistor (MAX5184) tolerance.
_______________________________________________________________________________________
3
10-Bit, 40MHz, Current/Voltage-Output DACs
Typical Operating Characteristics
(AV = DV = +3V, AGꢁD = DGꢁD = 0, I = 1mA, 400Ω differential output, C = 5pF, T = +25°C, unless otherwise noted.)
DD
DD
FS
L
A
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY vs.
INPUT CODE
DIFFERENTIAL NONLINEARITY vs.
INPUT CODE
3.0
2.5
2.0
1.5
1.0
0.6
0.5
0.4
0.3
0.2
0.1
0.4
0.3
0.2
0.1
0
MAX5184
MAX5181
-0.1
-0.2
-0.3
0
-0.1
-0.2
0
128 256 384 512 640 768 896 1024
INPUT CODE
0
128 256 384 512 640 768 896 1024
INPUT CODE
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT vs.
TEMPERATURE
DIGITAL SUPPLY CURRENT vs.
TEMPERATURE
8
3.0
2.5
2.0
4.00
3.75
3.50
7
6
MAX5184
MAX5181
MAX5184
MAX5181
5
4
MAX5184
MAX5181
1.5
1.0
3.25
3.00
3
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
SHUTDOWN CURRENT vs.
SUPPLY VOLTAGE
STANDBY CURRENT vs.
SUPPLY VOLTAGE
STANDBY CURRENT vs.
TEMPERATURE
0.14
610
600
590
580
570
600
590
580
570
560
550
MAX5184
0.12
0.10
0.08
0.06
0.04
MAX5184
MAX5181
MAX5181
MAX5181
MAX5184
3.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
2.5
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
Typical Operating Characteristics (continued)
(AV = DV = +3V, AGꢁD = DGꢁD = 0, I = 1mA, 400Ω differential output, C = 5pF, T = +25°C, unless otherwise noted.)
DD
DD
FS
L
A
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
SHUTDOWN CURRENT vs.
TEMPERATURE
1.28
1.27
1.26
1.25
1.24
1.23
1.28
1.27
1.26
1.25
1.24
1.23
0.13
0.11
0.09
0.07
0.05
0.03
MAX5181
MAX5184
MAX5181
MAX5181
MAX5184
MAX5184
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
TEMPERATURE (°C)
OUTPUT CURRENT vs.
REFERENCE CURRENT
DYNAMIC RESPONSE FALL TIME
DYNAMIC RESPONSE RISE TIME
MAX5181/4toc15
MAX5181/4toc14
4.0
3.0
2.0
OUTP
150mV/
div
OUTP
150mV/
div
OUTN
150mV/
div
OUTN
150mV/
div
1.0
0
500ns/div
500ns/div
0
100
200
300
400
500
REFERENCE CURRENT (µA)
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
SETTLING TIME
FFT PLOT
MAX5181/4toc16
100
90
0
-10
f
f
= 2.2MHz
= 40MHz
OUT
CLK
-20
-30
OUTN
100mV/
div
-40
-50
-60
80
70
-70
-80
60
50
40
OUTP
100mV/
div
-90
-100
-110
-120
0
2
4
6
8
10 12 14 16 18 20
10 15 20 25 30 35 40 45 50 55 60
CLOCK FREQUENCY (MHz)
12.5ns/div
OUTPUT FREQUENCY (MHz)
_______________________________________________________________________________________
5
10-Bit, 40MHz, Current/Voltage-Output DACs
Typical Operating Characteristics (continued)
(AV = DV = +3V, AGꢁD = DGꢁD = 0, I = 1mA, 400Ω differential output, C = 5pF, T = +25°C, unless otherwise noted.)
DD
DD
FS
L
A
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
FREQUENCY AND CLOCK FREQUENCY
78
62.4
62.2
62.0
f
= 20MHz
CLK
f
= 40MHz
= 10MHz
CLK
f
= 50MHz
= 60MHz
CLK
76
74
72
61.8
61.6
61.4
61.2
f
CLK
f
CLK
70
68
61.0
60.8
f
= 30MHz
2100
CLK
66
500
900
1300
1700
0
500
1000
1500
2000
2500
OUTPUT FREQUENCY (kHz)
OUPUT FREQUENCY (kHz)
MULTITONE SPURIOUS-FREE DYNAMIC RANGE
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
vs. OUTPUT FREQUENCY
20
74
72
70
68
0
-20
-40
-60
-80
66
64
-100
-120
62
60
-140
0
2
4
6
8
10 12 14 16 18 20
0.5
0.75
1.0
1.25
1.5
OUTPUT FREQUENCY (MHz)
FULL-SCALE OUTPUT CURRENT (mA)
6
_______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
Pin Description
PIN
1
NAME
CREF
OUTP
OUTꢁ
AGꢁD
FUNCTION
REFO
2
Positive Analog Output. Current output for MAX5181; voltage output for MAX5184.
ꢁegative Analog Output. Current output for MAX5181; voltage output for MAX5184.
Analog Ground
3
4
5
AV
Analog Positive Supply, +2.7V to +3.3V
DD
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGꢁD
1: Power-up DAC with PD = DGꢁD
6
7
DACEꢁ
PD
X: Enter shutdown mode with PD = DV
(X = don’t care)
DD
Power-Down Select
0: Enter DAC standby mode (DACEꢁ = DGꢁD) or power-up DAC (DACEꢁ = DV
1: Enter shutdown mode
)
DD
8
9
Active-Low Chip Select
Clock Input
CS
CLK
REN
D0
10
Active-Low Reference Enable. Connect to DGꢁD to activate on-chip +1.2V reference.
11
Data Bit D0 (LSB)
Data Bits D1–D8
12–19
20
D1–D8
D9
Data Bit D9 (MSB)
Digital Supply, +2.7V to +3.3V
Digital Ground
21
DV
DD
22
DGꢁD
REFR
REFO
23
Reference Input
24
Reference Output
_______________________________________________________________________________________
7
10-Bit, 40MHz, Current/Voltage-Output DACs
provides a +1.2V output. Due to its limited 10µA output
Detailed Description
drive capability, REFO must be buffered with an exter-
The MAX5181/MAX5184 are 10-bit digital-to-analog con-
nal amplifier if heavier loading is required.
verters (DACs) capable of operating with clock speeds
The MAX5181/MAX5184 also employ a control amplifier
designed to regulate simultaneously the full-scale out-
put current (I ) for both outputs of the devices. The
FS
output current is calculated as follows:
up to 40MHz. Each converter consists of separate input
and DAC registers, followed by a current source array
capable of generating up to 1.5mA full-scale output cur-
rent (Figure 1). An integrated +1.2V voltage reference
and control amplifier determine the data converters’ full-
scale output currents/voltages. Careful reference design
ensures close gain matching and excellent drift charac-
teristics. The MAX5184’s voltage output operation fea-
tures matched 400Ω on-chip resistors that convert the
current-array current into a voltage.
I
FS
= 8 · I
REF
where I
REFO SET
is the reference output current (I
=
REF
REF
/R
V
) and I is the full-scale output current.
FS
R
is the reference resistor that determines the
SET
amplifier’s output current on the MAX5181 (Figure 2).
This current is mirrored into the current source array,
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
Internal Reference and
Control Amplifier
The MAX5181/MAX5184 provide an integrated 50ppm/°C,
+1.2V, low-noise bandgap reference that can be dis-
abled and overridden by an external reference voltage.
REFO serves either as an external reference input or an
integrated reference output. If REN is connected to
DGꢁD, the internal reference is selected and REFO
The MAX5184 converts this output current into a differ-
ential output voltage (V
) with two internal, ground-
OUT
referenced 400Ω load resistors. Using the internal
+1.2V reference voltage, the MAX5184’s integrated
AV
AGND
CS
DACEN
PD
DD
REN
1.2V REF
REFO
REFR
CREF
CURRENT-
SOURCE ARRAY
OUTP
OUTN
DAC SWITCHES
9.6k*
OUTPUT
LATCHES
OUTPUT
LATCHES
400Ω* 400Ω*
MSB
DECODE
MSB
DECODE
CLK
MAX5181
MAX5184
INPUT
LATCHES
INPUT
LATCHES
DV
DD
DGND
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5184 ONLY.
D9–D0
Figure 1. Functional Diagram
8
_______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
reference output-current resistor (R
= 9.6kΩ) sets
supply current is reduced to 1µA. To enter this mode,
SET
I
to 125µA and I to 1mA.
connect PD to DV . To return to active mode, connect
DD
REF
FS
PD to DGꢁD and DACEꢁ to DV . About 50µs are
DD
External Reference
required for the parts to leave shutdown mode and settle
to their outputs’ values prior to shutdown. Table 1 lists the
power-down mode selection.
To disable the MAX5181/MAX5184’s internal reference,
connect REN to DV . A temperature-stable, external
DD
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
Timing Information
Figure 4 shows a detailed timing diagram for the
MAX5181/MAX5184. With each high transition of the
clock, the input latch is loaded with the digital value set
by bits D9 through D0. The content of the input latch is
then shifted to the DAC register, and the output up-
dates at the rising edge of the next clock.
Standby Mode
To enter the lower-power standby mode, connect digital
inputs PD and DACEꢁ to DGꢁD. In standby, both the
reference and the control amplifier are active with the
current array inactive. To exit this condition, DACEꢁ
must be pulled high with PD held at DGꢁD. The
MAX5181/MAX5184 typically require 50µs to wake up
and let both outputs and the reference settle.
Outputs
The MAX5181 output is designed to supply full-scale
output currents of 1mA into 400Ω loads in parallel with
a capacitive load of 5pF. The MAX5184 features inte-
grated 400Ω resistors that restore the array current to
proportional, differential voltages of 400mV. These dif-
ferential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed oper-
ational amplifier to convert the differential voltage into a
single-ended voltage.
Shutdown Mode
For lowest power consumption, the MAX5181/MAX5184
provide a power-down mode in which the reference, con-
trol amplifier, and current array are inactive and the DAC
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
DGND
REN
+1.2V
BANDGAP
REFERENCE
MAX4040
REFO
R
SET
I
FS
C
*
CURRENT-
SOURCE ARRAY
COMP
I
AGND
REF
REFR
R
SET
R
**
SET
9.6k
MAX5181
MAX5184
AGND
*COMPENSATION CAPACITOR (C
= 100nF)
**9.6kΩ REFERENCE CURRENT-SET RESISTOR
COMP
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
R
FOR MAX5181.
SET
Figure 2. Setting IFS with the Internal +1.2V Reference and the Control Amplifier
_______________________________________________________________________________________
9
10-Bit, 40MHz, Current/Voltage-Output DACs
Table 1. Power-Down Mode Selection
PD
DACEN (DAC ENABLE)
POWER-DOWN MODE
Standby
OUTPUT STATE
(POWER-DOWN SELECT)
MAX5181
MAX5184
High-Z
AGꢁD
0
0
1
X
0
Wake-Up
Last state prior to standby mode
MAX5181
MAX5184
High-Z
AGꢁD
1
Shutdown
X = Don’t care
DV
DD
10µF
0.1µF
REN
+1.2V
DGND
AV
DD
BANDGAP
REFERENCE
EXTERNAL
+1.2V
REFERENCE
REFO
REFR
I
FS
CURRENT-
SOURCE ARRAY
MAX6520
AGND
9.6k*
R
SET
AGND
MAX5181
MAX5184
*9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
R
FOR MAX5181.
SET
Figure 3. MAX5181/MAX5184 with External Reference
been nullified. For a DAC, the deviations are measured
every single step.
Applications Information
Static and Dynamic
Performance Definitions
Differential Nonlinearity
Differential nonlinearity (DꢁL) (Figure 5b) is the differ-
ence between an actual step height and the ideal value
of 1LSB. A DꢁL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Integral Nonlinearity
Integral nonlinearity (IꢁL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
10 ______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
t
t
t
CH
CLK
CL
CLK
D0–D9
N - 1
N
N + 1
t
DS
t
DH
OUT
N - 1
N
N + 1
Figure 4. Timing Diagram
Offset Error
where V is the fundamental amplitude, and V through
1 2
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
V are the amplitudes of the 2nd- through 5th-order
5
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion com-
ponent.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5181. The differential
voltage across OUTP and OUTꢁ is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
I/Q Reconstruction
in a QAM Application
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
The low-distortion performance of two MAX5181/
MAX5184s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) archi-
tectures where two separate buses carry the I and Q
data. A QAM signal is both amplitude (AM) and phase
modulated, created by summing two independently
modulated carriers of identical frequency but different
phase (90° phase difference).
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first five harmonics to the fun-
damental itself. This is expressed as:
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5181/MAX5184 may be used to reconstruct the
analog I and Q components.
2
2
2
2
(V + V + V + V )
5
2
3
4
THD = 20 ⋅log
V
1
______________________________________________________________________________________ 11
10-Bit, 40MHz, Current/Voltage-Output DACs
7
6
6
1 LSB
5
4
5
4
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
AT STEP
3
2
3
2
1
0
011 (1/2 LSB )
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
AT STEP
1
0
001 (1/4 LSB )
000
001
010
011
100
101
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
IDEAL FULL-SCALE OUTPUT
7
6
5
ACTUAL
3
2
1
0
DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
IDEAL DIAGRAM
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
ACTUAL
OFFSET
POINT
OFFSET ERROR
(+1 1/4 LSB)
4
0
IDEAL OFFSET
POINT
000 100
101
110
111
000
001
010
011
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5c. Offset Error
Figure 5d. Gain Error
The I/Q reconstruction system is completed by a quad-
rature modulator that combines the reconstructed com-
ponents with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
replica of the desired analog waveforms. This memory
shares a common clock with the DAC.
For each clock cycle, a counter adds one count to the
address for the waveform memory. The memory then
loads the next value to the DAC, which generates an
analog output voltage corresponding to that data value.
A DAC output filter can either be a simple or complex
lowpass filter, depending on the AWG requirements for
waveform function and frequencies. The main limita-
tions of the AWG’s flexibility are DAC resolution and
dynamic performance, memory length, clock frequen-
cy, and the filter characteristics.
Using the MAX5181/MAX5184 for
Arbitrary Waveform Generation
Designing a traditional arbitrary waveform generator
(AWG) requires five major functional blocks (Figure 8a):
clock generator, counter, waveform memory, DAC for
waveform reconstruction, and output filter. The wave-
form memory contains the sequentially stored digital
Although the MAX5181/MAX5184 offer high-frequency
operation and excellent dynamics, they are suitable for
12 ______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
+3V
AV
DD
+
+3V
10µF
0.1µF
+
0.1µF
10µF
0.1µF
402Ω
DV
AV
DD
DD
CREF
+5V
-5V
402Ω
402Ω
OUTP
CLK
OUTPUT
400Ω*
D0–D9
MAX5181
MAX5184
MAX4108
OUTN
REFO
REFR
402Ω
0.1µF
400Ω*
R
**
SET
DGND
REN
AGND
**MAX5181 ONLY
*400Ω RESISTORS INTERNAL TO MAX5184 ONLY.
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
AV
DV
DD
DD
+3V
+3V
I COMPONENT
BP
FILTER
10
MAX5181
MAX5184
DIGITAL
SIGNAL
PROCESSOR
IF
0°
CARRIER
FREQUENCY
AV
DV
DD
DD
Σ
90°
Q COMPONENT
BP
FILTER
10
MAX5181
MAX5184
MAX2452
QUADRATURE
MODULATOR
Figure 7. Using the MAX5181/MAX5184 for I/Q Signal Reconstruction
______________________________________________________________________________________ 13
10-Bit, 40MHz, Current/Voltage-Output DACs
AV
DV
DD
DD
LOWPASS
RECONSTRUCTION
FILTER
DATA
10
WAVEFORM
MEMORY
(RAM)
COUNTER
ADR
CLOCK
GENERATOR
MAX5181
MAX5184
FILTERED
WAVEFORM
(ANALOG OUTPUT)
400Ω*
VARIABLE
fc
9.6k*
*MAX5181 ONLY
Figure 8a. Traditional Arbitrary Waveform Generation
CLOCK
GENERATOR
AV
DV
DD
DD
LOWPASS
RECONSTRUCTION
FILTER
A
DATA
10
D
WAVEFORM
MEMORY
(RAM)
D
E
R
PIR
ADR
PHASE
ACCUMULATOR
MAX5181
MAX5184
FILTERED
WAVEFORM
(ANALOG OUTPUT)
PHASE
INCREMENT
REGISTER
400Ω*
ACCUMULATOR
FEEDBACK LOOP
FOR DATA BITS
VARIABLE
fc
9.6k*
*MAX5181 ONLY
Figure 8b. Direct Digital Synthesis AWG
relaxed requirements in resolution (10-bit AWGs). To
increase an AWG’s high-frequency accuracy, tempera-
ture stability, wide-band tuning, and past phase-contin-
uos frequency switching, the user may approach a
direct digital synthesis (DDS) AWG (Figure 8b). This
DDS loop supports standard waveforms that are repeti-
tive, such as sine, square, TTL, and triangular wave-
forms. DDS allows for precise control of the
data-stream input to the DAC. Data for one complete
output waveform cycle is sequentially stored in a RAM.
As the RAM addresses are changing, the DAC con-
verts the incoming data bits into a corresponding volt-
age waveform. The resulting output signal frequency is
proportional to the frequency rate at which the RAM
addresses are changed.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the MAX5181/MAX5184’s performance. Unwanted
digital crosstalk may couple through the input, refer-
ence, power-supply, and ground connections, which
may affect dynamic specifications like SꢁR or SFDR. In
addition, electromagnetic interference (EMI) can either
couple into or be generated by the MAX5181/
MAX5184. Therefore, grounding and power-supply
decoupling guidelines for high-speed, high-frequency
applications should be closely followed.
First, a multilayer PC board with separate ground and
power-supply planes is recommended. High-speed
signals should be run on controlled impedance lines
14 ______________________________________________________________________________________
10-Bit, 40MHz, Current/Voltage-Output DACs
directly above the ground plane. Since the MAX5181/
MAX5184 have separate analog and digital ground
buses (AGꢁD and DGꢁD, respectively), the PC board
should also have separate analog and digital ground
sections with only one point connecting the two. Digital
signals should run above the digital ground plane, and
analog signals should run above the analog ground
plane.
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with addi-
tional decoupling capacitors forming a pi network can
also improve performance.
Chip Information
TRAꢁSISTOR COUꢁT: 9464
Both devices have two power-supply inputs: analog
V
DD
(AV ) and digital V
(DV ). Each AV
input
DD
DD
DD
DD
SUBSTRATE COꢁꢁECTED TO AGꢁD
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close as possible to the ground plane.
The DV
pins should also have separate 10µF and
DD
0.1µF capacitors adjacent to their respective pins. Try
to minimize analog load capacitance for proper opera-
tion. For best performance, bypass with low-ESR 0.1µF
capacitors to AV
.
DD
______________________________________________________________________________________ 15
10-Bit, 40MHz, Current/Voltage-Output DACs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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