MAX5189BEEI-T [MAXIM]
D/A Converter, 1 Func, Parallel, 8 Bits Input Loading, 0.025us Settling Time, PDSO28, 0.150 INCH, 0.025 INCH PITCH, QSOP-28;
| 型号： | MAX5189BEEI-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Parallel, 8 Bits Input Loading, 0.025us Settling Time, PDSO28, 0.150 INCH, 0.025 INCH PITCH, QSOP-28 |
| 文件： | 总15页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1581; Rev 3; 12/01
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
General Description
Features
The MAX5186 contains two 8-bit, simultaneous-update,
current-output digital-to-analog converters (DACs)
designed for superior performance in communications
systems requiring analog signal reconstruction with low
distortion and low-power operation. The MAX5189 pro-
vides equal specifications, with on-chip precision resis-
tors for voltage output operation. The MAX5186/
MAX5189 are designed for a 10pVs glitch operation to
minimize unwanted spurious signal components at the
output. An on-board +1.2V bandgap circuit provides a
well-regulated, low-noise reference that can be dis-
abled for external reference operation.
o +2.7V to +3.3V Single-Supply Operation
o Wide Spurious-Free Dynamic Range:
70dB at f = 2.2MHz
OUT
o Fully Differential Outputs for Each DAC
o
o
0.ꢀ5 FSR ꢁain Mismatch
0.ꢂꢀꢃ Phase Mismatch
o Low-Current Standby or Full Shutdown Modes
o Internal +ꢂ.2V, Low-Noise Bandgap Reference
o Small 28-Pin QSOP Package
The MAX5186/MAX5189 are designed to provide a high
level of signal integrity for the least amount of power dissi-
pation. Both DACs operate from a single supply voltage
of +2.7V to +3.3V. Additionally, these DACs have three
modes of operation: normal, low-power standby, and
complete shutdown, which provides the lowest possible
power dissipation with a 1µA (max) shutdown current. A
fast wake-up time (0.5µs) from standby mode to full DAC
operation allows power conservation by activating the
DACs only when required.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 QSOP
MAX5186BEEI
MAX5189BEEI
28 QSOP
The MAX5186/MAX5189 are packaged in a 28-pin
QSOP and are specified for the extended (-40°C to
+85°C) temperature range. For higher resolution, dual
10-bit versions, refer to the MAX5180/MAX5183 data
sheet.
Pin Configuration
TOP VIEW
Applications
Signal Reconstruction of I and Q
Transmit Signals
CREF1
OUT1P
OUT1N
AGND
1
2
3
4
5
6
7
8
9
28 CREF2
27 OUT2P
26 OUT2N
25 REFO
24 REFR
Digital Signal Processing
Arbitrary Waveform Generation (AWG)
Imaging Applications
AV
DD
MAX5186
MAX5189
DACEN
PD
23 DGND
22 DV
21 D7
20 D6
19 D5
18 D4
17 D3
16 D2
15 D1
DD
CS
CLK
N.C. 10
REN 11
DGND 12
DGND 13
D0 14
QSOP
________________________________________________________________ Maxim Integrated Products
ꢂ
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
ABSOLUTE MAXIMUM RATINGS
AV , DV
to AGꢁD, DGꢁD ................................ -0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DD
Digital Input to DGꢁD.............................................. -0.3V to +6V
OUT1P, OUT1ꢁ, OUT2P, OUT2ꢁ, CREF1,
28-Pin QSOP (derate 9.00mW/°C above +70°C) ....... 725mW
Operating Temperature Ranges
MAX518_BEEI................................................. -40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
CREF2 to AGꢁD.................................................. -0.3V to +6V
V
to AGꢁD ......................................................... -0.3V to +6V
REF
AGꢁD to DGꢁD................................................... -0.3V to +0.3V
AV to DV .................................................................... 3.3V
DD
DD
Maximum Current into Any Pin........................................... 50mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
ꢁ
8
-1
Bits
LSB
LSB
Integral ꢁonlinearity
IꢁL
DꢁL
0.25
0.25
+1
+1
Differential ꢁonlinearity
Guaranteed monotonic
-1
MAX5186
MAX5189
(ꢁote 1)
-1
+1
Zero-Scale Error
LSB
LSB
-4
+4
Full-Scale Error
-20
4
+20
DYNAMIC PERFORMANCE
Output Settling Time
Glitch Impulse
To 0.5LSB error band
25
10
72
70
-70
-68
52
52
-60
50
10
ns
pVs
f
f
f
f
f
f
= 550kHz
OUT
OUT
OUT
OUT
OUT
OUT
Spurious-Free Dynamic Range
to ꢁyquist
SFDR
THD
SꢁR
f
f
= 40MHz
= 40MHz
dBc
dB
CLK
= 2.2MHz, T = +25°C
A
57
46
= 550kHz
Total Harmonic Distortion
to ꢁyquist
CLK
= 2.2MHz, T = +25°C
A
-63
= 550kHz
Signal-to-ꢁoise-Ratio to ꢁyquist
f
f
= 40MHz
= 2.2MHz
dB
CLK
= 2.2MHz, T = +25°C
A
DAC-to-DAC Output Isolation
Clock and Data Feedthrough
Output ꢁoise
dB
nVs
OUT
All 0s to all 1s
pA/√Hz
Gain Mismatch Between DAC
Outputs
f
f
= 2.2MHz, T = +25°C
A
0.5
1
LSB
OUT
Phase Mismatch Between DAC
Outputs
= 2.2MHz
0.15
degrees
OUT
2
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
ANALOG OUTPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Full-Scale Output Voltage
Voltage Compliance of Output
Output Leakage Current
Full-Scale Output Current
V
400
mV
V
FS
-0.3
-1
0.8
1
DACEꢁ = 0, MAX5186 only
MAX5186 only
µA
mA
I
FS
0.5
1
1.5
DAC External Output Resistor
Load
R
L
MAX5186 only
400
Ω
REFERENCE
Output Voltage Range
V
1.12
1.2
50
1.28
V
REF
Output Voltage Temperature
Drift
TCV
ppm/°C
REF
Reference Output Drive
Capability
I
10
µA
REFOUT
Reference Supply Rejection
0.5
8
mV/V
Current Gain (I /I
)
mA/mA
FS REF
POWER REQUIREMENTS
Analog Power-Supply Voltage
Analog Supply Current
Digital Power-Supply Voltage
Digital Supply Current
AV
2.7
2.7
3.3
5.0
3.3
5.0
1.5
V
DD
IAV
PD = 0, DACEꢁ = 1, digital inputs at 0 or DV
2.7
mA
V
DD
DD
DD
DV
IDV
PD = 0, DACEꢁ = 1, digital inputs at 0 or DV
PD = 0, DACEꢁ = 0, digital inputs at 0 or DV
4.2
1.0
mA
mA
DD
STAꢁDBY
DD
Standby Current
I
DD
PD = 1, DACEꢁ = X, digital inputs at 0 or DV
(X = don’t care)
DD
Shutdown Current
I
0.5
1
µA
SHDꢁ
LOGIC INPUTS AND OUTPUTS
Digital Input Voltage High
Digital Input Voltage Low
Digital Input Current
V
2
V
V
IH
V
0.8
1
IL
I
Iꢁ
V
Iꢁ
= 0 or DV
DD
µA
pF
Digital Input Capacitance
TIMING CHARACTERISTICS
C
Iꢁ
10
DAC1 DATA to CLK Rise
Setup Time
t
10
10
0
ns
ns
ns
ns
DS1
DS2
DH1
DH2
DAC2 DATA to CLK Fall
Setup Time
t
DAC1 CLK Rise to DATA
Hold Time
t
t
DAC2 CLK Fall to DATA
Hold Time
0
_______________________________________________________________________________________
3
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= DV
= +3V 10ꢀ, AGꢁD = DGꢁD = 0, f
= 40MHz, I = 1mA, 400Ω differential output, C = 5pF, T = T
to T
,
MAX
DD
DD
CLK
FS
L
A
MIꢁ
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
CS Fall to CLK Rise Time
CS Fall to CLK Fall Time
SYMBOL
CONDITIONS
MIN
TYP
5
MAX
UNITS
ns
5
ns
DACEꢁ Rise Time to V
0.5
50
µs
OUT
PD Fall Time to V
Clock Period
µs
OUT
t
25
10
10
ns
CLK
Clock High Time
Clock Low Time
t
ns
CH
t
CL
ns
Note 1: Excludes reference and reference resistor (MAX5189) tolerance.
Typical Operating Characteristics
(AV
= DV
= +3V, AGꢁD = DGꢁD = 0, 400Ω differential output, I = 1mA, C = 5pF, T = +25°C, unless otherwise noted.)
DD FS L A
DD
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
2.55
2.53
2.51
2.49
2.47
2.45
0.150
0.125
0.100
0.075
0.050
0.025
0.100
0.075
0.050
0.025
MAX5186
MAX5189
0
-0.025
-0.050
-0.075
0
-0.025
-0.050
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
32 64 96 128 160 192 224 256
INPUT CODE
0
32 64 96 128 160 192 224 256
INPUT CODE
SUPPLY VOLTAGE (V)
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
DIGITAL SUPPLY CURRENT
vs. SUPPLY VOLTAGE
4.0
3.5
3.0
2.5
2.0
1.5
10
8
5
MAX5189
4
3
2
1
0
MAX5186
MAX5189
6
MAX5189
MAX5186
MAX5186
4
2
0
-40
-15
10
35
60
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
Typical Operating Characteristics (continued)
(AV
= DV
= +3V, AGꢁD = DGꢁD = 0, 400Ω differential output, I = 1mA, C = 5pF, T = +25°C, unless otherwise noted.)
DD
DD
FS
L
A
STANDBY CURRENT vs. SUPPLY VOLTAGE
STANDBY CURRENT vs. TEMPERATURE
SHUTDOWN CURRENT vs. SUPPLY VOLTAGE
610
600
590
580
570
560
0.80
600
590
580
570
560
550
540
0.75
0.70
MAX5186
MAX5186
MAX5189
MAX5186
0.65
0.60
MAX5189
MAX5189
0.55
0.50
0.45
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4.0
2.5
3.0
3.5
4.5
5.0
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
OUTPUT CURRENT
vs. REFERENCE CURRENT
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
4
3
1.28
1.27
1.26
1.25
1.24
1.23
1.28
1.27
1.26
1.25
1.24
1.23
2
1
0
MAX5189
MAX5186
MAX5189
MAX5186
300
0
100
200
400
500
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
REFERENCE CURRENT (µA)
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DYNAMIC RESPONSE RISE TIME
DYNAMIC RESPONSE FALL TIME
SETTLING TIME
OUT_P
150mV/
div
OUT_P
150mV/
div
OUT_N
100mV/
div
OUT_N
150mV/
div
OUT_N
150mV/
div
OUT_P
100mV/
div
50ns/div
50ns/div
12.5ns/div
_______________________________________________________________________________________
5
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
Typical Operating Characteristics (continued)
(AV
= DV
= +3V, AGꢁD = DGꢁD = 0, 400Ω differential output, I = 1mA, C = 5pF, T = +25°C, unless otherwise noted.)
DD FS L A
DD
SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK FREQUENCY
FFT PLOT, DAC1
FFT PLOT, DAC2
100
90
80
70
60
50
40
0
-10
0
-10
f
= 2.2MHz
= 40MHz
f
= 2.2MHz
= 40MHz
OUT
CLK
OUT
CLK
f
f
-20
-20
-30
-30
-40
-50
-60
-40
-50
-60
DAC2
DAC1
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
10 15 20 25 30 35 40 45 50 55 60
CLOCK FREQUENCY (MHz)
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
OUTPUT FREQUENCY (MHz)
OUTPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC1
78
SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT
FREQUENCY AND CLOCK FREQUENCY, DAC2
78
SPURIOUS-FREE DYNAMIC RANGE
vs. FULL-SCALE OUTPUT CURRENT
74
72
70
68
f
= 40MHz
CLK
f
= 60MHz
CLK
76
74
72
70
68
66
76
74
72
70
68
66
f
= 60MHz
CLK
f
= 20MHz
CLK
f
= 40MHz
f
= 20MHz
CLK
CLK
66
64
f
= 50MHz
CLK
f
CLK
= 10MHz
f
f
= 10MHz
CLK
= 50MHz
CLK
62
60
f
= 30MHz
f
= 30MHz
CLK
CLK
500 700 900 1100 1300 1500 1700 1900 2100 2300
OUTPUT FREQUENCY (kHz)
500 700 900 1100 1300 1500 1700 1900 2100 2300
OUTPUT FREQUENCY (kHz)
0.5
0.75
1.0
1.25
1.5
FULL-SCALE OUTPUT CURRENT (mA)
MULTITONE
SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
SIGNAL-TO-NOISE PLUS DISTORTION
vs. OUTPUT FREQUENCY
62.5
62.0
61.5
61.0
60.5
60.0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
DAC2
DAC1
-120
0
500
1000
1500
2000
2500
0
2.5
5
7.5 10 12.5 15 17.5
OUTPUT FREQUENCY (kHz)
OUTPUT FREQUENCY (MHz)
6
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
Pin Description
PIN
1
NAME
CREF1
OUT1P
OUT1ꢁ
AGꢁD
FUNCTION
Reference Bias Bypass, DAC1
2
Positive Analog Output, DAC1. Current output for MAX5186; voltage output for MAX5189.
ꢁegative Analog Output, DAC1. Current output for MAX5186; voltage output for MAX5189.
Analog Ground
3
4
5
AV
Analog Positive Supply, +2.7V to +3.3V
DD
DAC Enable, Digital Input
0: Enter DAC standby mode with PD = DGꢁD.
1: Power-up DAC with PD = DGꢁD.
6
7
DACEꢁ
PD
X: Enter shutdown mode with PD = DV
(X = don’t care).
DD
Power-Down Select
0: Enter DAC standby mode (DACEꢁ = DGꢁD) or power-up DAC (DACEꢁ = DV ).
DD
1: Enter shutdown mode.
8
9
Active-Low Chip Select
CS
CLK
Clock input
10
11
12
13
14
15–20
21
22
23
24
25
26
27
28
ꢁ.C.
REN
DGꢁD
DGꢁD
D0
ꢁo Connect. Do not connect to this pin.
Active-Low Reference Enable. Connect to DGꢁD to activate on-chip +1.2V reference.
Digital Ground
Digital Ground
Data Bit D0 (LSB)
D1–D6
D7
Data Bits D1–D6
Data Bit D7 (MSB)
DV
Digital Supply, +2.7V to +3.3V
DD
DGꢁD
REFR
Digital Ground
Reference Input
REFO
Reference Output
OUT2ꢁ
OUT2P
CREF2
ꢁegative Analog Output, DAC2. Current output for MAX5186; voltage output for MAX5189.
Positive Analog Output, DAC2. Current output for MAX5186; voltage output for MAX5189.
Reference Bias Bypass, DAC2
_______________________________________________________________________________________
7
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
External Reference
Detailed Description
To disable the MAX5186/MAX5189’s internal reference,
The MAX5186/MAX5189 are dual, 8-bit digital-to-ana-
log converters (DACs) capable of operating with clock
speeds up to 40MHz. Each of these dual converters
consists of separate input and DAC registers, followed
by a current source array capable of generating up to
1.5mA full-scale output current (Figure 1). An integrat-
ed +1.2V voltage reference and control amplifier deter-
mine the data converters’ full-scale output currents/
voltages. Careful reference design ensures close gain
matching and excellent drift characteristics. The
MAX5189’s voltage output operation features matched
400Ω on-chip resistors that convert the current array
current into a voltage.
connect REN to DV . A temperature-stable, external
DD
reference may now be applied to drive the REFO pin to
set the full-scale output (Figure 3). Choose a reference
capable of supplying at least 150µA to drive the bias
circuit that generates the cascode current for the cur-
rent array. For improved accuracy and drift perfor-
mance, choose a fixed output voltage reference such
as the +1.2V, 25ppm/°C MAX6520 bandgap reference.
Standby Mode
To enter the lower power standby mode, connect digi-
tal inputs PD and DACEꢁ to DGꢁD. In standby, both
the reference and the control amplifier are active with
the current array inactive. To exit this condition, DACEꢁ
must be pulled high with PD held at DGꢁD. Both the
MAX5186/MAX5189 typically require 50µs to wake up
and let both outputs and reference settle.
Internal Reference and
Control Amplifier
The MAX5186/MAX5189 provide an integrated
50ppm/°C, +1.2V, low-noise bandgap reference that
can be disabled and overridden by an external refer-
ence voltage. REFO serves either as an external refer-
ence input or an integrated reference output. If REN is
connected to DGꢁD, the internal reference is selected
and REFO provides a +1.2V output. Due to its limited
10µA output drive capability, REFO must be buffered
with an external amplifier if heavier loading is required.
Shutdown Mode
For lowest power consumption, the MAX5186/MAX5189
provide a power-down mode in which the reference,
control amplifier, and current array are inactive and the
DACs’ supply current is reduced to 1µA. To enter this
mode, connect PD to DV . To return to active mode,
DD
connect PD to DGꢁD and DACEꢁ to DV . About 50µs
DD
are required for the parts to leave shutdown mode and
settle to their outputs’ values prior to shutdown. Table 1
lists the power-down mode selection.
The MAX5186/MAX5189 also employ a control amplifier
designed to simultaneously regulate the full-scale out-
put current (I ) for both outputs of the devices. The
FS
output current is calculated as follows:
Timing Information
Both DAC cells residing in the MAX5186/MAX5189
write to their outputs simultaneously (Figure 4). The
input latch of the first DAC (DAC1) is loaded after the
clock signal transitions high. When the clock signal
transitions low, the input latch of the second DAC
(DAC2) is loaded. The contents of both input latches
are simultaneously shifted to the DAC registers, and
their outputs update at the rising edge of the next
clock.
✕
I
FS
= 8
I
REF
where I
REFO SET
is the reference output current (I
=
REF
REF
/R
V
) and I is the full-scale output current.
FS
R
is the reference resistor that determines the
SET
amplifier’s output current on the MAX5186 (Figure 2).
This current is mirrored into the current source array
where it is equally distributed between matched current
segments and summed to valid output current readings
for the DACs.
The MAX5189 converts each output current (DAC1 and
Outputs
The MAX5186 outputs are designed to supply full-scale
output currents of 1mA into 400Ω loads in parallel with
a capacitive load of 5pF. The MAX5189 features inte-
grated 400Ω resistors that restore the array currents to
proportional, differential voltages of 400mV. These dif-
ferential output voltages can then be used to drive a
balun transformer or a low-distortion, high-speed oper-
ational amplifier to convert the differential voltage into a
single-ended voltage.
DAC2) into an output voltage (V
, V
) with two
OUT1 OUT2
internal, ground-referenced 400Ω load resistors. Using
the internal +1.2V reference voltage, the MAX5189’s
integrated reference output-current resistor (R
=
SET
9.6kΩ) sets I
to 125µA and I to 1mA.
FS
REF
8
_______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
AV
AGND
CS
DACEN
PD
DD
REN
1.2V REF
REFO
REFR
CREF1
CREF2
CURRENT-
SOURCE ARRAY
OUT1P
DAC1 SWITCHES
DAC2 SWITCHES
OUT1N
OUT2N
OUT2N
9.6k*Ω
OUTPUT
LATCHES
OUTPUT
LATCHES
400Ω* 400Ω* 400Ω* 400Ω*
MSB
DECODE
MSB
DECODE
CLK
MAX5186
MAX5189
INPUT
LATCHES
INPUT
LATCHES
DV
DD
DGND
*INTERNAL 400Ω AND 9.6kΩ
RESISTORS FOR MAX5189 ONLY.
D7–D0
Figure 1. Functional Diagram
Offset Error
Applications Information
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (IꢁL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Differential Nonlinearity
Differential nonlinearity (DꢁL) (Figure 5b) is the differ-
ence between an actual step height and the ideal value
of 1LSB. A DꢁL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
_______________________________________________________________________________________
9
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
OPTIONAL EXTERNAL BUFFER
FOR HEAVIER LOADS
REN
+1.2V
DGND
MAX4040
BANDGAP
REFERENCE
REFO
REFR
I
FS
C
CURRENT-
SOURCE ARRAY
COMP*
I
REF
AGND
**
R
SET
9.6kΩ
R
SET
MAX5186
MAX5189
AGND
V
R
REF
I
=
REF
SET
*COMPENSATION CAPACITOR (C
= 100nF)
**9.6kΩ REFERENCE CURRENT-SET RESISTOR
COMP
INTERNAL TO MAX5189 ONLY. USE EXTERNAL
R
FOR MAX5186.
SET
Figure 2. Setting I with the Internal +1.2V Reference and the Control Amplifier
FS
DV
DD
10µF
0.1µF
DGND
REN
+1.2V
AV
DD
BANDGAP
REFERENCE
EXTERNAL
+1.2V
REFERENCE
REFO
REFR
I
FS
CURRENT-
SOURCE ARRAY
MAX6520
AGND
*
9.6kΩ
R
SET
MAX5186
MAX5189
AGND
*9.6kΩ REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5189 ONLY. USE EXTERNAL
FOR MAX5186.
R
SET
Figure 3. MAX5186/MAX5189 with External Reference
10 ______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
Table 1. Power-Down Mode Selection
PD
DACEN (DAC
ENABLE)
POWER-DOWN
MODE
OUTPUT STATE
(POWER-DOWN SELECT)
MAX5186
MAX5189
High-Z
AGꢁD
0
0
1
0
1
X
Standby
Wake-Up
Shutdown
Last state prior to standby mode
MAX5186
MAX5189
High-Z
AGꢁD
X = Don’t care
t
t
t
CH
CLK
CL
CLK
D0–D7
DAC1
DAC2
DAC1
DAC2
DAC1
DAC2
t
t
t
t
DH1
DS1
DS2
DH1
OUT1
OUT2
N - 2
N - 2
N - 1
N - 1
N
N
Figure 4. Timing Diagram
Digital Feedthrough
where V is the fundamental amplitude, and V through
1 2
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
V are the amplitudes of the 2nd- through 5th-order
5
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest distortion
component.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5186. The differential
voltage across OUT1P (or OUT2P) and OUT1ꢁ (or
OUT2ꢁ) is converted into a single-ended voltage by
designing an appropriate operational amplifier configu-
ration (Figure 6).
2
2
2
2
(V + V + V
+ V )
5
2
3
4
THD = 20×log
V
1
______________________________________________________________________________________ 11
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
7
6
6
5
5
1 LSB
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
4
4
AT STEP
011 (1/2 LSB )
3
3
2
1
0
1 LSB
2
1
0
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
AT STEP
001 (1/4 LSB )
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 5a. Integral Nonlinearity
Figure 5b. Differential Nonlinearity
IDEAL FULL-SCALE OUTPUT
7
6
5
ACTUAL
3
2
1
0
DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
IDEAL DIAGRAM
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
ACTUAL
OFFSET
POINT
OFFSET ERROR
(+1 1/4 LSB)
4
0
IDEAL OFFSET
POINT
000 100
101
110
111
000
001
010
011
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 5c. Offset Error
Figure 5d. Gain Error
MAX5189’s dual DACs may be used to reconstruct the
analog I and Q components.
I/Q Reconstruction in a QAM Application
The MAX5186/MAX5189’s low distortion supports ana-
log reconstruction of in-phase (I) and quadrature (Q)
carrier components typically used in quadrature ampli-
tude modulation (QAM) architectures where I and Q
data are interleaved on a common data bus. A QAM
signal is both amplitude and phase modulated, created
by summing two independently modulated carriers of
identical frequency but different phase (90° phase dif-
ference).
The I/Q reconstruction system is completed by a quad-
rature modulator that combines the reconstructed I and
Q components with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
Grounding and Power-Supply Decoupling
Grounding and power-supply decoupling strongly influ-
ence the MAX5186/MAX5189’s performance. Unwanted
digital crosstalk may couple through the input, refer-
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain and the MAX5186/
12 ______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
ence, power-supply, and ground connections, which
necting the two. Digital signals should run above the
digital ground plane, and analog signals should run
above the analog ground plane. Digital signals should
be kept far away from the sensitive analog reference
and clock input.
may affect dynamic specifications like signal-to-noise
ratio or SFDR. In addition, electromagnetic interference
(EMI) can either couple into or be generated by the
MAX5186/MAX5189. Therefore, grounding and power-
supply decoupling guidelines for high-speed, high-fre-
quency applications should be closely followed.
Both devices have two power-supply inputs: analog
V
DD
(AV ) and digital V
(DV ). Each AV
input
DD
DD
DD
DD
First, a multilayer printed circuit (PC) board with sepa-
rate ground and power-supply planes is recommend-
ed. High-speed signals should be run on controlled
impedance lines directly above the ground plane.
Since the MAX5186/MAX5189 have separate analog
and digital ground buses (AGꢁD and DGꢁD, respec-
tively), the PC board should also have separate analog
and digital ground sections with only one point con-
should be decoupled with parallel 10µF and 0.1µF
ceramic-chip capacitors. These capacitors should be
as close to the pin as possible, and their opposite ends
should be as close to the ground plane as possible.
The DV
pins should also have separate 10µF and
DD
0.1µF capacitors adjacent to their respective pins. Try
to minimize analog load capacitance for proper opera-
tion. For best performance, it is recommended to
+3V
+
10µF
AV
AV
DD
DD
+3V
0.1µF
+
0.1µF
0.1µF
10µF
0.1µF
AV
DV
DD
DD
CREF1
402Ω
CREF2
+5V
-5V
402Ω
402Ω
CLK
OUT1P
OUTPUT 1
*
400Ω
D0–D7
MAX5186
MAX5189
MAX4108
REFO
0.1µF
OUT1N
402Ω
*
400Ω
REFR
402Ω
+5V
402Ω
402Ω
RSET**
OUT2P
OUT2N
OUTPUT 2
400Ω*
MAX4108
-5V
DGND
REN
AGND
402Ω
*
400Ω
**MAX5186 ONLY
*400Ω RESISTORS INTERNAL TO MAX5189 ONLY.
Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier
______________________________________________________________________________________ 13
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
+3V
+3V
+3V
I COMPONENT
BP
DAC1
FILTER
DIGITAL
SIGNAL
PROCESSOR
IF
0°
CARRIER
FREQUENCY
MAX5186
MAX5189
Σ
90°
Q COMPONENT
BP
DAC2
FILTER
MAX2452
QUADRATURE
MODULATOR
Figure 7. Using the MAX5186/MAX5189 for I/Q Signal Reconstruction
bypass CREF1 and CREF2 with low-ESR 0.1µF capaci-
Chip Information
TRAꢁSISTOR COUꢁT: 9464
SUBSTRATE COꢁꢁECTED TO AGꢁD
tors to AV
.
DD
The power-supply voltages should also be decoupled
with large tantalum or electrolytic capacitors at the
point they enter the PC board. Ferrite beads with addi-
tional decoupling capacitors forming a pi network can
also improve performance.
14 ______________________________________________________________________________________
Dual, 8-Bit, 40MHz, Current/Voltage,
Simultaneous-Output DACs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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