MAX5234AEUB [MAXIM]
Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs; 单电源3V / 5V ，电压输出，双路，高精度12位DAC
| 型号： | MAX5234AEUB |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single-Supply 3V/5V, Voltage-Output, Dual, Precision 12-Bit DACs |
| 文件： | 总19页 (文件大小：564K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2330; Rev 0; 1/02
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
General Description
Features
The MAX5234/MAX5235 precision, dual-output, 12-bit
digital-to-analog converters (DACs) consume only 360µA
from a single 5V (MAX5235) or 325µA from a single 3V
(MAX5234) supply. These devices feature output buffers
that swing Rail-to-Rail®. The internal gain amplifiers maxi-
mize the dynamic range of the DAC output.
ꢀ Guaranteed 1/2LSB INL (max)
ꢀ Low Supply Current
325µA (Normal Operation)
0.4µA (Full Power-Down Mode)
ꢀ Single-Supply Operation
3V (MAX5234)
The MAX5234/MAX5235 feature a 13.5MHz 3-wire seri-
al interface compatible with SPI™, QSPI™, and
MICROWIRE™. Each DAC input is organized as an
input register followed by a DAC register. A 16-bit shift
register loads data into the input registers. Input regis-
ters update the DAC registers independently or simulta-
neously. In addition, programmable control bits allow
power-down with 1kΩ or 200kΩ internal loads.
5V (MAX5235)
ꢀ Space-Saving 10-Pin µMAX Package
ꢀ Output Buffers Swing Rail-to-Rail
ꢀ Power-On Reset Clears Registers and DACs
to Zero
The MAX5234/MAX5235 are fully specified over the
extended industrial temperature range (-40°C to +85°C)
and are available in space-saving 10-pin µMAX packages.
ꢀ Programmable Shutdown Modes with 1kΩ or
200kΩ Internal Loads
ꢀ Resets to Zero
ꢀ 13.5MHz SPI/QSPI/MICROWIRE-Compatible,
Applications
3-Wire Serial Interface
Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adjustment
Motion Control
ꢀ Buffered Output Drives 5kΩ || 100pF
Ordering Information
INL
µP-Controlled Systems
TEMP
PIN-
PART
RANGE
PACKAGE
(LSB)
0.5
1
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
10 µMAX
10 µMAX
10 µMAX
10 µMAX
MAX5234AEUB
MAX5234BEUB
MAX5235AEUB
MAX5235BEUB
0.5
1
Pin Configuration
TOP VIEW
OUTA
REFA
GND
LDAC
CS
1
2
3
4
5
10 OUTB
9
8
7
6
REFB
MAX5234
MAX5235
V
DD
DIN
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
SPI/QSPI are trademarks of Motorola, Inc.
SCLK
µMAX
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND .............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
Digital Inputs to GND ..............................................-0.3V to +6V
REF_, OUT_ to GND ................................-0.3V to (V + 0.3V)
Maximum Current into Any Pin............................................50mA
10-Pin µMAX (derate 5.60mW/°C above +70°C).........444mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX5235
(V
= +4.5V to +5.5V, GND = 0, V
= V
= +2.5V, R = 5kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical
MAX
DD
REFA
REFB
L
L
A
MIN
values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
12
Bits
LSB
MAX5235A (Note 1)
MAX5235B (Note 1)
0.5
Integral Nonlinearity
INL
1
Differential Nonlinearity
Offset Error
DNL
1
5
LSB
mV
LSB
V
V
(Note 2)
OS
Gain Error
3
Full-Scale Voltage
V
Code = FFFhex, T = +25°C (Note 3)
4.087
4.095
2
4.103
FS
A
Full-Scale Temperature
Coefficient
TCV
Normalized to 4.095V
ppm/°C
FS
Offset Temperature Coefficient
Power-Supply Rejection
DC Crosstalk
TCV
8
µV/°C
µV
OS
PSR
4.5V ≤ V
≤ 5.5V
15
200
100
DD
(Note 4)
µV
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
Reference Current in Shutdown
V
R
(Note 5)
0.25
28
2.60
1
V
REF
Minimum with code 555 hex and AAA hex
37
kΩ
µA
REF
REF
I
MULTIPLYING MODE PERFORMANCE
Reference -3dB Bandwidth,
Slew-Rate Limited
Input code = FFF hex, V
_ = 0.5V
_ = 3.6V
+
+
REF
REF
REF
P-P
P-P
350
-80
79
kHz
dB
1.5V
DC
Input code = 000 hex, V
1.8V , f = 1kHz
DC
Reference Feedthrough
Signal-to-Noise plus Distortion
Ratio
Input code = FFF hex, V
1.5V , f = 10kHz
DC
_ = 2V
+
P-P
SINAD
dB
2
_______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
ELECTRICAL CHARACTERISTICS—MAX5235 (continued)
(V
= +4.5V to +5.5V, GND = 0, V
= V
= +2.5V, R = 5kΩ, C = 100pF, T = T
to T
, unless otherwise noted. Typical
MAX
DD
REFA
REFB
L
L
A
MIN
values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
V
DD
0.3 x
V
IL
V
DD
Input Hysteresis
V
200
8
mV
µA
pF
HYS
Input Leakage Current
Input Capacitance
Digital inputs = 0 or V
DD
1
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.6
10
V/µs
µs
To 0.5LSB, V
=
4V,
STEP
Voltage-Output Settling Time
0.25V < V
< (V - 0.25V)
OUT
DD
0 to
Output-Voltage Swing
(Note 6)
V
V
DD
Time Required for Output to Settle
(Note 7)
(Note 7)
70
70
µs
After Turning on V
DD
Time Required for Output to
Settle After Exiting Full Power-
Down
µs
µs
Time Required for Output to
Settle After Exiting DAC Power-
Down
(Note 7)
60
Digital Feedthrough
CS = V , f
= 100kHz, V
= 5V
P-P
5
nV-s
nV-s
DD SCLK
SCLK
Major-Carry Glitch Energy
POWER SUPPLIES
Power-Supply Voltage
Power-Supply Current
40
V
4.5
5.5
450
5
V
DD
I
(Note 8)
360
1
µA
DD
Full power-down mode
Power-Supply Current in Power-
Down and Shutdown Modes
I
One DAC shutdown mode
Both DACs shutdown mode
190
26
215
42
µA
SHDN
_______________________________________________________________________________________
3
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
ELECTRICAL CHARACTERISTICS—MAX5234
(V
= +2.7V to +3.6V, GND = 0, V
= V
= +1.25V, R = 5kΩ, C = 100pF, T = T
to T
, unless otherwise noted.
MAX
DD
REFA
REFB
L
L
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
STATIC PERFORMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
12
Bits
LSB
MAX5234A (Note 1)
0.5
1
Integral Nonlinearity
INL
MAX5234B (Note 1)
Differential Nonlinearity
Offset Error
DNL
1
LSB
mV
V
(Note 2)
5
OS
Gain Error
GE
6
LSB
V
Full-Scale Voltage
V
Code = FFFhex, T = +25°C (Note 3)
2.041 2.0475 2.054
FS
A
Temperature Coefficient
Offset Temperature Coefficient
Power-Supply Rejection
DC Crosstalk
TCV
Normalized to 2.0475V
4
8
ppm/°C
µV/°C
µV
FS
TCV
OS
PSR
2.7V ≤ V
≤ 3.6V
18
280
100
DD
(Note 4)
µV
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
Reference Current in Shutdown
V
R
(Note 5)
0.25
28
1.50
1
V
REF
Minimum with code 555 hex and AAA hex
37
kΩ
µA
REF
REF
I
MULTIPLYING MODE PERFORMANCE
Reference -3dB Bandwidth, Slew-
Rate Limited
Input code = FFF hex, V
_ = 0.5V
_ = 1.6V
_ = 0.6V
+
+
+
REF
REF
REF
P-P
P-P
P-P
350
-80
79
kHz
dB
0.75V
DC
Input code = 000 hex, V
0.8V , f = 1kHz
DC
Reference Feedthrough
Signal-to-Noise plus Distortion
Ratio
Input code = FFF hex, V
0.9V , f = 10kHz
DC
SINAD
dB
DIGITAL INPUTS
0.7 x
Input High Voltage
Input Low Voltage
V
V
V
IH
V
DD
0.3 x
V
IL
V
DD
Input Hysteresis
V
200
8
mV
µA
pF
HYS
Input Leakage Current
Input Capacitance
Digital inputs = 0 or V
1
DD
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.6
10
V/µs
µs
To 0.5LSB, V
=
2V,
STEP
Voltage-Output Settling Time
Output-Voltage Swing
0.25V < V
< (V - 0.25V)
OUT
DD
0 to
(Note 6)
V
V
DD
4
_______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
ELECTRICAL CHARACTERISTICS—MAX5234 (continued)
(V
= +2.7V to +3.6V, GND = 0, V
= V
= +1.25V, R = 5kΩ, C = 100pF, T = T
to T
, unless otherwise noted.
MAX
DD
REFA
REFB
L
L
A
MIN
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Time Required for Output to Settle
(Note 7)
60
µs
After Turning on V
DD
Time Required for Output to
Settle After Exiting Full Power-
Down
(Note 7)
(Note 7)
60
50
µs
µs
Time Required for Output to
Settle After Exiting DAC Power-
Down
Digital Feedthrough
CS = V , f
= 100kHz, V
= 3V
5
nV-s
nV-s
DD SCLK
SCLK
P-P
Major Carry Glitch Energy
POWER SUPPLIES
Power-Supply Voltage
Power-Supply Current
115
V
2.7
3.6
430
5
V
DD
I
(Note 8)
325
0.4
175
25
µA
DD
Full power-down mode
Power-Supply Current in Power-
Down and Shutdown Modes
I
One DAC shutdown mode
Both DACs shutdown mode
200
40
µA
SHDN
TIMING CHARACTERISTICS—MAX5235 (FIGURES 1 AND 2)
(V
= +4.5V to +5.5V, GND = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
74
30
30
30
0
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
t
ns
t
ns
CL
t
ns
CSS
CSH
t
ns
t
30
0
ns
DS
DH
DIN Hold Time
t
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
t
t
10
30
75
30
40
ns
CS0
CS1
ns
t
ns
CSW
LDAC Pulse Width Low
CS Rise to LDAC Rise Hold Time
t
ns
LDL
t
(Note 9)
ns
CSLD
_______________________________________________________________________________________
5
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
TIMING CHARACTERISTICS—MAX5234 (FIGURES 1 AND 2)
(V
= +2.7V to +3.6V, GND = 0, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
74
30
30
30
0
TYP
MAX
UNITS
ns
SCLK Clock Period
t
CP
CH
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
t
ns
t
ns
CL
t
ns
CSS
CSH
t
ns
t
30
0
ns
DS
DH
DIN Hold Time
t
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
t
t
10
30
75
30
75
ns
CS0
CS1
ns
t
ns
CSW
LDAC Pulse Width Low
CS Rise to LDAC Rise Hold Time
t
ns
LDL
t
(Note 9)
ns
CSLD
Note 1: Accuracy is guaranteed in the following way:
V
V
_
REF
ACCURACY GUARANTEED FROM CODE
TO CODE
4095
DD
3
1.250
2.500
20
10
5
4095
Note 2: Offset is measured at the code closest to 10mV.
Note 3: Gain from V _ to V _ is typically 1.638 x CODE/4096.
REF
OUT
Note 4: DC crosstalk is measured as follows: set DAC A to midscale, and DAC B to zero, and measure DAC A output; then change
DAC B to full scale and measure ∆V for DAC A. Repeat the same measurement with DAC A and DAC B interchanged.
OUT
DC crosstalk is the maximum ∆V
measured.
OUT
Note 5: The DAC output voltage is derived by gaining up V
by 1.638 x CODE/4096. This gain factor may cause V
to try to
REF
OUT
exceed the supplies. The maximum value of V
in the reference input range spec prevents this from happening at full
REF
scale. The minimum V
value of 0.25V is determined by linearity constraints, not DAC functionality.
REF
Note 6: Accuracy is better than 1LSB for V
= 10mV to V
- 180mV.
OUT
DD
Note 7: Guaranteed by design. Not production tested.
Note 8: R = ∞ and digital inputs are at either V
or GND. V = full-scale output voltage.
OUT
LOAD
DD
Note 9: This timing requirement applies only to CS rising edges, which execute commands modifying the DAC input register contents.
6
_______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Typical Operating Characteristics
(V
= +5V (MAX5235) V
= +3V (MAX5234), R = 5kΩ, C = 100pF, V
= +1.25V (MAX5234), V
= +2.5V (MAX5235), C
DD
DD
L
L
REF
REF REF
= 0.1µF ceramic || 2.2µF electrolytic, both DACs on, V
= full scale, T = +25°C, unless otherwise noted.)
OUT
A
INTEGRAL NONLINEARITY
vs. DIGITAL CODE (MAX5235)
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (MAX5234)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5234)
0.5
0.4
0.25
0.20
0.15
0.10
0.05
0
0.4
0.3
0.2
0.1
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
-0.25
-0.1
-0.2
-0.3
-0.4
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
MAX5234
SUPPLY CURRENT vs. TEMPERATURE
MAX5235
SUPPLY CURRENT vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (MAX5235)
0.25
0.20
0.15
0.10
0.05
0
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
-0.05
-0.10
-0.15
-0.20
-0.25
NO LOAD
NO LOAD
0
0
0
500 1000 1500 2000 2500 3000 3500 4000
DIGITAL INPUT CODE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX5234
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5234
MAX5235
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.50
0.45
0.40
0.35
0.30
0.25
400
350
300
250
200
150
100
50
400
350
300
250
200
150
100
50
0.20
0.15
0.10
0.05
0
NO LOAD
NO LOAD
NO LOAD
0
0
-40
-15
10
35
60
85
2.7
2.8
2.9
3.0
3.1
3.2
3.3
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
7
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Typical Operating Characteristics (continued)
(V
= +5V (MAX5235) V
= +3V (MAX5234), R = 5kΩ, C = 100pF, V
= +1.25V (MAX5234), V
= +2.5V (MAX5235), C
DD
DD
L
L
REF
REF REF
= 0.1µF ceramic || 2.2µF electrolytic, both DACs on, V
= full scale, T = +25°C, unless otherwise noted.)
OUT
A
MAX5234
BOTH DACs SHUTDOWN SUPPLY
CURRENT vs. TEMPERATURE
MAX5234
MAX5235
FULL POWER-DOWN SUPPLY CURRENT
vs. TEMPERATURE
ONE DAC SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
30
29
28
27
26
25
180
179
178
177
176
175
1.0
0.9
0.8
0.7
0.6
0.5
24
23
22
21
20
174
173
172
171
170
0.4
0.3
0.2
0.1
0
NO LOAD
-15
NO LOAD
NO LOAD
-40
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX5235
BOTH DACs SHUTDOWN SUPPLY
CURRENT vs. TEMPERATURE
MAX5235
ONE DAC SHUTDOWN SUPPLY CURRENT
vs. TEMPERATURE
MAX5234
FULL-SCALE OUTPUT vs. TEMPERATURE
30
29
28
27
26
25
190
180
170
160
150
140
2.0455
2.0454
2.0453
2.0452
2.0451
2.0450
2.0449
24
23
22
21
20
130
120
110
100
90
NO LOAD
NO LOAD
-15
NO LOAD
-40
10
35
60
85
-40
-15
10
35
60
85
-40
10
35
60
85
-15
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX5235
MAX5234
MAX5235
FULL-SCALE OUTPUT vs. TEMPERATURE
FULL-SCALE ERROR vs. RESISTIVE LOAD
FULL-SCALE ERROR vs. RESISTIVE LOAD
4.0970
4.0965
4.0960
4.0955
4.0950
4.0945
4.0940
4.0935
4.0930
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
NO LOAD
-40
-15
10
35
60
85
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
TEMPERATURE (°C)
R (kΩ)
L
R (kΩ)
L
8
_______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Typical Operating Characteristics (continued)
(V
= +5V (MAX5235) V
= +3V (MAX5234), R = 5kΩ, C = 100pF, V
= +1.25V (MAX5234), V
= +2.5V (MAX5235), C
DD
DD
L
L
REF
REF REF
= 0.1µF ceramic || 2.2µF electrolytic, both DACs on, V
= full scale, T = +25°C, unless otherwise noted.)
OUT
A
MAX5234
DYNAMIC RESPONSE RISE TIME
MAX5235
DYNAMIC RESPONSE RISE TIME
MAX5234
DYNAMIC RESPONSE FALL TIME
MAX5234 toc19
MAX5234 toc20
MAX5234 toc21
CS
1V/div
CS
1V/div
CS
2V/div
OUT_
1V/div
OUT_
1V/div
OUT_
2V/div
2µs/div
4µs/div
2µs/div
MAX5235
DYNAMIC RESPONSE FALL TIME
MAX5234
CROSSTALK
MAX5235
CROSSTALK
MAX5234 toc23
MAX5234 toc22
MAX5234 toc24
OUTB
2V/div
OUTB
5V/div
CS
2V/div
OUTA
1mV/div
SHUTDOWN
OUTA
1mV/div
SHUTDOWN
OUT_
2V/div
2ms/div
2µs/div
40µs/div
MAX5234
DIGITAL FEEDTHROUGH
MAX5235
DIGITAL FEEDTHROUGH
MAX5234
MAJOR-CARRY GLITCH
MAX5234 toc25
MAX5234 toc26
MAX5234 toc27
SCLK
2V/div
SCLK
5V/div
CS
1V/div
OUT_
1mV/div
OUT_
50mV/div
AC -COUPLED
OUT_
1mV/div
40µs/div
40µs/div
1µs/div
_______________________________________________________________________________________
9
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Typical Operating Characteristics (continued)
(V
= +5V (MAX5235) V
= +3V (MAX5234), R = 5kΩ, C = 100pF, V
= +1.25V (MAX5234), V
= +2.5V (MAX5235), C
DD
DD
L
L
REF
REF REF
= 0.1µF ceramic || 2.2µF electrolytic, both DACs on, V
= full scale, T = +25°C, unless otherwise noted.)
OUT
A
MAX5235
FULL-SCALE OUTPUT VOLTAGE
vs. REFERENCE VOLTAGE
MAX5234
FULL-SCALE OUTPUT VOLTAGE
vs. REFERENCE VOLTAGE
MAX5235
MAJOR-CARRY GLITCH
MAX5234 toc28
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
2.25
2.00
1.75
CS
1.50
2V/div
1.25
1.00
0.75
OUT_
50mV/div
AC-COUPLED
0.50
0.25
0
2µs/div
0
0.5
1.0
1.5
(V)
2.0
2.5
0
0.25
0.50
V
0.75
(V)
1.00
1.25
V
REF
REF
output voltage proportional to the digital input code with
an inverted rail-to-rail ladder network (Figure 3).
Pin Description
PIN
NAME
FUNCTION
External Reference
The reference inputs accept both AC and DC values
with a voltage range extending from 0.25V to 2.6V for
the MAX5235 and 0.25V to 1.5V for the MAX5234. For
proper operation do not exceed the input voltage
range limits. Determine the output voltage using the fol-
lowing equation:
1
OUTA
DAC A Output
2
3
4
5
6
7
8
REFA
GND
LDAC
CS
Reference for DAC A
Ground
Load DACs A and B
Chip Select Input
Shift Register Serial Clock Input
Serial Data Input
SCLK
DIN
V
OUT
_ = (V
_ x NB / 4096) x 1.6384V/V
REF
where NB is the numeric value of the DACs binary input
code (0 to 4095), V
_ is the reference voltage, and
REF
V
Positive Supply
DD
1.6384V/V is the gain of the internal output amplifier.
9
REFB
OUTB
Reference for DAC B
DAC B Output
The code-dependent reference input impedance
ranges from a minimum of 28kΩ to several GΩ at code
0. The code-dependent reference input capacitance is
typically 23pF.
10
Detailed Description
The MAX5234/MAX5235 12-bit, voltage-output DACs
are easily configured with a 3-wire SPI, QSPI,
MICROWIRE serial interface. The devices include a 16-
bit data-in/data-out shift register and have an input con-
sisting of an input register and a DAC register. In
addition, these devices employ precision trimmed inter-
nal resistors to produce a gain of 1.6384V/V, maximizing
the output voltage swing, and a programmable shut-
down output impedance of 1kΩ or 200kΩ. The full-scale
output voltage is 4.095V for the MAX5235 and 2.0475V
for the MAX5234. These devices produce a weighted
Output Amplifier
The output amplifiers have internal resistors that pro-
vide for a gain of 1.6384V/V. These trimmed resistors
minimize gain error. The output amplifiers have a typi-
cal slew rate of 0.6V/µs and settle to 1/2LSB within 10µs
(typ) with a load of 5kΩ in parallel with 100pF. Use the
serial interface to set the shutdown output impedance
of the amplifiers to 1kΩ or 200kΩ.
10 ______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
COMMAND EXECUTED
CS
SCLK
1
8
9
16
D5 D4 D3 D2 D1 D0 S0
(1)
DIN
C1 C0
D10 D9
D11
C2
D8 D7
D6
Figure 1. Serial Interface Timing
t
LDL
t
CSLD
LDAC
t
CSW
CS
t
t
CSS
CSO
t
CSH
t
CS1
SCLK
t
t
CL
CH
t
CP
DIN
t
t
DH
DS
Figure 2. Detailed Serial Interface Timing
ously. The control bits and D11–D8 allow the DACs to
Serial Interface
operate independently.
The 3-wire serial interface (SPI, QSPI, and MICROWIRE
compatible) used in the MAX5234/MAX5235 allows for
complete control of DAC operations (Figures 4 and 5).
Figures 1 and 2 show the timing for the serial interface.
The serial word consists of 3 control bits followed by 12
data bits (MSB first) and 1 sub-bit as described in
Tables 1, 2, and 3. When the 3 control bits are all zero
or all 1, D11–D8 are used as additional control bits,
allowing for greater DAC functionality.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI and MICROWIRE), with CS low dur-
ing this period. The control bits and D11–D8 determine
which registers update and the state of the registers
when exiting shutdown. The 3-bit control and D11–D8
determine the following:
• Registers to be updated
• Selection of the power-down modes
The digital inputs allow any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC register(s) simultane-
The general timing diagram of Figure 1 illustrates data
acquisition. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
______________________________________________________________________________________ 11
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
either DAC input register, then LDAC must remain
Table 1. Serial Data Format
asserted for at least 30ns following the CS rising edge.
MSB <----------- 16 bits of serial data -----------> LSB
This requirement applies only for serial commands that
modify the value of the DAC input registers.
3 Control Bits
C2...C0
MSB......12 Data Bits.....LSB
D11................................D0
Sub Bit
S0
Applications Information
Definitions
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers,
depending on the control bits and D11–D8. The maxi-
mum clock frequency guaranteed for proper operation
is 13.5MHz. Figure 2 depicts a more detailed timing
diagram of the serial interface.
Integral Nonlinearity (INL)
Integral nonlinearity (Figure 6a) is the deviation of the
values on an actual transfer function from a straight
line. This straight line can be either a best-straight-line
fit (closest approximation to the actual transfer curve)
or a line drawn between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. For a DAC, the deviations are measured at every
single step.
Power-Down and Shutdown Modes
As described in Tables 2 and 3, several serial interface
commands put one or both of the DACs into shutdown
mode. Shutdown modes are completely independent
for each DAC. In shutdown, the amplifier output
becomes high impedance, and OUT_ terminates to
GND through the 200kΩ (typ) gain resistors. Optionally
(see Tables 2 and 3), OUT_ can have a termination of
1kΩ to GND.
Differential Nonlinearity (DNL)
Differential nonlinearity (Figure 6b) is the difference
between an actual step height and the ideal value of
1LSB. If the magnitude of the DNL is less than 1LSB, the
DAC guarantees no missing codes and is monotonic.
Full power-down mode shuts down the main bias gen-
erator and both DACs. The shutdown impedance of the
DAC outputs can still be controlled independently, as
described in Tables 2 and 3.
Offset Error
The offset error (Figure 6c) is the difference between
the ideal and the actual offset point. For a DAC, the off-
set point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated for by trimming.
A serial interface command exits shutdown mode and
updates a DAC register. Each DAC can exit shutdown
at the same time or independently (see Tables 2 and
3). For example, if both DACs are shut down, updating
the DAC A register causes DAC A to power up, while
DAC B remains shut down. In full power-down mode,
powering up either DAC also powers up the main bias
generator. To change from full power-down to both
DACs shutdown mode requires the waking of at least
one DAC between states.
Gain Error
Gain error (Figure 6d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its new
output value within the converter’s specified accuracy.
When powering up the MAX5234/MAX5235 (powering
V
), allow 60µs (MAX5234) or 70µs (MAX5235) for the
DD
output to stabilize. When exiting full power-down mode,
allow 60µs max (MAX5234) or 70µs max (MAX5235) for
the output to stabilize. When exiting DAC shutdown
mode, allow 50µs max (MAX5234) or 60µs max
(MAX5235) for the output to stablize.
Digital Feedthrough
Digital feedthrough is noise generated on the DAC’s
output when any digital input transitions. Proper board
layout and grounding significantly reduces this noise,
but there is always some feedthrough caused by the
DAC itself.
Load DAC Input (LDAC)
Asserting LDAC asynchronously loads the DAC regis-
ters from their corresponding input registers (DACs that
are shut down remain shut down). The LDAC input is
totally asynchronous and does not require any activity
on CS, SCLK, or DIN in order to take effect. If LDAC is
asserted coincident with a rising edge of CS, which
executes a serial command modifying the value of
Unipolar Output
Figure 7 shows the MAX5234/MAX5235 configured for
unipolar, rail-to-rail operation with a gain of 1.6384V/V.
The MAX5235 produces a 0 to 4.095V output with 2.5V
reference while the MAX5234 produces a range of 0 to
12 ______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Table 2. Serial Interface Programming Commands
16-BIT SERIAL WORD
FUNCTION
C2
0
C1
0
C0
1
D11..............D0
12-bit DAC data
12-bit DAC data
S0*
0
Load input register A; DAC registers are unchanged.
Load input register A; all DAC registers are updated.
0
1
0
0
Load all DAC registers from the shift register (start up both DACs
with new data, and load the input registers).
0
1
1
0
1
0
12-bit DAC data
0
0
Update both DAC registers from their respective input registers
(start up both DACs with data previously stored in the input
registers).
X X X X X X X X X X X X
1
1
0
1
1
0
12-bit DAC data
12-bit DAC data
0
0
Load input register B; DAC registers are unchanged.
Load input register B; all DAC registers are updated.
Power down both DACs respectively according to bits P1A and
P1B (see Table 3). Internal bias remains active.
1
0
1
0
1
0
P1A P1B X X X X X X X X X X
0 0 1 X X X X X X X X X
0
0
Update DAC register A from input register A (start up DAC A with
data previously stored in input register A).
Full power-down. Power down the main bias generator and
power down both DACs respectively according to bits P1A and
P1B (see Table 3).
0
0
0
0
0
0
0 1 1 P1A P1B X X X X X X X
1 0 1 X X X X X X X X X
0
0
Update DAC register B from input register B (start up DAC B with
data previously stored in input register B).
0
0
0
0
0
0
1 1 0 P1A X X X X X X X X
1 1 1 P1B X X X X X X X X
0
0
Power down DAC A according to bit P1A (see Table 3).
Power down DAC B according to bit P1B (see Table 3).
X = Don’t care.
* = S0 must be zero for proper operation.
2.0475V output with a 1.25V reference. Table 4 lists the
unipolar output codes.
Table 3. P1 Shutdown Modes
P1(A/B)
SHUTDOWN MODE
Bipolar Output
The MAX5234/MAX5235 can be configured for a bipo-
lar output, as shown in Figure 8. The output voltage is
given by the equation:
0
1
Shut down with internal 1kΩ load to GND
Shut down with internal 200kΩ load to GND
Digital Calibration and
Threshold Selection
V
OUT
= V
[((1.6348 x NB) / 4096) - 1]
REF
Figure 10 shows the MAX5234/MAX5235 in a digital
calibration application. With a bright light value applied
to the photodiode (on), the DAC is digitally ramped until
it trips the comparator. The microprocessor (µP) stores
this “high” calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration. The
µP then programs the DAC to set an output voltage at
the midpoint of the two calibrated values. Applications
include tachometers, motion sensing, automatic read-
ers, and liquid clarity analysis.
where NB represents the numeric value of the DAC’s
binary input code. Table 5 shows digital codes and the
corresponding output voltage for Figure 8’s circuit.
Using an AC Reference
In applications where the reference has an AC signal
component, the MAX5234/MAX5235 have multiplying
capabilities within the reference input voltage range
specifications. Figure 9 shows a technique for applying
a sinusoidal input to REF_, where the AC signal is offset
before being applied to the reference input.
______________________________________________________________________________________ 13
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Table 4. Unipolar Code Table
(Gain = 1.6384)
121kΩ
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
77.25kΩ
OUT_
4095
4096
R
R
R
1111 1111 1 111 (0)
1000 0000 0 001 (0)
1000 0000 0 000 (0)
0111 1111 1 111 (0)
0000 0000 0001 (0)
+V
× 1.6384
× 1.6384
REF
2R
2R
D0
2R
D9
2R
D10
2R
2049
4096
D11
1kΩ
+V
REF
REF_
GND
2048
4096
+V
× 1.6384 = V
REF
REF
SHOWN FOR ALL ONES ON DAC
2047
4096
Figure 3. Simplified DAC Circuit Diagram
+V
× 1.6384
× 1.6384
REF
5V
SS
1
+V
REF
4096
0000 0000 0 000 (0)
0V
Note: () are for the sub-bit.
MOSI
DIN
SCLK
CS
Table 5. Bipolar Code Table
SPI/QSPI
PORT
MAX5234
MAX5235
SCK
I/O
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
2047
2048
+V
1111 1111 1 111 (0)
REF
Figure 4. SPI/QSPI Interface Connections
1
+V
1000 0000 0 001 (0)
1000 0000 0 000 (0)
0111 1111 111 (0)
REF
2048
0V
SK
SO
I/O
SCLK
DIN
CS
1
-V
REF
2048
MICROWIRE
PORT
MAX5234
MAX5235
2047
2048
-V
0000 0000 001 (0)
REF
2048
2048
-V
= -V
REF
REF
0000 0000 000 (0)
Figure 5. Connections for MICROWIRE
Note: () are for the sub-bit.
14 ______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
7
6
6
1LSB
5
4
5
4
DIFFERENTIAL LINEARITY
ERROR (-1/4LSB)
AT STEP
011 (1/2LSB )
3
2
3
2
1
0
1LSB
DIFFERENTIAL
LINEARITY ERROR (+1/4LSB)
AT STEP
001 (1/4LSB )
1
0
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 6a. Integral Nonlinearity
Figure 6b. Differential Nonlinearity
IDEAL FULL-SCALE OUTPUT
ACTUAL
3
7
6
5
DIAGRAM
GAIN ERROR
(-1 1/4LSB)
2
IDEAL DIAGRAM
IDEAL DIAGRAM
ACTUAL
FULL-SCALE
OUTPUT
1
0
ACTUAL
OFFSET
POINT
OFFSET ERROR
(+1 1/4LSB)
4
0
IDEAL OFFSET
POINT
000
001
010
011
000 100
101
110
111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 6c. Offset Error
Figure 6d. Gain Error
______________________________________________________________________________________ 15
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
5V/3V
REF_
5V/3V
REF_
10kΩ
10kΩ
V
DD
V
DD
MAX5234
MAX5235
121kΩ
MAX5234
MAX5235
121kΩ
V+
V-
77.25kΩ
77.25kΩ
V
0.06384R
R
OUT
OUT_
DAC_
DAC_
OUT_
1kΩ
1kΩ
GND
GND
GAIN = 1.6384V/V
Figure 7. Unipolar Output Circuit (Rail-to-Rail)
Figure 8. Bipolar Output Circuit
5V/3V
V+
5V/3V
26kΩ
5V/3V
REF_
PHOTODIODE
AC
REFERENCE
INPUT
V
DD
MAX495
MAX5234
MAX5235
121kΩ
V
DD
REF_
V+
121kΩ
10kΩ
500mV
P-P
77.25kΩ
V
77.25kΩ
OUT
OUT_
OUT_
DAC_
µP
DAC_
V-
DIN
MAX5234
MAX5235
1kΩ
R
PULLDOWN
1kΩ
GND
GND
Figure 9. External Reference with AC Components
Figure 10. Digital Calibration
Digital Control of Gain and Offset
The two DACs can be used to control the offset and
gain for curve-fitting nonlinear functions, such as trans-
ducer linearization or analog compression/expansion
applications. The input signal is used as the reference
for the gain-adjust DAC, whose output is summed with
the output from the offset-adjust DAC. The relative
weight of each DAC output is adjusted by R1, R2, R3,
and R4 (Figure 11).
Sharing a Common DIN Line
Several MAX5234/MAX5235 may share one common
DIN signal line (Figure 12). In this configuration, the
data bus is common to all devices; data is not shifted
through a daisy-chain. The SCLK and DIN lines are
shared by all devices, but each IC needs its own dedi-
cated CS line.
Power-Supply Considerations
On power-up, the input and DAC registers clear (set to
zero code). Bypass the power supply with a 4.7µF
16 ______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
V
DD
121kΩ
MAX5234
MAX5235
REFA
77.25kΩ
OUTA
V
IN
R1
R3
CS
SCLK
DIN
INPUT
DAC
DAC A
DAC B
SHIFT
REGISTER
R2
REG A
REG A
INPUT
REG B
DAC
REG B
V
OUT
OUTB
REFB
R4
V
REF
77.25kΩ
121kΩ
VOUT = (GAIN) (OFFSET)
2NA R2
4096 R1 + R2
R4
R3
2NB R4
4096 R3
–
V
REF
=
V
1 +
IN
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DAC A.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DAC B.
GND
Figure 11. Digital Control of Gain and Offset
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX5234
MAX5235
MAX5234
MAX5235
MAX5234
MAX5235
SCLK
SCLK
DIN
SCLK
DIN
DIN
Figure 12. Multiple MAX5234/MAX5235 Sharing a Common DIN Line
capacitor in parallel with a 0.1µF capacitor to GND.
Minimize lead lengths to reduce lead inductance.
back to the MAX5234/MAX5235 GND. Carefully lay out
the traces between channels to reduce AC cross-cou-
pling and crosstalk. Wire-wrapped boards and sockets
are not recommended. If noise becomes an issue,
shielding may be required.
Grounding and Layout Considerations
Digital and AC transient signals on GND can create
noise at the output. Connect GND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance
ground plane or star connect all ground return paths
Chip Information
TRANSISTOR COUNT: 4184
PROCESS: BiCMOS
______________________________________________________________________________________ 17
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Functional Diagram
GND
V
REFA
DD
121kΩ
LDAC
DECODE CONTROL
77.25kΩ
OUTA
INPUT
REG A
DAC
REG A
DAC A
16-BIT
SHIFT
1kΩ
REGISTER
SR
CONTROL
121kΩ
MAX5234
MAX5235
77.25kΩ
OUTB
INPUT
REG B
DAC
REG B
DAC B
1kΩ
CS DIN
SCLK
REFB
18 ______________________________________________________________________________________
Single-Supply 3V/5V, Voltage-Output, Dual,
Precision 12-Bit DACs
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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