MAX5251BCAP+_技术文档

19-1172; Rev 0; 12/96

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

__________________Ge n e ra l De s c rip t io n

______________________________Fe a t u re s

The +3V MAX5251 combines four low-power, voltage-

output, 10-bit digital-to-analog converters (DACs) and

four precision output amplifiers in a space-saving, 20-

pin package. In addition to the four voltage outputs,

each amplifier’s negative input is also available to the

user. This facilitates specific gain configurations, remote

sensing, and high output drive capacity, making the

MAX5251 ideal for industrial-process-control applica-

tions. Other features include software shutdown, hard-

ware shutdown lockout, an active-low reset that clears

all registers and DACs to zero, a user-programmable

logic output, and a serial-data output.

♦ Four 10-Bit DACs with Configurable

Output Amplifiers

♦ +3.0V to +3.6V Single-Supply Operation

♦ Low Supply Current: 0.8mA Normal Operation

3µA Shutdown Mode

♦ Available in 20-Pin SSOP

♦ Power-On Reset Clears all Registers and

DACs to Zero

♦ SPI/QSPI and Microwire Compatible

♦ Simultaneous or Independent Control of DACs

via 3-Wire Serial Interface

Each DAC has a double-buffered input organized as an

input register followed by a DAC register. A 16-bit serial

word loa d s d a ta into e a c h inp ut/DAC re g is te r. The

3-wire serial interface is compatible with SPI™/QSPI™

and Microwire™. It allows the input and DAC registers to

be updated independently or simultaneously with a sin-

gle software command. All logic inputs are TTL/CMOS-

logic compatible.

♦ User-Programmable Digital Output

♦ Schmitt-Trigger Digital Inputs for Direct

Optocoupler Interface

♦ 12-Bit Upgrade Available: MAX5253

_________________Ord e rin g In fo rm a t io n

INL

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

________________________Ap p lic a t io n s

Digital Offset and Gain Adjustment

Microprocessor-Controlled Systems

Industrial Process Controls

MAX5251ACPP 0°C to +70°C

MAX5251BCPP 0°C to +70°C

MAX5251ACAP 0°C to +70°C

MAX5251BCAP 0°C to +70°C

20 Plastic DIP

20 SSOP

±1/2

±1

±1/2

±1

20 SSOP

Automatic Test Equipment

Ordering Information continued on last page.

Remote Industrial Controls

Pin Configuration appears at end of data sheet.

Motion Control

_________________________________________________________________________Fu n c t io n a l Dia g ra m

V

DD

DOUT

REFAB

CL

PDL

AGND

DGND

FBA

DECODE

CONTROL

MAX5251

OUTA

INPUT

REGISTER A

DAC

DAC A

REGISTER A

FBB

OUTB

INPUT

REGISTER B

DAC

REGISTER B

16-BIT

SHIFT

REGISTER

DAC B

DAC C

FBC

OUTC

INPUT

REGISTER C

DAC

REGISTER C

FBD

OUTD

SR

CONTROL

INPUT

REGISTER D

DAC

REGISTER D

LOGIC

OUTPUT

DAC D

REFCD

DIN SCLK

CS

UPO

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

ABSOLUTE MAXIMUM RATINGS

V

to AGND............................................................-0.3V to +6V

to DGND ...........................................................-0.3V to +6V

Operating Temperature Ranges

DD

V

MAX5251_C_P ......................................................0°C to +70°C

MAX5251_E_P ...................................................-40°C to +85°C

MAX5251BMJP ................................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

DD

AGND to DGND..................................................................±0.3V

REFAB, REFCD to AGND...........................-0.3V to (V + 0.3V)

OUT_, FB_ to AGND...................................-0.3V to (V + 0.3V)

DD

Digital Inputs to DGND.............................................-0.3V to +6V

DOUT, UPO to DGND ................................-0.3V to (V + 0.3V)

DD

Continuous Current into Any Pin.......................................±20mA

Continuous Power Dissipation (T = +70°C)

A

MAX251

Plastic DIP (derate 8.00mW/°C above +70°C) .................640mW

SSOP (derate 8.00mW/°C above +70°C) ......................640mW

CERDIP (derate 11.11mW/°C above +70°C).................889mW

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, R = 5kΩ, C = 100pF, T = T

DD

to T , unless otherwise

MAX

L

A

MIN

noted. Typical values are at T = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bits

STATIC PERFORMANCE—ANALOG SECTION

Resolution

N

10

MAX5251AC/E

±0.25

±0.5

Integral Nonlinearity

(Note 1)

INL

LSB

MAX5251BC/E

MAX5251BMJP

±1.0

±2.0

±1.0

±6.0

Differential Nonlinearity

Offset Error

DNL

Guaranteed monotonic

LSB

mV

V

OS

Offset-Error Tempco

Gain Error (Note 1)

Gain-Error Tempco

Power-Supply Rejection Ratio

6

ppm/°C

LSB

GE

±2.4

800

1

ppm/°C

µV/V

PSRR

V

DD

= +3.0V to +3.6V

100

MREAFTECRHEINNGCEPEINRPFUOTRMANCE (T = +25°C)

A

Reference Input Range

V

REF

0

V

DD

- 1.4

V

Reference Input Resistance

R

Code dependent, minimum at code 554 hex

10

kΩ

REF

2

_______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

ELECTRICAL CHARACTERISTICS (continued)

(V = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, R = 5kΩ, C = 100pF, T = T

DD

to T , unless otherwise

MAX

L

A

MIN

noted. Typical values are at T = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

MULTIPLYING-MODE PERFORMANCE

Reference -3dB Bandwidth

V

= 0.67Vp-p

650

-84

kHz

dB

REF

Reference Feedthrough

Input code = all 0s, V

= 1.6Vp-p at 1kHz

REF

Signal-to-Noise Plus

SINAD

V

REF

= 1Vp-p at 25kHz, code = full scale

72

dB

Distortion Ratio

DIGITAL INPUTS

Input High Voltage

V

2.0

V

IH

Input Low Voltage

V

IL

0.6

Input Leakage Current

Input Capacitance

I

V

IN

= 0V or V

DD

0.01

8

±1.0

µA

pF

IN

C

IN

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

Output Settling Time

Output Voltage Swing

Current into FB_

V

I

= 2mA

V - 0.5

DD

V

OH

SOURCE

V

OL

I

= 2mA

0.13

0.4

SINK

SR

0.6

12

V/µs

µs

To ±1/2LSB, V

= 1.25V

STEP

Rail-to-rail (Note 2)

0 to V

V

DD

0

0.1

±1

µA

OUT_ Leakage Current

in Shutdown

R

= ∞

0.01

20

µA

µs

L

Start-Up Time Exiting

Shutdown Mode

Digital Feedthrough

5

nV-s

CS = V , DIN = 100kHz

DD

Digital Crosstalk

POWER SUPPLIES

Supply Voltage

V

(Note 3)

(Note 4)

3.0

3.6

0.98

20

V

DD

Supply Current

I

DD

0.82

3

mA

µA

Supply Current in Shutdown

Reference Current in Shutdown

0.01

±1

Note 1: Guaranteed from code 5 to code 1023 in unity-gain configuration.

Note 2: Accuracy is better than 1LSB for V = 6mV to V - 80mV, guaranteed by PSR test at the endpoints.

OUT

DD

Note 3: Remains operational with supply voltage as low as +2.7V.

Note 4: R = ∞, digital inputs at DGND or V

.

DD

L

_______________________________________________________________________________________

3

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

ELECTRICAL CHARACTERISTICS (continued)

(V = +3.0V to +3.6V, AGND = DGND = 0V, REFAB = REFCD = 1.25V, R = 5kΩ, C = 100pF, T = T

DD

to T , unless otherwise

MAX

L

A

MIN

noted. Typical values are at T = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)

A

PARAMETER

SYMBOL

CONDITIONS

MIN

100

40

TYP

MAX

UNITS

ns

TSICMLIKNGClCocHkAPReAriCodTERISTICS (Figure t6)

CP

CH

SCLK Clock Period

t

ns

SCLK Pulse Width High

SCLK Pulse Width Low

t

ns

MAX251

t

40

ns

CL

t

40

ns

CS Fall to SCLK Rise Setup Time

CSS

CSH

t

0

40

0

ns

SCLK Rise to CS Rise Hold Time

DIN Setup Time

t

DS

DIN Hold Time

t

DH

SCLK Rise to DOUT Valid

Propagation Delay

t

C

= 200pF

120

ns

D01

D02

L

SCLK Fall to DOUT Valid

Propagation Delay

t

40

ns

SCLK Rise to CS Fall Delay

CS Rise to SCLK Rise Hold Time

CS Pulse Width High

CS0

CS1

t

100

CSW

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = +3.3V, T = +25°C, unless otherwise noted.)

DD

A

SUPPLY CURRENT

vs. TEMPERATURE

REFERENCE VOLTAGE INPUT

FREQUENCY RESPONSE

INTEGRAL NONLINEARITY

vs. REFERENCE VOLTAGE

0.25

1000

950

900

850

800

750

700

650

600

550

500

0

-4

REFAB SWEPT 0.67Vp-p

R = 5kΩ

0

-0.25

-0.50

-0.75

-1.00

-1.25

L

C = 100pF

L

-8

-12

-16

-20

R = 5kΩ

L

CODE = FFC hex

-55 -40 -20

0

20 40 60 80 100 120

0

500k 1.0M 1.5M 2.0M 2.5M 3.0M

FREQUENCY (Hz)

0

0.5

1.0

1.5

2.0

2.5

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

4

_______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = +3.3V, T = +25°C, unless otherwise noted.)

DD

A

SUPPLY CURRENT

vs. SUPPLY VOLTAGE

TOTAL HARMONIC DISTORTION

PLUS NOISE vs. FREQUENCY

OUTPUT FFT PLOT

1000

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0

-20

DAC CODE = FULL SCALE

REFAB = 1Vp-p

V

REF

= 1kHz, 0.006V TO 1.6V

950

900

850

800

750

700

650

600

550

500

R = 5kΩ

L

R = 5kΩ

L

C = 100pF

L

C = 100pF

L

-40

-60

-80

CODE = FFC hex

-100

2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6

SUPPLY VOLTAGE (V)

0.1

1

10

100

0.5

1.6

2.7

3.8

4.9

6.0

FREQUENCY (kHz)

REFERENCE FEEDTHROUGH

AT 1kHz

FULL-SCALE ERROR

vs. LOAD

0

-0.5

-1.0

-1.5

-2.0

-2.5

0

REFAB INPUT SIGNAL

-20

-40

V

REF

= 1.6Vp-p @ 1kHz

R = 5kΩ

L

C = 100pF

L

-60

OUTA FEEDTHROUGH

-80

-100

0.5

1.2

1.9

2.6

3.3

4.0

0.01

0.1

1

10

100

FREQUENCY (kHz)

LOAD (kΩ)

_______________________________________________________________________________________

5

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(V = +3.3V, V

= 1.25V, R = 5kΩ, C = 100pF, T = +25°C, unless otherwise noted.)

L L

A

REF

DD

MAJOR-CARRY TRANSITION

DIGITAL FEEDTHROUGH (SCLK = 100kHz)

MAX5251-07

MAX5251-08

MAX251

SCLK,

2V/div

CS

5V/div

OUTB,

OUTA,

AC COUPLED

50mV/div

AC COUPLED

10mV/div

10µs/div

2µs/div

CS = PDL = CL = 3.3V, DIN = 0V

DAC A CODE SET TO 800 hex

ANALOG CROSSTALK

DYNAMIC RESPONSE

MAX5251-12

MAX5251-13

OUTA,

500mV/div

GND

OUTB,

AC COUPLED

10mV/div

10µs/div

DAC A CODE SWITCHING FROM 00C hex TO FFC hex

DAC B CODE SET TO 800 hex

SWITCHING FROM CODE 000 hex TO FB4 hex

OUTPUT AMPLIFIER GAIN = +2.6

6

_______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

______________________________________________________________P in De s c rip t io n

1

NAME

AGND

FBA

FUNCTION

Analog Ground

2

DAC A Output Amplifier Feedback

DAC A Output Voltage

3

OUTA

OUTB

4

DAC B Output Voltage

5

6

7

FBB

REFAB

CL

DAC B Output Amplifier Feedback

Reference Voltage Input for DAC A and DAC B

Clears All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low.

8

Chip-Select Input. Active low.

CS

DIN

9

Serial-Data Input

Serial-Clock Input

10

SCLK

11

12

13

14

15

16

17

18

19

20

DGND

DOUT

UPO

Digital Ground

Serial-Data Output

User-Programmable Logic Output

Power-Down Lockout. Active low. Locks out software shutdown if low.

Reference Voltage Input for DAC C and DAC D

DAC C Output Amplifier Feedback

DAC C Output Voltage

PDL

REFCD

FBC

OUTC

OUTD

FBD

DAC D Output Voltage

DAC D Output Amplifier Feedback

Positive Power Supply

V

DD

_______________________________________________________________________________________

7

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

The impedance at each reference input is code depen-

dent, ranging from a low value of 10kΩ when both

DACs connected to the reference have an input code

of 554 hex, to a high value exceeding several giga

ohms (leakage current) with an input code of 000 hex.

Because the input impedance at the reference pins is

c od e d e p e nd e nt, loa d re g ula tion of the re fe re nc e

source is important.

FB_

OUT_

R

2R

S0

2R

S1

2R

D0

2R

D9

2R

The REFAB and REFCD reference inputs have a 10kΩ

guaranteed minimum input impedance. When the two

reference inputs are driven from the same source, the

e ffe c tive minimum imp e d a nc e is 5kΩ. Driving the

REFAB and REFCD pins separately improves reference

accuracy.

MAX251

REF_

AGND

In shutdown mode, the MAX5251’s REFAB and REFCD

inputs enter a high-impedance state with a typical input

leakage current of 0.01µA.

SHOWN FOR ALL 1s ON DAC

The reference input capacitance is also code depen-

dent and typically ranges from 20pF with an input code

of all 0s to 100pF at full scale.

Figure 1. Simplified DAC Circuit Diagram

Ou t p u t Am p lifie rs

All MAX5251 DAC outputs are internally buffered by pre-

cision amplifiers with a typical slew rate of 0.6V/µs.

Access to each output amplifier’s inverting input pro-

vides the user greater flexibility in output gain setting/

signal conditioning (see the Applications Information

section).

_______________De t a ile d De s c rip t io n

The MAX5251 contains four voltage-output digital-to-

analog converters (DACs) that are easily addressed

using a simple 3-wire serial interface. It includes a

16-bit data-in/data-out shift register, and each DAC has

a doubled-buffered input composed of an input register

and a DAC register (see Functional Diagram). In addi-

tion to the four voltage outputs, each amplifier’s nega-

tive input is available to the user.

With a full-scale transition at the MAX5251 output, the

typical settling time to ±1/2LSB is 12µs when loaded

with 5kΩ in parallel with 100pF (loads less than 2kΩ

degrade performance).

The DACs are inverted R-2R ladder networks that con-

vert a digital input (10 data bits plus 2 sub-bits) into

equivalent analog output voltages in proportion to the

applied reference voltage inputs. DACs A and B share

the REFAB reference input, while DACs C and D share

the REFCD reference input. The two reference inputs

allow different full-scale output voltage ranges for each

pair of DACs. Figure 1 shows a simplified circuit dia-

gram of one of the four DACs.

The MAX5251 outp ut a mp lifie r’s outp ut d yna mic

responses and settling performances are shown in the

Typical Operating Characteristics.

P o w e r-Do w n Mo d e

The MAX5251 features a software-programmable shut-

down that reduces supply current to a typical value of

3µA. The power-down lockout pin (PDL) must be high to

enable shutdown mode. Writing 1100XXXXXXXXXXXX as

the input-control word puts the MAX5251 in shutdown

mode (Table 1).

Re fe re n c e In p u t s

The two reference inputs accept positive DC and AC

signals. The voltage at each reference input sets the

full-s c a le outp ut volta g e for its two c orre s p ond ing

DACs . The re fe re nc e inp ut volta g e ra ng e is 0V to

(V

DD

- 1.4V). The output voltages (V

are repre-

OUT_)

sented by a digitally programmable voltage source as:

V

OUT_

= (V x NB / 1024 ) x Gain

REF

where NB is the numeric value of the DAC’s binary

input code (0 to 1023), V is the reference voltage,

REF

and Gain is the externally set voltage gain.

8

_______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

In shutdown mode, the MAX5251 output amplifiers and

the reference inputs enter a high-impedance state. The

serial interface remains active. Data in the input regis-

ters is retained in shutdown, allowing the MAX5251 to

recall the output states prior to entering shutdown. Exit

shutdown mode either by recalling the previous config-

uration or by updating the DACs with new data. When

powering up the device or bringing it out of shutdown,

allow 20µs for the outputs to stabilize.

SCLK

SK

DIN

SO

SI*

MAX5251

MICROWIRE

PORT

DOUT*

S e ria l-In t e rfa c e Co n fig u ra t io n s

The MAX5251’s 3-wire serial interface is compatible

with b oth Mic rowire ™ (Fig ure 2) a nd SPI™/QSPI™

(Figure 3). The serial input word consists of two address

bits and two control bits followed by 10+2 data bits

(MSB first), as shown in Figure 4. The 4-bit address/

control code determines the MAX5251’s response out-

lined in Table 1. The connection between DOUT and

the serial-interface port is not necessary, but may be

used for data echo. Data held in the MAX5251’s shift

register can be shifted out of DOUT and returned to the

microprocessor (µP) for data verification.

CS

I/O

*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5251,

BUT MAY BE USED FOR READBACK PURPOSES.

Figure 2. Connections for Microwire

+3.3V

The MAX5251’s d ig ita l inp uts a re d oub le b uffe re d .

Depending on the command issued through the serial

interface, the input register(s) can be loaded without

affecting the DAC register(s), the DAC register(s) can

be loaded directly, or all four DAC registers can be

up d a te d s imulta ne ous ly from the inp ut re g is te rs

(Table 1).

SS

DOUT*

MISO*

DIN

MOSI

SCK

MAX5251

SPI/QSPI

PORT

SCLK

S e ria l-In t e rfa c e De s c rip t io n

The MAX5251 requires 16 bits of serial data. Table 1

lists the serial-interface programming commands. For

c e rta in c omma nd s , the 10+ 2 d a ta b its a re “d on’t

cares.” Data is sent MSB first and can be sent in two

8-bit packets or one 16-bit word (CS must remain low

until 16 bits are transferred). The serial data is com-

posed of two DAC address bits (A1, A0) and two con-

trol b its (C1, C0), followe d b y the 10+ 2 d a ta b its

D9…D0, S1, S0 (Figure 4). Set both sub-bits (S0, S1) to

zero. The 4-bit address/control code determines:

CS

I/O

CPOL = 0, CPHA = 0

*THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX5251,

BUT MAY BE USED FOR READBACK PURPOSES.

Figure 3. Connections for SPI/QSPI

• The register(s) to be updated

• The clock edge on which data is to be clocked out

MSB ..................................................................................LSB

16 Bits of Serial Data

via the serial-data output (DOUT)

• The state of the user-programmable logic output

(UPO)

Address

Bits

Control

Bits

Data Bits

MSB.................................LSB

• If the part is to go into shutdown mode (assuming

PDL is high)

A1 A0 C1 C0 D9 ...................................D0 S1 S0

• How the part is configured when exiting shutdown

4 Address/

10+2 Data Bits

Control Bits

mode.

Figure 4. Serial-Data Format

_______________________________________________________________________________________

9

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

Table 1. Serial-Interface Programming Commands

16-BIT SERIAL WORD

FUNCTION

D9.................D0

MSB.............LSB

A1 A0 C1 C0

S1 S0

0

1

0

1

0

1

0

1

10-bit DAC data

0

Load input register A; DAC registers unchanged.

Load input register B; DAC registers unchanged.

Load input register C; DAC registers unchanged.

Load input register D; DAC registers unchanged.

MAX251

0

1

0

1

0

1

10-bit DAC data

0

Load input register A; all DAC registers updated.

Load input register B; all DAC registers updated.

Load input register C; all DAC registers updated.

Load input register D; all DAC registers updated.

Update all DAC registers from their respective input registers (also exit

shutdown mode).

0

1

0

XXXXXXXXXX

X

1

0

1

0

1

0

1

0

10-bit DAC data

XXXXXXXXXX

0

Load all DAC registers from shift register (also exit shutdown mode).

Enter shutdown mode (provided PDL = 1).

UPO goes low (default).

X

UPO goes high.

No operation (NOP) to DAC registers

Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers

updated.

1

0

1

0

XXXXXXXXXX

X

Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers

updated (default).

“X” = Don’t care

Figure 5 shows the serial-interface timing requirements.

The chip-select pin (CS) must be low to enable the

DAC’s serial interface. When CS is high, the interface

control circuitry is disabled. CS must go low at least

change the clock edge on which serial data is shifted

out of DOUT also loads data from all input registers to

their respective DAC registers.

S e ria l-Da t a Ou t p u t (DOUT)

The serial-data output, DOUT, is the internal shift regis-

ter’s output. The MAX5251 can be programmed so that

data is clocked out of DOUT on SCLK’s rising edge

(Mode 1) or falling edge (Mode 0). In Mode 0, output

data at DOUT lags input data at DIN by 16.5 clock

c yc le s , ma inta ining c omp a tib ility with Mic rowire ,

SPI/QSPI, and other serial interfaces. In Mode 1, output

data lags input data by 16 clock cycles. On power-up,

DOUT defaults to Mode 0 timing.

t

before the rising serial clock (SCLK) edge to prop-

CSS

e rly c loc k in the firs t b it. Whe n CS is low, d a ta is

clocked into the internal shift register via the serial-data

input pin (DIN) on SCLK’s rising edge. The maximum

guaranteed clock frequency is 10MHz. Data is latched

into the appropriate MAX5251 input/DAC registers on

CS’s rising edge.

The programming command Load-All-DACs-From-Shift-

Register allows all input and DAC registers to be simul-

taneously loaded with the same digital code from the

input shift register. The no operation (NOP) command

leaves the register contents unaffected and is useful

when the MAX5251 is configured in a daisy chain (see

the Daisy Chaining Devices section). The command to

Us e r-P ro g ra m m a b le Lo g ic Ou t p u t (UP O)

The user-programmable logic output, UPO, allows an

external device to be controlled via the MAX5251 serial

interface (Table 1).

10 ______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

CS

COMMAND

EXECUTED

SCLK

DIN

1

8

9

16

A0

D6

DATA PACKET (N)

D6

D4

C1 C0 D9 D8 D7

D3 D2 D1 D0 S1 S0

A1

D5

DOUT

(MODE 0)

A0 C1

D9 D8 D7

D3

D1 D0 S1

C0

D5

D2

S0 A1

MSB FROM

PREVIOUS WRITE

DATA PACKET (N)

A1

DATA PACKET (N-1)

DOUT

(MODE 1)

A0

D6

D5

D4

C1

D9 D8 D7

D3

D1 D0 S1

A1

C0

D2

S0

MSB FROM

PREVIOUS WRITE

DATA PACKET (N)

DATA PACKET (N-1)

Figure 5. Serial-Interface Timing Diagram

t

CSW

CS

t

CP

t

CSH

t

CH

CSS

t

CL

CSO

t

CS1

SCLK

t

DS

t

DH

DIN

t

DO2

t

DO1

DOUT

Figure 6. Detailed Serial-Interface Timing Diagram

Since the MAX5251’s DOUT pin has an internal active

pull-up, the DOUT sink/source capability determines

the time required to discharge/charge a capacitive

P o w e r-Do w n Lo c k o u t (PDL)

The power-down lockout pin PDL disables software

shutdown when low. When in shutdown, transitioning

PDL from high to low wakes up the part with the output

set to the state prior to shutdown. PDL could also be

used to wake up the device asynchronously.

load. Refer to the serial-data-out V

and V specifi-

OH

OL

cations in the Electrical Characteristics.

Figure 8 shows an alternate method of connecting sev-

eral MAX5251s. In this configuration, the data bus is

common to all devices; data is not shifted through a

daisy chain. More I/O lines are required in this configu-

ration because a dedicated chip-select input (CS) is

required for each IC.

Da is y Ch a in in g De vic e s

Any number of MAX5251s can be daisy chained by

connecting the DOUT pin of one device to the DIN pin

of the following device in the chain (Figure 7).

______________________________________________________________________________________ 11

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX5251

SCLK

DIN

MAX251

DOUT

DIN

CS

DIN

CS

DIN

CS

TO OTHER

SERIAL DEVICES

Figure 7. Daisy-Chaining MAX5251s

DIN

SCLK

CS1

CS2

TO OTHER

SERIAL DEVICES

CS3

CS

MAX5251

SCLK

DIN

SCLK

DIN

Figure 8. Multiple MAX5251s Sharing a Common DIN Line

12 ______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

Bip o la r Ou t p u t

The MAX5251 outputs can be configured for bipolar

operation using Figure 11’s circuit:

__________Ap p lic a t io n s In fo rm a t io n

Un ip o la r Ou t p u t

For a unipolar output, the output voltages and the refer-

ence inputs have the same polarity. Figure 9 shows the

MAX5251 unipolar output circuit, which is also the typi-

cal operating circuit. Table 2 lists the unipolar output

codes.

V

OUT

= V

[(2NB / 1024) - 1]

REF

where NB is the numeric value of the DAC’s binary

input code. Table 3 shows digital codes (offset binary)

a nd c orre s p ond ing outp ut volta g e s for Fig ure 11’s

circuit.

For rail-to-rail outputs, see Figure 10. This circuit shows

the MAX5251 with the output amplifiers configured with

a closed-loop gain of +2.6 to provide 0V to 3.25V full-

scale range when a 1.25V reference is used.

+3.3V

REFERENCE INPUTS

MAX5251

Table 2. Unipolar Code Table

V

DD

REFAB

REFCD

FBA

DAC CONTENTS

ANALOG OUTPUT

DAC A

DAC B

MSB

LSB

OUTA

FBB

1023

+V_REF( ——— )

1024

1 1 1 1

1 1 1 1 1 1 (0 0 )

513

+V_REF( ——— )

1024

1000

1 0 0 0

0 1 1 1

0000 01(00)

0 0 0 0 0 0 (0 0 )

1 1 1 1 1 1 (0 0 )

OUTB

FBC

512

+VREF

+V_REF( ——— ) = ————

1024

2

DAC C

DAC D

OUTC

FBD

511

+V_REF( ——— )

1024

1

+V_REF( ——— )

1024

0 0 0 0

0 0 0 0 0 1 (0 0 )

0 0 0 0 0 0 (0 0 )

OUTD

0V

AGND

DGND

Table 3. Bipolar Code Table

Figure 9. Unipolar Output Circuit

DAC CONTENTS

ANALOG OUTPUT

MSB

LSB

511

+V_REF( ——— )

512

1 1 1 1

1 1 1 1 1 1 (0 0 )

1

+V_REF( ——— )

512

1000

1 0 0 0

0 1 1 1

0000 01(00)

0 0 0 0 0 0 (0 0 )

1 1 1 1 1 1 (0 0 )

0V

1

-V_REF( ——— )

512

511

-V_REF( ——— )

512

0 0 0 0

0 0 0 0 0 1 (0 0 )

0 0 0 0 0 0 (0 0 )

512

-V_REF( ——— ) = -V

REF

512

( ) Sub-bits

______________________________________________________________________________________ 13

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

Us in g a n AC Re fe re n c e

In applications where the reference has AC signal com-

ponents, the MAX5251 has multiplying capability within

the reference input range specifications. Figure 12

shows a technique for applying a sine-wave signal to

the reference input where the AC signal is offset before

being applied to REFAB/REFCD. The reference voltage

must never be more negative than DGND.

+3.3V

REFERENCE INPUTS

REFAB

MAX5251

10k

V

REFCD

FBA

DD

16k

DAC A

DAC B

DAC C

DAC D

OUTA

10k

FBB

The MAX5251’s total harmonic distortion plus noise

(THD + N) is typically less than -72dB (full-scale code),

given a 1Vp-p signal swing and input frequencies up to

25kHz. The typ ic a l -3d B fre q ue nc y is 650kHz, a s

shown in the Typical Operating Characteristics graphs.

MAX251

16k

OUTB

FBC

10k

16k

Dig it a lly P ro g ra m m a b le Cu rre n t S o u rc e

The c irc uit of Fig ure 13 p la c e s a n NPN tra ns is tor

(2N3904 or similar) within the op-amp feedback loop to

implement a digitally programmable, unidirectional cur-

rent source. This circuit can be used to drive 4–20mA

current loops, which are commonly used in industrial-

control applications. The output current is calculated

with the following equation:

OUTC

FBD

10k

16k

OUTD

AGND

DGND

V

= V

= 1.25V

REFAB REFCD

I

= (V

/ R) x (NB / 1024)

OUT

REF

16k

10k

A = 1 +

V

= 2.6

where NB is the numeric value of the DAC’s binary

inp ut c od e a nd R is the s e ns e re s is tor s hown in

Figure 13.

Figure 10. Unipolar Rail-to-Rail Output Circuit

+3.3V

AC

REFERENCE

INPUT

26k

1/2 MAX492

REF_

R1

R2

REF_

10k

V

DD

+3.3V

500mVp-p

FB_

V

OUT

DAC

DAC_

OUT_

-3.3V

MAX5251

AGND

R1 = R2 = 10kΩ ± 0.1%

MAX5251

DGND

Figure 11. Bipolar Output Circuit

Figure 12. AC Reference Input Circuit

14 ______________________________________________________________________________________

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

MAX251

__________________P in Co n fig u ra t io n

REF_

TOP VIEW

V

L

MAX5251

I

OUT

DAC_

1

2

3

4

5

6

7

8

9

AGND

FBA

V

DD

20

19

18

17

OUT_

FB_

FBD

2N3904

OUTA

OUTB

FBB

OUTD

OUTC

MAX5251

16 FBC

15

R

REFAB

CL

REFCD

14 PDL

13

CS

UPO

DIN

12 DOUT

11 DGND

Figure 13. Digitally Programmable Current Source

SCLK 10

P o w e r-S u p p ly Co n s id e ra t io n s

DIP/SSOP

On power-up, all input and DAC registers are cleared

(set to zero code) and DOUT is in Mode 0 (serial data

is shifted out of DOUT on the clock’s falling edge).

For rated MAX5251 performance, limit REFAB/REFCD

to less than 1.4V below V . Bypass V

with a 4.7µF

DD

capacitor in parallel with a 0.1µF capacitor to AGND.

Use short lead lengths and place the bypass capaci-

tors as close to the supply pins as possible.

Gro u n d in g a n d La yo u t Co n s id e ra t io n s

Digital or AC transient signals between AGND and

DGND c a n c re a te nois e a t the a na log outp uts . Tie

AGND and DGND together at the DAC, then tie this

point to the highest-quality ground available.

Good printed circuit board ground layout minimizes

crosstalk between DAC outputs, reference inputs, and

digital inputs. Reduce crosstalk by keeping analog

lines away from digital lines. Wire-wrapped boards are

not recommended.

______________________________________________________________________________________ 15

+3 V, Qu a d , 1 0 -Bit Vo lt a g e -Ou t p u t DAC

w it h S e ria l In t e rfa c e

_Ord e rin g In fo rm a t io n (c o n t in u e d )

___________________Ch ip In fo rm a t io n

TRANSISTOR COUNT: 4337

INL

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

MAX5251AEPP -40°C to +85°C 20 Plastic DIP

MAX5251BEPP -40°C to +85°C 20 Plastic DIP

MAX5251AEAP -40°C to +85°C 20 SSOP

MAX5251BEAP -40°C to +85°C 20 SSOP

MAX5251BMJP -55°C to +125°C 20 CERDIP*

±1/2

±1

±1/2

±1

MAX251

±2

*Contact factory for availability and processing to MIL-STD-883.

________________________________________________________P a c k a g e In fo rm a t io n

INCHES

MILLIMETERS

DIM

MIN

0.068

MAX

0.078

0.008

0.015

0.008

MIN

1.73

0.05

0.25

0.09

MAX

1.99

0.21

0.38

0.20

A

A1 0.002

B

C

D

E

e

0.010

0.004

SEE VARIATIONS

α

0.205

0.209

5.20

5.38

E

H

0.0256 BSC

0.65 BSC

H

L

0.301

0.311

0.037

8˚

7.65

0.63

0˚

7.90

0.95

8˚

0.025

0˚

C

α

L

INCHES

MILLIMETERS

DIM PINS

MAX

6.33

MIN MAX MIN

0.239 0.249 6.07

0.278 0.289 7.07

0.317 0.328 8.07

0.397 0.407 10.07

e

D

14

16

20

24

28

6.33

SSOP

7.33

SHRINK

A

8.33

SMALL-OUTLINE

PACKAGE

10.33

21-0056A

B

A1

D

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX5251BCAP+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	D/A Converter, 4 Func, Serial Input Loading, 12us Settling Time, PDSO20, SSOP-20
文件：	总16页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX5251BCAP+ [MAXIM]

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MAX5253ACAP+T