MAX525ACPP [MAXIM]
Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial Interface; 低功耗，四通道，12位电压输出DAC ，串行接口
| 型号： | MAX525ACPP |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Low-Power, Quad, 12-Bit Voltage-Output DAC with Serial Interface |
| 文件： | 总16页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1098; Rev 1; 12/96
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
__________________Ge n e ra l De s c rip t io n
______________________________Fe a t u re s
The MAX525 combines four low-power, voltage-output,
12-bit digital-to-analog converters (DACs) and four pre-
cision output amplifiers in a space-saving, 20-pin pack-
a g e . In a d d ition to the four volta g e outp uts , e a c h
amplifier’s negative input is also available to the user.
This facilitates specific gain configurations, remote
sensing, and high output drive capacity, making the
MAX525 ideal for industrial-process-control applica-
tions. Other features include software shutdown, hard-
ware shutdown lockout, an active-low reset which clears
all registers and DACs to zero, a user-programmable
logic output, and a serial-data output.
♦ Four 12-Bit DACs with Configurable
Output Amplifiers
♦ +5V Single-Supply Operation
♦ Low Supply Current: 0.85mA Normal Operation
10µA Shutdown Mode
♦ Available in 20-Pin SSOP
♦ Power-On Reset Clears all Registers and
DACs to Zero
♦ Capable of Recalling Last State Prior to Shutdown
♦ SPI/QSPI and Microwire Compatible
Each DAC has a double-buffered input organized as an
input register followed by a DAC register. A 16-bit serial
word loads data into each input/DAC register. The serial
inte rfa c e is c omp a tib le with SPI™/QSPI™ a nd
Microwire™. It allows the input and DAC registers to be
updated independently or simultaneously with a single
software command. The DAC registers can be simulta-
neously updated via the 3-wire serial interface. All logic
inputs are TTL/CMOS-logic compatible.
♦ Simultaneous or Independent Control of DACs
via 3-Wire Serial Interface
♦ User-Programmable Digital Output
_________________Ord e rin g In fo rm a t io n
INL
(LSB)
PART
TEMP. RANGE PIN-PACKAGE
MAX525ACPP
MAX525BCPP
MAX525ACAP
MAX525BCAP
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
20 Plastic DIP
20 Plastic DIP
20 SSOP
±1/2
±1
________________________Ap p lic a t io n s
Industrial Process Controls
±1/2
±1
Automatic Test Equipment
20 SSOP
Digital Offset and Gain Adjustment
Motion Control
Ordering Information continued on last page.
Remote Industrial Controls
Pin Configuration appears at end of data sheet.
Microprocessor-Controlled Systems
_________________________________________________________________________Fu n c t io n a l Dia g ra m
V
DD
DOUT
REFAB
CL
PDL
AGND
DGND
FBA
DECODE
CONTROL
MAX525
OUTA
INPUT
REGISTER A
DAC
DAC A
REGISTER A
FBB
OUTB
INPUT
REGISTER B
DAC
REGISTER B
16-BIT
SHIFT
REGISTER
DAC B
DAC C
FBC
OUTC
INPUT
REGISTER C
DAC
REGISTER C
FBD
OUTD
SR
CONTROL
INPUT
REGISTER D
DAC
REGISTER D
LOGIC
OUTPUT
DAC D
REFCD
DIN SCLK
CS
UPO
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
V
to AGND............................................................-0.3V to +6V
to DGND ...........................................................-0.3V to +6V
Operating Temperature Ranges
DD
V
MAX525_C_P ........................................................0°C to +70°C
MAX525_E_P .....................................................-40°C to +85°C
MAX525_MJP ..................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
AGND to DGND..................................................................±0.3V
REFAB, REFCD to AGND...........................-0.3V to (V + 0.3V)
OUT_, FB_ to AGND...................................-0.3V to (V + 0.3V)
DD
DD
Digital Inputs to DGND.............................................-0.3V to +6V
DOUT, UPO to DGND ................................-0.3V to (V + 0.3V)
DD
MAX25
Continuous Current into Any Pin.......................................±20mA
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 8.00mW/°C above +70°C) .................640mW
SSOP (derate 8.00mW/°C above +70°C) ......................640mW
CERDIP (derate 11.11mW/°C above +70°C).................889mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF, T = T
to T , unless otherwise
MAX
DD
L
L
A
MIN
noted. Typical values are at T = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
12
Bits
MAX525A
MAX525B
±0.25
±0.5
±1.0
±1.0
±6.0
Integral Nonlinearity
(Note 1)
INL
DNL
LSB
Differential Nonlinearity
Offset Error
Guaranteed monotonic
LSB
mV
V
OS
Offset-Error Tempco
Gain Error (Note 1)
Gain-Error Tempco
Power-Supply Rejection Ratio
6
ppm/°C
LSB
GE
-0.8
1
±2.0
600
ppm/°C
µV/V
PSRR
4.5V ≤ V ≤ 5.5V
100
DD
MATCHING PERFORMANCE (T = +25°C)
A
Gain Error
GE
-0.8
±1.0
±2.0
±6.0
±1.0
LSB
mV
Offset Error
Integral Nonlinearity
REFERENCE INPUT
Reference Input Range
Reference Input Resistance
Reference Current in Shutdown
INL
±0.35
LSB
V
REF
0
V
- 1.4
±1
V
DD
R
Code-dependent, minimum at code 555 hex
10
kΩ
µA
REF
0.01
2
_______________________________________________________________________________________
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF, T = T
to T , unless otherwise
MAX
DD
L
L
A
MIN
noted. Typical values are at T = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MULTIPLYING-MODE PERFORMANCE
Reference -3dB Bandwidth
V
= 0.67Vp-p
650
-84
kHz
dB
REF
Reference Feedthrough
Input code = all 0s, V
= 3.6Vp-p at 1kHz
REF
Signal-to-Noise Plus
SINAD
V
REF
= 1Vp-p at 25kHz
72
dB
Distortion Ratio
DIGITAL INPUTS
Input High Voltage
V
2.4
V
V
IH
Input Low Voltage
V
IL
0.8
Input Leakage Current
Input Capacitance
I
V
IN
= 0V or V
DD
0.01
8
±1.0
µA
pF
IN
C
IN
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
Output Voltage Swing
Current into FB_
V
I
= 2mA
V - 0.5
DD
V
V
OH
SOURCE
V
OL
I
= 2mA
0.13
0.4
SINK
SR
0.6
12
V/µs
µs
To ±1/2LSB, V
= 2.5V
STEP
Rail to rail (Note 2)
0 to V
V
DD
0
0.1
±1
µA
OUT_ Leakage Current
in Shutdown
R
= ∞
0.01
µA
µs
L
Start-Up Time Exiting
Shutdown Mode
15
Digital Feedthrough
5
5
nV-s
nV-s
CS = V , DIN = 100kHz
DD
Digital Crosstalk
POWER SUPPLIES
Supply Voltage
V
4.5
5.5
0.98
20
V
DD
Supply Current
I
DD
(Note 3)
(Note 3)
0.85
10
mA
µA
µA
Supply Current in Shutdown
Reference Current in Shutdown
0.01
±1
Note 1: Guaranteed from code 11 to code 4095 in unity-gain configuration.
Note 2: Accuracy is better than 1.0LSB for V = 6mV to V - 60mV, guaranteed by PSR test on end points.
OUT
DD
Note 3: R = ∞, digital inputs at DGND or V
.
L
DD
_______________________________________________________________________________________
3
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V ±10%, AGND = DGND = 0V, REFAB = REFCD = 2.5V, R = 5kΩ, C = 100pF, T = T
to T , unless otherwise
MAX
DD
L
L
A
MIN
noted. Typical values are at T = +25°C. Output buffer connected in unity-gain configuration (Figure 9).)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
t
100
40
ns
ns
ns
ns
CP
MAX25
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
40
CL
t
40
CS Fall to SCLK Rise Setup Time
CSS
CSH
t
0
40
0
ns
ns
ns
SCLK Rise to CS Rise Hold Time
DIN Setup Time
t
DS
DIN Hold Time
t
DH
SCLK Rise to DOUT Valid
Propagation Delay
t
C
C
= 200pF
= 200pF
80
ns
ns
D01
D02
LOAD
LOAD
80
SCLK Fall to DOUT Valid
Propagation Delay
t
t
40
40
ns
ns
ns
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold Time
CS Pulse Width High
CS0
CS1
t
t
100
CSW
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, T = +25°C, unless otherwise noted.)
DD
A
SUPPLY CURRENT
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
0.3
1000
950
900
850
800
750
700
650
600
550
500
0
-4
REFAB SWEPT 0.67Vp-p
0.2
0.1
R = 5kΩ
L
C = 100pF
L
0
-8
-0.1
-0.2
-0.3
-0.4
-0.5
-12
-16
-20
CODE = FFF hex
R = 5kΩ
L
-55 -40 -20
0
20 40 60 80 100 120
0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4
REFERENCE VOLTAGE (V)
0
500k 1M 1.5M 2M 2.5M 3M
FREQUENCY (Hz)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, T = +25°C, unless otherwise noted.)
DD
A
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT FFT PLOT
0
-20
0.50
1000
DAC CODE = ALL 1s
REFAB = 1Vp-p
V
REF
= 1kHz, 0.006V TO 3.6V
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
950
900
850
800
750
700
650
600
R = 5kΩ
L
R = 5kΩ
L
C = 100pF
L
C = 100pF
L
-40
-60
-80
CODE = FFF hex
-100
0.5
1.6
2.7
3.8
4.9
6.0
100
1
10
4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
SUPPLY VOLTAGE (V)
FREQUENCY (kHz)
FREQUENCY (kHz)
FULL-SCALE ERROR
vs. LOAD
REFERENCE FEEDTHROUGH
AT 1kHz
0
0
-20
-40
-60
-80
REFAB INPUT SIGNAL
-1
-2
-3
-4
V
REF
= 3.6Vp-p @ 1kHz
R = 5kΩ
L
C = 100pF
L
OUTA FEEDTHROUGH
-5
-100
0.5
0.01
0.1
1
10
100
1.2
1.9
2.6
3.3
4.0
LOAD (kΩ)
FREQUENCY (kHz)
_______________________________________________________________________________________
5
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, T = +25°C, unless otherwise noted.)
DD
A
MAJOR-CARRY TRANSITION
DIGITAL FEEDTHROUGH (SCLK = 100kHz)
MAX25
SCLK,
2V/div
CS
5V/div
OUTB,
OUTA,
AC COUPLED
100mV/div
AC COUPLED
10mV/div
10µs/div
2µs/div
V
REF
= 2.5V, R = 5kΩ, C = 100pF
V
REF
= 2.5V, R = 5kΩ, C = 100pF
L
L
L
L
CS = PDL = CL = 5V, DIN = 0V
DAC A CODE SET TO 800 hex
ANALOG CROSSTALK
DYNAMIC RESPONSE
OUTA,
1V/div
OUTA,
1V/div
GND
OUTB,
AC COUPLED
10mV/div
10µs/div
10µs/div
V
REF
= 2.5V, R = 5kΩ, C = 100pF
L L
V
REF
= 2.5V, R = 5kΩ, C = 100pF
L
L
DAC A CODE SWITCHING FROM 00B hex TO FFF hex
DAC B CODE SET TO 800 hex
SWITCHING FROM CODE 000 hex TO FB4 hex
OUTPUT AMPLIFIER GAIN = +2
6
_______________________________________________________________________________________
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
______________________________________________________________P in De s c rip t io n
PIN
1
NAME
AGND
FBA
FUNCTION
Analog Ground
2
DAC A Output Amplifier Feedback
DAC A Output Voltage
3
OUTA
OUTB
4
DAC B Output Voltage
5
6
7
FBB
REFAB
CL
DAC B Output Amplifier Feedback
Reference Voltage Input for DAC A and DAC B
Clear All DACs and Registers. Resets all outputs (OUT_, UPO, DOUT) to 0, active low.
8
Chip-Select Input. Active low.
CS
DIN
9
Serial-Data Input
Serial Clock Input
10
SCLK
11
12
13
14
15
16
17
18
19
20
DGND
DOUT
UPO
Digital Ground
Serial-Data Output
User-Programmable Logic Output
Power-Down Lockout. Active low. Locks out software shutdown if low.
Reference Voltage Input for DAC C and DAC D
DAC C Output Amplifier Feedback
DAC C Output Voltage
PDL
REFCD
FBC
OUTC
OUTD
FBD
DAC D Output Voltage
DAC D Output Amplifier Feedback
Positive Power Supply
V
DD
_______________________________________________________________________________________
7
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
The impedance at each reference input is code-depen-
dent, ranging from a low value of 10kΩ when both
DACs connected to the reference have an input code
of 555 hex, to a high value exceeding several gigohms
FB_
(le a ka g e c urre nts ) with a n inp ut c od e of 000 he x.
OUT_
R
R
R
Because the input impedance at the reference pins is
c od e -d e p e nd e nt, loa d re g ula tion of the re fe re nc e
source is important.
2R
D0
2R
D9
2R
D10
2R
D11
2R
MAX25
The REFAB and REFCD reference inputs have a 10kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance is 5kΩ. A voltage refer-
ence with a load regulation of 6ppm/mA, such as the
MAX873, would typ ic a lly d e via te b y 0.025LSB
(0.061LSB worst case) when driving both MAX525 ref-
e re nc e inp uts s imulta ne ous ly a t 2.5V. Driving the
REFAB and REFCD pins separately improves reference
accuracy.
REF_
AGND
SHOWN FOR ALL 1s ON DAC
In shutdown mode, the MAX525’s REFAB and REFCD
inputs enter a high-impedance state with a typical input
leakage current of 0.01µA.
Figure 1. Simplified DAC Circuit Diagram
_______________De t a ile d De s c rip t io n
The reference input capacitance is also code depen-
dent and typically ranges from 20pF with an input code
of all 0s to 100pF with an input code of all 1s.
The MAX525 contains four 12-bit, voltage-output digi-
ta l-to-a na log c onve rte rs (DACs ) tha t a re e a s ily
addressed using a simple 3-wire serial interface. It
includes a 16-bit data-in/data-out shift register, and
each DAC has a doubled-buffered input composed of
an input register and a DAC register (see Functional
Diagram). In addition to the four voltage outputs, each
amplifier’s negative input is available to the user.
Ou t p u t Am p lifie rs
All MAX525 DAC outputs are internally buffered by preci-
sion amplifiers with a typical slew rate of 0.6V/µs. Access
to the inverting input of each output amplifier provides
the us e r g re a te r fle xib ility in outp ut g a in s e tting /
signal conditioning (see the Applications Information sec-
tion).
The DACs are inverted R-2R ladder networks that con-
vert 12-bit digital inputs into equivalent analog output
voltages in proportion to the applied reference voltage
inputs. DACs A and B share the REFAB reference input,
while DACs C and D share the REFCD reference input.
The two reference inputs allow different full-scale output
voltage ranges for each pair of DACs. Figure 1 shows a
simplified circuit diagram of one of the four DACs.
With a full-scale transition at the MAX525 output, the
typical settling time to ±1/2LSB is 12µs when loaded
with 5kΩ in parallel with 100pF (loads less than 2kΩ
degrade performance).
The MAX525 output amplifier’s output dynamic respons-
es and settling performances are shown in the Typical
Operating Characteristics.
Re fe re n c e In p u t s
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets the
full-s c a le outp ut volta g e for its two c orre s p ond ing
P o w e r-Do w n Mo d e
The MAX525 features a software-programmable shut-
down that reduces supply current to a typical value of
10µA. The power-down lockout (PDL) pin must be high to
enable the shutdown mode. Writing 1100XXXXXXXXXXXX
as the input-control word puts the MAX525 in power-
down mode (Table 1).
DACs. The reference input voltage range is 0V to (V
DD
- 1.4V). The output voltages (V
are represented by
OUT_)
a digitally programmable voltage source as:
V
OUT_
= (V x NB / 4096) x Gain
REF
where NB is the numeric value of the DAC’s binary
input code (0 to 4095), V is the reference voltage,
REF
and Gain is the externally set voltage gain.
8
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Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
In power-down mode, the MAX525 output amplifiers
and the reference inputs enter a high-impedance state.
SCLK
SK
The serial interface remains active. Data in the input
re g is te rs is re ta ine d in p owe r-d own, a llowing the
MAX525 to recall the output states prior to entering
shutdown. Start up from power-down either by recalling
the previous configuration or by updating the DACs
with new data. When powering up the device or bring-
ing it out of shutdown, allow 15µs for the outputs to sta-
bilize.
DIN
SO
SI*
MAX525
MICROWIRE
PORT
DOUT*
CS
I/O
S e ria l-In t e rfa c e Co n fig u ra t io n s
The MAX525’s 3-wire serial interface is compatible
with b oth Mic rowire ™ (Fig ure 2) a nd SPI™/QSPI™
(Figure 3). The serial input word consists of two address
b its a nd two c ontrol b its followe d b y 12 d a ta b its
(MSB first), as shown in Figure 4. The 4-bit address/
control code determines the MAX525’s response out-
lined in Table 1. The connection between DOUT and
the serial-interface port is not necessary, but may be
used for data echo. Data held in the MAX525’s shift
register can be shifted out of DOUT and returned to the
microprocessor (µP) for data verification.
*THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX525,
BUT MAY BE USED FOR READBACK PURPOSES.
Figure 2. Connections for Microwire
+5V
The MAX525’s d ig ita l inp uts a re d oub le b uffe re d .
Depending on the command issued through the serial
interface, the input register(s) can be loaded without
affecting the DAC register(s), the DAC register(s) can
be loaded directly, or all four DAC registers can be
up d a te d s imulta ne ous ly from the inp ut re g is te rs
(Table 1).
SS
DOUT*
MISO*
DIN
MOSI
SCK
MAX525
SPI/QSPI
PORT
SCLK
S e ria l-In t e rfa c e De s c rip t io n
The MAX525 requires 16 bits of serial data. Table 1 lists
the serial-interface programming commands. For cer-
tain commands, the 12 data bits are “don’t cares.” Data
is sent MSB first and can be sent in two 8-bit packets or
one 16-bit word (CS must remain low until 16 bits are
transferred). The serial data is composed of two DAC
address bits (A1, A0) and two control bits (C1, C0),
followed by the 12 data bits D11…D0 (Figure 4). The
4-bit address/control code determines:
CS
I/O
CPOL = 0, CPHA = 0
*THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX525,
BUT MAY BE USED FOR READBACK PURPOSES.
Figure 3. Connections for SPI/QSPI
• The register(s) to be updated
• The clock edge on which data is to be clocked out
MSB ..................................................................................LSB
16 Bits of Serial Data
via the serial-data output (DOUT)
• The state of the user-programmable logic output
(UPO)
Address
Bits
Control
Bits
Data Bits
MSB.............................................LSB
• If the part is to go into shutdown mode (assuming
PDL is high)
A1 A0 C1 C0 D11................................................D0
• How the part is configured when coming out of shut-
4 Address/
12 Data Bits
Control Bits
down mode.
Figure 4. Serial-Data Format
_______________________________________________________________________________________
9
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
Table 1. Serial-Interface Programming Commands
16-BITSERIAL WORD
FUNCTION
D11.................D0
MSB LSB
A1
A0
C1
C0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
Load input register A; DAC registers unchanged.
Load input register B; DAC registers unchanged.
Load input register C; DAC registers unchanged.
Load input register D; DAC registers unchanged.
MAX25
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
Load input register A; all DAC registers updated.
Load input register B; all DAC registers updated.
Load input register C; all DAC registers updated.
Load input register D; all DAC registers updated.
0
1
1
0
0
0
1
0
1
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
XXXXXXXXXXXX
12-bit DAC data
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
Update all DAC registers from their respective input registers (start-up).
Load all DAC registers from shift register (start-up).
Shutdown (provided PDL = 1)
UPO goes low (default)
UPO goes high
No operation (NOP) to DAC registers
Mode 1, DOUT clocked out on SCLK’s rising edge. All DAC registers
updated.
1
1
1
0
1
1
0
0
XXXXXXXXXXXX
XXXXXXXXXXXX
Mode 0, DOUT clocked out on SCLK’s falling edge. All DAC registers
updated (default).
“X” = Don’t care
Figure 5 shows the serial-interface timing requirements.
The chip-select pin (CS) must be low to enable the
DAC’s serial interface. When CS is high, the interface
control circuitry is disabled. CS must go low at least
change the clock edge on which serial data is shifted
out of DOUT also loads data from all input registers to
their respective DAC registers.
S e ria l-Da t a Ou t p u t (DOUT)
The serial-data output, DOUT, is the internal shift regis-
ter’s output. The MAX525 can be programmed so that
data is clocked out of DOUT on SCLK’s rising edge
(Mode 1) or falling edge (Mode 0). In Mode 0, output
data at DOUT lags input data at DIN by 16.5 clock
c yc le s , ma inta ining c omp a tib ility with Mic rowire ™,
SPI™/QSPI™, and other serial interfaces. In Mode 1,
output data lags input data by 16 clock cycles. On
power-up, DOUT defaults to Mode 0 timing.
t
before the rising serial clock (SCLK) edge to prop-
CSS
e rly c loc k in the firs t b it. Whe n CS is low, d a ta is
clocked into the internal shift register via the serial-data
input pin (DIN) on SCLK’s rising edge. The maximum
guaranteed clock frequency is 10MHz. Data is latched
into the appropriate MAX525 input/DAC registers on
CS’s rising edge.
The programming command Load-All-DACs-From-Shift-
Register allows all input and DAC registers to be simul-
taneously loaded with the same digital code from the
input shift register. The no operation (NOP) command
leaves the register contents unaffected and is useful
when the MAX525 is configured in a daisy chain (see
the Daisy Chaining Devices section). The command to
Us e r-P ro g ra m m a b le Lo g ic Ou t p u t (UP O)
The user-programmable logic output, UPO, allows an
external device to be controlled via the MAX525 serial
interface (Table 1).
10 ______________________________________________________________________________________
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
CS
COMMAND
EXECUTED
SCLK
1
8
9
16
A0
D8
DATA PACKET (N)
D8
D6
D6
DIN
A1
A1
C1 C0 D11 D10 D9
D7
D5 D4 D3 D2 D1 D0
DOUT
(MODE 0)
A0 C1
D11 D10 D9
D5
D3 D2 D1
C0
D7
D4
D0 A1
MSB FROM
PREVIOUS WRITE
DATA PACKET (N)
A1
DATA PACKET (N-1)
DOUT
(MODE 1)
A0
D8
D7
D6
C1
D11 D10 D9
D5
D3 D2 D1
A1
C0
D4
D0
MSB FROM
PREVIOUS WRITE
DATA PACKET (N)
DATA PACKET (N-1)
Figure 5. Serial-Interface Timing Diagram
t
CSW
CS
t
CP
t
CSH
t
t
CH
CSS
t
t
CL
CSO
t
CS1
SCLK
t
DS
t
DH
DIN
t
DO2
t
DO1
DOUT
Figure 6. Detailed Serial-Interface Timing Diagram
Since the MAX525’s DOUT pin has an internal active
pull-up, the DOUT sink/source capability determines
the time required to discharge/charge a capacitive
P o w e r-Do w n Lo c k o u t (PDL)
The power-down lockout pin PDL disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL could also be
used to asynchronously wake up the device.
load. Refer to the serial-data-out V
and V specifi-
OH
OL
cations in the Electrical Characteristics.
Figure 8 shows an alternate method of connecting sev-
eral MAX525s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
Da is y Ch a in in g De vic e s
Any number of MAX525s can be daisy chained by con-
necting the DOUT pin of one device to the DIN pin of
the following device in the chain (Figure 7).
______________________________________________________________________________________ 11
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX525
MAX525
MAX525
MAX25
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
CS
SCLK
DIN
DOUT
DOUT
DOUT
CS
TO OTHER
SERIAL DEVICES
Figure 7. Daisy-Chaining MAX525s
DIN
SCLK
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
MAX525
MAX525
MAX525
SCLK
DIN
SCLK
DIN
SCLK
DIN
Figure 8. Multiple MAX525s Sharing a Common DIN Line
12 ______________________________________________________________________________________
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
Bip o la r Ou t p u t
The MAX525 outputs can be configured for bipolar
__________Ap p lic a t io n s In fo rm a t io n
Un ip o la r Ou t p u t
For a unipolar output, the output voltages and the refer-
ence inputs have the same polarity. Figure 9 shows the
MAX525 unipolar output circuit, which is also the typi-
cal operating circuit. Table 2 lists the unipolar output
codes.
operation using Figure 11’s circuit.
V
OUT
= V [(2NB / 4096) - 1]
REF
where NB is the numeric value of the DAC’s binary
input code. Table 3 shows digital codes (offset binary)
a nd c orre s p ond ing outp ut volta g e s for Fig ure 11’s
circuit.
For rail-to-rail outputs, see Figure 10. This circuit shows
the MAX525 with the output amplifiers configured with a
closed-loop gain of +2 to provide 0V to 5V full-scale
range when a 2.5V reference is used.
Table 2. Unipolar Code Table
+5V
REFERENCE INPUTS
MAX525
DAC CONTENTS
ANALOG OUTPUT
V
DD
REFAB
REFCD
FBA
MSB
LSB
4095
+VREF ( ——— )
4096
1 1 1 1
1 1 1 1 1 1 1 1
DAC A
DAC B
OUTA
FBB
2049
+VREF ( ——— )
4096
1000
1 0 0 0
0 1 1 1
0000
0001
2048
+VREF
OUTB
FBC
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
+VREF ( ——— ) = ————
4096
2
2047
+VREF ( ——— )
4096
DAC C
DAC D
OUTC
FBD
1
+VREF ( ——— )
4096
0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
0V
OUTD
AGND
DGND
Table 3. Bipolar Code Table
DAC CONTENTS
ANALOG OUTPUT
MSB
LSB
Figure 9. Unipolar Output Circuit
2047
+VREF ( ——— )
2048
1 1 1 1
1 1 1 1 1 1 1 1
1
+VREF ( ——— )
2048
1000
1 0 0 0
0 1 1 1
0000
0001
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0V
1
-VREF ( ——— )
2048
2047
-VREF ( ——— )
2048
0 0 0 0
0 0 0 0
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
2048
-VREF ( ——— ) = -V
REF
2048
1
Note: 1LSB = (V ) (
)
REF
4096
______________________________________________________________________________________ 13
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
Us in g a n AC Re fe re n c e
In applications where the reference has AC signal com-
+5V
REFERENCE INPUTS
REFAB
ponents, the MAX525 has multiplying capability within
the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to
the reference input where the AC signal is offset before
being applied to REFAB/REFCD. The reference voltage
must never be more negative than DGND.
MAX525
10k
V
REFCD
FBA
DD
10k
DAC A
DAC B
DAC C
DAC D
OUTA
10k
MAX25
FBB
The MAX525’s total harmonic distortion plus noise (THD
+ N) is typically less than -72dB, given a 1Vp-p signal
swing and input frequencies up to 25kHz. The typical
-3dB frequency is 650kHz, as shown in the Typical
Operating Characteristics graphs.
10k
OUTB
FBC
10k
10k
Dig it a lly P ro g ra m m a b le Cu rre n t S o u rc e
The c irc uit of Fig ure 13 p la c e s a n NPN tra ns is tor
(2N3904 or similar) within the op-amp feedback loop to
implement a digitally programmable, unidirectional cur-
rent source. This circuit can be used to drive 4mA to
20mA c urre nt loop s , whic h a re c ommonly us e d in
industrial-control applications. The output current is cal-
culated with the following equation:
OUTC
FBD
10k
10k
OUTD
AGND
DGND
I
= (V
/ R) x (NB / 4096)
OUT
REF
V
= V
= 2.5V
REFAB REFCD
where NB is the numeric value of the DAC’s binary
inp ut c od e a nd R is the s e ns e re s is tor s hown in
Figure 13.
Figure 10. Unipolar Rail-to-Rail Output Circuit
+5V
AC
REFERENCE
INPUT
26k
R1
R2
1/2 MAX492
REF_
REF_
+5V
10k
V
DD
500mVp-p
FB_
V
OUT
DAC
OUT_
DAC_
OUT_
-5V
R1 = R2 = 10kΩ ± 0.1%
MAX525
MAX525
AGND
DGND
Figure 11. Bipolar Output Circuit
Figure 12. AC Reference Input Circuit
14 ______________________________________________________________________________________
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
MAX25
__________________P in Co n fig u ra t io n
REF_
V
L
TOP VIEW
MAX525
I
OUT
DAC_
1
2
3
4
5
6
7
8
9
AGND
FBA
V
DD
20
19
18
17
16
15
OUT_
FB_
2N3904
FBD
OUTA
OUTB
FBB
OUTD
OUTC
FBC
MAX525
R
REFAB
CL
REFCD
14 PDL
13
CS
UPO
Figure 13. Digitally Programmable Current Source
DIN
12 DOUT
11 DGND
SCLK 10
P o w e r-S u p p ly Co n s id e ra t io n s
On power-up, all input and DAC registers are cleared
(set to zero code) and DOUT is in Mode 0 (serial data
is shifted out of DOUT on the clock’s falling edge).
DIP/SSOP
For rated MAX525 performance, limit REFAB/REFCD to
less than 1.4V below V . Bypass V
with a 4.7µF
DD
DD
capacitor in parallel with a 0.1µF capacitor to AGND.
Use short lead lengths and place the bypass capaci-
tors as close to the supply pins as possible.
Gro u n d in g a n d La yo u t Co n s id e ra t io n s
Digital or AC transient signals between AGND and
DGND c a n c re a te nois e a t the a na log outp uts . Tie
AGND and DGND together at the DAC, then tie this
point to the highest-quality ground available.
Good printed circuit board ground layout minimizes
crosstalk between DAC outputs, reference inputs, and
digital inputs. Reduce crosstalk by keeping analog
lines away from digital lines. Wire-wrapped boards are
not recommended.
______________________________________________________________________________________ 15
Lo w -P o w e r, Qu a d , 1 2 -Bit Vo lt a g e -Ou t p u t DAC
w it h S e ria l In t e rfa c e
_Ord e rin g In fo rm a t io n (c o n t in u e d )
___________________Ch ip In fo rm a t io n
TRANSISTOR COUNT: 4337
INL
(LSBs)
PART
TEMP. RANGE PIN-PACKAGE
MAX525BC/D
0°C to +70°C Dice*
±1
MAX525AEPP -40°C to +85°C 20 Plastic DIP
MAX525BEPP -40°C to +85°C 20 Plastic DIP
MAX525AEAP -40°C to +85°C 20 SSOP
MAX525BEAP -40°C to +85°C 20 SSOP
MAX525AMJP -55°C to +125°C 20 CERDIP**
MAX525BMJP -55°C to +125°C 20 CERDIP**
±1/2
±1
MAX25
±1/2
±1
±1/2
±1
* Dice are specified at T = +25°C, DC parameters only.
A
**Contact factory for availability and processing to MIL-STD-883.
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.068
MAX
0.078
0.008
0.015
0.008
MIN
1.73
0.05
0.25
0.09
MAX
1.99
0.21
0.38
0.20
A
A1 0.002
B
C
D
E
e
0.010
0.004
SEE VARIATIONS
α
0.205
0.209
5.20
5.38
E
H
0.0256 BSC
0.65 BSC
H
L
0.301
0.311
0.037
8˚
7.65
0.63
0˚
7.90
0.95
8˚
0.025
0˚
C
α
L
INCHES
MILLIMETERS
DIM PINS
MIN MAX MIN
0.239 0.249 6.07
0.239 0.249 6.07
0.278 0.289 7.07
0.317 0.328 8.07
MAX
6.33
6.33
7.33
8.33
e
D
D
D
D
D
14
16
20
24
28
SSOP
SHRINK
A
SMALL-OUTLINE
PACKAGE
0.397 0.407 10.07 10.33
21-0056A
B
A1
D
.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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