MAX5295EUE+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 2us Settling Time, PDSO16, 6.50 X 5 MM, MO-153AB, TSSOP-16;
| 型号： | MAX5295EUE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 2us Settling Time, PDSO16, 6.50 X 5 MM, MO-153AB, TSSOP-16 |
| 文件： | 总33页 (文件大小：927K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3005; Rev 0; 11/03
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
General Description
Features
The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltage-
output digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at
the 12-bit level. The DACs operate from a 2.7V to 3.6V
analog supply and a separate 1.8V to 3.6V digital sup-
ply. The 20MHz 3-wire serial interface is compatible
with SPI™, QSPI™, MICROWIRE™, and digital signal
processor (DSP) protocol applications. Multiple devices
can share a common serial interface in direct access or
daisy-chained configuration. The MAX5290–MAX5295
provide two multifunctional, user-programmable, digital
I/O ports. The externally selectable power-up states of
the DAC outputs are either zero scale, midscale, or full
scale. Software-selectable FAST and SLOW settling
modes decrease settling time in FAST mode, or reduce
supply current in SLOW mode.
o Dual, 12-/10-/8-Bit Serial DACs in 4mm x 4mm
Thin QFN and TSSOP Packages
o 3µs (max) 12-Bit Settling Time to 1/2 LSB
o Integral Nonlinearity
1 LSB (max) MAX5290/MAX5291 A-Grade (12-Bit)
1 LSB (max) MAX5292/MAX5293 (10-Bit)
1/2 LSB (max) MAX5294/MAX5295 (8-Bit)
o Guaranteed Monotonic, 1 LSB (max) DNL
o Two User-Programmable Digital I/O Ports
o Single +2.7V to +3.6V Analog Supply
o +1.8V to AV
Digital Supply
DD
o 20MHz 3-Wire SPI-/QSPI-/MICROWIRE- and
DSP-Compatible Serial Interface
The MAX5290/MAX5291 are 12-bit DACs, the MAX5292/
MAX5293 are 10-bit DACs, and the MAX5294/MAX5295
are 8-bit DACs. The MAX5290/ MAX5292/MAX5294 pro-
vide unity-gain-configured output buffers, while the
MAX5291/MAX5293/MAX5295 provide force-sense-con-
figured output buffers. The MAX5290– MAX5295 are
specified over the extended -40°C to +85°C temperature
range, and are available in space-saving 4mm x 4mm,
16-pin thin QFN and 6.5mm x 5mm, 14-pin and 16-pin
TSSOP packages.
o Glitch-Free Outputs Power Up to Zero Scale,
Midscale or Full Scale
o Unity-Gain- or Force-Sense-Configured Output
Buffers
Ordering Information
Applications
Portable Instrumentation
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
14 TSSOP
MAX5290AEUD*
MAX5290BEUD
MAX5290AETE*
MAX5290BETE*
MAX5291AEUE*
MAX5291BEUE
MAX5291AETE*
MAX5291BETE*
MAX5292EUD
MAX5292ETE*
MAX5293EUE
MAX5293ETE*
MAX5294EUD
MAX5294ETE*
MAX5295EUE
MAX5295ETE*
Automatic Test Equipment (ATE)
Digital Offset and Gain Adjustment
Automatic Tuning
14 TSSOP
16 Thin QFN-EP**
16 Thin QFN-EP**
16 TSSOP
Programmable Voltage and Current Sources
Programmable Attenuators
16 TSSOP
Industrial Process Controls
16 Thin QFN-EP**
16 Thin QFN-EP**
14 TSSOP
Motion Control
Microprocessor (µP)-Controlled Systems
Power Amplifier Control
16 Thin QFN-EP**
16 TSSOP
Fast Parallel-DAC to Serial-DAC Upgrades
16 Thin QFN-EP**
14 TSSOP
16 Thin QFN-EP**
16 TSSOP
Selector Guide and Pin Configurations appear at end of data
sheet.
16 Thin QFN-EP**
*Future product—contact factory for availability. Specifications
are preliminary.
SPI/QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
**EP = Exposed paddle.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ABSOLUTE MAXIMUM RATINGS
AV
to DV ........................................................................ 6V
Maximum Current into Any Pin ......................................... 50mA
DD
DD
AGND to DGND.................................................................. 0.3V
Continuous Power Dissipation (T = +70°C)
A
AV
DV
to AGND, DGND.............................................-0.3V to +6V
to AGND, DGND ............................................-0.3V to +6V
14-Pin TSSOP (derate 9.1mW/°C above +70°C) .........727mW
16-Pin TSSOP (derate 9.4mW/°C above +70°C) .........755mW
16-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Junction Temperature .....................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
DD
FB_, OUT_,
REF to AGND........-0.3V to the lower of (AV + 0.3V) or +6V
DD
SCLK, DIN, CS, PU,
DSP to DGND.......-0.3V to the lower of (DV + 0.3V) or +6V
DD
UPIO1, UPIO2
to DGND...............-0.3V to the lower of (DV + 0.3V) or +6V
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(AV
= 2.7V to 3.6V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V, R = 10kΩ, C = 100pF, T = T
to T
, unless
MAX
DD
DD
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY
MAX5290/MAX5291
12
10
8
Resolution
N
MAX5292/MAX5293
MAX5294/MAX5295
Bits
MAX5290A/MAX5291A (12-bit)
MAX5290B/MAX5291B (12-bit)
MAX5292/MAX5293 (10-bit)
MAX5294/MAX5295 (8-bit)
1
4
V
AV
(Note 2)
= 2.5V at
= 2.7V
REF
2
Integral Nonlinearity
INL
LSB
DD
0.5
1
0.125
0.5
Differential Nonlinearity
Offset Error
DNL
Guaranteed monotonic (Note 2)
1
LSB
mV
MAX5290A/MAX5291A (12-bit), decimal code = 40
MAX5290B/MAX5291B (12-bit), decimal code = 82
MAX5292/MAX5293 (10-bit), decimal code = 21
MAX5294/MAX5295 (8-bit), decimal code = 5
5
5
5
5
25
25
25
V
OS
ppm of
FS/°C
Offset-Error Drift
Gain Error
5
MAX5290A/MAX5291A (12-bit)
4
20
5
MAX5290B/MAX5291B (12-bit)
Full-scale output
10
3
GE
LSB
MAX5292/MAX5293 (10-bit)
MAX5294/MAX5295 (8-bit)
0.5
2
ppm of
FS/°C
Gain-Error Drift
1
2
_______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 2.7V to 3.6V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V, R = 10kΩ, C = 100pF, T = T
to T
, unless
MAX
DD
DD
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power-Supply Rejection
Ratio
PSRR
Full-scale output, AV
= 2.7V to 3.6V
200
µV/V
DD
REFERENCE INPUT
Reference Input Range
V
R
0.25
145
AV
V
REF
DD
Reference Input
Resistance
Normal operation (no code dependence)
Shutdown mode
200
0.5
kΩ
REF
Reference Leakage
Current
I
1
µA
REF
DAC OUTPUT CHARACTERISTICS
Unity gain
85
67
SLOW mode,
full scale
Force sense
Unity gain
Output Voltage Noise
µV
RMS
140
110
FAST mode,
full scale
Force sense
Unity-gain output
0
0
AV
DD
Output Voltage Range
(Note 4)
V
Force-sense output
AV / 2
DD
DC Output Impedance
Short-Circuit Current
Power-Up Time
38
45
30
40
Ω
AV
= 3V, OUT_ to AGND, full scale, FAST mode
mA
DD
From DV
applied, interface is functional
60
µs
µs
DD
Wake-Up Time
Coming out of shutdown, outputs settled
Output OUT_ and FB_
Open-Circuit Leakage
Current
Programmed in shutdown mode, force-sense
outputs only
0.01
µA
DIGITAL OUTPUTS (UPIO_)
DV
0.5
-
DD
Output High Voltage
V
I
I
= 2mA
SOURCE
V
V
OH
Output Low Voltage
V
= 2mA
SINK
0.4
OL
DIGITAL INPUTS (SCLK, CS, DIN, DSP, UPIO_)
2.7V ≤ DV
≤ 3.6V
≤ 3.6V
2.4
DD
Input High Voltage
V
V
V
IH
0.7 x
DV
< 2.7V
DD
DV
DD
2.7V ≤ DV
0.6
0.2
1
DD
Input Low Voltage
V
IL
DV
< 2.7V
DD
Input Leakage Current
Input Capacitance
I
0.1
10
µA
pF
IN
C
IN
_______________________________________________________________________________________
3
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 2.7V to 3.6V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V, R = 10kΩ, C = 100pF, T = T
to T , unless
MAX
DD
DD
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
PU INPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DV
200mV
-
DD
Input High Voltage
V
V
IH-PU
Input Low Voltage
V
200
200
mV
nA
IL-PU
IN-PU
PU still considered floating when connected to a
tri-state bus
Input Leakage Current
I
DYNAMIC PERFORMANCE
Fast mode
Slow mode
3.6
1.6
Voltage-Output Slew
Rate
SR
V/µs
MAX5290/MAX5291 from code 322 to
code 4095 to 1/2 LSB
2
1.5
1
3
3
2
6
6
4
MAX5292/MAX5293 from code 82 to
FAST mode
code 1023 to 1/2 LSB
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB
Voltage-Output Settling
Time (Note 5)
µs
MAX5290/MAX5291 from code 322 to
code 4095 to 1/2 LSB
3
MAX5292/MAX5293 from code 82 to
SLOW mode
2.5
2
code 1023 to 1/2 LSB
MAX5294/MAX5295 from code 21 to
code 255 to 1/2 LSB
FB_ Input Voltage
FB_ Input Current
0
V
/ 2
V
REF
0.1
µA
Unity gain
200
150
Reference -3dB
Bandwidth (Note 6)
kHz
Force sense
CS = DV , code = zero scale, any digital input
DD
Digital Feedthrough
0.1
nV-s
from 0 to DV
and DV
to 0, f = 100kHz
DD
DD
Digital-to-Analog Glitch
Impulse
Major carry transition
(Note 3)
2
nV-s
nV-s
DAC-to-DAC Crosstalk
15
4
_______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(AV
= 2.7V to 3.6V, DV
= 1.8V to AV , AGND = 0, DGND = 0, V
= 2.5V, R = 10kΩ, C = 100pF, T = T
to T
, unless
MAX
DD
DD
DD
REF
L
L
A
MIN
otherwise noted. Typical values are at T = +25°C.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Range
AV
DV
2.7
1.8
3.6
V
V
DD
Digital Supply Voltage
Range
AV
DD
DD
Unity gain
0.55
0.9
0.8
µA
mA
SLOW mode, all digital inputs
at DGND or DV , no load,
DD
V
= 2.5V
REF
Force sense
Unity gain
1.2
2
Operating Supply
Current
I
+
AVDD
I
DVDD
0.85
1.2
FAST mode, all digital inputs
at DGND or DV , no load,
DD
mA
µA
V
= 2.5V
REF
Force sense
2
I
AVDD(SHDN)
+
Shutdown Supply
Current
No clocks, all digital inputs at DGND or DV , all
DD
2.5
DACs in shutdown mode
I
DVDD(SHDN)
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1)
(DV
= 2.7V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
2.7V < DV
(Note 7)
(Note 7)
< 3.6V
DD
20
SCLK
SCLK Pulse-Width High
t
20
20
10
5
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
t
ns
CSS
CSH
t
ns
t
10
12
5
ns
CS0
t
ns
DS
t
ns
DH
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
t
C = 20pF, UPIO_ = DOUTDC1 mode
30
30
ns
ns
DO1
DO2
L
SCLK Fall to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 or DOUTRB
L
mode
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
10
45
ns
ns
CS1
t
CSW
_______________________________________________________________________________________
5
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V Logic) (Figure 1) (continued)
(DV
= 2.7V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
100
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
20
20
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
C = 20pF, from 8th rising edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
20
100
20
ns
ns
ns
ns
LDL
LDS
LDAC Effective Delay
Figure 6
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
100
100
GP
GPO Output High-Impedance
Time
t
ns
GPZ
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1)
(DV
= 1.8V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
1.8V < DV
(Note 7)
(Note 7)
< 3.6V
DD
10
SCLK
SCLK Pulse-Width High
t
40
40
20
0
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Hold Time
SCLK Rise to CS Fall Setup Time
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
t
ns
CSS
CSH
t
ns
t
10
20
5
ns
CS0
t
ns
DS
t
ns
DH
SCLK Rise to DOUTDC1 Valid
Propagation Delay
t
t
C = 20pF, UPIO_ = DOUTDC1 mode
60
60
ns
ns
DO1
DO2
L
SCLK Fall to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 or DOUTRB
L
mode
CS Rise to SCLK Rise Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
20
90
ns
ns
CS1
t
CSW
6
_______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Disabled (1.8V Logic) (Figure 1) (continued)
(DV
= 1.8V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
200
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
40
40
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
C = 20pF, from 8th rising edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
40
200
40
ns
ns
ns
ns
LDL
LDAC Effective Delay
Figure 6
LDS
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
200
200
GP
GPO Output High-Impedance
Time
t
ns
GPZ
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2)
(DV
= 2.7V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
2.7V < DV
(Note 7)
(Note 7)
< 3.6V
DD
20
SCLK
SCLK Pulse-Width High
t
20
20
10
10
5
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Fall Setup Time
DSP Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Fall to CS Fall Delay
SCLK Fall to DSP Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
t
t
ns
CSS
DSS
CSH
ns
t
ns
t
t
10
10
12
5
ns
CS0
DS0
ns
t
ns
DS
t
ns
DH
SCLK Rise to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC1 or DOUTRB
L
mode
t
t
30
30
ns
ns
DO1
DO2
SCLK Fall to DOUTDC0 Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 mode
L
CS Rise to SCLK Fall Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
10
45
20
20
ns
ns
ns
ns
CS1
t
t
CSW
DSW
DSP Pulse-Width High
DSP Pulse-Width Low
t
(Note 8)
DSPWL
_______________________________________________________________________________________
7
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (3V, 3.3V Logic) (Figure 2) (continued)
(DV
= 2.7V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
100
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
20
20
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
C = 20pF, from 8th falling edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
20
100
20
ns
ns
ns
ns
LDL
LDAC Effective Delay
Figure 6
LDS
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
100
100
GP
GPO Output High-Impedance
Time
t
ns
GPZ
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2)
(DV
= 1.8V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
1.8V < DV
(Note 7)
(Note 7)
< 3.6V
DD
10
SCLK
SCLK Pulse-Width High
t
40
40
20
20
0
CH
SCLK Pulse-Width Low
t
ns
CL
CS Fall to SCLK Fall Setup Time
DSP Fall to SCLK Fall Setup Time
SCLK Fall to CS Rise Hold Time
SCLK Fall to CS Fall Delay
SCLK Fall to DSP Fall Delay
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
t
t
ns
CSS
DSS
CSH
ns
t
ns
t
t
10
15
20
5
ns
CS0
DS0
ns
t
ns
DS
t
ns
DH
SCLK Rise to DOUT_ Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC1 or DOUTRB
L
mode
t
t
60
60
ns
ns
DO1
DO2
SCLK Fall to DOUTDC0 Valid
Propagation Delay
C = 20pF, UPIO_ = DOUTDC0 mode
L
CS Rise to SCLK Fall Hold Time
CS Pulse-Width High
t
MICROWIRE and SPI modes 0 and 3
20
90
40
40
ns
ns
ns
ns
CS1
t
t
CSW
DSW
DSP Pulse-Width High
DSP Pulse-Width Low
t
DSPWL
(Note 8)
8
_______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
TIMING CHARACTERISTICS—DSP Mode Enabled (1.8V Logic) (Figure 2) (continued)
(DV
= 1.8V to 3.6V, DGND = 0, T = T
MIN
to T , unless otherwise noted.)
MAX
DD
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when
Exiting DOUTDC0, DOUTDC1, or
DOUTRB UPIO_ Modes
C = 20pF, from end of write cycle to UPIO_
L
in high impedance
t
200
ns
DOZ
DOUTRB Tri-State Time from CS
Rise
C = 20pF, from rising edge of CS to UPIO_
in high impedance
L
t
40
40
ns
ns
DRBZ
DOUTRB Tri-State Enable Time
from 8th SCLK Fall
C = 20pF, from 8th falling edge of SCLK to
L
UPIO_ driven out of tri-state
t
ZEN
LDAC Pulse-Width Low
t
t
Figure 5
40
200
40
ns
ns
ns
ns
LDL
LDAC Effective Delay
Figure 6
LDS
CLR, MID, SET Pulse-Width Low
GPO Output Settling Time
t
Figure 5
CMS
t
Figure 6
200
200
GP
GPO Output High-Impedance
Time
t
ns
GPZ
Note 1: For the force-sense versions, FB_ is connected to its respective OUT_. V
OUT
(max) = V
/ 2, unless otherwise noted.
REF
Note 2: Linearity guaranteed from decimal code 82 to 4095 for the MAX5290B/MAX5291B (12-bit, B-grade), code 21 to 1023 for the
MAX5292/MAX5293 (10-bit), and code 5 to 255 for the MAX5294/MAX5295 (8-bit).
Note 3: DAC-to-DAC crosstalk is measured as follows: outputs of DACA and DACB are set to full scale and the output of DACB is
measured. While keeping DACB unchanged, the output of DACA is transitioned to zero scale and the ∆V
of DACB is
OUT
measured. The procedure is repeated with DACA and DACB interchanged. DAC-to-DAC crosstalk is the maximum ∆V
OUT
measured.
Note 4: Represents the functional range. The linearity is guaranteed at V
tion for linearity at other voltages.
= 2.5V. See the Typical Operating Characteristics sec-
REF
Note 5: Guaranteed by design.
Note 6: The reference -3dB bandwidth is measured with a 0.1V
sine wave on V and with the input code at full scale.
REF
P-P
Note 7: In some daisy-chain modes, data is required to be clocked in on one clock edge and the shifted data clocked out on the fol-
lowing edge. In the case of a 1/2 clock-period delay, it is necessary to increase the minimum high/low clock times to 25ns
(2.7V) or 50ns (1.8V).
Note 8: The falling edge of DSP starts a DSP-type bus cycle, provided that CS is also active low to select the device. DSP active low
and CS active low must overlap by a minimum of 10ns (2.7V) or 20ns (1.8V). CS can be permanently low in this mode of
operation.
_______________________________________________________________________________________
9
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Typical Operating Characteristics
(AV = DV = 3V, V
= 2.5V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)
DD
DD
REF
L
L
A
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
4
3
1.00
0.75
0.50
0.25
0
UNITY GAIN
B-GRADE
UNITY GAIN
2
1
0
-1
-2
-3
-4
-0.25
-0.50
-0.75
-1.00
0
1024
2048
3072
4096
0
256
512
768
1024
4096
256
DIGITAL INPUT CODE
DIGITAL INPUT CODE
INTEGRAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (12-BIT)
0.50
0.25
0
0.2
0.1
0
UNITY GAIN
UNITY GAIN
B-GRADE
-0.25
-0.50
-0.1
-0.2
0
64
128
192
256
0
1024
2048
3072
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT)
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT)
0.02
0.01
0
0.050
0.025
0
UNITY GAIN
UNITY GAIN
-0.01
-0.02
-0.025
-0.050
0
64
128
192
0
256
512
768
1024
DIGITAL INPUT CODE
DIGITAL INPUT CODE
10 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Typical Operating Characteristics (continued)
(AV = DV = 3V, V
= 2.5V, R = 10kΩ, C = 100pF, speed mode = FAST, PU = floating, T = +25°C, unless otherwise noted.)
DD
DD
REF
L
L
A
INTEGRAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE (12-BIT)
4
2
0
0.2
0.1
0
UNITY GAIN
B-GRADE
UNITY GAIN
B-GRADE
-2
-0.1
-0.2
-4
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
OFFSET ERROR vs. TEMPERATURE
GAIN ERROR vs. TEMPERATURE
0
-2
0
-2
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
FORCE SENSE
UNITY GAIN
-4
-4
FORCE SENSE
-6
-6
UNITY GAIN
-8
-8
UNITY GAIN: 1 LSB = 0.6mV
FORCE SENSE: 1 LSB = 0.3mV
-10
-10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
REFERENCE INPUT BANDWIDTH
5
0
V
= 0.1V AT 2.5V
P-P DC
REF
-5
-10
-15
-20
-25
-30
0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
______________________________________________________________________________________ 11
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Pin Description
PIN
MAX5290
MAX5292
MAX5294
MAX5291
MAX5293
MAX5295
NAME
FUNCTION
THIN QFN
TSSOP
THIN QFN
TSSOP
Clock Enable. Connect DSP to DV
at power-up to transfer
DD
data on the rising edge of SCLK. Connect DSP to DGND at
1
2
1
3
DSP
power-up to transfer data on the falling edge of SCLK.
2
3
3
4
2
3
4
5
DIN
CS
Serial Data Input
Active-Low Chip-Select Input
Serial Clock Input
4
5
4
6
SCLK
5
6
5
7
DV
Digital Supply
DD
6
7
6
8
DGND
AGND
Digital Ground
7
8
7
9
Analog Ground
8
9
8
10
11
12
13
14
—
15
AV
Analog Supply
DD
9
10
—
11
—
—
12
9
OUTB
FBB
DACB Output
—
10
—
11, 13
12
10
11
12
—
13
Feedback for DACB Output Buffer
Reference Input
REF
FBA
Feedback for DACA Output Buffer
No Connection. Not internally connected.
DACA Output
N.C.
OUTA
Power-Up State Select Input. Connect PU to DV to set OUTA
DD
and OUTB to full scale upon power-up. Connect PU to DGND to
set OUTA and OUTB to zero upon power-up. Leave PU floating
to set OUTA and OUTB to midscale upon power-up.
14
13
14
16
PU
15
16
14
1
15
16
1
2
UPIO2
UPIO1
User-Programmable Input/Output 2
User-Programmable Input/Output 1
Exposed Paddle (QFN Only). Not internally connected. Do not
connect to circuitry.
—
—
—
—
EP
12 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Functional Diagrams
AV
DV
AGND
DGND
DD
DD
CS
SCLK
DIN
SERIAL
INTERFACE
CONTROL
MAX5290
MAX5292
MAX5294
DSP
16-BIT SHIFT
REGISTER
DOUT
REGISTER
MUX
UPIO1
UPIO2
UPIO1 AND
UPIO2
LOGIC
POWER-DOWN
LOGIC AND
REGISTER
DECODE
CONTROL
PU
OUTA
INPUT
REGISTER
DAC
REGISTER
DAC A
REF
OUTB
INPUT
REGISTER
DAC
REGISTER
DAC B
______________________________________________________________________________________ 13
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Functional Diagrams (continued)
AV
DV
AGND
DGND
DD
DD
CS
SCLK
DIN
SERIAL
INTERFACE
CONTROL
MAX5291
MAX5293
MAX5295
DSP
16-BIT SHIFT
REGISTER
DOUT
REGISTER
MUX
UPIO1
UPIO2
UPIO1 AND
UPIO2
LOGIC
POWER-DOWN
LOGIC AND
REGISTER
FBA
DECODE
CONTROL
PU
OUTA
INPUT
REGISTER
DAC
REGISTER
DAC A
REF
FBB
OUTB
INPUT
REGISTER
DAC
REGISTER
DAC B
14 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Use the serial interface to set the shutdown output
Detailed Description
impedance of the amplifiers to 1kΩ or 100kΩ for the
The MAX5290–MAX5295 dual, 12-/10-/8-bit, voltage-
MAX5290/MAX5292/MAX5294 and 1kΩ or high imped-
ance for the MAX5291/MAX5293/MAX5295. The DAC
outputs can drive a 2kΩ (typ) load and are stable with
up to 500pF (typ) of capacitive load.
output digital-to-analog converters (DACs) offer
buffered outputs and a 3µs maximum settling time at
the 12-bit level. The DACs operate from a single 2.7V to
3.6V analog supply and a separate 1.8V to AV
digi-
DD
tal supply. The MAX5290–MAX5295 include an input
register and DAC register for each channel and a
16-bit data-in/data-out shift register. The 3-wire serial
interface is compatible with SPI, QSPI, MICROWIRE,
and DSP applications. The MAX5290–MAX5295 pro-
vide two user-programmable digital I/O ports, which
are programmed through the serial interface. The exter-
nally selectable power-up states of the DAC outputs
are either zero scale, midscale, or full scale.
Power-On Reset
At power-up, all DAC outputs power up to full scale,
midscale, or zero scale, depending on the configuration
of the PU input. Connect PU to DV
to set OUT_ to full
DD
scale upon power-up. Connect PU to DGND to set
OUT_ to zero scale upon power-up. Leave PU floating
to set OUT_ to midscale.
Digital Interface
The MAX5290–MAX5295 use a 3-wire serial interface
Reference Input
The reference input, REF, accepts both AC and DC val-
ues with a voltage range extending from 0.25V to
that is compatible with SPI, QSPI, MICROWIRE, and
DSPs (Figures 1 and 2). Connect DSP to DV
before
DD
power-up to clock data in on the rising edge of SCLK.
Connect DSP to DGND before power-up to clock data in
on the falling edge of SCLK. After power-up, the device
enters DSP frame sync mode on the first rising edge of
DSP. Refer to the Programmer’s Handbook for details.
AV . The voltage at REF (V
) sets the full-scale out-
REF
DD
put of the DACs. Determine the output voltage using
the following equation:
Unity-gain versions:
V
OUT_
= (V
x CODE) / 2N
REF
Each MAX5290–MAX5295 includes a 16-bit input shift
register. The data is loaded into the input shift register
through the serial interface. The 16 bits can be sent in
two serial 8-bit packets or one 16-bit word (CS must
remain low until all 16 bits are transferred). The data is
loaded MSB first. For the MAX5290/MAX5291, the 16
bits consist of 4 control bits (C3–C0) and 12 data bits
(D11–D0) (see Table 1). For the 10-bit MAX5292/
MAX5293 devices, D11–D2 are the data bits and D1
and D0 are sub-bits. For the 8-bit MAX5294/
MAX5295 devices, D11–D4 are the data bits and
D3–D0 are sub-bits. Set all sub-bits to zero for optimum
performance.
Force-sense versions (FB_ connected to OUT_):
= 0.5 x (V
x CODE) / 2N
V
OUT
REF
where CODE is the numeric value of the DAC’s binary
input code and N is the bits of resolution. For the
MAX5290/MAX5291, N = 12 and CODE ranges from 0
to 4095. For the MAX5292/MAX5293, N = 10 and
CODE ranges from 0 to 1023. For the MAX5294/
MAX5295, N = 8 and CODE ranges from 0 to 255.
Output Buffers
The DACA and DACB output-buffer amplifiers of the
MAX5290–MAX5295 are unity-gain stable with Rail-to-
Rail® output voltage swings and a typical slew rate of
5.7V/µs. The MAX5290/MAX5292/MAX5294 provide
unity-gain outputs, while the MAX5291/MAX5293/
MAX5295 provide force-sense outputs. For the
MAX5291/MAX5293/MAX5295, access to the output
amplifier’s inverting input provides flexibility in output gain
setting and signal conditioning (see the Applications
Information section).
Each DAC channel includes two registers: an input reg-
ister and the DAC register. At power-up, the DAC out-
put is set according to the state of PU. The DACs are
double-buffered, which allows any of the following for
each channel:
• Loading the input register without updating the DAC
register
• Loading the DAC register without updating the input
register
The MAX5290–MAX5295 offer FAST and SLOW-settling
time modes. In the FAST mode, the settling time is 3µs
(max), and the supply current is 2mA (max). In the SLOW
mode, the settling time is 6µs (max), and the supply cur-
rent drops to 0.8mA (max). See the Digital Interface sec-
tion for settling-time mode programming details.
• Updating the DAC register from the input register
• Updating the input and DAC registers simultaneously
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
______________________________________________________________________________________ 15
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Table 1. Serial Write Data Format
MSB
16 BITS OF SERIAL DATA
LSB
CONTROL BITS
C2 C1
DATA BITS
C3
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
t
CH
SCLK
DIN
t
CL
t
DS
C3
C2
C1
D0
t
t
t
CSH
CS0
DH
t
CSS
CS
t
CSW
t
CS1
t
DO1
DOUTDC1*
DOUT VALID
t
DO2
DOUTDC0
OR
DOUTRB*
DOUT VALID
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT SECTION FOR DETAILS.
Figure 1. Serial-Interface Timing Diagram (DSP Mode Disabled)
t
CL
SCLK
DIN
t
CH
t
DS
C3
C2
C1
D0
t
t
DH
CS0
t
CSH
t
CSS
CS
t
CSW
t
CS1
t
DSS
t
DS0
DSP
t
t
t
D02
DSW
DSPWL
DOUTDC0*
DOUT VALID
t
D01
DOUTDC1
OR
DOUTRB*
DOUT VALID
*UPIO1/UPIO2 CONFIGURED AS DOUTDC_ (DAISY-CHAIN DATA OUTPUT, MODE 0 OR 1) OR DOUTRB (READ-BACK DATA OUTPUT).
SEE THE DATA OUTPUT SECTION FOR DETAILS.
Figure 2. Serial-Interface Timing Diagram (DSP Mode Enabled)
16 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Serial-Interface Programming Commands
Tables 2a, 2b, and 2c provide all of the serial-interface
programming commands for the MAX5290–MAX5295.
Table 2a shows the basic DAC programming com-
mands, Table 2b gives the advanced-feature program-
ming commands, and Table 2c provides the 24-bit
read commands. Figures 3 and 4 illustrate the serial-
interface diagrams for read and write operations.
Loading Input and DAC Registers
The MAX5290–MAX5295 contain a 16-bit shift register
that is followed by a 12-bit input register and a 12-bit
DAC register for each channel (see the Functional
Diagrams). Tables 3, 4, and 5 highlight a few of the com-
mands for the loading of the input and DAC registers.
See Table 2a for all DAC programming commands.
V
V
DD
DD
MICROWIRE
SPI OR QSPI
MAX5290–
MAX5295
MAX5290–
MAX5295
V
DV
V
DV
DD
DD
DD
DD
DSP
DSP
SK
SO
SCK
MOSI
SCLK
SCLK
DIN
DIN
I/O
CS
SS OR I/O
CS
MICROWIRE OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
✕
CS
ONLY IF SCLK COUNT = N 16
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SPI (CPOL = 1, CPHA = 1) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
✕
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
ONLY IF SCLK COUNT = N 16
CS
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 3. MICROWIRE and SPI (CPOL = 0, CPHA = 0 or CPOL = 1, CPHA = 1) DAC Writes
DSP
SPI OR QSPI
MAX5290–
MAX5295
MAX5290–
MAX5295
V
DGND
V
DGND
SS
SS
DSP
DSP
TCLK, SCLK, OR CLKX
DT OR DX
SCK
MOSI
SCLK
SCLK
DIN
DIN
TFS OR FSX
CS
SS OR I/O
CS
DSP OR SPI (CPOL = 0, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
✕
CS
ONLY IF SCLK COUNT = N 16
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D4
D3
D2
D1
D0
DSP OR SPI (CPOL = 1, CPHA = 0) 8-BIT CONTROL DATA OR 12-BIT DAC DATA WRITE:
COMMAND TAKES EFFECT HERE
ONLY IF SCLK COUNT = N 16
✕
CS MUST REMAIN LOW BETWEEN BYTES ON A 16-BIT WRITE OPERATION
CS
SCLK
DIN
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D3
D2
D1
D0
Figure 4. DSP and SPI (CPOL = 0, CPHA = 1 or CPOL = 1, CPHA = 0) DAC Writes
______________________________________________________________________________________ 17
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
18 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
______________________________________________________________________________________ 19
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
CS
20 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Default register values at power-up correspond to the
Advanced Feature
Programming Commands
Refer to the Programmer’s Handbook for details.
state of PU, e.g. input and DAC registers are set to
800hex if PU is floating, FFFhex if PU = DV , and
DD
000hex if PU= DGND.
Select Bits (MA, MB)
The select bits allow synchronous updating of any com-
bination of channels. The select bits command the
loading of the DAC register from the input register of
each channel. Set the select bit M_ = 1 to load the DAC
register “_” with data from the input register “_”, where
“_” is replaced with A or B depending on the selected
channel. Setting the select bit to M_ = 0 results in no
action for that channel (Table 6).
DAC Programming Examples:
To load input register A from the shift register, leaving
DAC register A unchanged (DAC output unchanged),
use the command in Table 3.
The MAX5290–MAX5295 can load DAC register A from
the shift register, leaving input register A unchanged,
by using the command in Table 4.
To load input register A and DAC register A simultane-
ously from the shift register, use the command in Table 5.
For the 10-bit and 8-bit versions, set sub-bits = 0 for
best performance.
Table 3. Load Input Register A from Shift Register
DATA
CONTROL BITS
DATA BITS
D6 D5
DIN
0
0
0
0
D11
D10
D9
D8
D7
D4
D4
D3/0
D3/0
D2/0
D2/0
D1/0
D1/0
D0/0
D0/0
Table 4. Load DAC Register A from Shift Register
DATA
CONTROL BITS
DATA BITS
D6 D5
DIN
0
0
0
1
D11
D10
D9
D8
D7
Table 5. Load Input Register A and DAC Register A from Shift Register
DATA
CONTROL BITS
DATA BITS
DIN
0
0
1
0
D11
D10
D9
D8
D7
D6 D5
D4
D3/0
D2/0
D1/0
MB
D0/0
MA
Table 6. Select Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
0
X
X
X
X
X
X
X
X
X = Don’t care.
Table 7. Select Bits Programming Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
0
X
X
X
X
X
X
X
X
1
0
X = Don’t care.
______________________________________________________________________________________ 21
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Select Bits Programming Example:
Shutdown-Mode Bits (PDA0, PDA1, PDB0, PDB1)
To load DAC register B from input register B while
keeping channel A unchanged, set MB = 1 and MA =
0, as in the command in Table 7.
Use the shutdown-mode bits to shut down each DAC
independently. Set PD_0 and PD_1 according to Table
8 to select the shutdown mode for DAC_, where “_” is
replaced with A or B depending on the selected chan-
nel. The three possible states for unity-gain versions
are 1) normal operation, 2) shutdown with 1kΩ output
impedance, and 3) shutdown with 100kΩ output imped-
ance. The three possible states for force-sense ver-
sions are 1) normal operation, 2) shutdown with 1kΩ
output impedance, and 3) shutdown with high-imped-
ance output. Table 9 shows the command for writing to
the shutdown mode bits.
Table 8. Shutdown-Mode Bits
PD_1
PD_0
DESCRIPTIONS
Shutdown with 1kΩ termination to ground
on DAC_ output.
0
0
Shutdown with 100kΩ termination to
ground on DAC_ output for unity-gain
versions. Shutdown with high-impedance
output for force-sense versions.
Shutdown-Mode Bits Write Example:
0
1
To put a unity-gain version’s DACA into shutdown
mode with internal 1kΩ termination to ground and
DACB into the shutdown mode with the internal 100kΩ
termination to ground, use the command in Table 10
(applicable to unity-gain output only).
1
1
0
1
Ignored.
DAC_ is powered up in its normal operating
mode.
To read back the shutdown-mode bits, use the com-
mand in Table 11.
Table 9. Shutdown-Mode Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
1
0
X
X
X
X
X
PDB1 PDB0 PDA1 PDA0
X = Don’t care.
Table 10. Shutdown-Mode Bits Write Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
0
1
0
X
X
X
X
X
0
1
0
0
X = Don’t care.
Table 11. Shutdown-Mode Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
X
1
X
1
X
0
X
0
X
1
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUTRB
X = Don’t care.
X
PDB1 PDB0 PDA1 PDA0
Table 12. Settling-Time-Mode Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
1
0
X
X
X
X
X
X
X
SPDB SPDA
X = Don’t care.
22 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Settling-Time-Mode Bits (SPDA, SPDB)
The settling-time-mode bits select the settling time
(FAST mode or SLOW mode) of the MAX5290–
MAX5295. Set SPD_ = 1 to select FAST mode or set
SPD_ = 0 to select SLOW mode, where “_” is replaced
by A or B, depending on the selected channel (see
Table 12). FAST mode provides a 3µs maximum set-
tling time and SLOW mode provides a 10µs maximum
settling time. Default settling-time mode bits are [0, 0]
(SLOW mode for both DACs).
Settling-Time-Mode Write Example:
To configure DACA into FAST mode and DACB into
SLOW mode, use the command in Table 13.
To read back the settling-time-mode bits, use the com-
mand in Table 14.
CPOL and CPHA Control Bits
The CPOL and CPHA control bits of the
MAX5290–MAX5295 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the CPOL = 0
and CPHA = 0 or set CPOL = 1 and CPHA = 1 for
MICROWIRE and SPI applications requiring the clocking
of data in on the rising edge of SCLK. Set the CPOL = 0
Table 13. Settling-Time-Mode Write Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
1
0
X
X
X
X
X
X
X
0
1
X = Don’t care.
Table 14. Settling-Time-Mode Read Command
DATA
DIN
CONTROL BITS
DATA BITS
1
X
1
X
1
X
0
X
1
X
1
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUTRB
X = Don’t care.
X
SPDB SPDA
Table 15. CPOL and CPHA Bits
CPOL
CPHA
DESCRIPTION
Default values at power-up when DSP is connected to DV . Data is clocked in on the rising edge
of SCLK.
DD
0
0
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
0
1
1
1
0
1
Data is clocked in on the falling edge of SCLK.
Data is clocked in on the rising edge of SCLK.
Table 16. CPOL and CPHA Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
1
0
0
0
0
X
X
X
X
X
X
CPOL CPHA
X = Don’t care.
Table 17. CPOL and CPHA Read Command
DATA
DIN
CONTROL BITS
DATA BITS
1
X
1
X
1
X
1
X
0
X
0
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUTRB
X
CPOL CPHA
X = Don’t care.
______________________________________________________________________________________ 23
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
and CPHA = 1 or set CPOL = 1 and CPHA = 0 for DSP
and SPI applications requiring the clocking of data in on
the falling edge of SCLK (refer to the Programmer’s
Handbook and see Table 15 for details). At power-up, if
Table 19 shows how UPIO1 and UPIO2 are selected for
configuration. The UP0–UP3 bits select the desired
functions for UPIO1 and/or UPIO2 (see Table 22).
Default states of UP10_ are high impedance. If using
DSP = DV , the default value of CPHA is zero and if
DD
UP10_, connect 10kΩ pullup resistors from each UPIO
DSP = DGND, the default value of CPHA is one. The
default value of CPOL is zero at power-up.
pin to DV
.
DD
UPIO Programming Example:
To set only UPIO1 as LDAC and leave UPIO2
unchanged, write the command in Table 20.
To write to the CPOL and CPHA bits, use the command
in Table 16.
To read back the device’s CPOL and CPHA bits, use
the command in Table 17.
The UPIO selection and configuration bits can be read
back from the MAX5290–MAX5295 when UPIO1 or
UPIO2 is configured as a DOUTRB output. Table 21
shows the read-back data format for the UPIO bits.
Writing a 1110 101X XXXX XXXX initiates a read operation
of the UPIO bits. The data is clocked out starting on the
9th clock cycle of the sequence. UP3-2 through UP0-2
provide the UP3–UP0 configuration bits for UPIO2 (see
Table 22), and UP3-1 through UP0-1 provide the
UP3–UP0 configuration bits for UPIO1.
UPIO Bits (UPSL1, UPSL2, UP0–UP3)
The MAX5290–MAX5295 provide two user-programma-
ble input/output (UPIO) ports: UPIO1 and UPIO2. These
ports have 15 possible configurations, as shown in
Table 22. UPIO1 and UPIO2 can be programmed inde-
pendently or simultaneously by writing to the UPSL1,
UPSL2, and UP0–UP3 bits (see Table 18).
Table 18. UPIO Write Command
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
0
0
X
UPSL2 UPSL1 UP3
UP2
UP1
UP0
X
X
X = Don’t care.
Table 19. UPIO Selection Bits (UPSL1 and UPSL2)
UPSL2
UPSL1
UPIO PORT SELECTED
None selected
0
0
1
1
0
1
0
1
UPIO1 selected
UPIO2 selected
Both UPIO1 and UPIO2 selected
Table 20. UPIO Programming Example
DATA
CONTROL BITS
DATA BITS
DIN
1
1
1
0
1
0
0
X
0
1
0
0
0
0
X
X
X
X = Don’t care.
Table 21. UPIO Read Command
DATA
DIN
CONTROL BITS
DATA BITS
1
X
1
X
1
X
0
X
1
X
0
X
1
X
X
X
X
X
X
X
X
DOUTRB
X
X
UP3-2 UP2-2 UP1-2 UP0-2 UP3-1 UP2-1 UP1-1 UP0-1
X = Don’t care.
24 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
User-Programmable Input/Output (UPIO)
Configuration
Drive LDAC low to asynchronously load the DAC regis-
ters from their corresponding input registers (DACs that
are in shutdown remain shut down). The LDAC function
does not require any activity on CS, SCLK, or DIN. If
LDAC is brought low coincident with a rising edge of
CS, (which executes a serial command modifying the
value of either DAC input register), then LDAC must
remain asserted for at least 120ns following the CS ris-
ing edge. This requirement applies only to serial com-
mands that modify the value of the DAC input registers.
See Figures 5 and 6 for timing details.
Table 22 lists the possible configurations for UPIO1 and
UPIO2. UPIO1 and UPIO2 use the selected function
when configured by the UP3–UP0 configuration bits.
LDAC
LDAC controls loading of the DAC registers. When
LDAC is high, the DAC registers are latched, and any
change in the input registers does not affect the con-
tents of the DAC registers or the DAC outputs. When
LDAC is low, the DAC registers are transparent, and the
values stored in the input registers are fed directly to the
DAC registers, and the DAC outputs are updated.
Table 22. UPIO Configuration Register Bits (UP3–UP0)
UPIO CONFIGURATION BITS
FUNCTION
DESCRIPTION
UP3
UP2
UP1
UP0
Active-Low Load DAC Input. Drive low to asynchronously load all DAC registers
with data from input registers.
0
0
0
0
LDAC
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
SET
MID
CLR
PDL
Active-Low Input. Drive low to set all input and DAC registers to full scale.
Active-Low Input. Drive low to set all input and DAC registers to midscale.
Active-Low Input. Drive low to set all input and DAC registers to zero scale.
Active-Low Power-Down Lockout Input. Drive low to disable software shutdown.
Reserved This mode is reserved. Do not use.
Active-Low 1kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. Drive
SHDN1K low to pull OUTA and OUTB to AGND with 1kΩ.
0
1
1
0
SHDN1K
Active-Low 100kΩ Shutdown Input. Overrides PD_1 and PD_0 settings. For the
MAX5290/MAX5292/MAX5294, drive SHDN100K low to pull OUTA and OUTB to
AGND with 100kΩ. For the MAX5291/MAX5293/MAX5295, drive SHDN100K low to
leave OUTA and OUTB high impedance.
0
1
1
1
SHDN100K
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
DOUTRB Data Read-Back Output
DOUTDC0 Mode 0 Daisy-Chain Data Output. Data is clocked out on the falling edge of SCLK.
DOUTDC1 Mode 1 Daisy-Chain Data Output. Data is clocked out on the rising edge of SCLK.
GPI
General-Purpose Logic Input
GPOL
GPOH
General-Purpose Logic-Low Output
General-Purpose Logic-High Output
Toggle Input. Toggles DAC outputs between data in input registers and data in
DAC registers. Drive low to set all DAC outputs to values stored in input registers.
Drive high to set all DAC outputs to values stored in DAC registers.
1
1
1
1
1
1
0
1
TOGG
FAST/SLOW Settling-Time Mode Input. Drive low to select FAST mode (3µs) or
drive high to select SLOW settling mode (10µs). Overrides the SPDA and SPDB
settings.
FAST
______________________________________________________________________________________ 25
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
SET, MID, CLR
t
LDL
The SET, MID, and CLR signals force the DAC outputs
to full scale, midscale, or zero scale (Figure 5). These
signals cannot be active at the same time.
LDAC
TOGG
The active-low SET input forces the DAC outputs to full
scale when SET is low. When SET is high, the DAC out-
puts follow the data in the DAC registers.
PDL
The active-low MID input forces the DAC outputs to mid-
scale when MID is low. When MID is high, the DAC out-
puts follow the data in the DAC registers.
t
CMS
CLR,
MID, OR
SET
The active-low CLR input forces the DAC outputs to zero
scale when CLR is low. When CLR is high, the DAC out-
puts follow the data in the DAC registers.
t
S
0.5 LSB
V
OUT_
If CLR, MID, or SET signals go low in the middle of a write
command, reload the data to ensure accurate results.
PDL AFFECTS DAC OUPTUTS (V
) ONLY IF DACS WERE PREVIOUSLY SHUT DOWN.
OUT_
Figure 5. Asynchronous Signal Timing
Power-Down Lockout (PDL)
The PDL active-low software-shutdown lockout input
overrides (not overwrites), the PD_0 and PD_1 shut-
down mode bits. PDL cannot be active at the same
time as SHDN1K or SHDN100K (see the Shutdown
Mode (SHDN1K, SHDN100K) section).
END OF
CYCLE*
t
GP
GPO_
LDAC
If the PD_0 and PD_1 bits command the DAC to shut
down prior to PDL going low, the DAC returns to shut-
down mode immediately after PDL goes high, unless
the PD_0 and PD_1 bits are changed in the meantime.
t
LDS
Shutdown Mode (SHDN1K, SHDN100K)
The SHDN1K and SHDN100K are active-low signals
that override (not overwrite) the PD_1 and PD_0 bit set-
tings. For the MAX5290/MAX5292/MAX5294, drive
SHDN1K low to select shutdown mode with OUTA and
OUTB internally terminated with 1kΩ to ground, or drive
SHDN100K low to select shutdown with an internal
100kΩ termination. For the MAX5291/MAX5293/
MAX5295, drive SHDN1K low for shutdown with 1kΩ
output termination, or drive SHDN100K low for shut-
down with high-impedance outputs.
*END-OF-CYCLE REPRESENTS THE RISING EDGE OF CS OR THE 16TH
ACTIVE CLOCK EDGE, DEPENDING ON THE MODE OF OPERATION.
Figure 6. GPO_ and LDAC Signal Timing
•
The source of read-back data on DOUTRB is the
DOUT register. Daisy-chain DOUTDC_ data comes
directly from the shift register.
•
•
Read-back data on DOUTRB is only present after a
DAC read command. Daisy-chain data is present on
DOUTDC_ for any DAC write after the first 16 bits
are written.
Data Output (DOUTRB, DOUTDC0, DOUTDC1)
UPIO1 and UPIO2 can be configured as serial data
outputs, DOUTRB (data out for read back), DOUTDC0
(data out for daisy-chaining, mode 0), and DOUTDC1
(data out for daisy-chaining, mode 1). The differences
between DOUTRB and DOUTDC0 (or DOUTDC1) are
as follows:
The DOUTRB idle state (CS = high) for read back is
high impedance. Daisy-chain DOUTDC_ idles high
when inactive to avoid floating the data input in the
next device in the daisy-chain.
See Figures 1 and 2 for timing details.
26 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
GPI, GPOL, GPOH
UPIO1 and UPIO2 can each be configured as a gener-
al-purpose logic input (GPI), a general-purpose logic-
low output (GPOL), or general-purpose logic-high
output (GPOH).
LF1 is one, then a falling edge has occurred on the
UPIO1 or UPIO2 input since the last read or reset. If
LR2 or LR1 is one, then a rising edge has occurred
since the last read or reset.
GPOL outputs a constant logic low, and GPOH outputs
a constant logic high (see Figure 6).
The GPI can detect interrupts from µPs or microcon-
trollers. It provides three functions:
TOGG
Use the TOGG input to toggle a DAC output between
the values in the input register and DAC register. A
delay of greater than 100ns from the end of the previ-
ous write command is required before the TOGG signal
can be correctly switched between the new value and
the previously stored value. When TOGG = 0, the out-
put follows the information in the input registers. When
TOGG = 1, the output follows the information in the
DAC register (Figure 5).
1) Sample the signal at GPI at the time of the read
(RTP1 and RTP2).
2) Detect whether or not a falling edge has occurred
since the last read or reset (LF1 and LF2).
3) Detect whether or not a rising edge has occurred
since the last read or reset (LR1 and LR2).
RTP1, LF1, and LR1 represent the data read from
UPIO1. RTP2, LF2, and LR2 represent the data read
from UPIO2.
FAST
The MAX5290–MAX5295 have two settling-time-mode
options: FAST (3µs max at 12 bits) and SLOW (6µs max
at 12 bits). To select the FAST mode, drive FAST low,
and to select SLOW mode, drive FAST high. This over-
rides (not overwrites) the SPDA and SPDB bit settings.
To issue a read command for the UPIO configured as
GPI, use the command in Table 23.
Once the command is issued, RTP1 and RTP2 provide
the real-time status (0 or 1) of the inputs at UPIO1 or
UPIO2, respectively, at the time of the read. If LF2 or
Table 23. GPI Read Command
DATA
DIN
CONTROL BITS
DATA BITS
1
X
1
X
1
X
1
X
0
X
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUTRB
X = Don’t care.
RTP2
LF2
LR2
RTP1
LF1
LR1
Table 24. Unipolar Code Table (Gain = +1)
DAC CONTENTS
ANALOG OUTPUT
MSB
1111
1000
1000
0111
0000
0000
LSB
1111
0001
0000
1111
0001
0000
DAC_
REF
OUT_
= V x CODE / 4096
1111
0000
0000
1111
0000
0000
+V
+V
(4095 / 4096)
(2049 / 4096)
REF
REF
V
OUT_
REF
CODE IS THE DAC_ INPUT
CODE (0 TO 4095 DECIMAL).
+V
(2048 / 4096) = V
/ 2
REF
REF
MAX5290
+V
(2047 / 4096)
REF
+V
(1 / 4096)
0
REF
Figure 7. Unipolar Output Circuit
______________________________________________________________________________________ 27
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Configurable Output Gain
Applications Information
The MAX5291/MAX5293/MAX5295 have force-sense out-
puts, which provide a connection directly to the inverting
terminal of the output op amp, yielding the most flexibility.
The advantage of the force-sense output is that specific
gains can be set externally for a given application. The
gain error for the MAX5291/MAX5293/MAX5295 is speci-
fied in a unity-gain configuration (op-amp output and
inverting terminals connected) and additional gain error
results from external resistor tolerances. The force-sense
DACs allow many useful circuits to be created with only a
few simple external components.
Unipolar Output
Figure 7 shows the unity gain of the MAX5290 in a
unipolar output configuration. Table 24 lists the unipolar
output codes.
Bipolar Output
The MAX5290 outputs can be configured for bipolar
operation, as shown in Figure 8. The output voltage is
given by the following equation:
V
OUT_
= V
x (CODE - 2048) / 2048
REF
where CODE represents the numeric value of the
DAC’s binary input code (0 to 4095 decimal). Table 25
shows digital codes and the corresponding output volt-
age for the Figure 8 circuit.
An example of a custom, fixed gain using the
MAX5291’s force-sense output is shown in Figure 9. In
this example, the external reference is set to 1.25V, and
the gain is set to +1.1V/V with external discrete resis-
tors to provide an approximate 0 to 1.375V DAC output
voltage range.
Table 25. Bipolar Code Table (Gain = +1)
V
OUT_
= [(0.5 x V
x CODE) / 4096] x [1 + (R2 / R1)]
REF
DAC CONTENTS
ANALOG OUTPUT
where CODE represents the numeric value of the
DAC’s binary input code (0 to 4095 decimal).
MSB
1111
1000
1000
0111
0000
0000
LSB
1111
0001
0000
1111
0001
0000
1111
0000
0000
1111
0000
0000
+V
(2047 / 2048)
REF
In this example, if R2 = 12kΩ and R1 = 10kΩ, set the
gain = 1.1V/V:
+V
(1 / 2048)
0
REF
V
OUT_
= [(0.5 x 1.25V x CODE) / 4096] x 2.2
+V
-V
(1 / 2048)
REF
(2047 / 2048)
REF
-V
(2048 / 2048) = -V
REF
REF
10kΩ
10kΩ
V+
DAC_
REF
OUT_
V
R2 = 12kΩ
OUT_
REF
DAC_
0.1%
MAX5291
25ppm
OUT_
FB_
V-
R1 = 10kΩ
0.1%
25ppm
MAX5290
Figure 8. Bipolar Output Circuit
Figure 9. Configurable Output Gain
28 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
niques, such as a multilayer board with a low-induc-
tance ground plane. Wire-wrapped boards and sockets
are not recommended. For optimum system perfor-
mance, use printed circuit (PC) boards with separate
analog and digital ground planes. Connect the two
ground planes together at the low-impedance power-
supply source.
Power-Supply and Layout Considerations
Bypass the analog and digital power supplies with a
10µF capacitor in parallel with a 0.1µF capacitor to ana-
log ground (AGND) and digital ground (DGND) (see
Figure 10). Minimize lead lengths to reduce lead induc-
tance. If noise is an issue, use shielding and/or ferrite
beads to increase isolation.
Using separate power supplies for AV
improves noise immunity. Connect AGND and DGND at
the low-impedance power-supply source (see Figure 11).
and DV
DD
Digital and AC transient signals coupling to AGND cre-
ate noise at the output. Connect AGND to the highest
quality ground available. Use proper grounding tech-
DD
AV
DV
DD
DD
0.1µF
10µF
DV
0.1µF
10µF
ANALOG SUPPLY
AV AGND
DIGITAL SUPPLY
DV DGND
V
REF
DD
DD
AV
DD
DD
REF
0.1µF*
10µF*
OUTA
MAX5290–MAX5295
CS
SCLK
DIN
FBA
10µF
10µF
MAX5291/
MAX5293/
MAX5295
ONLY
FBB
PU
0.1µF
0.1µF
OUTB
DSP
UPIO1
UPIO2
AV
AGND
DV
DGND
DV
DD
DGND
DIGITAL
CIRCUITRY
DD
DD
AGND**
DGND**
MAX5290–MAX5295
*REMOVE BYPASS CAPACITORS ON REF FOR AC-REFERENCE INPUTS.
**CONNECT ANALOG AND DIGITAL GROUND PLANES AT THE
LOW-IMPEDANCE POWER-SUPPLY SOURCE.
Figure 11. Separate Analog and Digital Power Supplies
Figure 10. Bypassing Power Supplies and Reference
______________________________________________________________________________________ 29
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Pin Configurations
TOP VIEW
UPIO2
1
2
3
4
5
6
7
8
16 PU
UPIO1
DSP
DIN
1
2
3
4
5
6
7
14 UPIO2
13 PU
UPIO1
DSP
DIN
15 OUTA
14 FBA
13 REF
12 FBB
11 OUTB
12 OUTA
11 REF
MAX5291
MAX5293
MAX5295
CS
MAX5290
MAX5292
MAX5294
CS
SCLK
10 OUTB
SCLK
DV
9
8
AV
DD
DD
DV
10 AV
DD
DD
DGND
AGND
DGND
9
AGND
16 TSSOP
14 TSSOP
16 15 14 13
16 15 14 13
DSP
1
2
3
4
DSP
1
2
3
4
12 OUTA
11 N.C.
10 REF
12 FBA
11 REF
10 FBB
DIN
CS
DIN
CS
MAX5290
MAX5292
MAX5294
MAX5291
MAX5293
MAX5295
SCLK
9
OUTB
SCLK
9
OUTB
5
6
7
8
5
6
7
8
(4mm x 4mm) THIN QFN
(4mm x 4mm) THIN QFN
Chip Information
Selector Guide
TRANSISTOR COUNT: 16,758
OUTPUT
INL
RESOLUTION
(LSBs
BUFFER
PART
PROCESS: BiCMOS
(BITS)
CONFIGURATION
MAX)
MAX5290AEUD*
MAX5290BEUD
MAX5290AETE*
MAX5290BETE
MAX5291AEUE*
MAX5291BEUE
MAX5291AETE*
MAX5291BETE
MAX5292EUD
MAX5292ETE
MAX5293EUE
MAX5293ETE
MAX5294EUD
MAX5294ETE
MAX5295EUE
MAX5295ETE
Unity Gain
Unity Gain
12
12
12
12
12
12
12
12
10
10
10
10
8
1
4
Unity Gain
1
Unity Gain
4
Force Sense
Force Sense
Force Sense
Force Sense
Unity Gain
1
4
1
4
1
Unity Gain
1
Force Sense
Force Sense
Unity Gain
1
1
0.5
0.5
0.5
0.5
Unity Gain
8
Force Sense
Force Sense
8
8
*Future product—contact factory for availability. Specifications
are preliminary.
30 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
______________________________________________________________________________________ 31
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
32 ______________________________________________________________________________________
Buffered, Fast-Settling, Dual, 12-/10-/8-Bit,
Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 33
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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