MAX530ACNG+_技术文档

19-0168; Rev 3; 7/95

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

♦ Buffered Voltage Output

♦ Internal 2.048V Voltage Reference

The MAX530 is a low-power, 12-bit, voltage-output digi-

tal-to-analog converter (DAC) that uses single +5V or

dual ±5V supplies. This device has an on-chip voltage

reference plus an output buffer amplifier. Operating cur-

rent is only 250µA from a single +5V supply, making it

ideal for portable and battery-powered applications. In

addition, the SSOP (Shrink-Small-Outline-Package) mea-

sures only 0.1 square inches, using less board area than

an 8-pin DIP. 12-bit resolution is achieved through laser

trimming of the DAC, op amp, and reference. No further

adjustments are necessary.

♦ Operates from Single +5V or Dual ±5V Supplies

♦ Low Power Consumption:

250µA Operating Current

40µA Shutdown-Mode Current

♦ SSOP Package Saves Space

♦ Relative Accuracy: ±¹₂LSB Max Over

/

Temperature

♦ Guaranteed Monotonic Over Temperature

Internal gain-setting resistors can be used to define a

DAC outp ut volta g e ra ng e of 0V to + 2.048V, 0V to

+4.096V, or ±2.048V. Four-quadrant multiplication is pos-

sible without the use of external resistors or op amps. The

parallel logic inputs are double buffered and are compati-

ble with 4-bit, 8-bit, and 16-bit microprocessors. For DACs

with similar features but with a serial data interface, refer

to the MAX531/MAX538/MAX539 data sheet.

♦ 4-Quadrant Multiplication with No External

Components

♦ Power-On Reset

♦ Double-Buffered Parallel Logic Inputs

______________Ord e rin g In fo rm a t io n

ERROR

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

1

/

________________________Ap p lic a t io n s

Battery-Powered Data-Conversion Products

Minimum Component-Count Analog Systems

Digital Offset/Gain Adjustment

MAX530ACNG

MAX530BCNG

0°C to +70°C 24 Narrow Plastic DIP

±

2

±1

1

/

±

MAX530ACWG 0°C to +70°C 24 Wide SO

MAX530BCWG 0°C to +70°C 24 Wide SO

2

±1

1

/

±

MAX530ACAG

MAX530BCAG

MAX530BC/D

0°C to +70°C 24 SSOP

0°C to +70°C Dice*

Industrial Process Control

±1

Arbitrary Function Generators

Automatic Test Equipment

Ordering Information continued on last page.

* Dice are tested at T = +25°C, DC parameters only.

Microprocessor-Controlled Calibration

A

________________Fu n c t io n a l Dia g ra m

__________________P in Co n fig u ra t io n

REFOUT

18

REFIN ROFS

TOP VIEW

13

22

D1/D9

D2/D10

D3/D11

D4

D0/D8

1

2

24

21

20

RFB

2.048V

REFERENCE

V

DD

23

22

ROFS

RFB

3

17

14

VOUT

REFGND

AGND

DAC LATCH

4

21

20

19

18

17

MAX530

D5

D6

D7

A0

VOUT

23

12

19

5

POWER-ON

RESET

V

DD

V

SS

DGND

6

MAX530

V

SS

REFOUT

REFGND

LDAC

7

15

8

12-BIT DAC LATCH

CLR

A0

8

9

A1

WR

CONTROL

LOGIC

9

16

15

14

13

NBL

INPUT

LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

11

10

16

CS

CLR

10

11

12

WR

CS

AGND

REFIN

LDAC

DGND

24

D0/D8

1

2

3

4

D4

5 6 7

D6

D2/D10

D1/D9

DIP/SO/SSOP

D3/D11 D5 D7

________________________________________________________________ Maxim Integrated Products

1

Ca ll t o ll fre e 1 -8 0 0 -9 9 8 -8 8 0 0 fo r fre e s a m p le s o r lit e ra t u re .

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

ABSOLUTE MAXIMUM RATINGS

VOUT to AGND (Note 1) .............................................. V

V

SS, DD

V

DD

to DGND and V to AGND ................................-0.3V, +6V

DD

Continuous Current, Any Input ........................................±20mA

V

SS

to DGND and V to AGND .................................-6V, +0.3V

SS

Continuous Power Dissipation (T = +70°C)

A

V

DD

to V ............................................................... -0.3V, +12V

SS

Narrow Plastic DIP (derate 13.33mW/°C above +70°C)......1067mW

Wide SO (derate 11.76mW/°C above +70°C) .......... 941mW

SSOP (derate 8.00mW/°C above +70°C) ..................640mW

Operating Temperature Ranges:

MAX530_C_ _ ...................................................0°C to +70°C

MAX530_E_ _ ................................................-40°C to +85°C

Storage Temperature Range .............................-65°C to +165°C

Lead Temperature (soldering, 10sec ) .......................... +300°C

AGND to DGND........................................................-0.3V, +0.3V

REFGND to AGND........................................-0.3V, (V + 0.3V)

Digital Input Voltage to DGND ................... -0.3V, (V + 0.3V)

DD

REFIN.................................................(V - 0.3V), (V + 0.3V)

SS

MAX530

REFOUT .............................................(V - 0.3V), (V + 0.3V)

SS

REFOUT to REFGND................................... -0.3V, (V + 0.3V)

RFB ...................................................(V - 0.3V), (V + 0.3V)

SS

ROFS .................................................(V - 0.3V), (V + 0.3V)

SS

Note 1: The output may be shorted to V , V , DGND, or AGND if the continuous package power dissipation and current ratings

DD SS

are not exceeded. Typical short-circuit currents are 20mA.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS—Single +5V Supply

(V

DD

= 5V ±10%, V = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 33µF,

REFOUT

SS

R

= 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

STATIC PERFORMANCE

Resolution

N

12

Bits

MAX530AC/AE

±0.5

LSB

±1

Relative Accuracy

INL

DNL

V

= 5V (Note 2)

DD

MAX530BC/BE

Differential Nonlinearity

Unipolar Offset Error

Guaranteed monotonic

= 5V

±1

8

LSB

V

OS

V

MAX530_C/E

0

1

3

DD

Unipolar Offset

Temperature Coefficient

TCV

ppm/°C

LSB/V

OS

Unipolar Offset-Error

Power-Supply Rejection

PSRR

GE

4.5V ≤ V ≤ 5.5V (Note 3)

0.4

1

DD

DAC latch = all 1s,

VOUT < V - 0.4V

DD

Gain Error (Note 2)

MAX530_C/E

±1

LSB

(Note 2)

Gain-Error Temperature Coefficient

Gain-Error Power-Supply Rejection

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range

1

ppm/°C

LSB/V

PSRR

4.5V ≤ V ≤ 5.5V (Note 3)

0.4

1

DD

0

2

V

DD

- 0.4

V

kΩ

Ω

Resistive Load

VOUT = 2V, load regulation ≤ ±1LSB

DC Output Impedance

0.2

20

Short-Circuit Current

I

SC

mA

REFERENCE INPUT (REFIN)

Reference Input Range

0

V

DD

- 2

V

Reference Input Resistance

Reference Input Capacitance

AC Feedthrough

Code dependent, minimum at code 555hex

Code dependent (Note 4)

(Note 5)

40

10

kΩ

pF

dB

50

-80

2

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)

(V

= 5V ±10%, V = 0V, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT, C

= 33µF,

DD

SS

REFOUT

R

= 10kΩ, C = 100pF, T = T

to T

, unless otherwise noted.)

CONDITIONS

L

A

MIN

MAX

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

REFERENCE OUTPUT (REFOUT)

T

= +25°C

2.024

2.017

2.013

2.048

2.072

2.079

2.083

2

A

Reference Tolerance

V

DD

= 5.0V

MAX530BC

MAX530BE

V

REFOUT

Reference Output Resistance

Power-Supply Rejection Ratio

Noise Voltage

R

(Note 8)

4.5V ≤ V

Ω

REFOUT

PSRR

≤ 5.5V

300

µV/V

µVp-p

DD

e

0.1Hz to 10kHz

MAX530AC/AE

MAX530BC/BE

400

30

n

50

Temperature Coefficient

ppm/°C

µF

30

Minimum Required External

Capacitor

C

3.3

MIN

DYNAMIC PERFORMANCE

Voltage Output Slew Rate

Voltage Output Settling Time

Digital Feedthrough

T

= +25°C

0.15

0.25

25

5

V/µs

µs

A

To ±0.5LSB, VOUT = 2V

WR = V , digital inputs all 1s to all 0s

DD

nV-s

Unity gain (Note 5)

Gain = 2 (Note 5)

68

Signal-to-Noise Plus

Distortion Ratio

SINAD

dB

DIGITAL INPUTS (D0-D7, LDAC, CLR, CS, WR, A0, A1)

Logic High Input

V

2.4

4.5

V

IH

Logic Low Input

V

IL

0.8

±1

Digital Leakage Current

Digital Input Capacitance

POWER SUPPLIES

Positive Supply-Voltage Range

Positive Supply Current

SWITCHING CHARACTERISTICS

Address to WR Setup

Address to WR Hold

CS to WR Setup

V

= 0V or V

µA

pF

IN

DD

8

V

DD

(Note 6)

Outputs unloaded, all digital inputs = 0V or V

5.5

V

I

DD

250

400

µA

DD

t

5

ns

AWS

t

AWH

t

0

CWS

CS to WR Hold

t

0

CWH

t_DS

Data to WR Setup

45

0

t_DH

Data to WR Hold

WR Pulse Width

t

45

WR

LDAC Pulse Width

t

LDAC

CLR Pulse Width

t

CLR

Internal Power-On Reset

Pulse Width

t

(Note 4)

1.3

10

µs

POR

_______________________________________________________________________________________

3

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies

(V = 5V ±10%, V = -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT,

DD

SS

C

= 33µF, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

REFOUT

L

A

MIN

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX UNITS

STATIC PERFORMANCE

Resolution

N

12

Bits

MAX530

MAX530AC/AE

MAX530BC/BE

±0.5

LSB

±1.5

Relative Accuracy

INL

DNL

V

= 5V, V = -5V

DD SS

Differential Nonlinearity

Bipolar Offset Error

Guaranteed monotonic

= 5V, V = -5V

±1

±8

LSB

V

OS

V

MAX530_C/E

0

3

DD

SS

Bipolar Offset

Temperature Coefficient

TCV

ppm/°C

LSB/V

OS

Bipolar Offset-Error

Power-Supply Rejection

4.5V ≤ V ≤ 5.5V

DD

PSRR

0.4

1

-5.5V ≤ V ≤ -4.5V (Note 3)

SS

Gain Error

MAX530_C/E

±1

LSB

Gain-Error Temperature Coefficient

Gain-Error Power-Supply Rejection

DAC VOLTAGE OUTPUT (VOUT)

Output Voltage Range

TC

1

ppm/°C

LSB/V

PSRR

4.5V ≤ V ≤ 5.5V, -5.5V ≤ V ≤ -4.5V (Note 3)

0.4

1

DD

SS

V

SS

+ 0.4

V

DD

- 0.4

V

kΩ

Ω

Resistive Load

VOUT = 2V, load regulation ≤ ±1LSB

2

DC Output Impedance

0.2

20

Short-Circuit Current

I

SC

mA

REFERENCE INPUT (REFIN)

Reference Input Range

V

SS

+ 2

V

DD

- 2

V

Reference Input Resistance

Reference Input Capacitance

AC Feedthrough

Code dependent, minimum at code 555hex

Code dependent (Note 4)

(Note 5)

40

10

kΩ

pF

dB

50

-80

REFERENCE OUTPUT (REFOUT)—Specifications are identical to those under Single +5V Supply

DYNAMIC PERFORMANCE—Specifications are identical to those under Single +5V Supply

DIGITAL INPUTS (D0-D7, LDAC, CLR, CS, WR, A0, A1)—Specifications are identical to those under Single +5V Supply

POWER SUPPLIES

Positive Supply Voltage

Negative Supply Voltage

Positive Supply Current

Negative Supply Current

V

(Note 6)

(Note 7)

4.5

5.5

-4.5

400

200

V

DD

V

SS

-5.5

I

DD

Outputs unloaded, all digital inputs = 0V or V

250

150

µA

DD

I

SS

Outputs unloaded, all digital inputs = 0V or V

DD

SWITCHING CHARACTERISTICS—Specifications are identical to those under Single +5V Supply

4

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

ELECTRICAL CHARACTERISTICS—Dual ±5V Supplies (continued)

(V = 5V ±10%, V = -5V ±10%, AGND = DGND = REFGND = 0V, REFIN = 2.048V (external), RFB = ROFS = VOUT,

DD

SS

C

= 33µF, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.)

MAX

REFOUT

L

A

MIN

Note 2: In single supply, INL and GE are calculated from code 11 to code 4095.

Note 3: Zero Code, Bipolar and Gain Error PSRR are input referred specifications. In Unity Gain, the specification is 500µV.

In Gain = 2 and Bipolar modes, the specification is 1mV.

Note 4: Guaranteed by design.

Note 5: REFIN = 1kHz, 2.0Vp-p.

Note 6: For specified performance, V = 5V ±10% is guaranteed by PSRR tests.

DD

Note 7: For specified performance, V = -5V ±10% is guaranteed by PSRR tests.

SS

Note 8: Tested at I

= 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics).

OUT

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(T = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted).

A

INTEGRAL NONLINEARITY vs.

DIGITAL INPUT CODE (11–4095)

DIGITAL INPUT CODE (0–11)

OUTPUT SINK CAPABILITY vs.

OUTPUT PULL-DOWN VOLTAGE

16

14

12

10

8

0.25

0

0.25

DUAL

SUPPLIES

0

-0.50

6

SINGLE

SUPPLY

4

-1.00

-1.25

2

-0.25

0

0.2

0.4

0.6

0.8

1.0

0

2

4

6

8

10

12

11 512 1024 1536 2048 2560 3072 3584 4095

DIGITAL INPUT CODE (DECIMAL)

OUTPUT PULL-DOWN VOLTAGE (V)

DIGITAL INPUT CODE (DECIMAL)

OUTPUT SOURCE CAPABILITY vs.

OUTPUT PULL-UP VOLTAGE

REFERENCE VOLTAGE vs.

TEMPERATURE

ANALOG FEEDTHROUGH vs.

FREQUENCY

-110

-100

-90

8

7

6

5

4

3

2.055

2.050

-80

-70

REFIN = 2V

p-p

-60

-50

-40

-30

-20

-10

2

1

0

CODE = ALL 0s,

DUAL SUPPLIES (±5V)

0

2.045

0

1

2

3

4

5

1

10

100

1k

10k 100k 1M

-60 -40 -20

0 20 40 60 80 100 120

140

OUTPUT PULL-UP VOLTAGE (V)

FREQUENCY (Hz)

TEMPERATURE (°C)

_______________________________________________________________________________________

5

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )

(T = +25°C, single supply (+5V), unity gain, code = all 1s, unless otherwise noted).

A

SUPPLY CURRENT vs. TEMPERATURE

GAIN vs. FREQUENCY

AMPLIFIER SIGNAL-TO- NOISE RATIO

300

4

80

70

60

50

40

30

20

10

REFIN = 4Vp-p

290

2

0

MAX530

280

270

260

250

-2

-4

-6

-8

DUAL SUPPLIES (±5V)

-10

-12

240

230

-14

0

60

100

-60 -40 -20

0

20 40

80

1

100

1k

10k

100k

10

100

1k

10k

100k

TEMPERATURE (°C)

FREQUENCY (Hz)

GAIN AND PHASE vs.

FREQUENCY

REFERENCE OUTPUT VOLTAGE

vs. REFERENCE LOAD CURRENT

SUPPLY CURRENT vs. REFIN

-200

180

250

200

2.0480

2.0475

(G = 2)

(G = 1)

REFGND = AGND

-100

GAIN

2.0470

2.0465

2.0460

2.0455

2.0450

150

100

50

0

-100

-200

0

PHASE

REFGND = V

DD

REFIN = EXTERNAL

-180

-300

0

1

10

100

800

0

50 100 150 200 250 300 350 400 450 500

REFIN (mV)

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

REFERENCE LOAD CURRENT (mA)

FREQUENCY (kHz)

SETTLING TIME (RISING)

DIGITAL FEEDTHROUGH

SETTLING TIME (FALLING)

A

B

A

B

5µs/div

2µs/div

A: DIGITAL INPUTS RISING EDGE,

B: VOUT NO LOAD, 1V/div

A: DIGITAL INPUTS FALLING EDGE, 5V/div

B: VOUT, NO LOAD, 1V/div

DUAL SUPPLY (±5V)

A: D0...D7 = 100kHz, 4Vp-p

B: VOUT, 10mV/div

,

DUAL SUPPLY (±5V)

LDAC = LOW

LDAC = CS = HIGH

BIPOLAR CONFIGURATION

V

REFIN

= 2V

V

REFIN

= 2V

6

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

1

2

3

4

5

6

7

D1/ D9

D2/ D10

D3/ D11

D4

D1 Input Dta, when A0 = 0 and A1 = 1, or D9 Input when A0 = A1 = 1*

D2 Input Dta, when A0 = 0 and A1 = 1, or D10 Input when A0 = A1 = 1*

D3 Input Dta, when A0 = 0 and A1 = 1, or D11 (MSB) Input when A0 = A1 =1*

D4 Input Dta, or tie to D0 and multiplex when A0 = 1 and A1 = 0*

D5 Input Dta, or tie to D1 and multiplex when A0 = 1 and A1 = 0*

D6 Input Dta, or tie to D2 and multiplex when A0 = 1 and A1 = 0*

D7 Input Dta, or tie to D3 and multiplex when A0 = 1 and A1 = 0*

D5

D6

D7

Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM),

and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.)

8

9

A0

A1

Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and

A1 = 0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing.

10

11

12

WR

CS

Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1.

Chip Select (active low). Enables addressing and writing to this chip from common bus lines.

Digital Ground

DGND

Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to

REFOUT (pin 18) to use the internal 2.048V reference.

13

REFIN

14

15

AGND

CLR

Analog Ground

Clear (active low). A low on CLR resets the DAC latches to all 0s.

Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input

latch to the DAC latch and updates VOUT.

16

17

LDAC

Reference Ground must be connected to AGND when using the internal reference. Connect to V

DD

REFGND

REFOUT

to disable the internal reference and save power.

18

19

20

21

22

23

24

Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC.

Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation.

Voltage Output. Op-amp buffered DAC output.

V

SS

VOUT

RFB

Feedback Pin. Op-amp feedback resistor. Always connect to VOUT.

Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output.

Positive Power Supply (+5V)

ROFS

V

DD

D0/D8

D0 (LSB) Input Dta when A0 = 0 and A1 = 1, or D8 Input when A0 = A1= 1*

* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode.

_______________________________________________________________________________________

7

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

tion, however, the output voltage would be the inverse of

________________De ta ile d De s c ription

the reference voltage. The MAX530’s topology makes the

ladder output voltage the same polarity as the reference

input, which makes the device suitable for single-supply

operation. The BiCMOS op amp is then used to buffer,

invert, or amplify the ladder signal.

The MAX530 consists of a parallel-input logic interface, a

12-bit R-2R ladder, a reference, and an op amp. The

Functional Diagram shows the control lines and signal

flow through the input data latch to the DAC latch, as well

as the 2.048V reference and output op amp. Total supply

current is typically 250µA with a single +5V supply. This

circuit is ideal for battery-powered, microprocessor-con-

trolled applications where high accuracy, no adjustments,

and minimum component count are key requirements.

Ladder resistors are nominally 80kΩ to conserve power

and are laser trimmed for gain and linearity. The input

impedance at REFIN is code dependent. When the DAC

register is all 0s, all rungs of the ladder are grounded

and REFIN is open or no load. Maximum loading (mini-

mum REFIN impedance) occurs at code 010101... or

555hex. Minimum reference input impedance at this

code is guaranteed to be not less than 40kΩ.

MAX530

R-2R La dde r

The MAX530 uses an “inverted” R-2R ladder network with

a BiCMOS op amp to convert 12-bit digital data to analog

voltage levels. Figure 1 shows a simplified diagram of the

R-2R DAC and op amp. Unlike a standard DAC, the

MAX530 uses an “inverted” ladder network. Normally, the

REFIN pin is the current output of a standard DAC and

would be connected to the summing junction, or virtual

ground, of an op amp. In this standard DAC configura-

The REFIN and REFOUT pins allow the user to choose

between driving the R-2R ladder with the on-chip refer-

ence or an external reference. REFIN may be below ana-

log ground when using dual supplies. See the External

Reference and Four-Quadrant Multiplication sections for

more information.

In t e rn a l Re fe re n c e

The on-chip reference is laser trimmed to generate

2.048V at REFOUT. The output stage can source and

sink current so REFOUT can settle to the correct volt-

age quickly in response to code-dependent loading

changes. Typically source current is 5mA and sink cur-

rent is 100µA.

2R

ROFS

2R

MAX530

RFB

VOUT

OUTPUT

R

REFOUT connects the internal reference to the R-2R

DAC ladder at REFIN. The R-2R ladder draws 50µA

maximum load current. If any other connection is made

to REFOUT, ensure that the total load current is less

than 100µA to avoid gain errors.

BUFFER

2R 2R

2R

LSB

MSB

*

R = 80kΩ

REFIN

AGND

A separate REFGND pin is provided to isolate refer-

ence currents from other analog and digital ground

currents. To achieve specified noise performance, con-

nect a 33µF capacitor from REFOUT to REFGND (see

Figure 2). Using smaller capacitance values increases

noise, and values less than 3.3µF may compromise the

reference’s stability. For applications requiring the low-

est noise, insert a buffered RC filter between REFOUT

a nd REFIN. Whe n us ing the inte rna l re fe re nc e ,

REFGND must be connected to AGND. In applications

not requiring the internal reference, connect REFGND

REFOUT

2.048V

CLR

DAC LATCH

MSB

LSB

NBL

INPUT

LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

REFGND

D0/D8

D1/D9

D4

D2/D10

D6

*SHOWN FOR ALL 1s

to V , which shuts down the reference and saves typ-

D3/D11

D5 D7

DD

ically 100µA of V supply current.

DD

Figure 1. Simplified MAX530 DAC Circuit

8

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

Ex t e rn a l Re fe re n c e

R

S

REFOUT

An e xte rna l re fe re nc e in the ra ng e (V

+ 2V) to

SS

TOTAL

REFERERNCE

NOISE

C

S

(V

DD

- 2V) may be used with the MAX530 in dual-sup-

ply, unity-gain operation. In single-supply, unity-gain

operation, the reference must be positive and may not

C

REFOUT

TEK 7A22

exceed (V

- 2V). The reference voltage determines

DD

300

250

200

150

100

50

1.8

1.6

1.4

1.2

1.0

0.8

the DAC’s full-s c a le outp ut. Be c a us e of the c od e -

dependent nature of reference input impedances, a

high-quality, low-output-impedance amplifier (such as

the MAX480 low-power, precision op amp) should be

used to drive REFIN.

SINGLE POLE ROLLOFF

C

= 3.3µF

REFOUT

If an upgrade to the internal reference is required, the

2.5V MAX873A is id e a l: ± 15mV initia l a c c ura c y,

7ppm/°C (max) temperature coefficient.

0.6

0.4

0.2

0.0

P o w e r-On Re s e t

C

= 47µF

REFOUT

An internal power-on reset (POR) circuit forces the

DAC register to reset to all 0s when V is first applied.

0

DD

The POR pulse is typically 1.3µs; however, it may take

2ms for the internal reference to charge its large filter

capacitor and settle to its trimmed value.

0.1

1

10

100

1000

FREQUENCY (kHz)

Figure 2. Reference Noise vs. Frequency

In addition to POR , a clear (CLR) pin, when held low,

sets the DAC register to all 0s. CLR operates asynchro-

nously and independently from chip select (CS). With

the DAC input at all 0s, the op-amp output is at zero for

Ou t p u t Bu ffe r

The output amplifier uses a folded cascode input stage

and a type AB output stage. Large output devices with

low s e rie s re s is ta nc e a llow the outp ut to s wing to

ground in single-supply operation. The output buffer is

unity-gain stable. Input offset voltage and supply cur-

rent are laser trimmed. Settling time is 25µs to 0.01% of

final value. The output is short-circuit protected and

can drive a 2kΩ load with more than 100pF of load

capacitance. The op amp may be placed in unity-gain

(G = 1), in a gain of two (G = 2), or in a bipolar-output

mode by using the ROFS and RFB pins. These pins are

used to define a DAC output voltage range of 0V to

+2.048V, 0V to +4.096V or ±2.048V, by connecting

ROFS to VOUT, GND, or REFIN. RFB is always con-

nected to VOUT. Table 1 summarizes ROFS usage.

unity-gain and G = 2 configurations, but it is at -V

for the bipolar configuration.

REF

S h u t d o w n Mo d e

The MAX530 is designed for low power consumption.

Understanding the circuit allows power consumption

management for maximum efficiency. In single-supply

mode (V

= +5V, V = GND) the initial supply cur-

DD

SS

rent is typically only 160µA, including the reference, op

a mp , a nd DAC. This low c urre nt oc c urs whe n the

power-on reset circuit clears the DAC to all 0s and

forces the op-amp output to zero (unipolar mode only).

See the Supply Current vs. REFIN graph in the Typical

Operating Characteristics. Under this condition, there

is no internal load on the reference (DAC = 000hex,

REFIN is open circuit) and the op amp operates at its

minimum quiescent current. The CLR signal resets the

MAX530 to these same conditions and can be used to

control a power-saving mode when the DAC is not

being used by the system.

Table 1. ROFS Usage

ROFS

CONNECTED TO:

DAC OUTPUT

RANGE

OP-AMP

GAIN

VOUT

AGND

REFIN

0V to 2.048V

0V to 4.096V

G = 1

G = 2

-2.048V to +2.048V

Bipolar

Note: Assumes RFB = VOUT and REFIN = REFOUT = 2.048V

_______________________________________________________________________________________

9

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

REFOUT

REFIN

ROFS

33µF

2.048V

REFERENCE

RFB

MAX530

REFGND

AGND

V

OUT

2N7002

DAC

POWER-ON

RESET

DGND

MAX530

V

DD

+5V

12-BIT DAC LATCH

CLR

V

SS

NBL

INPUT

LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

A0

A1

CS

CONTROL

LOGIC

WR

LDAC

D0/D8

D1/D9

D4

D2/D10

D6

D3/D11

D5 D7

Figure 3. Low-Current Shutdown Mode

An additional 110µA of supply current can be saved

when the internal reference is not used by connecting

modes. This reduces the total single-supply operating

current from 250µA (400µA max) to typically 40µA in

shutdown mode.

REFGND to V . A low on resistance N-channel FET,

DD

such as the 2N7002, can be used to turn off the internal

reference to create a shutdown mode with minimum

current drain (Figure 3). When CLR is high, the transis-

tor pulls REFGND to AGND and the reference and DAC

operate normally. When CLR goes low, REFGND is

A small error voltage is added to the reference output

by the reference current flowing through the N-channel

pull-down transistor. The switch’s on resistance should

be less than 5Ω. A typical reference current of 100µA

would add 0.5mV to REFOUT. Since the reference cur-

rent and on resistance increase with temperature, the

overall temperature coefficient will degrade slightly.

pulled up to V and the reference is shut down. At the

DD

same time, CLR resets the DAC register to all 0s, and

the op-amp output goes to 0V for unity-gain and G = 2

As data is loaded into the DAC and the output moves

above GND, the op-amp quiescent current increases to

its nominal value and the total operating current aver-

ages 250µA. Using dual supplies (±5V), the op amp is

Table 2. Input Latch Addressing

CLR CS WR LDAC A0 A1

DATA UPDATED

Reset DAC Latches

No Operation

L

H

X

H

X

L

H

L

X

H

L

H

L

X

H

L

X

H

L

X

H

L

fully biased continuously, and the V supply current is

DD

more constant at 250µA. The V current is typically

SS

150µA.

No Operation

The MAX530 logic inputs are compatible with TTL and

CMOS logic levels. However, to achieve the lowest

power dissipation, drive the digital inputs with rail-to-rail

CMOS logic. With TTL logic levels, the power require-

ment increases by a factor of approximately 2.

NBH (D8-D11)

NBM (D4-D7)

H

X

L

NBL (D0-D3)

X

L

Update DAC Only

DAC NOT UPDATED

NBH and Update DAC

X

L

H

10 ______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

ADDRESS BUS VALID

V

IH

A0-A1

CS

V

IL

t

AWH

t

CWS

t

CWH

WR

t

WR

t

AWS

t

DS

t

DH

V

IL

IH

DATA BITS

(8-BIT BYTE OR

4-BIT NIBBLE)

DATA BUS

VALID

CLR

t

CLR

LDAC

t

LDAC

V

IH + IL

2

NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS

Figure 4. MAX530 Write-Cycle Timing Diagram

for the high, middle, or low data nibbles. The µP sends

chip select (CS) and write (WR) signals to latch in each of

three nibbles in three cycles when the data is valid.

P a ra lle l Lo g ic In t e rfa c e

Designed to interface with 4-bit, 8-bit, and 16-bit micro-

processors (µPs), the MAX530 uses 8 data pins and

double-buffered logic inputs to load data as 4 + 4 + 4

or 8 + 4. The 12-bit DAC latch is updated simultane-

ously through the control signal LDAC. Signals A0, A1,

WR, and CS select which input latches to update. The

12-bit data is broken down into nibbles (NB); NBL is

the enable signal for the lowest 4 bits, NBM is the

enable for the middle 4 bits, and NBH is the enable for

the highest and most significant 4 bits. Table 2 lists the

address decoding scheme.

Figure 7 shows a typical interface to an 8-bit or a 16-bit

µP. Connect 8 data bits from the data bus to pins D0-D7

on the MAX530. With LDAC held high, the user can load

+

NBH or NBL NBM in any order. Figure 8a shows the

corresponding timing sequence. For fastest throughput,

use Figure 8b’s sequence. Address lines A0 and A1 are

tied together and the DAC is loaded in 2 cycles as 8 + 4.

In this scheme, with LDAC

held low, the DAC latch is

transparent. Always load NBL and NBM first, followed by

NBH.

Refer to Figure 4 for the MAX530 write-cycle timing

diagram.

LDAC is asynchronous with respect to WR. If LDAC is

brought low before or at the same time WR goes high,

LDAC must remain low for at least 50ns to ensure the cor-

rect data is latched. Data is latched into DAC registers on

LDAC’s rising edge.

Figure 5 shows the circuit configuration for a 4-bit µP

application. Figure 6 shows the corresponding timing

sequence. The 4 low bits (D0-D3) are connected in paral-

lel to the other 4 bits (D4-D7) and then to the µP bus.

Address lines A0 and A1 enable the input data latches

______________________________________________________________________________________ 11

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

DATA BUS

D0-D7

D0-D3

DATA BUS

D0-D3

D4-D7

FROM

SYSTEM

RESET

FROM

SYSTEM

RESET

D0-D3

CLR

MAX530

CS LDAC

A0, A1

WR

MAX530

CS LDAC

A0-A1

WR

MC6800

MC6809

02

E

EN DECODER

A13-A15

R/W

DECODER

R/W

EN

ADDRESS BUS A0, A1

A0

A0-A15

A0-A15 ADDRESS BUS

A13-A15

Figure 7. 8-Bit and 16-Bit µP Interface

Figure 5. 4-Bit µP Interface

A0 = 1, A1 = 1

NBH

NBM

A0 = 1, A1 = 0

NBL

CS

A0 = 0, A1 = 1

WR

LDAC

DAC UPDATE

Figure 6. 4-Bit µP Timing Sequence

A0 = A1 = 1

NBH

A0 = A1 = 0

NBL & NBM

CS

WR

LDAC

DAC UPDATE

Figure 8a. 8-Bit and 16-Bit µP Timing Sequence Using LDAC

12 ______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

A0 = A1 = 0

NBL & NBM

A0 = A1 = 1

NBH

CS

WR

LDAC = 0 (DAC LATCH IS TRANSPARENT)

DAC UPDATE

Figure 8b. 8-Bit and 16-Bit µP Timing Sequence with LDAC = 0

A 0V to 4.096V unipolar output range is set up by con-

necting ROFS to AGND and RFB to VOUT (Figure 10).

Table 4 shows the DAC-latch contents vs. VOUT. The

Un ip o la r Co n fig u ra t io n

The MAX530 is configured for a 0V to +2.048V unipolar

output range by connecting ROFS and RFB to VOUT

(Figure 9). The converter operates from either single or

dual supplies in this configuration. See Table 3 for the

MAX530 operates from either single or dual supplies in

-12

this mode. In this range, 1LSB = (2)(REFIN)(2

) =

-11

(REFIN)(2

).

DAC-latch contents (input) vs. the analog VOUT (output).

-12

In this range, 1LSB = REFIN (2

).

+5V

V

DD

V

DD

REFIN

ROFS

REFOUT

33µF

MAX530

AGND

ROFS

RFB

AGND

DGND

V

OUT

VOUT

DGND

V

OUT

REFGND

G = 2

V

SS

V

SS

G = 1

0V TO -5V

Figure 9. Unipolar Configuration (0V to +2.048V Output)

Figure 10. Unipolar Configuration (0V to +4.096V Output)

______________________________________________________________________________________ 13

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

Table 3. Unipolar Binary Code Table

Table 4. Unipolar Binary Code Table

(0V to V

Output), Gain = 1

(0V to 2V

Output), Gain = 2

REFIN

OUTPUT

INPUT

OUTPUT

INPUT

4095

4096

4095

4096

(V

)

1111 1111

1000 0000

1111

0001

+2 (V

)

1111 1111

1000 0000

1111

0001

REFIN

MAX530

2049

4096

2049

4096

(V

REFIN

)

+2 (V

)

REFIN

2048

4096

2048

4096

(V

)

= +V

/2

REFIN

= +V

REFIN

1000 0000

0111 1111

+2 (V

)

0000

1111

1000 0000

0111 1111

REFIN

0000

1111

REFIN

2047

4096

2047

4096

(V

)

+2 (V

)

REFIN

1

4096

0000 0000

(V

)

0001

0000

0000 0000

)

0001

0000

REFIN

4096

OV

Bip o la r Co n fig u ra t io n

bipolar range is set up by con-

necting ROFS to REFIN and RFB to VOUT, and operat-

ing from d ua l (± 5V) s up p lie s (Fig ure 11). Ta b le 5

Table 5. Bipolar (Offset Binary) Code Table

A -V

to +V

REFIN

(-V

to +V

Output)

REFIN

OUTPUT

INPUT

shows the DAC-latch contents (input) vs. VOUT (out-

-11

put). In this range, 1 LSB = REFIN (2

).

2047

)

(+V

REFIN

1111 1111

1111

2048

Fo u r-Qu a d ra n t Mu lt ip lic a t io n

The MAX530 can be used as a four-quadrant multiplier

by connecting ROFS to REFIN and RFB to VOUT and,

us ing (1) a n offs e t b ina ry d ig ita l c od e , (2) b ip ola r

p owe r s up p lie s , a nd (3) a b ip ola r a na log inp ut a t

1

2048

1000 0000

0111 1111

(+V

)

0001

0000

1111

REFIN

0V

REFIN within the range V + 2V to V - 2V, as shown

SS

DD

in Figure 12.

1

2048

(-V

REFIN

)

In general, a 12-bit DAC’s output is (D)(V

)(G),

REFIN

where “G” is the gain (1 or 2) and “D” is the binary rep-

12

resentation of the digital input divided by 2 or 4,096.

2047

2048

0000 0000

(-V

)

0001

0000

REFIN

This formula is precise for unipolar operation. However,

for bipolar, offset binary operation, the MSB is really a

polarity bit. No resolution is lost, because there is the

same number of steps. The output voltage, however,

has been shifted from a range of, for example, 0V to

4.096V (G = 2) to a range of -2.048V to +2.048V.

2048

(-V

REFIN

)

= -V

REFIN

Keep in mind that when using the DAC as a four-quad-

rant multiplier, the scale is skewed. The negative full

scale is -V

- 1LSB.

, while the positive full scale is +V

REFIN

14 ______________________________________________________________________________________

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

MAX530

+5V

V

DD

REFIN

ROFS

REFIN

ROFS

REFOUT

REFGND

33µF

MAX530

RFB

AGND

DGND

RFB

AGND

V

OUT

V

OUT

DGND

VOUT

REFGND

V

SS

-5V

Figure 12. Four-Quadrant Multiplying Circuit

Figure 11. Bipolar Configuration (-2.048V to +2.048V Output)

cations, connect V to AGND at the chip. The best

SS

__________Ap p lic a t io n s In fo rm a t io n

ground connection may be achieved by connecting

the AGND, REFGND, and DGND pins together and

connecting that point to the system analog ground

plane. If DGND is connected to the system digital

ground, digital noise may get through to the DAC’s ana-

log portion.

S in g le -S u p p ly Lin e a rit y

As with any amplifier, the MAX530’s output op amp offset

can be positive or negative. When the offset is positive, it

is easily accounted for. However, when the offset is nega-

tive, the output cannot follow linearly when there is no

negative supply. In that case, the amplifier output (VOUT)

remains at ground until the DAC voltage is sufficient to

overcome the offset and the output becomes positive.

The resulting transfer function is shown in Figure 13.

Bypass V

(and V in dual-supply mode) with a

SS

DD

0.1µF ceramic capacitor connected between V

and

DD

AGND (a nd b e twe e n V

a nd AGND). Mount the

SS

capacitors with short leads close to the device.

Normally, linearity is measured after allowing for zero

error and gain error. Since, in single-supply operation,

the actual value of a negative offset is unknown, it can-

not be accounted for during test. In the MAX530, linear-

ity and gain error are measured from code 11 to code

4095 (see Note 2 under Electrical Characteristics). The

output amplifier offset does not affect monotonicity, and

these DACs are guaranteed monotonic starting with

code zero. In dual-supply operation, linearity and gain

error are measured from code 0 to 4095.

AC Co n s id e ra t io n s

Digital Feedthrough

High-speed data at any of the digital input pins may

couple through the DAC package and cause internal

stray capacitance to appear as noise at the DAC out-

put, even though LDAC and CS are held high (see

Typ ic a l Op e ra ting Cha ra c te ris tic s ). This d ig ita l

feedthrough is tested by holding LDAC and CS high

and toggling the data inputs from all 1s to all 0s.

P o w e r-S u p p ly Byp a s s in g

a n d Gro u n d Ma n a g e m e n t

Best system performance is obtained with printed cir-

cuit boards that use separate analog and digital ground

planes. Wire-wrap boards are not recommended. The

two ground planes should be connected together at the

low-impedance power-supply source.

Analog Feedthrough

Because of internal stray capacitance, higher-frequen-

cy analog input signals at REFIN may couple to the

output, even when the input digital code is all 0s, as

shown in the Typical Operating Characteristics graph

Analog Feedthrough vs. Frequency. It is tested by set-

ting CLR to low (which sets the DAC latches to all 0s)

and sweeping REFIN.

AGND and REFGND should be connected together,

and then to DGND at the chip. For single-supply appli-

______________________________________________________________________________________ 15

+5 V, Lo w -P o w e r, P a ra lle l-In p u t ,

Vo lt a g e -Ou t p u t , 1 2 -Bit DAC

___________________Ch ip To p o g ra p h y

D3/D11 D1/D9

V

DD

RFB

POSITIVE OFFSET

D4 D2/D10 D0/D8

ROFS

MAX530

4

3

2

1

0

NEGATIVE OFFSET

VOUT

1

2

3

4

5

6

7

8

D5

D6

0. 133"

(3. 378mm)

DAC CODE (LSBs)

V

SS

D7

A0

Figure 13. Single-Supply DAC Transfer Function

REFOUT

_Ord e rin g In fo rm a t io n (c o n t in u e d )

REFGND

LDAC

A1

ERROR

(LSB)

PART

TEMP. RANGE PIN-PACKAGE

DGND

AGND

WR CS

CLR

1

REFIN

/

MAX530AENG -40°C to +85°C 24 Narrow Plastic DIP

MAX530BENG -40°C to +85°C 24 Narrow Plastic DIP

MAX530AEWG -40°C to +85°C 24 Wide SO

MAX530BEWG -40°C to +85°C 24 Wide SO

MAX530AEAG -40°C to +85°C 24 SSOP

MAX530BEAG -40°C to +85°C 24 SSOP

±

2

0. 087"

(2. 210mm)

±1

1

/

±

2

±1

1

/

±

2

TRANSISTOR COUNT: 913;

SUBSTRATE CONNECTED TO V

±1

DD.

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX530ACNG+
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	D/A Converter, 1 Func, Parallel, Word Input Loading, 25us Settling Time, PDIP24, PLASTIC, DIP-24
文件：	总16页 (文件大小：141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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