MAX5331UCB+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, PQFP64, TQFP-64;
| 型号： | MAX5331UCB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, PQFP64, TQFP-64 信息通信管理 转换器 |
| 文件： | 总16页 (文件大小：893K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3563; Rev 1; 5/05
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
General Description
Features
♦ Integrated 12-Bit DAC and 32-Channel SHA with
SRAM and Sequencer
The MAX5331/MAX5332/MAX5333 are 12-bit digital-to-
analog converters (DACs) with 32 sample-and-hold
(SHA) outputs for applications where a high number of
programmable voltages are required. These devices
include a clock oscillator and a sequencer that updates
the DAC with codes from an internal SRAM. No external
components are required to set offset and gain.
♦ 32 Voltage Outputs
♦ 0.03% FSR (typ) Output Linearity
♦ 3.2mV Output Resolution
♦ Flexible Output Voltage Range
♦ Remote Ground Sensing
The MAX5331/MAX5332/MAX5333 feature a -4.5V to
+9.2V output voltage range. Other features include a
3.2mV/step resolution, with output linearity error, typi-
cally 0.03% of full-scale range (FSR). The 100kHz
refresh rate updates each SHA every 320µs, resulting
in negligible output droop. Remote ground sensing
allows the outputs to be referenced to the local ground
of a separate device.
♦ Fast Sequential Loading: 1.3µs per Register
♦ Burst- and Immediate-Mode Addressing
♦ No External Components Required for Setting
Gain and Offset
♦ Integrated Output Clamp Diodes
♦ Three Output-Impedance Options
MAX5331 (50Ω), MAX5332 (500Ω), and
MAX5333 (1kΩ)
These devices are controlled through a 20MHz
SPI™/QSPI™/MICROWIRE™-compatible 3-wire serial
interface. Immediate update mode allows any channel’s
output to be updated within 20µs. Burst mode allows
multiple values to be loaded into memory in a single,
high-speed data burst. All channels are updated within
330µs of data being loaded.
Ordering Information
PART
TEMP RANGE
0°C to +85°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
0°C to +85°C
PIN-PACKAGE
64 TQFP
MAX5331UCB
MAX5331UTK*
MAX5332UCB
MAX5332UTK*
MAX5333UCB
68 Thin QFN
64 TQFP
Each device features an output clamp and output resis-
tors for filtering. The MAX5331 features a 50Ω output
impedance and is capable of driving up to 250pF of
output capacitance. The MAX5332 features a 500Ω out-
put impedance and is capable of driving up to 10nF of
output capacitance. The MAX5333 features a 1kΩ out-
put impedance and is capable of driving up to 10nF of
output capacitance.
68 Thin QFN
64 TQFP
MAX5333UTK*
0°C to +85°C
68 Thin QFN
*Future product—contact factory for availability.
Pin Configurations
The MAX5331/MAX5332/MAX5333 are available in 12mm
x 12mm, 64-pin TQFP and 10mm x 10mm, 68-pin thin
QFN packages.
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N.C.
N.C.
GS
1
2
3
4
5
6
7
8
9
48
47 CH
46
V
DD
________________________Applications
V
SS
MEMS Mirror Servo Control
Industrial Process Control
Automatic Test Equipment
Instrumentation
V
45 OUT20
44 OUT19
43 OUT18
42 OUT17
41 OUT16
40 AGND
LDAC
RST
CS
DIN
SCLK
MAX5331
MAX5332
MAX5333
V
LOGIC
IMMED 10
ECLK 11
39 V
DD
38 OUT15
37 OUT14
36 OUT13
35 OUT12
34 OUT11
33 CL
CLKSEL 12
DGND 13
V
14
AGND 15
16
LSHA
V
SS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TQFP
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ABSOLUTE MAXIMUM RATINGS
V
V
V
V
to AGND.......................................................-0.3V to +12.2V
to AGND .........................................................-6.0V to +0.3V
Maximum Current Into Logic Inputs ................................. 20mA
DD
SS
DD
Continuous Power Dissipation (T = +70°C)
A
to V ...........................................................................+15V
64-Pin TQFP (derate 13.3mW/°C above +70°C) ............1066mW
68-Pin Thin QFN (derate 28.6mW/°C above +70°C)......2285mW
Operating Temperature Range...............................0°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
SS
, V
, V
to AGND or DGND..............-0.3V to +6V
LDAC LOGIC LSHA
REF to AGND............................................................-0.3V to +6V
GS to AGND................................................................V to V
CL and CH to AGND...................................................V to V
Logic Inputs to DGND..............................................-0.3V to +6V
DGND to AGND........................................................-0.3V to +2V
Maximum Current into OUT_ ............................................ 10mA
SS
SS
DD
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +10V, V = -4V, V
= V
= V
= +5V, V
= +2.5V, AGND = DGND = V
= 0, R ≥ 10MΩ, C = 50pF,
DD
SS
LOGIC
LDAC
LSHA
REF
GS L L
CLKSEL = +5V, f
= 400kHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
ECLK
A
MIN
MAX A
PARAMETER
DC CHARACTERISTICS
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
12
Bits
V
V
+
V
-
DD
SS
Output Range
V
(Note 1)
OUT_
0.75
2.4
Offset Voltage
Code = 4F3 hex
(Note 2)
15
50
200
1
mV
µV/°C
%
Offset Voltage Tempco
Gain Error
Gain Tempco
5
ppm/°C
%FSR
Integral Linearity Error
INL
DNL
V
V
= -3.25V to +7.6V
0.03
0.1
1
OUT_
OUT_
= -3.25V to +7.6V, monotonicity
Differential Linearity Error
0.5
LSB
mA
guaranteed to 12 bits
Sinking and sourcing
MAX5331
Maximum Output Drive Current
I
2
35
OUT
50
500
1000
250
10
65
DC Output Impedance
R
Ω
MAX5332
350
700
650
OUT
MAX5333
1300
MAX5331
pF
nF
Maximum Capacitive Load
MAX5332
MAX5333
10
DC Crosstalk
Internal oscillator enabled (Note 3)
Internal oscillator enabled
-90
-80
dB
dB
Power-Supply Rejection Ratio
PSRR
2
_______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +10V, V = -4V, V
= V
= V
= +5V, V
= +2.5V, AGND = DGND = V
= 0, R ≥ 10MΩ, C = 50pF,
GS L L
DD
SS
LOGIC
LDAC
LSHA
REF
CLKSEL = +5V, f
= 400kHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
ECLK
A
MIN
PARAMETER
DYNAMIC CHARACTERISTICS
Sample-and-Hold Settling
SCLK Feedthrough
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 4)
0.08
%
0.5
0.5
0.25
1
nV•s
nV•s
mV
f
Feedthrough
SEQ
Hold Step
1
Droop Rate
V
= 0 (Note 5)
300
µV/ms
OUT_
µV
Output Noise
250
RMS
REFERENCE INPUT
Input Resistance
Reference Input Voltage
GROUND-SENSE INPUT
Input Voltage Range
Input Bias Current
GS Gain
7
kΩ
V
I
2.5
1
V
REF
V
-0.5
-60
+0.5
0
V
GS
-0.5V ≤ V ≤ 0.5V
µA
V/V
GS
GS
(Note 6)
0.998
1.002
DIGITAL-INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
V
2.0
80
V
V
IH
V
0.8
1
IL
µA
TIMING CHARACTERISTICS (Figure 2)
Sequencer Clock Frequency
External Clock Frequency
SCLK Frequency
f
Internal oscillator
(Note 7)
100
120
480
20
kHz
kHz
MHz
ns
SEQ
f
f
ECLK
SCLK
SCLK Pulse-Width High
SCLK Pulse-Width Low
t
15
15
CH
t
ns
CL
CS-Low to SCLK-High Setup
Time
t
15
ns
CSSO
CS-High to SCLK-High Setup
Time
t
15
10
ns
ns
CSS1
SCLK-High to CS-Low Hold Time
t
CSH0
_______________________________________________________________________________________
3
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +10V, V = -4V, V
= V
= V
= +5V, V
= +2.5V, AGND = DGND = V
= 0, R ≥ 10MΩ, C = 50pF,
DD
SS
LOGIC
LDAC
LSHA
REF
GS
L
L
CLKSEL = +5V, f
= 400kHz, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
ECLK
A
MIN
PARAMETER
SCLK-High to CS-High Hold Time
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
RST-to-CS Low
SYMBOL
CONDITIONS
MIN
0
TYP
MAX UNITS
t
ns
ns
ns
CSH1
t
15
0
DS
t
DH
(Note 8)
500
µs
POWER SUPPLIES
Positive Supply Voltage
Negative Supply Voltage
Supply Difference
V
(Note 9)
(Note 9)
8.55
10
-4
11.60
-2.75
14.5
V
V
V
DD
V
-5.25
SS
V
- V (Note 9)
SS
DD
V
,
LOGIC
V
V
,
Logic Supply Voltage
4.75
-40
5
5.25
42
V
LDAC
LSHA
Positive Supply Current
Negative Supply Current
I
32
-32
1
mA
mA
DD
I
SS
(Note 10)
= 20MHz (Note 11)
1.5
3
Logic Supply Current
I
mA
LOGIC
f
2
SCLK
Note 1: The nominal zero-scale voltage (code = 0) is -4.0535V. The nominal full-scale voltage (code = FFF hex) is +9.0503V. The
output voltage is limited by the output range specification, restricting the usable range of DAC codes. The nominal zero-
scale voltage can be achieved when V < -4.9V, and the nominal full-scale voltage can be achieved when V
> +11.5V.
SS
DD
Note 2: Gain is calculated from measurements:
for voltages V
for voltages V
for voltages V
for voltages V
= 10V and V = -4V at codes C00 hex and 4F3 hex
DD
DD
DD
DD
SS
= 11.6V and V = -2.9V at codes FFF hex and 253 hex
SS
= 9.25V and V = -5.25V at codes D4F hex and 0 hex
SS
= 8.55V and V = -2.75V at codes C75 hex and 282 hex
SS
Note 3: Steady-state change in any output with an 8V change in an adjacent output.
Note 4: Settling during the first update for an 8V step. The output will settle to within the linearity specification on subsequent
updates. Tested with an external sequencer clock frequency of 480kHz.
Note 5: External clock mode with the external clock not toggling.
Note 6: The output voltage is the sum of the DAC output and the voltage at GS. GS gain is measured at 4F3 hex.
Note 7: The sequencer runs at f
= f
/ 4. Maximum speed is limited by settling of the DAC and SHAs. Minimum speed is
SEQ
ECLK
limited by acceptable droop and update time after a burst-mode update.
V rise to CS low = 500µs maximum.
DD
Note 8:
Note 9: Guaranteed by gain-error test.
Note 10: The serial interface is inactive. V = V
, V = 0.
LOGIC IL
IH
Note 11: The serial interface is active. V = V
, V = 0.
LOGIC IL
IH
4
_______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Typical Operating Characteristics
(V
DD
= +10V, V = -4V, V
= +2.5V, V = 0, T = +25°C, unless otherwise noted.)
SS
REF
GS
A
INTEGRAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
INTEGRAL NONLINEARITY
VS. TEMPERATURE
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.10
0.08
0.06
0.04
0.02
0
0.05
0.04
0.03
0.02
0.01
0
-0.02
-0.04
-0.06
-0.08
-0.10
250
930
1610
INPUT CODE
2290
2970
3650
250
930
1610
INPUT CODE
2290
2970
3650
-40
-15
10
35
60
85
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
VS. TEMPERATURE
OFFSET VOLTAGE
VS. TEMPERATURE
DROOP RATE vs. TEMPERATURE
100
10
0.30
0.25
0.20
0.15
0.10
0.05
0
-10
-12
-14
-16
-18
-20
V
V
= +8.55V
= -4V
CODE = 4F3 hex
EXTERNAL CLOCK MODE
NO CLOCK APPLIED
DD
SS
CODE = 4F3 hex
1
0.1
0.01
0.001
0.0001
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
NEGATIVE SUPPLY PSRR
VS. FREQUENCY
POSITIVE SUPPLY PSRR
VS. FREQUENCY
GAIN ERROR VS. TEMPERATURE
-90
-80
-70
0.05
0.04
0.03
0.02
0.01
0
-90
-80
-70
-60
-50
-40
-30
-60
-50
-40
-30
-20
-20
-10
CODE = C17 hex
OFFSET CODE = 4F3 hex
-10
0
0
0.001
0.01
0.1
1
10
100
-40
-15
10
35
60
85
0.01
0.1
1
10
100
FREQUENCY (kHz)
TEMPERATURE (°C)
FREQUENCY (kHz)
_______________________________________________________________________________________
5
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Typical Operating Characteristics (continued)
(V
DD
= +10V, V = -4V, V
= +2.5V, V = 0, T = +25°C, unless otherwise noted.)
SS
REF
GS
A
LOGIC SUPPLY CURRENT
VS. LOGIC INPUT HIGH VOLTAGE
LOGIC SUPPLY CURRENT
vs. LOGIC SUPPLY VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1200
1000
800
600
400
200
0
36
34
32
30
28
26
24
22
20
900
I
DD
800
700
600
500
400
I
SS
f
= 20MHz
SCLK
INTERFACE INACTIVE
INTERFACE INACTIVE
2.0
2.5
3.0
3.5
4.0
4.5
5.0
4.75
5.00
5.25
5.50
-40
-15
10
35
60
85
LOGIC INPUT HIGH VOLTAGE (V)
LOGIC SUPLY VOLTAGE (V)
TEMPERATURE (°C)
NEGATIVE SETTLING TIME
(8V STEP)
POSITIVE SETTLING TIME
(100mV STEP)
POSITIVE SETTLING TIME
(8V STEP)
MAX5331 toc14
MAX5331 toc13
MAX5331 toc15
3.5V
0
3.5V
3.5V
0
ECLK
ECLK
ECLK
0
V
OUT_
50mV/div
AC-COUPLED
V
OUT_
V
OUT_
5V/div
5V/div
1µs/div
1µs/div
1µs/div
NEGATIVE SETTLING TIME
(100mV STEP)
OUTPUT NOISE
MAX5331 toc17
MAX5331 toc16
3.5V
0
ECLK
OUT_
1mV/div
50mV/div
AC-COUPLED
V
OUT_
250µs/div
1µs/div
6
_______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Description
PIN
NAME
FUNCTION
TQFP
THIN QFN
1, 2
1, 2, 17, 34, 51, 68
N.C.
GS
No Connection. Not internally connected.
Ground-Sensing Input
+5V DAC Power Supply
Reset Input
3
3
4
4
V
LDAC
5
5
RST
CS
6
6
Chip-Select Input
Serial-Data Input
Serial-Clock Input
+5V Logic Power Supply
Immediate-Update Mode
External Sequencer Clock Input
Clock-Select Input
Digital Ground
7
7
DIN
8
8
SCLK
9
9
V
LOGIC
IMMED
ECLK
10
10
11
11
12
12
CLKSEL
DGND
13
13
14
14
V
+5V Sample-and-Hold Power Supply
Analog Ground
Negative Power Supply
Positive Power Supply
Output Clamp Low Voltage
Output 0
LSHA
15, 25, 40, 55, 62
15, 26, 42, 58, 65
AGND
16, 32, 46
16, 33, 48
V
SS
17, 39, 48
18, 41, 50
V
DD
18, 33, 49
19, 35, 52
CL
19
20
20
21
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
CH
Output 1
21
22
Output 2
22
23
Output 3
23
24
Output 4
24
25
Output 5
26
27
Output 6
27
28
Output 7
28
29
Output 8
29
30
Output 9
30
31
Output 10
31, 47, 64
34
32, 49, 67
36
Output Clamp High Voltage
Output 11
OUT11
OUT12
OUT13
OUT14
OUT15
OUT16
OUT17
35
37
Output 12
36
38
Output 13
37
39
Output 14
38
40
Output 15
41
43
Output 16
42
44
Output 17
_______________________________________________________________________________________
7
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Pin Description (continued)
PIN
NAME
FUNCTION
TQFP
43
44
45
50
51
52
53
54
56
57
58
59
60
61
63
THIN QFN
45
46
47
53
54
55
56
57
59
60
61
62
63
64
66
OUT18
OUT19
OUT20
OUT21
OUT22
OUT23
OUT24
OUT25
OUT26
OUT27
OUT28
OUT29
OUT30
OUT31
Output 18
Output 19
Output 20
Output 21
Output 22
Output 23
Output 24
Output 25
Output 26
Output 27
Output 28
Output 29
Output 30
Output 31
Reference Voltage Input
V
REF
CH
OUT0
ECLK
CLOCK
CLKSEL
SAMPLE-
AND-HOLD
ARRAY
R
E
G
I
SAMPLE
S
T
E
R
DATA READY
SEQUENCER
OUT31
CL
R
E
G
I
S
T
E
R
GAIN AND
OFFSET
CORRECTION
GS
READ ENABLE
12-BIT
DAC
SEQUENTIAL
ADDRESS
12 x 32
SRAM
REF
2: 1
M
LAST
U
ADDRESS
X
CS
SCLK
DIN
ADDR SELECT
WRITE ENABLE
D[11:0]
MAX5331
MAX5332
MAX5333
SERIAL
INTERFACE
IMMED
RST
Figure 1. Functional Diagram
_______________________________________________________________________________________
8
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
t
CSH1
CS
t
CSHO
t
CSS1
t
t
t
CL
CSSO
CH
SCLK
DIN
t
DH
t
DS
B23
B22
B0
Figure 2. Serial-Interface Timing Diagram
The maximum output voltage range depends on the
analog supply voltages available and the output clamp
voltages (see the Output Clamp section):
Detailed Description
Sample-and-Hold Amplifiers
The MAX5331/MAX5332/MAX5333 contain 32 buffered
SHA circuits with internal hold capacitors. Internal hold
capacitors minimize leakage current, dielectric absorp-
tion, feedthrough, and required board space. The
MAX5331/MAX5332/MAX5333 provide a very low
1µV/ms droop rate.
V
+ 0.75V ≤ V
≤ V - 2.4V
SS
OUT_
DD
The devices have a fixed theoretical output range
determined by the reference voltage, gain, and mid-
scale offset. The output voltage for a given input code
is calculated as follows:
Output
The MAX5331/MAX5332/MAX5333 include output buffers
on each channel. The devices contain output resistors in
series with the buffer output (Figure 3) for ease of output
filtering and capacitive load driving stability.
code
4096
V
=
× V
× 5.2428 -
OUT_
REF
Output loads increase the analog supply current (I
DD
1.6214 × V
+ V
GS
(
)
REF
and I ). Excessively loading the outputs drastically
SS
increases power dissipation. Do not exceed the maxi-
mum power dissipation specified in the Absolute
Maximum Ratings.
where code is the decimal value of the DAC input
code, V is the reference voltage, and V is the
REF
GS
voltage at the ground-sense input. With a 2.5V refer-
ence, the nominal end points are -4.0535V and
+9.0503V (Table 1). Note that these are “virtual” internal
end-point voltages and cannot be reached with all
Table 1. Code Table
DAC INPUT CODE
MSB LSB
1111 1111 1111
NOMINAL OUTPUT
VOLTAGE (V)
V
= +2.5V
REF
9.0503
6.15
2.5
Full-scale output.
1100 0111 0101
1000 0000 0000
0100 1111 0011
0010 1000 0010
0000 0000 0000
Maximum output with V
Midscale output.
= 8.55V.
DD
0
V
= 0. All outputs default to this code after power-up.
OUT_
-2.0
Minimum output with V = -2.75V.
SS
-4.0535
Zero-scale output.
_______________________________________________________________________________________
9
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
combinations of negative and positive power-supply
voltages. The nominal, usable DAC end-point codes for
the selected power supplies can be calculated as:
Output Clamp
The MAX5331/MAX5332/MAX5333 clamp the output
between two externally applied voltages. Internal
diodes at each channel restrict the output voltage to:
Lower end-point code = 2048 - ((2.5V - (V + 0.75) /
SS
3.2mV) (result ≥ 0)
Upper end-point code = 2048 + ((V
V
+ 0.7V ≥ V
≥ V
−
0.7V
CH
OUT_
CL
- 2.4 - 2.5V) /
DD
3.2mV) (result ≤ 4095)
The clamping diodes allow the MAX5331/MAX5332/
MAX5333 to drive devices with restricted input ranges.
The diodes also allow the outputs to be clamped during
power-up or fault conditions. To disable output clamping,
connect CH to V
voltages beyond the maximum output voltage range.
The resistive voltage-divider formed by the output resis-
tor (R ) and the load impedance (R ), scales the out-
O
L
and CL to V , setting the clamping
SS
put voltage. Determine V
as follows:
DD
OUT_
R
L
Scaling factor =
Serial Interface
The MAX5331/MAX5332/MAX5333 are controlled by an
SPI-/QSPI-/MICROWIRE-compatible 3-wire interface.
Serial data is clocked into the 24-bit shift register in an
MSB-first format, with the 12-bit DAC data and S3–S0
(all zeros) preceding the 5-bit SRAM address, 2-bit
control, and a fill zero (Figure 4). The input word is
framed by CS. The first rising edge of SCLK after CS
goes low clocks in the MSB of the input word.
R + R
L
O
V
= V
× scaling factor
OUT_
CHOLD
Ground Sense
The MAX5331/MAX5332/MAX5333 include a ground-
sense input (GS), which allows the output voltages to
be referenced to a remote ground. The voltage at GS is
added to the output voltage with unity gain. Note that
the resulting output voltage must be within the valid
output voltage range set by the power supplies.
V
REF
CH
GAIN
AND
OFFSET
R
O
OUT_
12-BIT
DAC
DAC
DATA
A = 1
V
C
HOLD
R
L
CL
ONE OF 32 SHA CHANNELS
GS
Figure 3. Analog Block Diagram
DATA
ADDRESS
CONTROL
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S3 S2 S1 S0 A4 A3 A2 A1 A0 C1 C0
0
0
0
0
0
0
MSB
LSB
Figure 4. Input-Word Sequence
10 ______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Table 2. Channel/Output Selection
A4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
OUTPUT
OUT0 selected
OUT1 selected
OUT2 selected
OUT3 selected
OUT4 selected
OUT5 selected
OUT6 selected
OUT7 selected
OUT8 selected
OUT9 selected
OUT10 selected
OUT11 selected
OUT12 selected
OUT13 selected
OUT14 selected
OUT15 selected
OUT16 selected
OUT17 selected
OUT18 selected
OUT19 selected
OUT20 selected
OUT21 selected
OUT22 selected
OUT23 selected
OUT24 selected
OUT25 selected
OUT26 selected
OUT27 selected
OUT28 selected
OUT29 selected
OUT30 selected
1
1
1
1
1
OUT31 selected
When each serial word is complete, the value is stored
in the SRAM at the address indicated and the control
bits are saved. Note that data may be corrupted if CS is
not held low for an integer multiple of 24 bits.
Serial-Input Data Format and
Control Codes
The 24-bit serial-input format, shown in Figure 4, com-
prises 16 bits (D12–D0 and S3–S0 = 0), 5 address bits
(A4–A0), 2 control bits (C1, C0), and a fill zero. The
address code selects the output channel as shown in
Table 2. The control code configures the device as fol-
lows:
All the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. Their switching thresh-
old is compatible with TTL and most CMOS logic levels.
1) If C1 = 1, immediate-update mode is selected.
If C1 = 0, burst mode is selected.
2) If C0 = 0, the internal sequencer clock is selected. If
C0 = 1, the external sequencer clock is selected.
This must be repeated with each data word to main-
tain external input.
______________________________________________________________________________________ 11
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
The operating modes can also be selected externally
through CLKSEL and IMMED. If the control bit in the
serial word and the external signal conflict, the signal
that is a logic 1 is dominant.
selected output is updated before the sequencer
resumes operation. Select immediate-update mode by
driving either IMMED or C1 high.
The sequencer is interrupted when CS is taken low. The
input word is then stored in the proper SRAM address.
The DAC conversion and SHA sample in progress are
completely transparent to the serial bus activity. The
SRAM location of the addressed channel is then modi-
fied with the new data. The DAC and SHA are updated
with the new voltage. The sequencer then resumes
scrolling at the interrupted SRAM address.
Modes of Operation
The MAX5331/MAX5332/MAX5333 feature three modes
of operation:
• Sequence mode
• Immediate-update mode
• Burst mode
This operation can take up to two cycles of the 10µs
sequencer clock. Up to one cycle is needed to allow the
sequencer to complete the operation in progress before
it is freed to update the new channel. An additional
cycle is required to read the new data from memory,
update the DAC, and strobe the sample-and-hold. The
sequencer resumes scrolling from the location at which
it was interrupted. Normal sequencing is suppressed
while loading data, thus preventing other channels from
being refreshed. Under conditions of extremely frequent
immediate updates (i.e., 1000 successive updates), this
can result in unacceptable droop.
Table 3. Update Mode
UPDATE MODE
Immediate-Update Mode
Burst Mode
UPDATE TIME
2/f
SEQ
33/f
SEQ
Sequence Mode
Sequence mode is the default operating mode. The
internal sequencer continuously scrolls through the
SRAM, updating each of the 32 SHAs. At each SRAM
address location, the stored 12-bit DAC code is loaded
to the DAC. Once settled, the DAC output is acquired
by the corresponding SHA. Using the internal
sequencer clock, the process typically takes 320µs to
update all 32 SHAs (10µs per channel). Using an exter-
nal sequencer clock, the update process takes 128
clock cycles (four clock cycles per channel).
Figure 5 shows an example of an immediate-update
operation. In this example, data for channel 20 is
loaded, while channel 7 is being refreshed. The
sequencer operation is interrupted, and no other chan-
nels are refreshed as long as CS is held low. Once CS
returns high, and the remainder of an f
period (if
SEQ
Immediate-Update Mode
Immediate-update mode is used to change the con-
tents of a single SRAM location, and update the corre-
sponding SHA output. In immediate-update mode, the
any) has expired, channel 20 is updated to the new
data. Once channel 20 has been updated, the
sequencer resumes normal operation at the interrupted
channel 7.
1/f
SEQ
7
1/f
SHA ARRAY
UPDATE
SEQUENCE
SEQ
1
2
3
SKIP 20
7
8
9
SHA ARRAY
UPDATE
SEQUENCE
6
7
SKIP
SKIP SKIP
7
8
5
6
7
CHANNEL 20
UPDATED
33 CYCLES TO UPDATE
ALL CHANNELS
CS
CS
INTERRUPTED
CHANNEL REFRESHED
LOAD MULTIPLE
ADDRESSES
LOAD ADDRESS 20
DIN
DIN
24-BIT
WORD
Figure 5. Immediate-Update-Mode Timing Example
Figure 6. Burst-Mode Timing Example
12 ______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Burst Mode
Power-On Reset
A power-on reset (POR) circuit sets all channels to 0V
(code 4F3 hex) in sequence, requiring 320µs. This pre-
vents damage to downstream ICs due to arbitrary refer-
ence levels being presented following system power-up.
This same function is available by driving RST low.
During the reset operation, the sequencer is run by the
internal clock, regardless of the state of CLKSEL. The
reset process cannot be interrupted, serial inputs are
ignored until the entire reset process is complete.
Burst mode allows multiple SRAM locations to be
loaded at high speed. During burst mode, the output
voltages are not updated until the data burst is com-
plete and control returns to the sequencer. Select burst
mode by driving both IMMED and C1 low.
The sequencer is interrupted when CS is taken low. All
or part of the memory can be loaded while CS is low.
Each data word is loaded into its specified SRAM
address. The DAC conversion and SHA sample in
progress are completely transparent to the serial bus
activity. When CS is taken high, the sequencer resumes
scrolling at the interrupted SRAM address. New values
are updated when their turn comes up in the sequence.
Applications Information
Power Supplies and Bypassing
Grounding and power-supply decoupling strongly influ-
ence device performance. Digital signals can couple
through the reference input, power supplies, and
ground connection. Proper grounding and layout can
reduce digital feedthrough and crosstalk. At the device
After burst mode is used, it is recommended that at
least one full sequencer loop (320µs) is allowed to
occur before the serial port is accessed again. This
ensures that all outputs are updated before the
sequencer is interrupted.
level, a 0.1µF capacitor is required for the V , V
,
SS
DD
and V inputs. They should be placed as close to the
L_
Figure 6 shows an example of a burst-mode operation.
As with the immediate-update example, CS falls while
channel 7 is being refreshed. Data for multiple chan-
nels is loaded, and no channels are refreshed as long
as CS remains low. Once CS returns high, sequencing
resumes with channel 7 and continues normal refresh
pins as possible. More substantial decoupling at the
board level is recommended and is dependent on the
number of devices on the board (Figure 7).
The MAX5331/MAX5332/MAX5333 have three separate
+5V logic power supplies, V
LDAC
trol logic of the SHA array. V
, V
LSHA
LOGIC
, and V
.
LDAC LOGIC
LSHA
V
powers the 12-bit DAC. V
powers the con-
operation. Thirty-three f
cycles are required before
SEQ
powers the serial
all channels have been updated.
interface, sequencer, internal clock, and SRAM.
Additional filtering of V and V improves the
External Sequencer Clock
LDAC
LSHA
An external clock may be used to control the sequencer,
altering the output update rate. The sequencer runs at
1/4 the frequency of the supplied clock (ECLK). The
external clock option is selected by driving either C0 or
CLKSEL high.
overall performance of the device.
Chip Information
TRANSISTOR COUNT: 16,229
PROCESS: BiCMOS
When CLKSEL is asserted, the internal clock oscillator
is disabled. This feature allows synchronizing the
sequencer to other system operations, or shutting down
of the sequencer altogether during high-accuracy sys-
tem measurements. The low 1µV/ms droop of these
devices ensures that no appreciable degradation of the
output voltages occurs, even during extended periods
of time when the sequencer is disabled.
______________________________________________________________________________________ 13
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
+5V
+10V
0.1µF
0.1µF
V
V
V
V
LDAC
LSHA
DD
LOGIC
REF
GS
+2.5V
OUT0
OUT1
CS
DIN
MAX5331
MAX5332
MAX5333
SCLK
IMMED
CLKSEL
ECLK
RST
OUT31
AGND
V
CL
DGND
SS
0.1µF
-4V
Figure 7. Typical Operating Circuit
Pin Configurations (continued)
TOP VIEW
52
53
54
34
33
32
CL
N.C.
V
OUT21
OUT22
SS
CH
OUT23 55
31 OUT10
56
57
58
59
60
61
62
63
30
29
28
27
26
25
24
23
OUT24
OUT25
AGND
OUT9
OUT8
OUT7
OUT6
AGND
OUT5
OUT4
OUT3
OUT26
OUT27
OUT28
OUT29
OUT30
MAX5331
MAX5332
MAX5333
OUT31 64
AGND 65
22 OUT2
21
20
19
18
OUT1
OUT0
CL
V
REF 66
CH 67
N.C. 68
V
DD
THIN QFN
14 ______________________________________________________________________________________
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE,
64L TQFP, 10x10x1.4mm
1
21-0083
B
2
PACKAGE OUTLINE,
64L TQFP, 10x10x1.4mm
2
21-0083
B
2
______________________________________________________________________________________ 15
12-Bit DACs with 32-Channel
Sample-and-Hold Outputs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
1
C
21-0142
2
PACKAGE OUTLINE
68L THIN QFN, 10x10x0.8mm
2
C
21-0142
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
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