MAX534ACEE_技术文档

19-1105; Rev 0; 8/96

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

_______________Ge n e ra l De s c rip t io n

____________________________Fe a t u re s

The MAX534 serial-input, voltage-output, 8-bit quad dig-

ital-to-analog converter (DAC) operates from a single

+4.5V to +5.5V supply. Internal precision buffers swing

rail to rail, and the reference input range includes both

ground and the positive rail. The MAX534 features a

2.5µA shutdown mode.

♦ +4.5V to +5.5V Single-Supply Operation

♦ Ultra-Low Supply Current:

0.8mA while Operating

2.5µA in Shutdown Mode

♦ Ultra-Small 16-Pin QSOP Package

The serial interface is double buffered: a 12-bit input

shift register is followed by four 8-bit buffer registers and

four 8-bit DAC registers. The 12-bit serial word consists

of eight data bits and four control bits (for DAC selection

and special programming commands). Both the input

and DAC registers can be updated independently or

simultaneously with a single software command. Two

additional asynchronous control pins, LDAC and CLR,

provide simultaneous updating or clearing of the input

and DAC registers.

♦ Ground to V

Reference Input Range

DD

♦ Output Buffer Amplifiers Swing Rail to Rail

♦ 10MHz Serial Interface Compatible with SPI, QSPI

(CPOL = CPHA = 0 or CPOL = CPHA = 1), and

Microwire

♦ Double-Buffered Registers for Synchronous

Updating

♦ Serial Data Output for Daisy Chaining

The interface is compatible with SPI™, QSPI™ (CPOL =

CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A

buffered data output allows daisy chaining of serial

devices.

♦ Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

♦ Software Shutdown

In addition to 16-pin DIP and CERDIP packages, the

MAX534 is available in a 16-pin QSOP that occupies the

same area as an 8-pin SO.

♦ Software-Programmable Logic Output (µC I/O

Extender)

For operation guaranteed to 2.7V, see the MAX533

data sheet.

♦ Asynchronous Hardware Clear Resets All Internal

Registers to Zero

________________________Ap p lic a t io n s

Digital Gain and Offset Adjustments

Programmable Attenuators

______________Ord e rin g In fo rm a t io n

INL

PART

TEMP. RANGE PIN-PACKAGE

(LSB)

Programmable Current Sources

Portable Instruments

MAX534ACPE

MAX534BCPE

MAX534ACEE

MAX534BCEE

MAX534BC/D

MAX534AEPE

MAX534BEPE

MAX534AEEE

MAX534BEEE

MAX534AMJE

MAX534BMJE

0°C to +70°C 16 Plastic DIP

0°C to +70°C 16 QSOP

±1

±2

±1

±2

±1

±2

±1

±2

±1

±2

__________________P in Co n fig u ra t io n

0°C to +70°C 16 QSOP

0°C to +70°C Dice*

TOP VIEW

-40°C to +85°C 16 Plastic DIP

-40°C to +85°C 16 QSOP

-55°C to +125°C 16 CERDIP**

OUTB

OUTA

REF

1

2

3

4

5

6

7

8

16

15

14

13

OUTC

OUTD

AGND

UPO

PDE

MAX534

V

DD

12 DGND

11 DIN

*Dice are tested at T = +25°C.

**Contact factory for availability and processing to MIL-STD-883.

LDAC

CLR

A

10

9

SCLK

CS

DOUT

Functional Diagram appears at end of data sheet.

DIP/QSOP

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

________________________________________________________________ Maxim Integrated Products

1

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

ABSOLUTE MAXIMUM RATINGS

V

DD

to DGND ..............................................................-0.3V, +6V

Continuous Power Dissipation (T = +70°C)

A

V

to AGND...............................................................-0.3V, +6V

Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW

QSOP (derate 8.3mW/°C above +70°C).....................667mW

CERDIP (derate 10.00mW/°C above +70°C)..............800mW

Operating Temperature Ranges

DD

Digital Input Voltage to DGND ....................................-0.3V, +6V

Digital Output Voltage to DGND....................-0.3V, (V + 0.3V)

AGND to DGND..................................................................±0.3V

DD

REF................................................................-0.3V, (V + 0.3V)

MAX534 _ C_ E ..................................................0°C to +70°C

MAX534 _ E_ E ...............................................-40°C to +85°C

MAX534 _ MJE .............................................-55°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10sec) .............................+300°C

DD

OUT_ ...........................................................................-0.3V, V

DD

MAX534

Maximum Current into Any Pin............................................50mA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V = +4.5V to +5.5V, V

= 4.096V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.

MAX

DD

REF

L

A

MIN

Typical values are at V = +5V and T = +25°C.)

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

STATIC ACCURACY

Resolution

8

Bits

MAX534A

MAX534B

±1

Integral Nonlinearity

(Note 1)

INL

LSB

±2

Differential Nonlinearity (Note 1)

Zero-Code Error

DNL

ZCE

Guaranteed monotonic (all codes)

Code = 00 hex

±1.0

±20

LSB

mV

Zero-Code-Error Supply

Rejection

Code = 00 hex, V = 4.5V to 5.5V

DD

1

LSB

Zero-Code Temperature

Coefficient

Code = 00 hex

Code = FF hex

±10

µV/°C

mV

Full-Scale Error

±30

1

Full-Scale Error Supply

Rejection

Code = FF hex, V = 4.5V to 5.5V

DD

LSB

Full-Scale Temperature

Coefficient

Code = FF hex

µV/°C

REFERENCE INPUTS

Input Voltage Range

Input Resistance

0

V

DD

322

460

10

598

kΩ

pF

dB

Input Capacitance

Channel-to-Channel Isolation

AC Feedthrough

(Note 2)

(Note 3)

-60

DAC OUTPUTS

Output Voltage Range

R

= open

0

V

REF

V

L

Code = FF hex, measured with I = 0mA to

L

1.6mA

Load Regulation

0.156 LSB/mA

2

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

ELECTRICAL CHARACTERISTICS (continued)

(V = +4.5V to +5.5V, V

= 4.096V, AGND = DGND = 0V, R = 10kΩ, C = 100pF, T = T

to T , unless otherwise noted.

MAX

DD

REF

L

A

MIN

Typical values are at V = +5V and T = +25°C.)

DD

A

PARAMETER

DIGITAL INPUTS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Input High Voltage

Input Low Voltage

Input Current

V

0.7V

V

IH

DD

V

IL

0.3V

DD

I

IN

V

= 0V or V

DD

±1.0

10

µA

pF

IN

Input Capacitance

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

C

(Note 4)

IN

V

OH

I

= 0.2mA

V - 0.5

DD

V

SOURCE

V

OL

I

= 1.6mA

0.4

SINK

DYNAMIC PERFORMANCE

Voltage-Output Slew Rate

CODE = FF hex

0.6

8

V/µs

µs

To 1/2LSB, from code 00 to code FF hex

(Note 5)

Output Settling Time

Digital Feedthrough and

Crosstalk

VREF = 0V, code 00 to code FF hex (Note 6)

Code 80 hex to code 7F hex

5

nV-s

dB

Digital-to-Analog Glitch Impulse

50

80

V

= 4Vp-p at 1kHz, code = FF hex

= 4Vp-p at 10kHz

REF

Signal-to-Noise Plus

Distortion Ratio

SINAD

V

70

REF

Multiplying Bandwidth

Wideband Amplifier Noise

POWER SUPPLIES

V

REF

= 0.5Vp-p, 3dB bandwidth

380

60

kHz

µV

RMS

Power-Supply Voltage

V

4.5

5.5

1.3

1.5

10

V

DD

MAX534C/E

MAX534M

0.8

2.5

Supply Current

I

DD

mA

µA

Shutdown Current

TIMING CHARACTERISTICS

(V = +4.5V to +5.5V, V

= 4.096V, AGND = DGND = 0V, C

= 100pF, T = T

to T , unless otherwise noted.

MAX

DD

REF

DOUT

A

MIN

Typical values are at V = +5V and T = +25°C.)

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

50

UNITS

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

V

Rise to CS Fall Setup Time

DD

t

µs

VDCS

LDAC

(Note 4)

60

40

50

40

50

40

50

90

100

20

25

t

ns

LDAC Pulse Width Low

CS Rise to LDAC Fall Setup

Time (Note 7)

t

CLL

20

25

t

CLR Pulse Width Low

CS Pulse Width High

CLW

t

CSW

_______________________________________________________________________________________

3

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

TIMING CHARACTERISTICS (continued)

(V = +4.5V to +5.5V, V

= 4.096V, AGND = DGND = 0V, C

= 100pF, T = T

to T , unless otherwise noted.

MAX

DD

REF

DOUT

A

MIN

Typical values are at V = +5V and T = +25°C.)

DD

A

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SERIAL-INTERFACE TIMING

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

10

SCLK Clock Frequency (Note 8)

f

MHz

ns

CLK

MAX534

8.3

40

50

40

50

40

50

SCLK Pulse Width High

SCLK Pulse Width Low

t

CH

t

ns

CL

CS Fall to SCLK Rise Setup

Time

t

ns

CSS

t

0

ns

SCLK Rise to CS Rise Hold Time

CSH

MAX534C/E

MAX534M

40

50

0

DIN to SCLK Rise to Setup Time

DIN to SCLK Rise to Hold Time

t

ns

DS

t

DH

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

MAX534C/E

MAX534M

200

230

210

250

SCLK Rise to DOUT Valid

Propagation Delay (Note 9)

t

DO1

DO2

SCLK Fall to DOUT Valid

Propagation Delay (Note 10)

ns

40

50

40

50

t

SCLK Rise to CS Fall Delay

CS0

CS1

CS Rise to SCLK Rise Setup

Time

t

Note 1: INL and DNL are measured with R referenced to ground. Nonlinearity is measured from the first code that is greater than

L

or equal to the maximum offset specification to code FF hex (full scale). See DAC Linearity and Voltage Offset section.

Note 2:

Note 3:

V

= 4Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all other

REF

DAC’s codes to 00 hex.

= 4Vp-p, 10kHz. DAC code = 00 hex.

V

REF

Note 4: Guaranteed by design, not production tested.

Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of V

’s final value.

OUT

Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other

DAC.

Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for t

or longer after CS goes high.

LDAC

Note 8: When DOUT is not used. If DOUT is used, f

max is 4MHz, due to the SCLK to DOUT propagation delay.

CLK

Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of V ).

DD

Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of V ).

DD

4

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s

(V = +5V, T = +25°C, unless otherwise noted.)

DD

A

SUPPLY CURRENT vs.

TEMPERATURE

DAC ZERO-CODE OUTPUT VOLTAGE vs.

OUTPUT SINK CURRENT

DAC FULL-SCALE OUTPUT VOLTAGE vs.

OUTPUT SOURCE CURRENT

1000

800

600

400

1.50

1.25

1.00

0.75

5.0

4.5

4.0

3.5

V

= 5V

REF

DAC CODE = 00 HEX

LOAD TO V

DAC CODE = FF HEX

DD

DAC CODE = 00 HEX

0.50

0.25

0

3.0

2.5

2.0

V

= 5V

REF

200

0

DAC CODE = FF HEX

LOAD TO GND

V

= 4.5V

REF

0

1

2

3

4

5

6

7

8

-55 -35 -15

5

25 45 65 85 105 125

0

2

4

6

8

10

12

DAC OUTPUT SINK CURRENT (mA)

TEMPERATURE (°C)

DAC OUTPUT SOURCE CODE (mA)

SHUTDOWN SUPPLY CURRENT vs.

TEMPERATURE

SUPPLY CURRENT vs.

REFERENCE VOLTAGE

5

3

2

1000

800

600

400

ALL DAC CODES = FF HEX

ALL DAC CODES = 00 HEX

1

0

200

0

-55 -35 -15

5

25 45 65 85 105 125

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

REFERENCE VOLTAGE (V)

TEMPERATURE (°C)

_______________________________________________________________________________________

5

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

______________________________________________________________P in De s c rip t io n

NAME

FUNCTION

1

2

3

4

5

OUTB

OUTA

REF

DAC B Voltage Output

DAC A Voltage Output

Reference-Voltage Input

MAX534

UPO

Software-Programmable Logic Output

PDE

Power-Down Enable. Must be high to allow software shutdown mode.

Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents

of each input latch to its respective DAC latch.

6

7

LDAC

CLR

Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and

sets all DAC outputs to zero.

Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling

edge of SCLK (Table 1).

8

DOUT

CS

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are

executed when CS returns high.

9

Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising

edge (A0 = A1 = 1, see Table 1).

10

SCLK

11

12

13

14

15

16

DIN

Serial Data Input. Data is clocked in on the rising edge of SCLK.

Digital Ground

DGND

V

DD

Power Supply, +4.5V to +5.5V

Analog Ground

AGND

OUTD

OUTC

DAC D Voltage Output

DAC C Voltage Output

6

_______________________________________________________________________________________

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

INSTRUCTION

EXECUTED

CS

• • •

SCLK

DIN

• • •

C1

A1

C0

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

A1 A0 C1 C0

D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

A0

DACA

DACD

DOUT

MODE 1

• • •

A1

A0 C1 C0 D7

D0

D6 D5 D4 D3 D2 D1

A1 A0 C1 C0 D7

D6 D5 D4 D3 D2 D1 D0

A1

DATA FROM PREVIOUS DATA INPUT

DOUT

MODE 0

(DEFAULT)

• • •

D0

A1 A0 C1 C0 D7

D6 D5 D4 D3 D2 D1 D0

A1 A0 C1 C0 D7

D6 D5 D4 D3 D2 D1

A1

Figure 1. 3-Wire Interface Timing

CS

t

CSW

t

CSH

t

CH

t

CP

CS0

CSS

t

CS1

t

CL

SCLK

DIN

t

DS

t

DH

t

D02

t

D01

DOUT

LDAC

t

CLL

t

LDAC

Figure 2. Detailed Serial-Interface Timing Diagram

_______________________________________________________________________________________

7

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

Serial Input Data Format and Control Codes

_______________De t a ile d De s c rip t io n

The 12-bit serial input format shown in Figure 3 com-

prises two DAC address bits (A1, A0), two control bits

(C1, C0), and eight bits of data (D7...D0).

S e ria l In t e rfa c e

At p owe r-on, the s e ria l inte rfa c e a nd a ll d ig ita l-to-

analog converters (DACs) are cleared and set to code

zero. The serial data output (DOUT) is set to transition

on SCLK’s falling edge.

The 4-bit address/control code configures the DAC as

shown in Table 1.

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

The MAX534 c ommunic a te s with mic rop roc e s s ors

through a synchronous, full-duplex, 3-wire interface

(Figure 1). Data is sent MSB first and can be transmit-

ted in one 4-bit and one 8-bit (byte) packet or in one

12-bit word. If a 16-bit word is used, the first four bits

are ignored. A 4-wire interface adds a line for LDAC

and allows asynchronous updating. The serial clock

(SCLK) synchronizes the data transfer. Data is transmit-

ted and received simultaneously.

MAX534

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

Address

0

1

8-Bit Data

(LDAC = H)

When performing a single update operation, A1 and A0

select the respective input register. At the rising edge

of CS, the selected input register is loaded with the cur-

re nt s hift-re g is te r d a ta . All DAC outp uts re ma in

unchanged. This preloads individual data in the input

register without changing the DAC outputs.

Figure 2 shows the detailed serial-interface timing.

Please note that the clock should be low if it is stopped

b e twe e n up d a te s . DOUT d oe s not g o into a hig h-

impedance state if the clock idles or CS is high.

Load Input and DAC Registers

Serial data is clocked into the data registers in MSB-first

format, with the address and configuration information

preceding the actual DAC data. Data is clocked in on

SCLK’s rising edge while CS is low. Data at DOUT is

clocked out 12 clock cycles later, either at SCLK’s falling

edge (default or mode 0) or rising edge (mode 1).

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

Address

1

8-Bit Data

(LDAC = H)

This command directly loads the selected DAC register

at CS’s rising edge. A1 and A0 set the DAC address.

Current shift-register data is placed in the selected

input and DAC registers.

Chip select (CS) must be low to enable the DAC. If CS

is high, the interface is disabled and DOUT remains

unchanged. CS must go low at least 40ns before the

first rising edge of the clock pulse to properly clock in

the firs t b it. With CS low, d a ta is c loc ke d into the

MAX534’s internal shift register on the rising edge of

the external serial clock. Always clock in the full 12 bits

because each time CS goes high the bits currently in

the input shift register are interpreted as a command.

SCLK can be driven at rates up to 10MHz.

For example, to load all four DAC registers simultaneously

with individual settings (DAC A = 1V, DAC B = 2V,

DAC C = 3V, and DAC D = 4V), four commands are

re q uire d . Firs t, p e rform thre e s ing le inp ut re g is te r

update operations for DACs A, B, and C (C1 = 0). The

final command loads input register D and updates all

four DAC registers from their respective input registers.

Software “LDAC ” Command

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

THIS IS THE FIRST BIT SHIFTED IN

0

1

0

x

MSB

LSB

A1

A0

C1 C0 ..

D

.

7

D1 D6 D0

DOUT

DIN

(LDAC = 1)

When this command is initiated, all DAC registers are

updated with the contents of their respective input reg-

isters at CS’s rising edge. With the exception of using

CS to execute, this performs the same function as the

asynchronous LDAC.

8-BIT DAC DATA

CONTROL AND

ADDRESS BITS

Figure 3. Serial Input Format

_______________________________________________________________________________________

8

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

Table 1. Serial-Interface Programming Commands

12-BIT SERIAL WORD

LDAC

FUNCTION

A1

A0

C1

C0

D7 . . . . . . . . D0

0

1

0

1

0

1

0

1

8-bit DAC data

1

Load input register A; all DAC outputs unchanged.

Load input register B; all DAC outputs unchanged.

Load input register C; all DAC outputs unchanged.

Load input register D; all DAC outputs unchanged.

0

1

0

1

0

1

8-bit DAC data

1

Load input register A; all DAC outputs updated

Load input register B; all DAC outputs updated

Load input register C; all DAC outputs updated

Load input register D; all DAC outputs updated.

Software LDAC commands. Update all DACs from

their respective input registers. Also bring the part out

of shutdown mode.

0

1

0

X X X X X X X X

1

Load all DACs with shift-register data. Also bring the

part out of shutdown mode.

1

0

8-bit DAC data

X

1

0

1

0

1

0

1

0

X X X X X X X X

X

Software shutdown (provided PDE is high)

UPO goes low.

UPO goes high.

No operation (NOP); shift data in shift registers.

Set DOUT phase—SCLK rising (mode 1). DOUT

clocked out on rising edge of SCLK. All DACs updated

from their respective input registers.

1

0

1

0

X X X X X X X X

X

Set DOUT phase—SCLK falling (mode 0). DOUT

clocked out on falling edge of SCLK. All DACs up-

dated from their respective registers (default).

Load All DACs with Shift-Register Data

User-Programmable Output (UPO)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

8-Bit Data

UPO

Output

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

x

Low

(LDAC = X)

High

When this command is initiated, all four DAC registers

are updated with shift-register data. This command

allows all DACs to be set to any analog value within the

reference range. It can be used to substitute CLR if

code 00 hex is programmed, which clears all DACs.

(LDAC = X)

This command initiates the user-programmable logic

output for controlling another device across an isolated

interface. Example devices are gain control of an amplifi-

er and a polarity output for a motor speed control.

Software Shutdown

No Operation (NOP)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1

0

x

0

x

(LDAC = X, PDE = H)

(LDAC = X)

This command shuts down all output buffer amplifiers,

reducing supply current to 10µA max.

The NOP command (no operation) allows data to be

shifted through the MAX534 shift register without affect-

ing the input or DAC registers. This is useful in daisy

chaining (also see the Daisy Chaining Devices section).

_______________________________________________________________________________________

9

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

For this command, the data bits are “Don't Cares.” As

Serial Data Output

an example, three MAX534s are daisy chained (A, B,

and C), and devices A and C need to be updated. The

36-bit-wide command would consist of one 12-bit word

for device C, followed by an NOP instruction for device

B and a third 12-bit word with data for device A. At CS’s

rising edge, device B will not change state.

DOUT is the internal shift register’s output. DOUT can

be programmed to clock out data on SCLK’s falling

edge (mode 0) or rising edge (mode 1). In mode 0, out-

put data lags input data by 12.5 clock cycles, maintain-

ing compatibility with Microwire and SPI. In mode 1,

output data lags input data by 12 clock cycles. On

power-up, DOUT defaults to mode 0 timing. DOUT

never three-states; it always actively drives either high

or low and remains unchanged when CS is high.

MAX534

Set DOUT Phase—SCLK Rising (Mode 1)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1

0

x

(LDAC = x)

The mode 1 command resets the serial-output DOUT to

transition at SCLK’s rising edge. Once this command is

issued, DOUT’s phase is latched and will not change

except on power-up or if the specific command to set

the phase to falling edge is issued.

SCLK

DIN

SK

SO

MAX534

MICROWIRE

PORT

This command also loads all DAC registers with the con-

tents of their respective input registers, and is identical to

the “LDAC” command.

I/0

CS

Set DOUT Phase—SCLK Falling (Mode 0, Default)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1

0

1

0

x

(LDAC = x)

Figure 4. Connections for Microwire

This command resets DOUT to transition at SCLK’s

falling edge. The same command also updates all DAC

registers with the contents of their respective input reg-

isters, identical to the “LDAC” command.

LDAC Operation (Hardware)

LDAC is typically used in 4-wire interfaces (Figure 7).

This command is level sensitive, and allows asynchro-

nous hardware control of the DAC outputs. With LDAC

low the DAC registers are transparent, and any time an

input register is updated, the DAC output immediately

follows.

MAX534

DIN

SCLK

CS

MOSI

SPI/QSPI

PORT

SCK

I/0

Clear DACs with CLR

Strobing the CLR pin low causes an asynchronous

clear of input and DAC registers and sets all DAC out-

puts to zero. Similar to the LDAC pin, CLR can be

invoked at any time, typically when the device is not

selected (CS = H). When the DAC data is all zeros, this

function is equivalent to the “Update all DACs from Shift

Registers” command.

Figure 5. Connections for SPI/QSPI

10 ______________________________________________________________________________________

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

Interfacing to the Microprocessor

An a lo g S e c t io n

The MAX534 is Microwire™ and SPI™/QSPI™ compati-

ble (Figures 4 and 5). For SPI and QSPI, clear the

CPOL and CPHA configuration bits (CPOL = CPHA =

0). The SPI/QSPI CPOL = CPHA = 1 configuration can

also be used if the DOUT output is ignored.

DAC Operation

The MAX534 uses a matrix decoding architecture for

the DACs, which saves power in the overall system.

The external reference voltage is divided down by a

resistor string placed in a matrix fashion. Row and col-

umn d e c od e rs s e le c t the a p p rop ria te ta b from the

resistor string to provide the needed analog voltages.

The resistor string presents a code-independent input

impedance to the reference and guarantees a mono-

tonic output. Figure 8 shows a simplified diagram of the

four DACs.

The MAX534 can interface with Intel’s 80C5X/80C3X

family in mode 0 if the SCLK clock polarity is inverted.

More universally, if a serial port is not available, three

lines from one of the parallel ports can be used for bit

manipulation.

Digital feedthrough at the voltage outputs is greatly

minimized by operating the serial clock only to update

the registers. The clock idle state is low.

Reference Input

The voltage at REF sets the full-scale output voltage for

all four DACs. The 460kΩ typical input impedance at

REF is code independent. The output voltage for any

DAC can be represented by a digitally programmable

voltage source as follows:

Daisy-Chaining Devices

Any number of MAX534s can be daisy-chained by con-

necting DOUT of one device to DIN of the following

de vic e in the c ha in. The NOP instruc tion (Ta ble 1)

allows data to be passed from DIN to DOUT without

changing the input or DAC registers of the passing

device. A 3-wire interface updates daisy-chained or

individual MAX534s simultaneously by bringing CS

high (Figure 6).

V

OUT

= (NB x V ) / 256

REF

where NB is the numerical value of the DAC’s binary

input code.

MAX534

SCLK

DIN

CS

SCLK

DIN

CS

SCLK

DIN

CS

SCLK

DIN

CS

DOUT

TO OTHER

SERIAL DEVICES

DEVICE B

DEVICE A

DEVICE C

MAX534

SCLK

DIN

CS

SCLK

DIN

CS

Figure 6. Daisy-chained or individual MAX534s are simultaneously updated by bringing CS high. Only three wires are required.

______________________________________________________________________________________ 11

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

DIN

SCLK

LDAC

CS1

CS2

CS3

TO OTHER

SERIAL

DEVICES

MAX534

CS

MAX534

LDAC

SCLK

DIN

SCLK

DIN

SCLK

DIN

Figure 7. Multiple MAX534s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an

individual CS.

Output Buffer Amplifiers

All MAX534 voltage outputs are internally buffered by

p re c is ion unity-g a in followe rs tha t s le w a t a b out

REF

R1

R15

R16

R0

0.6V/µs. The outputs can swing from GND to V . With

DD

a 0V to +4V (or +4V to 0V) output transition, the amplifi-

er outputs will typically settle to 1/2LSB in 8µs when

loaded with 10kΩ in parallel with 100pF.

D7

D6

D5

D4

The buffer amplifiers are stable with any combination of

resistive (≥10kΩ) or capacitive loads.

R255

LSB DECODER

D2 D1

D3

D0

DAC A

Figure 8. DAC Simplified Circuit Diagram

12 ______________________________________________________________________________________

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

Careful PC board layout minimizes crosstalk among

DAC outputs and digital inputs. Figure 10 shows sug-

gested circuit board layout to minimize crosstalk.

__________Ap p lic a t io n s In fo rm a t io n

DAC Lin e a rit y a n d Vo lt a g e Offs e t

The output buffer can have a negative input offset volt-

age that would normally drive the output negative, but

since there is no negative supply the output stays at 0V

(Figure 9). When linearity is determined using the end-

point method, it is measured between zero code (all

inputs 0) and full-scale code (all inputs 1) after offset

and gain error are calibrated out. However, in single-

s up p ly op e ra tion the ne xt c od e a fte r ze ro ma y not

change the output, so the lowest code that produces a

positive output is the lower endpoint.

Un ip o la r-Ou t p u t ,

Tw o -Qu a d ra n t Mu lt ip lic a t io n

In unipolar operation, the output voltages and the refer-

ence input are the same polarity. Figure 11 shows the

MAX534 unipolar configuration, and Table 2 shows the

unipolar code.

SYSTEM GND

OUTC

OUTB

P o w e r S e q u e n c in g

The voltage applied to REF should not exceed V

any time. If proper power sequencing is not possible,

connect an external Schottky diode between REF and

at

DD

OUTD

AGND

OUTA

REF

V

DD

to ensure compliance with the absolute maximum

ratings. Do not apply signals to the digital inputs before

the device is fully powered up.

P o w e r-S u p p ly Byp a s s in g

a n d Gro u n d Ma n a g e m e n t

Connect AGND and DGND together at the IC. This

ground should then return to the highest-quality ground

available. Bypass V

with a 0.1µF capacitor, located

DD

Figure 10. Suggested PC Board Layout for Minimizing

Crosstalk (Bottom View)

as close to V and DGND as possible.

DD

REFERENCE INPUT

3

+3V

13

V

DD

REFAB

MAX534

2

OUTA

DAC A

OUTPUT

VOLTAGE

1

OUTB

OUTC

OUTD

DAC B

DAC C

DAC D

SERIAL

INTERFACE

NOT SHOWN

16

0V

DAC CODE

NEGATIVE

OFFSET

15

DGND

12

AGND

14

Figure 11. Unipolar Output Circuit

______________________________________________________________________________________ 13

Figure 9. Effect of Negative Offset (Single Supply)

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

Table 2. Unipolar Code Table

DAC CONTENTS

ANALOG

OUTPUT

MSB

LSB

255

256

1 1 1 1

+V

(

––––

)

REF

MAX534

129

256

1 0 0 0

0 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

+V

(

––––

)

REF

V

REF

128

––––

2

+V

(

––––

)

= +

REF

256

127

+V

(

––––

)

REF

256

1

0 0 0 0

0 0 0 1

0 0 0 0

+V

(

––––

REF

256

0V

1

-8

Note: 1LSB = (V ) (2 ) = +V_REF(––––)

REF

256

_________________________________________________________Fu n c t io n a l Dia g ra m

V

DD

DOUT

REF

CLR LDAC

PDE

DGND

AGND

UPO

DECODE

CONTROL

MAX534

OUTA

INPUT

REGISTER A

DAC

REGISTER A

DAC A

DAC B

DAC C

DAC D

OUTB

OUTC

OUTD

12-BIT

SHIFT

REGISTER

INPUT

REGISTER B

DAC

REGISTER B

INPUT

REGISTER C

DAC

REGISTER C

SR

INPUT

REGISTER D

DAC

REGISTER D

CONTROL

SCLK

CS

DIN

14 ______________________________________________________________________________________

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

MAX534

___________________Ch ip In fo rm a t io n

TRANSISTOR COUNT: 6821

________________________________________________________P a c k a g e In fo rm a t io n

INCHES

MILLIMETERS

INCHES

MILLIMETERS

DIM

DIM PINS

MIN

0.061

MAX

MIN

MAX

1.73

0.25

1.55

0.31

0.25

MIN MAX MIN

MAX

4.98

0.18

8.74

1.40

8.74

0.76

9.98

A

0.068

1.55

16 0.189 0.196 4.80

16 0.0020 0.0070 0.05

20 0.337 0.344 8.56

20 0.0500 0.0550 1.27

24 0.337 0.344 8.56

24 0.0250 0.0300 0.64

28 0.386 0.393 9.80

28 0.0250 0.0300 0.64

D

S

D

S

D

S

D

S

D

A1 0.004 0.0098 0.127

A2 0.055

0.061

0.012

1.40

0.20

0.19

B

C

D

E

e

0.008

A

0.0075 0.0098

SEE VARIATIONS

e

0.150

0.157

3.81

3.99

A1

B

0.25 BSC

0.635 BSC

0.76

21-0055A

H

h

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.89

S

L

N

S

α

SEE VARIATIONS

0°

8°

0°

8°

E

H

QSOP

QUARTER

SMALL-OUTLINE

PACKAGE

h x 45°

α

A2

N

E

L

C

______________________________________________________________________________________ 15

+5 V, Lo w -P o w e r, 8 -Bit Qu a d DAC

w it h Ra il-t o -Ra il Ou t p u t Bu ffe rs

________________________________________________________P a c k a g e In fo rm a t io n

INCHES

MIN

MILLIMETERS

DIM

MAX

0.200

0.023

0.065

0.015

0.310

0.320

MIN

–

MAX

5.08

0.58

1.65

0.38

7.87

8.13

E1

E

A

B

–

0.014

0.36

0.97

0.20

5.59

7.37

D

B1 0.038

A

C

E

0.008

0.220

MAX534

E1 0.290

e

L

0.100

2.54

0.125

0.150

0.015

–

0.200

–

3.18

3.81

0.38

–

5.08

–

0°-15°

C

Q

L1

Q

S

L

L1

0.070

0.098

–

1.78

2.49

–

e

B1

S1 0.005

0.13

B

S1

S

INCHES

MILLIMETERS

DIM PINS

MIN

–

MAX MIN MAX

CERDIP

D

8

0.405

0.785

0.840

0.960

1.060

1.280

–

10.29

19.94

21.34

24.38

26.92

CERAMIC DUAL-IN-LINE

PACKAGE

14

16

18

20

24

–

(0.300 in.)

–

32.51

21-0045A

INCHES

MILLIMETERS

DIM

E

MIN

MAX

MIN

–

MAX

5.08

–

A

–

0.200

–

E1

D

A1 0.015

A2 0.125

A3 0.055

0.38

3.18

1.40

0.41

1.14

0.20

0.13

7.62

6.10

2.54

7.62

–

0.175

0.080

0.022

0.065

0.012

0.080

0.325

0.310

–

4.45

2.03

0.56

1.65

0.30

2.03

8.26

7.87

–

A3

A2

A1

A

B

0.016

B1 0.045

0.008

D1 0.005

0.300

E1 0.240

0.100

eA 0.300

C

L

0° - 15°

C

E

e

B1

eA

–

B

eB

L

–

0.400

0.150

10.16

3.81

0.115

2.92

D1

INCHES

MILLIMETERS

PKG. DIM

PINS

Plastic DIP

PLASTIC

DUAL-IN-LINE

PACKAGE

(0.300 in.)

MIN

MAX MIN

MAX

8

P

N

D

0.348 0.390 8.84

9.91

14

16

18

20

24

0.735 0.765 18.67 19.43

0.745 0.765 18.92 19.43

0.885 0.915 22.48 23.24

1.015 1.045 25.78 26.54

1.14 1.265 28.96 32.13

21-0043A

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX534ACEE
厂家：	MAXIM INTEGRATED PRODUCTS
描述：	+5V, Low-Power, 8-Bit Quad DAC with Rail-to-Rail Output Buffers + 5V ，低功耗， 8位四路DAC，具有轨至轨输出缓冲器
文件：	总16页 (文件大小：126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX534ACEE [MAXIM]

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