MAX537BCPE+ [MAXIM]
D/A Converter, 4 Func, Serial Input Loading, 3us Settling Time, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16;
| 型号： | MAX537BCPE+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 4 Func, Serial Input Loading, 3us Settling Time, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：2432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0230; Rev 3; 3/11
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
_______________General Description
____________________________Features
♦ Four 12-Bit DACs with Output Buffers
The MAX536/MAX537 combine four 12-bit, voltage-output
digital-to-analog converters (DACs) and four precision
output amplifiers in a space-saving 16-pin package.
Offset, gain, and linearity are factory calibrated to provide
the MAX536’s 1 ꢀLS total unadꢁusted error. The
MAX537 operates with 5ꢂ supplies, while the MAX536
uses -5ꢂ and +10.8ꢂ to +13.2ꢂ supplies.
♦ Simultaneous or Independent Control of Four
DACs via a 3-Wire Serial Interface
♦ Power-On Reset
♦ SPI/QSPI and MICROWIRE Compatible
♦
1 ꢀSB ꢁotal ꢂnadꢃusted Error ꢄMAꢅX3ꢆ6
♦ Full 12-Bit Performance without Adꢃustments
X5 Supplꢇ Operation ꢄMAꢅX3ꢈ6
Each DAC has a double-buffered input, organized as
an input register followed by a DAC register. A 16-bit
serial word is used to load data into each input/DAC
register. The serial interface is compatible with either
LPI/QLPI™ or MICROWIRE™, and allows the input and
DAC registers to be updated independently or simulta-
neously with a single software command. The DAC reg-
isters can be simultaneously updated with a hardware
LDAC pin. All logic inputs are TTꢀ/CMOL compatible.
♦
♦ Double-Buffered Digital Inputs
♦ Buffered 5oltage Output
♦ 1ꢆ-Pin DIP/SO Packages
______________ Ordering Information
PIN-
PACKAGE
INꢀ
ꢄꢀSB6
PARꢁ
ꢁEMP RANGE
________________________Applications
MAꢅX3ꢆACPE+
MAX536SCPE+
MAX536ACWE+
MAX536SCWE+
MAX536AEPE+
MAX536SEPE+
MAX536AEWE+
MAX536SEWE+
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 PDIP
0.5
1
Industrial Process Controls
Automatic Test Equipment
Digital Offset and Gain Adꢁustment
Motion Control Devices
16 PDIP
16 Wide LO
16 Wide LO
16 PDIP
0.5
1
0.5
1
16 PDIP
Remote Industrial Controls
Microprocessor-Controlled Lystems
16 Wide LO
16 Wide LO
0.5
1
+Denotes a lead(Pb)-free/RoHS-compliant package.
________________Functional Diagram
Ordering Information continued at end of data sheet.
V
DD
DGND
AGND
V
SS
TP
REFAB
SDO LDAC
__________________Pin Configuration
DECODE
CONTROL
TOP VIEW
MAX536/MAX537
OUTA
OUTB
OUTC
OUTD
INPUT
REG A
DAC
REG A
+
DAC A
OUTB
OUTA
OUTC
OUTD
V
1
2
3
4
5
6
7
8
16
15
INPUT
REG B
DAC
REG B
DAC B
DAC C
DAC D
16-BIT
SHIFT
REGISTER
V
SS
14 DD
MAX536
MAX537
AGND
INPUT
REG C
DAC
REG C
TP
13
REFAB
DGND
LDAC
SDI
REFCD
12
11
10
9
INPUT
REG D
DAC
REG D
SDO
SCK
CS
SR
CONTROL
SCK
REFCD
CS
DIP/SO
SDI
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ABSOꢀꢂꢁE MAꢅIMꢂM RAꢁINGS
ꢂ
DD
to AGND or DGND
Continuous Power Dissipation (T = +70°C)
A
MAX536............................................................-0.3ꢂ to +13.2ꢂ
MAX537.................................................................-0.3ꢂ to +7ꢂ
Plastic DIP (derate 10.53mW/°C above +70°C) .................842mW
Wide LO (derate 9.52mW/°C above +70°C).................762mW
Operating Temperature Ranges
ꢂ
to AGND or DGND ............................................-7ꢂ to +0.3ꢂ
LL
LDI, LCK, CS, LDAC, TP, LDO
to AGND or DGND..................................-0.3ꢂ to (ꢂ
REFAS, REFCD to AGND or DGND ..........-0.3ꢂ to (ꢂ
OUT_ to AGND or DGND ..........................................ꢂ
Maximum Current into Any Pin............................................50mA
MAX53_AC_E/SC_E.............................................0°C to +70°C
MAX53_AE_E/SE_E ..........................................-40°C to +85°C
Ltorage Temperature Range.............................-65°C to +150°C
ꢀead Temperature (soldering, 10s) .................................+300°C
Loldering Temperature (reflow) .......................................+260°C
+ 0.3ꢂ)
+ 0.3ꢂ)
DD
DD
to ꢂ
DD
LL
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
EꢀECꢁRICAꢀ CHARACꢁERISꢁICS—MAꢅX3ꢆ
(ꢂ
= +12ꢂ, ꢂ = -5ꢂ, REFAS/REFCD = 8ꢂ, AGND = DGND = 0ꢂ, R = 5kΩ, C = 100pF, T = T
to T
, unless
MAX
DD
LL
ꢀ
ꢀ
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMEꢁER
SYMBOꢀ
CONDIꢁIONS
MIN
ꢁYP
MAꢅ
ꢂNIꢁS
SꢁAꢁIC PERFORMANCE—ANAꢀOG SECꢁION
Resolution
N
12
Sits
MAX536A
MAX536S
MAX536AC
MAX536SC
MAX536AE
MAX536SE
1.0
2.0
2.0
3.0
2.5
3.5
0.50
1
T
T
= +25°C
A
Total Unadꢁusted Error (Note 1)
TUE
ꢀLS
= T
to T
MAX
A
MIN
MAX536A
MAX536S
0.15
Integral Nonlinearity
INꢀ
ꢀLS
ꢀLS
Differential Nonlinearity
DNꢀ
Guaranteed monotonic
1
MAX536A
MAX536S
MAX536AC
MAX536SC
MAX536AE
MAX536SE
2.5
5.0
5.0
7.5
6.1
8.5
1.0
1.5
2.0
T
= +25°C
A
A
Offset Error
Gain Error
mꢂ
T
= T
to T
MAX
MIN
R = ∞
-0.1
-0.6
ꢀ
ꢀLS
MAX536_C/E
MAX536_M
R = 5kΩ
ꢀ
ꢂ
Power-Lupply Reꢁection
DD
PLRR
PLRR
T
T
= +25°C, 10.8ꢂ < ꢂ
< 13.2ꢂ
0.02
0.03
0.125
0.30
ꢀLS/ꢂ
ꢀLS/ꢂ
A
A
DD
Ratio
Power-Lupply Reꢁection Ratio
ꢂ
= +25°C, -5.5ꢂ < ꢂ
< -4.5ꢂ
LL
DD
2
____________________________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
EꢀECꢁRICAꢀ CHARACꢁERISꢁICS—MAꢅX3ꢆ ꢄcontinued6
(ꢂ
= +12ꢂ, ꢂ = -5ꢂ, REFAS/REFCD = 8ꢂ, AGND = DGND = 0ꢂ, R = 5kΩ, C = 100pF, T = T
to T
, unless
MAX
DD
LL
ꢀ
ꢀ
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMEꢁER
SYMBOꢀ
CONDIꢁIONS
MIN
ꢁYP
MAꢅ
ꢂNIꢁS
MAꢁCHING PERFORMANCE ꢄꢁ = +2X°C6
A
MAX536A
MAX536S
1.0
2.0
1.0
2.5
5.0
1.0
Total Unadꢁusted Error
Gain Error
TUE
ꢀLS
ꢀLS
mꢂ
0.1
1.2
1.2
0.2
MAX536A
MAX536S
Offset Error
Integral Nonlinearity
INꢀ
ꢀLS
REFERENCE INPꢂꢁ
Reference Input Range
Reference Input Resistance
REF
0
5
ꢂ
DD
- 4
ꢂ
Code dependent, minimum at code 555
R
kΩ
REF
MꢂꢀꢁIPꢀYING-MODE PERFORMANCE
Reference 3dS Sandwidth
ꢂ
= 2ꢂ
700
-100
-82
kHz
dS
REF
P-P
ꢂ
ꢂ
= 10ꢂ
= 10ꢂ
at 400Hz
at 4kHz
REF
REF
P-P
Input code =
all 0s
Reference Feedthrough
P-P
Total Harmonic Distortion Plus
Noise
THD+N
ꢂ
ꢂ
= 2.0ꢂ
at 50kHz
0.024
%
REF
P-P
DIGIꢁAꢀ INPꢂꢁS ꢄSDI, SCK, CS, LDAC6
Input High ꢂoltage
ꢂ
2.4
ꢂ
ꢂ
IH
Input ꢀow ꢂoltage
ꢂ
0.8
Iꢀ
Input ꢀeakage Current
Input Capacitance (Note 2)
DIGIꢁAꢀ OꢂꢁPꢂꢁ ꢄSDO6
Output ꢀow ꢂoltage
= 0ꢂ or ꢂ
1.0
10
µA
pF
DD
IN
ꢂ
LDO sinking 5mA
0.13
0.40
10
ꢂ
Oꢀ
Output ꢀeakage Current
LDO = 0ꢂ to ꢂ
µA
DD
DYNAMIC PERFORMANCE ꢄR = XkΩ, C = 100pF6
ꢀ
ꢀ
ꢂoltage Output Llew Rate
Output Lettling Time
5
3
5
8
ꢂ/µs
µs
To 0.5 ꢀLS of full scale
Digital Feedthrough
nꢂ-s
nꢂ-s
Digital Crosstalk (Note 3)
POWER SꢂPPꢀIES
ꢂ
= 5ꢂ
REF
Positive Lupply Range
Negative Lupply Range
ꢂ
10.8
-4.5
13.2
-5.5
18
ꢂ
ꢂ
DD
ꢂ
LL
T
A
T
A
T
A
T
A
= +25°C
8
Positive Lupply Current
(Note 4)
I
mA
mA
DD
= T
to T
25
MIN
MAX
-6
-16
= +25°C
= T to T
Negative Lupply Current
(Note 4)
I
LL
-23
MIN
MAX
_______________________________________________________________________________________
3
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
EꢀECꢁRICAꢀ CHARACꢁERISꢁICS—MAꢅX3ꢆ ꢄcontinued6
(ꢂ
= +12ꢂ, ꢂ = -5ꢂ, REFAS/REFCD = 8ꢂ, AGND = DGND = 0ꢂ, R = 5kΩ, C = 100pF, T = T
to T
, unless
MAX
DD
LL
ꢀ
ꢀ
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMEꢁER
SYMBOꢀ
CONDIꢁIONS
MIN
ꢁYP
MAꢅ
ꢂNIꢁS
ꢁIMING CHARACꢁERISꢁICS ꢄNote X6
Internal Power-On Reset
Pulse Width (Note 2)
t
20
µs
POR
LCK Clock Period
t
100
30
ns
ns
ns
CP
LCK Pulse Width High
LCK Pulse Width ꢀow
t
CH
t
30
Cꢀ
CS Fall to LCK Rise
Letup Time
t
20
10
ns
ns
CLL
LCK Rise to CS Rise
Hold Time
t
CLH
LDI Letup Time
LDI Hold Time
t
40
0
26
ns
ns
DL
t
DH
LDO high
LDO low
LDO high
LDO low
78
50
81
53
105
80
LCK Rise to LDO ꢂalid
Propagation Delay (Note 6)
1kΩ pullup on LDO
to ꢂ
t
ns
DO1
DO2
=
DD,
C
50pF
1kΩ pullup on LDO
to ꢂ
ꢀOAD
110
85
LCK Fall to LDO ꢂalid
Propagation Delay (Note 7)
t
ns
ns
ns
=
50pF
DD,
C
ꢀ
OAD
CS Fall to LDO Enable
(Note 8)
t
27
40
45
60
Dꢂ
CS Rise to LDO Disable
(Note 9)
t
TR
t
Continuous LCK, LCK edge ignored
LCK edge ignored
20
20
ns
ns
LCK Rise to CS Fall Delay
CL0
CS Rise to LCK Rise
Hold Time
t
CL1
t
30
40
ns
ns
LDAC Pulse Width ꢀow
CS Pulse Width High
ꢀDAC
t
CLW
Note 1: TUE is specified with no resistive load.
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC
.
Note 4: Digital inputs at 2.4ꢂ; with digital inputs at CMOL levels, I
DD decreases slightly.
Note X: All input signals are specified with t
= t ≤ 5ns. ꢀogic input swing is 0 to 5ꢂ.
R
F
Note ꢆ: Lerial data clocked out of LDO on LCK’s falling edge. (LDO is an open-drain output for the MAX536. The MAX537’s LDO
pin has an internal active pullup.)
Note ꢈ: Lerial data clocked out of LDO on LCK’s rising edge.
Note 8: LDO changes from High-Z state to 90% of final value.
Note 9: LDO rises 10% toward High-Z state.
4
_______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
EꢀECꢁRICAꢀ CHARACꢁERISꢁICS—MAꢅX3ꢈ
(ꢂ
= +5ꢂ, ꢂ = -5ꢂ, REFAS/REFCD = 2.5ꢂ, AGND = DGND = 0ꢂ, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
LL
ꢀ
ꢀ
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMEꢁER
SYMBOꢀ
CONDIꢁIONS
MIN
ꢁYP
MAꢅ
ꢂNIꢁS
SꢁAꢁIC PERFORMANCE—ANAꢀOG SECꢁION
Resolution
N
12
Sits
ꢀLS
ꢀLS
MAX537A
MAX537S
0.15
0.50
1
Integral Nonlinearity
Differential Nonlinearity
INꢀ
DNꢀ
Guaranteed monotonic
1
MAX537A
MAX537S
MAX537AC
MAX537SC
MAX537AE
MAX537SE
3.0
6.0
6.0
9.0
7.0
11.0
1.5
3.0
0.5
0.7
T
= +25°C
A
A
Offset Error
mꢂ
T
= T
to T
MAX
MIN
R = ∞
-0.3
-0.8
0.01
0.02
ꢀ
Gain Error
ꢀLS
R
= 5kΩ
ꢀ
A
A
ꢂ
ꢂ
Power-Lupply Reꢁection Ratio
Power-Lupply Reꢁection Ratio
PLRR
PLRR
T
T
= +25°C, 4.5ꢂ ≤ ꢂ
≤ 5.5ꢂ
DD
ꢀLS/ꢂ
ꢀLS/ꢂ
DD
LL
= +25°C, -5.5ꢂ ≤ ꢂ ≤ -4.5ꢂ
LL
MAꢁCHING PERFORMANCE ꢄꢁ = +2X°C6
A
Gain Error
0.1
0.3
1.25
3.0
ꢀLS
mꢂ
MAX537A
MAX537S
Offset Error
0.3
6.0
Integral Nonlinearity
INꢀ
0.35
1.0
ꢀLS
REFERENCE INPꢂꢁ
Reference Input Range
Reference Input Resistance
REF
0
5
ꢂ
DD -
2.2
ꢂ
RREF
Code dependent, minimum at code 555 hex
kΩ
MꢂꢀꢁIPꢀYING-MODE PERFORMANCE
Reference 3dS Sandwidth
ꢂ
= 2ꢂ
700
kHz
dS
REF
P-P
ꢂ
= 10ꢂ
at
at
REF
P-P
-100
400Hz
= 10ꢂ
Reference Feedthrough
Input code = all 0s
ꢂ
REF
P-P
-82
4kHz
Total Harmonic Distortion Plus
THD+N
ꢂ
ꢂ
= 850mꢂ
at 100kHz
0.024
%
REF
P-P
Noise
DIGIꢁAꢀ INPꢂꢁS ꢄSDI, SCK, CS, ꢀDAC6
Input High ꢂoltage
ꢂ
2.4
ꢂ
ꢂ
IH
Input ꢀow ꢂoltage
ꢂ
0.8
1.0
10
Iꢀ
Input ꢀeakage Current
Input Capacitance (Note 2)
= 0ꢂ or ꢂ
µA
pF
IN
DD
_______________________________________________________________________________________
X
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
EꢀECꢁRICAꢀ CHARACꢁERISꢁICS—MAꢅX3ꢈ ꢄcontinued6
(ꢂ
= +5ꢂ, ꢂ = -5ꢂ, REFAS/REFCD = 2.5ꢂ, AGND = DGND = 0ꢂ, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
LL
ꢀ
ꢀ
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMEꢁER
SYMBOꢀ
CONDIꢁIONS
MIN
ꢁYP
MAꢅ
ꢂNIꢁS
DIGIꢁAꢀ OꢂꢁPꢂꢁ ꢄSDO6
ꢂ
-
ꢂ
-
DD
DD
Output High ꢂoltage
ꢂ
LDO sourcing 2mA
LDO sinking 2mA
ꢂ
ꢂ
OH
0.5
0.25
0.13
Output ꢀow ꢂoltage
ꢂ
0.40
Oꢀ
DYNAMIC PERFORMANCE ꢄR = XkΩ, C = 100pF6
ꢀ
ꢀ
ꢂoltage Output Llew Rate
Output Lettling Time
5
5
5
5
ꢂ/µs
µs
To 0.5 ꢀLS of full scale
Digital Feedthrough
nꢂ-s
nꢂ-s
Digital Crosstalk (Note 3)
POWER SꢂPPꢀIES
Positive Lupply Range
Negative Lupply Range
ꢂ
4.5
5.5
-5.5
12
ꢂ
ꢂ
DD
ꢂ
-4.5
LL
T
A
T
A
T
A
T
A
= +25°C
5.5
Positive Lupply Current (Note 4)
Negative Lupply Current (Note 4)
I
mA
mA
DD
= T
to T
16
MIN
MAX
= +25°C
= T to T
-4.7
-10
-14
I
LL
MIN
MAX
ꢁIMING CHARACꢁERISꢁICS ꢄNote X6
Internal Power-On Reset Pulse
Width (Note 2)
t
50
µs
POR
LCK Clock Period
t
100
35
35
40
0
ns
ns
ns
ns
ns
ns
ns
CP
LCK Pulse Width High
LCK Pulse Width ꢀow
t
MAX537_C/E
MAX537_C/E
MAX537_C/E
CH
t
Cꢀ
CS Fall to LCK Rise Letup Time
LCK Rise to CS Rise Hold Time
LDI Letup Time
t
CLL
CLH
t
t
MAX537_C/E
40
0
24
DL
DH
LDI Hold Time
t
LCK Rise to LDO ꢂalid
Propagation Delay (Note 6)
LCK Fall To LDO ꢂalid
Propagation Delay (Note 7)
t
C
C
= 50pF, MAX537_C/E
= 50pF, MAX537_C/E
116
123
200
210
ns
ns
DO1
DO2
ꢀOAD
ꢀOAD
t
ꢆ
_______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
EꢀECꢁRICAꢀ CHARACꢁERISꢁICS—MAꢅX3ꢈ ꢄcontinued6
(ꢂ
= +5ꢂ, ꢂ = -5ꢂ, REFAS/REFCD = 2.5ꢂ, AGND = DGND = 0ꢂ, R = 5kΩ, C = 100pF, T = T
to T , unless
MAX
DD
LL
ꢀ
ꢀ
A
MIN
otherwise noted. Typical values are at T = +25°C.)
A
PARAMEꢁER
CS Fall to LDO Enable
SYMBOꢀ
CONDIꢁIONS
= 50pF, MAX537_C/E
= 50pF, MAX537_C/E
MIN
ꢁYP
MAꢅ
140
ꢂNIꢁS
ns
t
C
C
75
70
Dꢂ
ꢀOAD
ꢀOAD
CS Rise to DLO Disable (Note 10)
LCK Rise to CS Fall Delay
CS Rise to LCK Rise Hold Time
LDAC Pulse Width High
t
TR
130
ns
t
Continuous LCK, LCK edge ignored
LCK edge ignored, MAX537_C/E
MAX537_C/E
35
35
ns
CLO
t
ns
CL1
t
50
ns
ꢀDAC
CS Pulse Width High
t
MAX537_C/E
100
ns
CLW
Note 2: Guaranteed by design.
Note 3: Crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other DAC
.
Note 4: Digital inputs at 2.4ꢂ; with digital inputs at CMOL levels, I
DD decreases slightly.
Note X: All input signals are specified with t
= t ≤ 5ns. ꢀogic input swing is 0 to 5ꢂ.
R
F
Note ꢆ: Lerial data clocked out of LDO on LCK’s falling edge. (LDO is an open-drain output for the MAX536. The MAX537’s LDO
pin has an internal active pullup.)
Note ꢈ: Lerial data clocked out of LDO on LCK’s rising edge.
Note 10: When disabled, LDO is internally pulled high.
_______________________________________________________________________________________
ꢈ
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
__________________________________________Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
MAX536
MAX536
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
MAX536
MAX536
INTEGRAL NONLINEARITY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
ERROR vs. REFERENCE VOLTAGE
1.0
0.200
20
10
V
= -5V
DAC CODE = ALL 1s
REFAB SWEPT 2V
SS
P-P
REFAB = 10V
V
MONITORED
P-P
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
OUTA
0.6
0.2
R = 10kΩ, C = 100pF
L
L
0
V
= +15V
DD
-10
R = NO LOAD, C = 0pF
L
L
-20
-30
-0.2
V
= +12V
DD
--0.6
-40
-50
-1.0
0
4
8
12
16
10
100
200
1k
10k
100k
1M
10M
REFERENCE VOLTAGE (V)
FREQUENCY (kHz)
FREQUENCY (Hz)
MAX536
MAX536
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. REFERENCE FREQUENCY
MAX536
SUPPLY CURRENT vs. TEMPERATURE
FULL-SCALE ERROR vs. LOAD
10
6
0.200
1
DAC CODE = ALL 1s
REFAB = 5V
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
P-P
0
-1
-2
-3
I
DD
V
V
= +15V
= -5V
DD
SS
2
R = 10kΩ, C = 100pF
L
L
-2
R = NO LOAD, C = 0pF
L
L
I
SS
-6
-4
-5
-10
100
60
20
TEMPERATURE (°C)
140
-60
-20
10
100
200
0.1
1
10
100
1000
FREQUENCY (kHz)
LOAD (kΩ)
MAX536
MAX536
REFERENCE FEEDTHROUGH AT 400Hz
REFERENCE FEEDTHROUGH AT 4kHz
REFAB,
5V/div
REFAB,
5V/div
0V
0V
OUTA,
100µV/div
OUTA,
200µV/div
500µs/div
50µs/div
INPUT CODE = ALL 0s
INPUT CODE = ALL 0s
8
_______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
MAX536
MAX536
MAX536
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
CS,
5V/div
CS,
5V/div
OUTA,
5V/div
OUTA,
2V/div
OUTA,
5mV/div
5µs/div
1µs/div
V
= +15V, V = -5V, REFAB = 5V, C = 100pF, R = 10kΩ
V
= +15V, V = -5V, REFAB = 10V, C = 100pF, R = 10kΩ
DD
SS
L
L
DD
SS
L
L
MAX536
MAX536
DIGITAL FEEDTHROUGH
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
CS,
5V/div
SCK,
5V/div
OUTA,
5V/div
OUTA,
-10V OFFSET
5mV/div
OUTA,
AC-COUPLED,
10mV/div
1µs/div
V
= +15V, V = -5V, REFAB = 10V, CS = HIGH,
SS
V
= +15V, V = -5V, REFAB = 10V, C = 100pF, R = 10kΩ
SS L L
DD
DD
1
DIN TOGGLING AT ⁄ THE CLOCK RATE,
2
OUTA = 5V
_______________________________________________________________________________________
9
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
MAX537
MAX537
INTEGRAL NONLINEARITY
ERROR vs. REFERENCE VOLTAGE
2.0
MAX537
MAX537
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
REFERENCE VOLTAGE INPUT
FREQUENCY RESPONSE
20
10
0.200
REFAB SWEPT 2V
P-P
REFAB = 2.5V
V
V
= +5V
= -5V
P-P
DD
SS
1.5
1.0
V
OUTA
MONITORED
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
0
0.5
0
-10
R = 10kΩ, C = 100pF
L
L
-20
-30
-0.5
-1.0
-1.5
-2.0
R = NO LOAD, C = 0pF
L
L
-40
-50
0
1
2
3
4
5
1k
10k
100k
1M
10M
10
100
200
V
REF
(V)
FREQUENCY (Hz)
FREQUENCY (kHz)
MAX537
MAX537
MAX537
FULL-SCALE ERROR vs. LOAD
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
2
1
5
3
0.200
REFAB = 1V
P-P
0.175
0.150
0.125
0.100
0.075
0.050
0.025
0
I
DD
V
V
= +5V
= -5V
DD
SS
0
1
-1
R = 10kΩ, C = 100pF
L
L
-1
-2
-3
-4
I
SS
-3
-5
R = NO LOAD, C = 0pF
L
L
100
60
20
TEMPERATURE (°C)
140
0.1
1
10
100
1000
-60
-20
10
100
200
LOAD (kΩ)
FREQUENCY (kHz)
MAX537
MAX537
REFERENCE FEEDTHROUGH AT 4kHz
REFERENCE FEEDTHROUGH AT 400Hz
REFAB,
1V/div
REFAB,
1V/div
0V
0V
OUTA,
OUTA,
AC-COUPLED,
100µV/div
AC-COUPLED,
100µV/div
50µs/div
500µs/div
INPUT CODE = ALL 0s
INPUT CODE = ALL 0s
10 ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
____________________________Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
MAX537
MAX537
NEGATIVE FULL-SCALE SETTLING TIME
(ALL BITS ON TO ALL BITS OFF)
MAX537
DYNAMIC RESPONSE (ALL BITS ON, OFF, ON)
CS,
5V/div
CS,
5V/div
OUTA,
5mV/div
OUTA,
1V/div
1µs/div
5µs/div
V
= +5V, V = -5V, REFAB = 2.5V, C = 100pF, R = 10kΩ
V
= +5V, V = -5V, REFAB = 2.5V, C = 100pF, R = 10kΩ
DD
SS
L
L
DD
SS
L
L
MAX537
MAX537
DIGITAL FEEDTHROUGH
POSITIVE FULL-SCALE SETTLING TIME
(ALL BITS OFF TO ALL BITS ON)
CS,
5V/div
SCK,
5V/div
OUTA,
AC-COUPLED,
20mV/div
OUTA,
5mV/div
100ns/div
1µs/div
V
= +5V, V = -5V, REFAB = 2.5V, CS = HIGH,
SS
V
= +5V, V = -5V, REFAB = 2.5V, C = 100pF, R = 10kΩ
DD
DD
SS
L
L
1
DIN TOGGLING AT ⁄ THE CLOCK RATE,
2
OUTA = 1.25V
______________________________________________________________________________________ 11
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
______________________________________________________________Pin Description
PIN
1
NAME
OUTS
OUTA
FꢂNCꢁION
DAC S Output ꢂoltage
DAC A Output ꢂoltage
Negative Power Lupply
Analog Ground
2
3
ꢂ
LL
4
AGND
REFAS
DGND
5
Reference ꢂoltage Input for DAC A and DAC S
Digital Ground
6
ꢀoad DAC Input (active low). Driving this asynchronous input low transfers the contents of all input
registers to their respective DAC registers.
7
8
LDAC
LDI
Lerial Data Input. Data is shifted into an internal 16-bit shift register on LCK's rising edge.
Chip-Lelect Input (active low). A low level on CS enables the input shift register and LDO.
On CS’s rising edge, data is latched into the appropriate register(s).
9
CS
10
11
LCK
LDO
Lhift Register Clock Input
Lerial Data Output. LDO is the output of the internal shift register. LDO is enabled when CS is low.
For the MAX536, LDO is an open-drain output. For the MAX537, LDO has an active pullup to ꢂ
.
DD
12
13
14
15
16
REFCD
TP
Reference ꢂoltage Input for DAC C and DAC D
Test Pin. Connect to ꢂ
Positive Power Lupply
for proper operation.
DD
ꢂ
DD
OUTD
OUTC
DAC D Output ꢂoltage
DAC C Output ꢂoltage
_______________Detailed Description
The MAX536/MAX537 contain four 12-bit voltage-output
DACs that are easily addressed using a simple 3-wire
serial interface. They include a 16-bit data-in/data-out
shift register, and each DAC has a double-buffered
input composed of an input register and a DAC register
(see the Functional Diagram on the front page).
R
R
R
V
OUT
2R
2R
2R
D9
2R
2R
D11
D0
D10
The DACs are “inverted” R-2R ladder networks that
convert 12-bit digital inputs into equivalent analog out-
put voltages in proportion to the applied reference-volt-
age inputs. DAC A and DAC S share the REFAS refer-
ence input, while DAC C and DAC D share the REFCD
reference input. The two reference inputs allow different
full-scale output voltage ranges for each pair of DACs.
Figure 1 shows a simplified circuit diagram of one of
the four DACs.
Reference Inputs
The two reference inputs accept positive DC and AC
signals. The voltage at each reference input sets
the full-scale output voltage for its two correspond-
ing DACs. The REFAS/REFCD voltage range is 0ꢂ to
REF
AGND
SHOWN FOR ALL 1s ON DAC
Figure 1. Simplified DAC Circuit Diagram
a digitally programmable voltage source as:
= N (ꢂ /4096
ꢂ
OUT_
S
REF)
where N is the numeric value of the DAC’s binary input
code (0 to 4095) and ꢂ
S
(ꢂ
- 4ꢂ) for the MAX536 and 0ꢂ to (ꢂ
- 2.2ꢂ) for the
DD
DD
is the reference voltage.
REF
MAX537. The output voltages ꢂ
_ are represented by
OUT
12 ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
The input impedance at each reference input is code
dependent, ranging from a low value of typically 6kΩ
(with an input code of 0101 0101 0101) to a high value
of 60kΩ (with an input code of 0000 0000 0000). Lince
the input impedance at the reference pins is code
dependent, load regulation of the reference source is
important.
is 5µs when loaded with 5kΩ in parallel with 100pF
(loads less than 5kΩ degrade performance).
Output dynamic responses and settling performances
of the MAX536/MAX537 output amplifier are shown in
the Typical Operating Characteristics.
Serial-Interface Configurations
The MAX536/MAX537’s 3-wire or 4-wire serial interface is
compatible with both MICROWIRE (Figure 2) and
LPI/QLPI (Figure 3). In Figures 2 and 3, LDAC can be tied
either high or low for a 3-wire interface, or used as the
fourth input with a 4-wire interface. The connection
between LDO and the serial-interface port is not neces-
sary, but may be used for data echo. (Data held in the
shift register of the MAX536/MAX537 can be shifted out
of LDO and returned to the microprocessor for data veri-
fication; data in the MAX536/MAX537 input/DAC regis-
ters cannot be read.)
The REFAS and REFCD reference inputs have a 5kΩ
guaranteed minimum input impedance. When the two
reference inputs are driven from the same source, the
effective minimum impedance becomes 2.5kΩ.
The reference input capacitance is also code depen-
dent and typically ranges from 125pF to 300pF.
Output Buffer Amplifiers
All MAX536/MAX537 voltage outputs are internally
buffered by precision unity-gain followers with a typical
slew rate of 5ꢂ/µs for the MAX536 and 3ꢂ/µs for the
MAX537.
With a 3-wire interface (CS, LCK, LDI) and LDAC tied
high, the DACs are double-buffered. In this mode,
depending on the command issued through the serial
interface, the input register(s) may be loaded
without affecting the DAC register(s), the DAC register(s)
can be loaded directly, or all four DAC registers may be
simultaneously updated from the input registers. With a 3-
wire interface (CS, LCK, LDI) and LDAC tied low (Figure
With a full-scale transition at the MAX536 output (0 to
8ꢂ or 8ꢂ to 0), the typical settling time to 0.5 ꢀLS is
3µs when loaded with 5kΩ in parallel with 100pF (loads
less than 5kΩ degrade performance).
With a full-scale transition at the MAX537 output (0 to
2.5ꢂ or 2.5ꢂ to 0), the typical settling time to 0.5 ꢀLS
5V
5V
†
1kΩ
†
1kΩ
R
P
R
P
SS
SDO*
MISO*
SCK
SK
SDI
MOSI
SCK
SDI
SO
SI*
SPI/QSPI
PORT
MAX536
MAX537
SCK
MAX536
MAX537
MICROWIRE
PORT
SDO*
CS
I/O
I/O
CS
I/O
I/O
LDAC**
LDAC**
CPOL = 0, CPHA = 0
*THE SDO-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
*THE SDO-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE MAX536,
BUT MAY BE USED FOR READBACK PURPOSES.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
**THE LDAC CONNECTION IS NOT REQUIRED WHEN USING THE 3-WIRE INTERFACE.
†
THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO V
DD,
†
THE MAX537 HAS AN INTERNAL ACTIVE PULLUP TO V
DD,
SO R IS NOT NECESSARY.
P
SO R IS NOT NECESSARY.
P
Figure 2. Connections for MICROWIRE
Figure 3. Connections for SPI/QSPI
_______________________________________________________________________________________ 13
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
CS
COMMAND
EXECUTED
SCK
1
8
9
16
SDI
D2 D1 D0
..........
..........
D15 D14 D13
MSB
LSB
SDO
...........
Q15
Q0
..........
MSB FROM
PREVIOUS WRITE
LSB FROM
PREVIOUS WRITE
Figure 4. 3-Wire Serial-Interface Timing Diagram (LDAC = GND or V
)
DD
CS
INPUT REGISTER(S)
UPDATED
SCK
1
8
9
16
SDI
..........D2 D1 D0
D15 D14 D13..........
MSB
LSB
SDO
..........
Q15
Q0
..........
MSB FROM
PREVIOUS WRITE
LSB FROM
PREVIOUS WRITE
LDAC
DACs
UPDATED
Figure 5. 4-Wire Serial-Interface Timing Diagram for Asynchronous DAC Updating Using LDAC
t
CSW
CS
t
CP
t
CSH
t
t
CH
CSS
t
t
CL
CSO
t
CSI
SCK
t
DS
t
DH
SDI
t
DO2
t
DV
t
TR
t
DO1
SDO
LDAC*
*USE OF LDAC IS OPTIONAL
t
LDAC
Figure 6. Detailed Serial-Interface Timing Diagram
14 ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
4), the DAC registers remain transparent. Any time an
input register is updated, the change appears at the DAC
output with the rising edge of CS.
Interface timing is optimized when serial data is clocked out
of the microcontroller/microprocessor on one clock edge
and clocked into the MAX536/MAX537 on the other edge.
Table 1 lists the serial-interface programming commands.
For certain commands, the 12 data bits are “don’t cares”.
The 4-wire interface (CS, LCK, LDI, LDAC) is similar to
the 3-wire interface with LDAC tied high, except LDAC is
a hardware input that simultaneously and asynchronously
loads all DAC registers from their respective input regis-
ters when driven low (Figure 5).
The programming command ꢀoad-All-DACs-From-Lhift-
Register allows all input and DAC registers to be simultane-
ously loaded with the same digital code from the input shift
register. The NOP (no operation) command allows the regis-
ter contents to be unaffected and is useful when the
MAX536/MAX537 are configured in a daisy-chain (see the
Daisy-Chaining Devices section). The command to change
the clock edge on which serial data is shifted out of the
MAX536/MAX537 LDO pin also loads data from all input reg-
isters to their respective DAC registers.
Serial-Interface Description
The MAX536/MAX537 require 16 bits of serial data. Data is
sent MLS first and can be sent in two 8-bit packets or one
16-bit word (CS must remain low until 16 bits are trans-
ferred). The serial data is composed of two DAC address
bits (A1, A0), two control bits (C1, C0), and the 12 data bits
D11…D0 (Figure 7). The 4-bit address/control code deter-
mines the following: 1) the register(s) to be updated and/or
the status of the input and DAC registers (i.e., whether they
are in transparent or latch mode), and 2) the edge on which
data is clocked out of LDO.
Serial-Data Output
The serial-data output, LDO, is the internal shift register’s
output. The MAX536/MAX537 can be programmed so that
data is clocked out of LDO on LCK’s rising (Mode 1) or
falling (Mode 0) edge . In Mode 0, output data at LDO lags
input data at LDI by 16.5 clock cycles, maintaining compati-
bility with MICROWIRE, LPI/QLPI, and other serial interfaces.
In Mode 1, output data lags input data by 16 clock cycles.
On power-up, LDO defaults to Mode 1 timing.
Figure 6 shows the serial-interface timing requirements. The
chip-select pin (CS) must be low to enable the DAC’s serial
interface. When CS is high, the interface control circuitry is
disabled and the serial data output pin (LDO) is driven high
(MAX537) or is a high-impedance open drain (MAX536). CS
must go low at least tCLL before the rising serial clock (LCK)
edge to properly clock in the first bit. When CS is low, data is
clocked into the internal shift register via the serial data input
pin (LDI) on LCK’s rising edge. The maximum guaranteed
clock frequency is 10MHz. Data is latched into the appropri-
ate MAX536/MAX537 input/DAC registers on CS’s rising
edge.
For the MAX536, LDO is an open-drain output that should be
pulled up to +5ꢂ. The data sheet timing specifications for
LDO use a 1kΩ pullup resistor. For the MAX537, LDO is a
complementary output and does not require an external
pullup.
Test Pin
The test pin (TP) is used for pre-production analysis of the IC.
Connect ꢁP to 5 for proper MAꢅX3ꢆ/MAꢅX3ꢈ operation.
DD
MLS..................................................................................ꢀLS
16 Sits of Lerial Data
Failure to do so affects DAC operation.
Daisy-Chaining Devices
Any number of MAX536/MAX537s can be daisy-chained by
connecting the LDO pin of one device (with a pullup resistor,
if appropriate) to the LDI pin of the following device in the
chain (Figure 8).
Address
Sits
Control
Sits
Data Sits
MLS.............................................ꢀLS
A1 A0 C1 C0 D11................................................D0
4 Address/
12 Data Sits
Control Sits
Lince the MAX537’s LDO pin has an internal active pullup,
the LDO sink/source capability determines the time required
to discharge/charge a capacitive load. Refer to the serial
Figure 7. Serial-Data Format (MSB Sent First)
data out ꢂ
and ꢂ
specifications in the Electrical
Oꢀ
OH
Characteristics.
______________________________________________________________________________________ 1X
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ꢁable 1. Serial-Interface Programming Commands
1ꢆ-BIꢁ SERIAꢀ WORD
ꢀDAC
FꢂNCꢁION
A1
0
A0
0
C1
0
C0
1
D11…D0
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
XXXXXXXXXXXX
XXXXXXXXXXXX
1
1
1
1
1
1
1
1
X
X
1
ꢀoad DAC A input register; DAC output unchanged.
ꢀoad DAC S input register; DAC output unchanged.
ꢀoad DAC C input register; DAC output unchanged.
ꢀoad DAC D input register; DAC output unchanged.
ꢀoad input register A; all DAC registers updated.
ꢀoad input register S; all DAC registers updated.
ꢀoad input register C; all DAC registers updated.
ꢀoad input register D; all DAC registers updated.
ꢀoad all DACs from shift register.
0
1
0
1
1
0
0
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
1
X
X
0
0
0
0
1
0
0
No operation (NOP)
X
1
0
Update all DACs from their respective input registers.
Mode 1 (default condition at power-up), DOUT clocked out on
LCK’s rising edge. All DACs updated from their respective
input registers.
1
1
1
0
XXXXXXXXXXXX
X
Mode 0, DOUT clocked out on LCK’s falling edge. All DACs
updated from their respective input registers.
1
0
1
0
XXXXXXXXXXXX
X
0
0
1
1
0
1
0
1
X
X
X
X
1
1
1
1
12-bit DAC data
12-bit DAC data
12-bit DAC data
12-bit DAC data
0
0
0
0
ꢀoad DAC A input register; DAC A is immediately updated.
ꢀoad DAC S input register; DAC S is immediately updated.
ꢀoad DAC C input register; DAC C is immediately updated.
ꢀoad DAC D input register; DAC D is immediately updated.
“X” = Don’t Care. LDAC provides true latch control: when LDAC is low, the DAC registers are transparent; when LDAC is high,
the DAC registers are latched.
Additionally, when daisy-chaining devices, the maximum
clock frequency is limited to:
When daisy-chaining MAX536s, the delay from CS
low to LCK high (t ) must be the greater of:
CLL
t
+ t
or
Dꢂ
DL
1
f
(max) = ——————————————
LCK
2 (t
+ t - 38ns + t
)
DL
DO
RC
t
+ t + t - t
RC DL CLW
TR
For example, with t
p
8.7MHz.
= 23ns (5ꢂ 10% supply with
RC
where t is the time constant of the external pullup resistor
RC
R = 1kΩ and C = 30pF), the maximum clock frequency is
(R ) and the load capacitance (C) at LDO. For t < 20ns,
p
CLL
RC
t
is simply t + t . Calculate t from the following
Dꢂ
DL
RC
Figure 9 shows an alternate method of connecting several
MAX536/MAX537s. In this configuration, the data bus is
common to all devices; data is not shifted through a
daisy-chain. More I/O lines are required in this configu-
ration because a dedicated chip-select input (CS) is
required for each IC.
equation:
ꢂ
PUꢀꢀUP
t
= R (C) ln
p
RC
(
)
]
[
ꢂ
- 2.4ꢂ
PUꢀꢀUP
where ꢂ
is the voltage to which the pullup resistor is
PUꢀꢀUP
connected.
1ꢆ ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
+5V
+5V
+5V
R *
P
1kΩ
R *
P
1kΩ
R *
P
1kΩ
MAX536
MAX537
MAX536
MAX537
MAX536
MAX537
SCK
SDI
CS
SCK
SDI
CS
SCK
SDI
CS
SCK
DIN
SDO
SDO
SDO
CS
TO OTHER
SERIAL DEVICES
* THE MAX537 HAS AN ACTIVE INTERNAL PULLUP, SO R IS NOT NECESSARY.
P
Figure 8. Daisy-Chaining MAX536/MAX537s with a 3-Wire Serial Interface
DIN
SCK
LDAC
CS1
CS2
TO OTHER
SERIAL DEVICES
CS3
CS
CS
CS
LDAC
LDAC
LDAC
MAX536
MAX537
MAX536
MAX537
MAX536
MAX537
SCK
SDI
SCK
SDI
SCK
SDI
Figure 9. Multiple devices sharing a common DIN line may be simultaneously updated by bringing LDAC low. CS1, CS2, CS3… are
driven separately, thus controlling which data are written to devices 1, 2, 3…
______________________________________________________________________________________ 1ꢈ
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Sits 6 and 7 are not used. Writes to these bits are ignored.
__________Applications Information
The PORT D Data Direction Register (DDRD) deter-
Interfacing to the M68HC11*
mines whether the port bits are inputs or outputs. Its
PORT D of the 68HC11 supports LPI. The four registers
configuration is shown below:
used for LPI operation are the Lerial Peripheral Control
Register, the Lerial Peripheral Ltatus Register, the Lerial
BIꢁ
Peripheral Data I/O Register, and PORT D’s Data Direction
7
6
5
4
3
2
1
0
Register. These registers have a default starting location of
$1000.
NAME
–
–
DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
On reset, the PORT D register (memory location $1008) is
cleared and bits 5-0 are configured as general-purpose
inputs. Letting bit 6 (LPE) of the Lerial Peripheral Control
Register (LPCR) configures PORT D for LPI as follows:
Letting DDD_ = 0 configures the port bit as an input, while
setting DDD_ = 1 configures the port bit as an output. Writes
to bits 6 and 7 have no effect.
In LPI mode with MLTR = 1, when a PORT D bit is expected
to be an input (SS, MILO, RXD), the corresponding DDRD bit
(DDD_) is ignored. If the bit is expected to be an output
(LCK, MOLI, TXD), the corresponding DDRD bit must be
set for the bit to be an output.
BIꢁ
7
NAME
–
6
5
4
3
2
1
0
–
SS
LCK MOLI MILO TXD RXD
ꢁable 2. Serial Peripheral Control-Register Definitions
NAME
DEFINIꢁION
Lerial Peripheral Interrupt Enable. Clearing LPIE disables the LPI hardware-interrupt request; the LPLR is polled to
determine when an LPI data transfer is complete. Letting LPIE requests a hardware interrupt when the Lerial Peripheral
Ltatus Register’s LPIF bit or MODF bit is set.
LPIE
Letting LPE (Lerial Peripheral Lystem Enable) configures PORT D for LPI. Clearing LPE configures the port as a general-
purpose I/O port.
LPE
DWOM
MLTR
When DWOM is set, the six PORT D outputs are open drain. When DWOM is cleared, the outputs are complementary.
Master/Llave select option
Determines clock polarity. When set, the serial clock idles high while data is not being transferred; when cleared, the
clock idles low.
CPOꢀ
CPHA
Determines the clock phase.
LPI Clock-Rate Lelect
LPR1
LPR0
0
0
1
1
0
1
0
1
µP clock divided by 2
µP clock divided by 4
µP clock divided by 16
µP clock divided by 32
LPR1/0
ꢁable 3. Serial Peripheral Status-Register Definitions
NAME
DEFINIꢁION
LPIF
LPIF is set when an LPI data transfer is complete. It is cleared by reading the LPLR and then accessing the LPDR.
The Write Collision flag is set when a write to the LPDR occurs while a data transfer is in progress. It is cleared by read-
ing the LPLR and then accessing the LPDR.
WCOꢀ
MODF
The Mode Fault flag detects master/slave conflicts in a multimaster environment. It is set when the “master” controller
has its SS line (PORT D) pulled low, and cleared by reading the LPLR followed by a write to the LPCR.
*M68HC11 is a Motorola microcontroller. General information about the device was obtained from M68HC11 technical manuals.
18 ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ꢁable 4. Mꢆ8HC11 Programming Code
______________________________________________________________________________________ 19
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Unipolar Output
SS is an input intended for use in a multimaster environ-
ment. However, SS or unused PORT D bit RXD, TXD, or
possibly MILO (if DAC readback is not used) should be
configured as a general-purpose output and used as CS by
setting the appropriate Data Direction Register bit.
For a unipolar output, the output voltages and the reference
inputs are the same polarity. Figure 10 shows the
MAX536/MAX537 unipolar output circuit, which is also the typ-
ical operating circuit. Table 5 lists the unipolar output codes.
The LPCR configuration (memory location $1028) is shown
below:
Bipolar Output
The MAX536/MAX537 outputs can be configured for
bipolar operation using Figure 11’s circuit. One op amp
and two resistors are required per DAC. With R1 = R2:
BIꢁ
7
6
5
4
3
2
1
0
ꢂ
OUT
= ꢂ [(2N /4096) - 1]
REF S
NAME
LPIE LPE DWOM MLTR CPOꢀ CPHA LPR1 LPR0
where N is the numeric value of the DAC’s binary input
S
code. Table 6 shows digital codes and corresponding
output voltages for Figure 11’s circuit.
SEꢁꢁING AFꢁER RESEꢁ
0
0
0
0
0
1
U*
SEꢁꢁING FOR ꢁYPICAꢀ SPI COMMꢂNICAꢁION
0** 1**
U*
ꢁable X. ꢂnipolar Code ꢁable
0
1
0
1
0
0
DAC CONꢁENꢁS
ANAꢀOG OꢂꢁPꢂꢁ
*U = Unknown
**Depends on µP clock frequency.
MSB
ꢀSB
4095
( ——— )
4096
1111
1111 1111
+ꢂ
REF
REF
Always configure the 68HC11 as the “master” controller
and the MAX536/MAX537 as the “slave” device.
2049
( ——— )
4096
1000
1000
0111
0000
0001
+ꢂ
When MLTR = 1 in the LPCR, a write to the Lerial
Peripheral Data I/O Register (LPDR), located at memory
location $102A, initiates the transmission/reception of
data. The data transfer is monitored and the appropri-
ate flags are set in the Lerial Peripheral Ltatus
Register (LPLR).
2048
4096
+ꢂREF
0000 0000
1111 1111
+ꢂ
REF
( ——— ) = ————
2
2047
+ꢂ
( ——— )
4096
REF
REF
The LPLR configuration is shown below:
1
BIꢁ
7
NAME
LPIF WCOꢀ
0000
0000
0000 0001
0000 0000
+ꢂ
( ——— )
4096
6
5
4
3
–
0
2
–
0
1
–
0
0
–
0
0ꢂ
–
MODF
RESEꢁ CONDIꢁIONS
0
ꢁable ꢆ. Bipolar Code ꢁable
0
0
0
DAC CONꢁENꢁS
MSB
ANAꢀOG OꢂꢁPꢂꢁ
ꢀSB
An example of 68HC11 programming code for a
two-byte LPI transfer to the MAX536/MAX537 is given in
Table 4. SS is used for CS, the high byte of MAX536/
MAX537 digital data is stored in memory location $0100,
and the low byte is stored in memory location $0101.
2047
1111
1111 1111
+ꢂ
( ——— )
2048
REF
REF
1
1000
1000
0111
0000
0001
+ꢂ
( ——— )
2048
0000 0000
1111 1111
0ꢂ
Interfacing to Other Controllers
When using MICROWIRE, refer to the section on Inter-
facing to the M68HC11 for guidance, since MICROWIRE
can be considered similar to LPI when CPOꢀ = 0 and
CPHA = 0. When interfacing to Intel’s 80C51/80C31
microcontroller family, use bit-pushing to configure a
desired port as the MAX536/MAX537 interface port. Sit-
pushing involves arbitrarily assigning I/O port bits as
interface control lines, and then writing to the port each
time a signal transition is required.
1
-ꢂ
-ꢂ
( ——— )
2048
REF
REF
2047
( ——— )
2048
0000
0000
0000 0001
0000 0000
2048
( ——— ) = -ꢂ
-ꢂ
REF
REF
2048
1
NOꢁE: 1 ꢀLS = (ꢂ
) (
REF
)
4096
20 ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
+12V (+5V)
REFERENCE INPUTS
MAX536
MAX537
13
TP
5
12
14
MAX536
MAX537
V
REFAB
REFCD
DD
R1
R2
2
DAC A
DAC B
V
REF
OUTA
OUTB
+12V (+5V)
1
V
OUT
DAC
OUTPUT
16
15
DAC C
DAC D
OUTC
OUTD
–5V
R1 = R2 = 10kΩ 0.1%
V
AGND
DGND
6
SS
4
3
NOTES: ( ) ARE FOR MAX537.
IS THE SELECTED REFERENCE INPUT FOR THE MAX536/MAX537.
-5V
NOTE: ( ) ARE FOR MAX537.
V
REF
Figure 10. Unipolar Output Circuit
Figure 11. Bipolar Output Circuit
+12V
(+5V)
+12V (+5V)
14
AC
15kΩ
REFERENCE
INPUT
5
13
TP
REFAB
V
DD
+4V (+750mV)
5
13
TP
14
+
10kΩ
REFAB
V
V
DD
IN
-4V
2
DAC A
(-750mV)
OUTA
-
1
DAC B
OUTB
AGND
4
MAX536/MAX537
MAX536/MAX537
+
V
DGND
6
SS
V
V
SS
AGND
4
DGND
BIAS
3
-
3
6
-5V
-5V
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
NOTES: ( ) ARE FOR MAX537.
DIGITAL INPUTS NOT SHOWN.
Figure 12. AC Reference Input Circuit
Figure 13. AGND Bias Circuit
______________________________________________________________________________________ 21
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Offsetting AGND
AGND can be biased from DGND to the reference voltage
to provide an arbitrary nonzero output voltage for a zero
input code (Figure 13). The output voltage ꢂ
is:
OUTA
ꢂ
= ꢂ
+ N (ꢂ )
OUTA
SIAL S IN
3
4
V
SS
where ꢂ
is the positive offset voltage (with respect
to DGND) applied to AGND, and N is the numeric
SIAL
S
value of the DAC’s binary input code. Lince AGND is
common to all four DACs, all outputs will be offset by
MAX536
MAX537
1N5817
ꢂ
in the same manner. As the voltage at AGND
SIAL
increases, the DAC’s resolution decreases because its
full-scale voltage swing is effectively reduced. AGND
should not be biased more negative than DGND.
AGND
Power-Supply Considerations
On power-up, ꢂ should come up first, ꢂ
next, then
LL
DD
REFAS or REFCD. If supply sequencing is not possible,
tie an external Lchottky diode between ꢂ and AGND
LL
Figure 14. When V and V
cannot be sequenced, tie a
DD
SS
as shown in Figure 14. On power-up, all input and DAC
registers are cleared (set to zero code) and LDO is in
Mode 0 (serial data is shifted out of LDO on the clock’s
rising edge).
Schottky diode between V and AGND.
SS
Using an AC Reference
In applications where the reference has AC signal compo-
nents, the MAX536/MAX537 have multiplying capability
within the reference input range specifications. Figure 12
shows a technique for applying a sine-wave signal to the
reference input where the AC signal is offset before being
applied to REFAS/REFCD. The reference voltage must
never be more negative than DGND.
For rated MAX536 performance, ꢂ
should be 4ꢂ
DD
higher than REFAS/REFCD and should be between
10.8ꢂ and 13.2ꢂ. When using the MAX537, ꢂ should
DD
be at least 2.2ꢂ higher than REFAS/REFCD and should
be between 4.75ꢂ and 5.5ꢂ. Sypass both ꢂ and ꢂ
DD
LL
with a 4.7µF capacitor in parallel with a 0.1µF capacitor
to AGND. Use short lead lengths and place the bypass
capacitors as close to the supply pins as possible.
The MAX536’s total harmonic distortion plus noise
(THD+N) is typically less than 0.012%, given a 5ꢂP-P signal
swing and input frequencies up to 35kHz, or given a 2ꢂP-P
swing and input frequencies up to 50kHz. The typical -3dS
frequency is 700kHz as shown in the Typical Operating
Characteristics graphs.
Grounding and Layout Considerations
Digital or AC transient signals between AGND and
DGND can create noise at the analog outputs. Tie
AGND and DGND together at the DAC, then tie this
point to the highest quality ground available.
For the MAX537, with an input signal amplitude of
0.85mꢂP-P, THD+N is typically less than 0.024% with a
5kΩ load in parallel with 100pF and input frequencies up
to 100kHz, or with a 2kΩ load in parallel with 100pF and
input frequencies up to 95kHz.
Good PCS ground layout minimizes crosstalk between
DAC outputs, reference inputs, and digital inputs.
Reduce crosstalk by keeping analog lines away from
digital lines. Wire-wrapped boards are not recommend-
ed.
22 ______________________________________________________________________________________
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Ordering Information (continued)
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHL status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHL status.
PIN-
PACKAGE
INꢀ
ꢄꢀSB6
PARꢁ
ꢁEMP RANGE
MAꢅX3ꢈACPE+
MAX537SCPE+
MAX537ACWE+
MAX537SCWE+
MAX537AEPE+
MAX537SEPE+
MAX537AEWE+
MAX537SEWE+
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
16 PDIP
0.5
1
16 PDIP
16 Wide LO
16 Wide LO
16 PDIP
0.5
1
PACKAGE
ꢁYPE
PACKAGE
CODE
OꢂꢁꢀINE
NO.
ꢀAND
PAꢁꢁERN NO.
0.5
1
16 PDIP
16 LO
P16+9
W16+7
21-0043
21-0042
—
16 PDIP
90-010ꢈ
16 Wide LO
16 Wide LO
0.5
1
+Denotes a lead(Pb)-free/RoHS-compliant package.
______________________________________________________________________________________ 23
Calibrated, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
Revision History
RE5ISION
NꢂMBER
RE5ISION
DAꢁE
PAGES
CHANGED
DESCRIPꢁION
0
1/94
Initial release
—
Removed dice and ceramic LS packages and changed voltage supply
specifications
3
3/11
1–7, 13, 21, 22, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
MAX537BCWE+
D/A Converter, 4 Func, Serial Input Loading, 5us Settling Time, PDSO16, 0.300 INCH, SOIC-16
MAXIM
MAX537BCWE-T
D/A Converter, 4 Func, Serial Input Loading, 3us Settling Time, PDSO16, 0.300 INCH, MS-013AA, SOIC-16
MAXIM
MAX537BEPE+
D/A Converter, 4 Func, Serial Input Loading, 3us Settling Time, PDIP16, 0.300 INCH, PLASTIC, MS-001AA, DIP-16
MAXIM
MAX537BEWE+T
D/A Converter, 4 Func, Serial Input Loading, 5us Settling Time, PDSO16, 0.300 INCH, SOIC-16
MAXIM
©2020 ICPDF网 联系我们和版权申明