MAX5393 [MAXIM]
Dual 256-Tap, Volatile, Low-Voltage Linear Taper Digital Potentiometers; 双256抽头，易失，低电压线性变化数字电位器
| 型号： | MAX5393 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual 256-Tap, Volatile, Low-Voltage Linear Taper Digital Potentiometers |
| 文件： | 总13页 (文件大小：2228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5035; Rev 0; 10/09
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
General Description
Features
The MAX5391/MAX5393 dual 256-tap, volatile, low-
voltage linear taper digital potentiometers offer three
end-to-end resistance values of 10kI, 50kI, and 100kI.
Operating from a single +1.7V to +5.5V power sup-
ply, these devices provide a low 35ppm/NC end-to-end
temperature coefficient. The devices feature an SPIK
interface.
S Dual 256-Tap Linear Taper Positions
S Single +1.7V to +5.5V Supply Operation
S Low 12µA Quiescent Supply Current
S 10kI, 50kI, and 100kI End-to-End Resistance
Values
S SPI-Compatible Interface
The small package size, low supply voltage, low sup-
ply current, and automotive temperature range of the
MAX5391/MAX5393 make the devices uniquely suitable
for the portable consumer market, battery backup indus-
trial applications, and the automotive market.
S Wiper Set to Midscale on Power-Up
S -40NC to +125NC Operating Temperature Range
Ordering Information
The MAX5391/MAX5393 include two digital potentio-
meters in a voltage-divider configuration. The MAX5391/
MAX5393 are specified over the -40NC to +125NC auto-
motive temperature range and are available in a 16-pin,
3mm x 3mm TQFN and a 14-pin TSSOP package,
respectively.
END-TO-END
RESISTANCE (kI)
PART
PIN-PACKAGE
MAX5391LATE+
MAX5391MATE+
MAX5391NATE+
MAX5393LAUD+
MAX5393MAUD+
MAX5393NAUD+
16 TQFN-EP*
16 TQFN-EP*
16 TQFN-EP*
14 TSSOP
10
50
100
10
14 TSSOP
50
Applications
Low-Voltage Battery Applications
Portable Electronics
14 TSSOP
100
Note: All devices are specified in the -40NC to +125NC tem-
perature range.
Mechanical Potentiometer Replacement
Offset and Gain Control
+Denotes a lead(Pb)-free/RoHS-compliant package
*EP = Exposed pad.
Adjustable Voltage References/Linear Regulators
Automotive Electronics
Functional Diagram
WA
V
DD
BYP
HA
LA
CHARGE
PUMP
CS
SCLK
DIN
LATCH
POR
256 DECODER
HB
SPI
MAX5391
MAX5393
WB
LB
LATCH
256 DECODER
GND
SPI is a trademark of Motorola, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND ...........................................................-0.3V to +6V
Continuous Power Dissipation (T = +70NC)
A
H_, W_, L_ to GND......................................-0.3V to the lower of
14-Pin TSSOP (derate 10mW/NC above +70NC) ......796.8mW
16-Pin TQFN (derate 14.7mW/NC above +70NC) ...1176.5mW
Operating Temperature Range ....................... -40NC to +125NC
Junction Temperature ....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
(V + 0.3V) or +6V
DD
All Other Pins to GND .............................................-0.3V to +6V
Continuous Current into H_, W_, and L_
MAX5391L/MAX5393L................................................... Q5mA
MAX5391M/MAX5393M................................................. Q2mA
MAX5391N/MAX5393N ................................................. Q1mA
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +1.7V to +5.5V, V = V , V = GND, T = T
to T
, unless otherwise noted. Typical values are at V = +1.8V,
MAX DD
H_
DD L_
A
MIN
T
= +25NC.) (Note 1)
A
PARAMETER
Resolution
DC PERFORMANCE (Voltage-Divider Mode)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
N
256
Tap
Integral Nonlinearity
INL
(Note 2)
(Note 2)
-0.5
-0.5
-0.5
+0.5
+0.5
+0.5
LSB
LSB
Differential Nonlinearity
Dual-Code Matching
DNL
Register A = Register B
(DV /V )/DT, no load
LSB
Ratiometric Resistor Tempco
5
ppm/NC
W
W
MAX5391L/MAX5393L
MAX5391M/MAX5393M
MAX5391N/MAX5393N
MAX5391L/MAX5393L
MAX5391M/MAX5393M
MAX5391N/MAX5393N
-3
-1
-2.2
-0.6
-0.3
2.2
0.6
0.3
Full-Scale Error
Zero-Scale Error
Code = FFh
Code = 00h
LSB
LSB
-0.5
3
1
0.5
DC PERFORMANCE (Variable Resistor Mode)
Integral Nonlinearity
R-INL
(Note 3)
(Note 3)
-1.0
-0.5
+1.5
+0.5
LSB
LSB
Differential Nonlinearity
R-DNL
DC PERFORMANCE (Resistor Characteristics)
I
pF
Wiper Resistance
R
(Note 4)
200
WL
Terminal Capacitance
Wiper Capacitance
C _, C _ Measured to GND
H
10
50
35
L
C _
Measured to GND
No load
pF
W
End-to-End Resistor Tempco
End-to-End Resistor Tolerance
AC PERFORMANCE
Crosstalk
TC
ppm/NC
%
R
DR
Wiper not connected
-25
+25
HL
(Note 5)
-90
600
100
50
dB
MAX5391L/MAX5393L
Code = 08H,
10pF load,
-3dB Bandwidth
BW
MAX5391M/MAX5393M
MAX5391N/MAX5393N
kHz
V
DD
= 1.8V
Total Harmonic Distortion Plus
Noise
THD+N Measured at W, V = 1V
H_
at 1kHz
0.02
%
RMS
MAX5391L/MAX5393L
400
1200
2200
Wiper Settling Time (Note 6)
t
S
MAX5391M/MAX5393M
MAX5391N/MAX5393N
ns
2
______________________________________________________________________________________
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.7V to +5.5V, V = V , V = GND, T = T
to T
, unless otherwise noted. Typical values are at V = +1.8V,
MAX DD
H_
DD L_
A
MIN
T
= +25NC.) (Note 1)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Charge-Pump Feedthrough at W_
POWER SUPPLIES
V
RW
f
= 600kHz, C
= 0nF
200
nV
P-P
CLK
OUT
Supply Voltage Range
V
DD
1.7
27
12
5.5
V
V
V
= 5.5V
= 1.7V
DD
Standby Current
FA
DD
DIGITAL INPUTS
V
DD
V
DD
V
DD
V
DD
= 2.6V to 5.5V
= 1.7V to 2.6V
= 2.6V to 5.5V
= 1.7V to 2.6V
70
75
Minimum Input High Voltage
V
% x V
% x V
IH
DD
30
25
+1
Maximum Input Low Voltage
V
IL
DD
Input Leakage Current
Input Capacitance
-1
FA
5
pF
TIMING CHARACTERISTICS—SPI (Note 7)
SCLK Frequency
f
10
MHz
ns
MAX
SCLK Clock Period
t
100
40
40
40
0
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCK Rise Setup Time
SCLK Rise to CS Rise Hold Time
DIN Setup Time
t
ns
t
ns
CL
t
ns
CSS
CSH
t
ns
t
40
0
ns
DS
DH
DIN Hold Time
t
ns
SCLK Rise to CS Fall Delay
t
10
ns
CS0
SCLK Rise to SCLK Rise Hold
Time
t
40
ns
ns
CS1
CS Pulse-Width High
t
100
CSW
Note 1: All devices are 100% production tested at T = +25NC. Specifications over temperature limits are guaranteed by design
A
and characterization.
Note 2: DNL and INL are measured with the potentiometer configured as a voltage-divider (Figure 1) with H_ = V
and L_ =
DD
GND. The wiper terminal is unloaded and measured with a high-input-impedance voltmeter.
Note 3: R-DNL and R-INL are measured with the potentiometer configured as a variable resistor (Figure 1). DNL and INL are
measured with the potentiometer configured as a variable resistor. H_ is unconnected and L_ = GND. For V = +5V, the
DD
wiper terminal is driven with a source current of 400FA for the 10kI configuration, 80FA for the 50kI configuration, and
40FA for the 100kI configuration. For V = +1.7V, the wiper terminal is driven with a source current of 150FA for the
DD
10kI configuration, 30FA for the 50kI configuration, and 15FA for the 100kI configuration.
Note 4: The wiper resistance is the value measured by injecting the currents given in Note 3 into W_ with L_ = GND.
R
= (V
- V )/I
.
W_
W_
H_ W_
Note 5: Drive HA with a 1kHz GND to V
amplitude tone. LA = LB = GND. No load. WB is at midscale with a 10pF load.
DD
Measure WB.
Note 6: The wiper-settling time is the worst-case 0 to 50% rise time, measured between tap 0 and tap 127. H_ = V , L_ = GND,
DD
and the wiper terminal is loaded with 10pF capacitance to ground.
Note 7: Digital timing is guaranteed by design and characterization, not production tested.
_______________________________________________________________________________________
3
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
H
N.C.
W
W
L
L
Figure 1. Voltage-Divider and Variable Resistor Configurations
Typical Operating Characteristics
(V
DD
= 1.8V, T = +25NC, unless otherwise noted.)
A
SUPPLY CURRENT
vs. DIGITAL INPUT VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
30
25
10,000
30
25
20
15
10
V
= 5V
DD
V
DD
= 5V
1000
100
10
20
15
10
5
V
= 2.6V
DD
V
V
= 2.6V
= 1.8V
DD
DD
V
= 1.8V
DD
1
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIGITAL INPUT VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
1.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2
V
(V)
DD
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (10kI)
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (50kI)
RESISTANCE (W_-TO-L_)
vs. TAP POSITION (100kI)
10
9
8
7
6
5
4
3
2
1
0
50
45
40
35
30
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
0
0
51
102
153
204
255
0
51
102
153
204
255
0
51
102
153
204
255
TAP POSITION
TAP POSITION
TAP POSITION
4
______________________________________________________________________________________
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Typical Operating Characteristics (continued)
(V
DD
= 1.8V, T = +25NC, unless otherwise noted.)
A
WIPER RESISTANCE
vs. WIPER VOLTAGE
END-TO-END RESISTANCE PERCENTAGE
CHANGE vs. TEMPERATURE
VARIABLE RESISTOR DNL
vs. TAP POSITION (10kI)
0.05
0.04
0.03
0.02
0.01
0
0.10
0.08
0.06
0.04
0.02
0
140
100kI
120
100
80
50kI
-0.02
-0.04
-0.06
-0.08
-0.10
10kI
V
= 5V
DD
-0.01
-0.02
-0.03
V
= 1.8V
DD
V
= 2.6V
DD
I
= 150µA
WIPER
60
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
WIPER VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
0
0
0
51
102
153
204
255
255
255
TAP POSITION
VARIABLE RESISTOR DNL
vs. TAP POSITION (50kI)
VARIABLE RESISTOR DNL
vs. TAP POSITION (100kI)
VARIABLE RESISTOR INL
vs. TAP POSITION (10kI)
0.10
0.08
0.06
0.04
0.02
0
0.10
0.08
0.06
0.04
0.02
0
1.0
0.8
0.6
0.4
0.2
0
-0.02
-0.04
-0.06
-0.08
-0.10
-0.02
-0.04
-0.06
-0.08
-0.10
-0.2
-0.4
-0.6
-0.8
-1.0
I
= 150µA
WIPER
I
= 30µA
51
I
= 15µA
51
WIPER
WIPER
0
102
153
204
255
0
102
153
204
255
51
102
153
204
TAP POSITION
TAP POSITION
TAP POSITION
VARIABLE RESISTOR INL
vs. TAP POSITION (50kI)
VARIABLE RESISTOR INL
vs. TAP POSITION (100kI)
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (10kI)
0.5
0.4
0.5
0.4
0.10
0.08
0.06
0.04
0.02
0
0.3
0.3
0.2
0.2
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.02
-0.04
-0.06
-0.08
-0.10
I
= 30µA
I
= 15µA
WIPER
WIPER
0
51
102
153
204
255
0
51
102
153
204
255
51
102
153
204
TAP POSITION
TAP POSITION
TAP POSITION
_______________________________________________________________________________________
5
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Typical Operating Characteristics (continued)
(V
DD
= 1.8V, T = +25NC, unless otherwise noted.)
A
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (50kI)
0.10
VOLTAGE-DIVIDER DNL
vs. TAP POSITION (100kI)
VOLTAGE-DIVIDER INL
vs. TAP POSITION (10kI)
0.10
0.08
0.06
0.04
0.02
0
0.5
0.4
0.08
0.06
0.04
0.02
0
0.3
0.2
0.1
0
-0.02
-0.04
-0.06
-0.08
-0.10
-0.02
-0.04
-0.06
-0.08
-0.10
-0.1
-0.2
-0.3
-0.4
-0.5
0
51
102
153
204
255
0
51
102
153
204
255
0
51
102
153
204
255
TAP POSITION
TAP POSITION
TAP POSITION
VOLTAGE-DIVIDER INL
vs. TAP POSITION (100kI)
VOLTAGE-DIVIDER INL
vs. TAP POSITION (50kI)
TAP-TO-TAP SWITCHING TRANSIENT
(CODE 127 TO CODE 128) (10kI)
MAX5391 toc21
0.5
0.4
0.5
0.4
0.3
0.3
V
W_-L_
0.2
0.2
20mV/div
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
CS
5V/div
0
51
102
153
204
255
0
51
102
153
204
255
400ns/div
TAP POSITION
TAP POSITION
TAP-TO-TAP SWITCHING TRANSIENT
TAP-TO-TAP SWITCHING TRANSIENT
MAX5391M P0WER-ON TRANSIENT
(CODE 127 TO CODE 128) (50kI)
(CODE 127 TO CODE 128) (100kI)
MAX5391 toc24
MAX5391 toc22
MAX5391 toc23
V
W_-L_
V
W_-L_
1V/div
20mV/div
V
W_-L_
20mV/div
CS
5V/div
CS
5V/div
V
DD
5V/div
2µs/div
1µs/div
1µs/div
6
______________________________________________________________________________________
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Typical Operating Characteristics (continued)
(V
DD
= 1.8V, T = +25NC, unless otherwise noted.)
A
MIDSCALE FREQUENCY
RESPONSE (10kI)
MIDSCALE FREQUENCY
RESPONSE (50kI)
MIDSCALE FREQUENCY
RESPONSE (100kI)
10
10
0
10
0
V
= 5V
DD
V
= 5V
V
DD
= 5V
DD
0
-10
-20
-30
V
= 1.8V
-10
-20
-30
-10
-20
-30
DD
V
= 1.8V
DD
V
= 1.8V
DD
V
= 1V
P-P
IN
V
= 1V
V = 1V
IN P-P
IN
P-P
0.01
1
100
10k
0.01
1
100
10k
0.01
1
100
10k
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
CROSSTALK vs. FREQUENCY
0.20
0
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
-20
-40
10kI
100kI
50kI
100kI
-60
-80
-100
-120
-140
50kI
10kI
0.01
0.1
1
10
100
0.01
0.1
1
10
100
1000
FREQUENCY (kHz)
FREQUENCY (kHz)
CHARGE-PUMP FEEDTHROUGH
BYP RAMP vs. C
AT W_ vs. C
BYP
BYP
120
100
80
60
40
20
0
700
600
500
400
300
200
100
0
0
0.02
0.04
0.05
0.08
0.10
0
200
400
600
800
CAPACITANCE (µF)
CAPACITANCE (pF)
_______________________________________________________________________________________
7
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Pin Configurations
TOP VIEW
TOP VIEW
12
11
10
9
+
GND
LB
1
2
3
4
5
6
7
14 LA
13 HA
12 WA
8
7
6
5
CS
N.C. 13
HA 14
HB
BYP
N.C.
GND
WB
I.C.
BYP
CS
11
V
DD
MAX5393
MAX5391
WA
LA
15
16
10 N.C.
*EP
9
8
SCLK
DIN
+
1
2
3
4
*EP = EXPOSED PAD
Pin Description
PIN
NAME
FUNCTION
MAX5391
(TQFN-EP)
MAX5393
(TSSOP)
Resistor B High Terminal. The voltage at HB can be higher or lower than the voltage at
LB. Current can flow into or out of HB.
1
2
3
3
4
2
HB
WB
LB
Resistor B Wiper Terminal
Resistor B Low Terminal. The voltage at LB can be higher or lower than the voltage at HB.
Current can flow into or out of LB.
4
5
5
1
I.C.
GND
N.C.
Internally Connected. Connect to GND.
Ground
6, 11, 13
10
No Connection. Not internally connected.
Internal Power-Supply Bypass. For additional charge-pump filtering, bypass to GND with
a capacitor close to the device.
7
6
BYP
8
9
7
8
Active-Low Chip-Select Input
Serial-Interface Data Input
Serial-Interface Clock Input
CS
DIN
10
12
9
SCLK
11
V
DD
Power-Supply Input. Bypass V
to GND with a 0.1FF capacitor close to the device.
DD
Resistor A High Terminal. The voltage at HA can be higher or lower than the voltage at
LA. Current can flow into or out of HA.
14
15
16
—
13
12
14
—
HA
WA
LA
Resistor A Wiper Terminal
Resistor A Low Terminal. The voltage at LA can be higher or lower than the voltage at HA.
Current can flow into or out of LA.
EP
Exposed Pad (MAX5391 Only). Connect to GND.
8
______________________________________________________________________________________
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
C
does affect the startup time of the charge pump;
BYP
Detailed Description
however, C
does not impact the ability to commu-
BYP
The MAX5391/MAX5393 dual 256-tap, volatile, low-volt-
age linear taper digital potentiometers offer three end-to-
end resistance values of 10kI, 50kI, and 100kI. Each
potentiometer consists of 255 fixed resistors in series
between terminals H_ and L_. The potentiometer wiper,
W_, is programmable to access any one of the 256 tap
points on the resistor string.
nicate with the device, nor is there a minimum C
requirement. The maximum wiper impedance specifi-
cation is not guaranteed until the charge pump is fully
BYP
settled. See the BYP Ramp vs. C
Operating Characteristics for C
pump settling time.
graph in the Typical
impact on charge-
BYP
BYP
SPI Digital Interface
The MAX5391/MAX5393 include a SPI interface that pro-
vides a 3-wire write-only serial-data interface to control
the wiper tap position through inputs chip select (CS),
data in (DIN), and data clock (SCLK). Drive CS low to
load data from DIN synchronously into the serial shift
register on the rising edge of each SCLK pulse. The
MAX5391/MAX5393 load the last 10 bits of clocked data
into the appropriate potentiometer control register once
CS transitions high. See Figures 2 and 3. Data written
to a memory register immediately updates the wiper
position. Keep CS low during the entire data stream to
prevent the data from being terminated.
The potentiometers in each device are programmable
independently of each other. The MAX5391/MAX5393
feature an SPI interface.
Charge Pump
The MAX5391/MAX5393 contain an internal charge
pump that guarantees the maximum wiper resistance,
R , to be less then 200I for supply voltages down to
WL
1.7V. Pins H_, W_, and L_ are still required to be less
than V + 0.3V. A bypass input, BYP, is provided to
DD
allow additional filtering of the charge-pump output, fur-
ther reducing clock feed through that may occur on H_,
W_, or L_. The nominal clock rate of the charge pump
is 600kHz. BYP should remain resistively unloaded as
any additional load would produce a ripple of approxi-
The first two bits A1:A0 (address bits) address one of
the two potentiometers. See Table 1. The power-on reset
(POR) circuitry sets the wiper to midscale.
mately I
/(600kHz x C
BYP
) volts. See the Charge-
BYP
Pump Feedthrough at W_ vs. C
graph in the Typical
BYP
Operating Characteristics for C
sizing guidelines with
BYP
respect to clock feedthrough to the wiper. The value of
Table 1. SPI Register Map
Bit Number
1
A1
0
2
A0
0
3
4
5
6
7
8
9
10
D0
D0
D0
D0
Bit Name
D7
D7
D7
D7
D6
D6
D6
D6
D5
D5
D5
D5
D4
D4
D4
D4
D3
D3
D3
D3
D2
D2
D2
D2
D1
D1
D1
D1
Write Wiper Register A
Write Wiper Register B
Write to Both A and B
0
1
1
1
COMMAND
STARTED 10-BIT
WIPER REGISTER
LOADED
CS
SCLK
DIN
A0
A1
D7
D6
D5
D4
D3
D0
D2
D1
Figure 2. SPI Digital Interface Format
_______________________________________________________________________________________
9
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
t
CSW
CS
t
CS1
t
CH
t
t
CP
t
CSH
CSO
t
CSS
t
CL
t
DH
t
DS
SCLK
DIN
Figure 3. SPI Timing Diagram
REG A: The data byte writes to register A, and the wiper
of potentiometer A moves to the appropriate position at
the rising edge of CS. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position clos-
est to LA. D[7:0] = FFh moves the wiper closest to HA.
D[7:0] is 80h following power-on.
Applications Information
Variable Gain Amplifier
Figure 4 shows a potentiometer adjusting the gain of a
noninverting amplifier. Figure 5 shows a potentiometer
adjusting the gain of an inverting amplifier.
REG B: The data byte writes to register B, and the wiper
of potentiometer B moves to the appropriate position at
the rising edge of CS. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position clos-
est to LB. D[7:0] = FFh moves the wiper to the position
closest to HB. D[7:0] is 80h following power-on.
Adjustable Dual Regulator
Figure 6 shows an adjustable dual linear regulator using
a dual potentiometer as two variable resistors.
Adjustable Voltage Reference
Figure 7 shows an adjustable voltage reference circuit
using a potentiometer as a voltage divider.
REG A and B: The data byte writes to registers A and
B, and the wipers of potentiometers A and B move to the
appropriate position. D[7:0] indicates the position of the
wiper. D[7:0] = 00h moves the wiper to the position clos-
est to L_. D[7:0] = FFh moves the wiper to the position
closest to H_. D[7:0] is 80h following power-on.
10 _____________________________________________________________________________________
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
H_
L_
V
IN
V
OUT
W_
V
IN
V
OUT
W_
H_
L_
Figure 4. Variable-Gain Noninverting Amplifier
Figure 5. Variable-Gain Inverting Amplifier
V
V
OUT1
OUT1
OUT2
OUT2
+2.5V
IN
V
REF
OUT
H_
L_
H_
L_
H_
MAX8866
V+
MAX6037
IN
W_
W_
W_
SET1
SET2
L_
GND
Figure 6. Adjustable Dual Linear Regulator
Figure 7. Adjustable Voltage Reference
______________________________________________________________________________________ 11
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Variable-Gain Current-to-Voltage Converter
Figure 8 shows a variable-gain current-to-voltage con-
verter using a potentiometer as a variable resistor.
Offset Voltage Adjustment Circuit
Figure 11 shows an offset voltage adjustment circuit
using a dual potentiometer.
LCD Bias Control
Figure 9 shows a positive LCD bias control circuit using
a potentiometer as a voltage-divider.
Process Information
PROCESS: BiCMOS
Programmable Filter
Figure 10 shows a programmable filter using a dual
potentiometer.
R3
+1.8V
H_
H_
W_
W_
R1
R2
V
OUT
I
S
L_
L_
V
OUT
V
OUT
= I x ((R3 x (1 + R2/R1)) + R2)
S
Figure 8. Variable Gain I-to-V Converter
Figure 9. Positive LCD Bias Control Using a Voltage-Divider
+1.8V
WA
WB
LA
HA
V
IN
LB
HB
V
OUT
V
IN
R3
V
OUT
R1
HA
LA
HB
LB
R2
WA
WB
Figure 10. Programmable Filter
Figure 11. Offset Voltage Adjustment Circuit
12 _____________________________________________________________________________________
Dual 256-Tap, Volatile, Low-Voltage
Linear Taper Digital Potentiometers
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character,
but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
14 TSSOP
PACKAGE CODE
U14+1
DOCUMENT NO.
21-0066
16 TQFN-EP
T1633+5
21-0136
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
13
©
2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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