MAX539BESA-T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 25us Settling Time, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | MAX539BESA-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 25us Settling Time, PDSO8, 0.150 INCH, SOIC-8 |
| 文件： | 总16页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0172; Rev 6; 2/97
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
_______________Ge n e ra l De s c rip t io n
___________________________Fe a t u re s
♦ Operate from Single +5V Supply
♦ Buffered Voltage Output
The MAX531/MAX538/MAX539 are low-power, voltage-
output, 12-bit digital-to-analog converters (DACs) speci-
fied for single +5V power-supply operation. The MAX531
c a n a ls o b e op e ra te d with ± 5V s up p lie s . The
MAX538/MAX539 draw only 140µA, and the MAX531
(with inte rna l re fe re nc e ) d ra ws only 260µA. The
MAX538/MAX539 come in 8-pin DIP and SO packages,
while the MAX531 comes in 14-pin DIP and SO pack-
ages. All parts have been trimmed for offset voltage,
gain, and linearity, so no further adjustment is necessary.
♦ Internal 2.048V Reference (MAX531)
♦ 140µA Supply Current (MAX538/MAX539)
♦ INL = ±1/2LSB (max)
♦ Guaranteed Monotonic over Temperature
♦ Flexible Output Ranges:
The MAX538’s buffer is fixed at a gain of +1 and the
MAX539’s buffer at a gain of +2. The MAX531’s internal
op amp may be configured for a gain of +1 or +2, as
well as for unipolar or bipolar output voltages. The
MAX531 can also be used as a four-quadrant multiplier
without external resistors or op amps.
0V to V
(MAX531/MAX539)
DD
V
to V
(MAX531)
SS
DD
0V to 2.6V (MAX531/MAX538)
♦ 8-Pin SO/DIP (MAX538/MAX539)
♦ Power-On Reset
For parallel data inputs, see the MAX530 data sheet.
♦ Serial Data Output for Daisy-Chaining
_______________________Ap p lic a t io n s
Battery-Powered Test Instruments
______________Ord e rin g In fo rm a t io n
ERROR
PART
TEMP. RANGE PIN-PACKAGE
Digital Offset and Gain Adjustment
Battery-Operated/Remote Industrial Controls
Machine and Motion Control Devices
Cellular Telephones
(LSB)
±1/2
±1
MAX531ACPD 0°C to +70°C
14 Plastic DIP
14 Plastic DIP
14 SO
MAX531BCPD
MAX531ACSD
MAX531BCSD
MAX531BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
±1/2
±1
14 SO
Dice*
±1
________________Fu n c t io n a l Dia g ra m
Ordering Information continued at end of data sheet.
*Dice are specified at T = +25°C only.
A
(MAX531 ONLY)
REFOUT
(MAX531 ONLY)
BIPOFF
REFIN
_________________P in Co n fig u ra t io n s
MAX531
RFB
2.048V
MAX538
MAX539
(MAX531
ONLY)
REFERENCE
(MAX531 ONLY)
TOP VIEW
VOUT
DAC
AGND
V
DD
DIN
SCLK
CS
V
1
2
3
4
8
7
6
5
DD
POWER-UP
RESET
DGND
(MAX531
ONLY)
VOUT
REFIN
AGND
CLR
(MAX531
ONLY)
DAC REGISTER
(12 BITS)
MAX538
MAX539
V
SS
CONTROL
LOGIC
DOUT
(MAX531
ONLY)
CS
SHIFT REGISTER
(12 BITS)
SCLK
DIN
4
BITS
DOUT
DIP/SO
(MSB)
(LSB)
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t
S e ria l 1 2 -Bit DACs
ABSOLUTE MAXIMUM RATINGS
V
to DGND and V to AGND ................................-0.3V, +6V
Continuous Power Dissipation (T = +70°C)
A
DD
DD
V
to DGND and V to AGND .................................-6V, +0.3V
8-Pin Plastic DIP (derate 9.09mW/°C above +70°C)....727mW
8-Pin SO (derate 5.88mW/°C above +70°C) ................471mW
14-Pin Plastic DIP (derate 10.00mW/°C above +70°C)...800mW
14-Pin SO (derate 8.33mW/°C above +70°C) ..............667mW
Operating Temperature Ranges
SS
SS
V
to V .................................................................-0.3V, +12V
DD
SS
AGND to DGND........................................................-0.3V, +0.3V
Digital Input Voltage to DGND ......................-0.3V, (V + 0.3V)
REFIN ..................................................(V - 0.3V), (V + 0.3V)
DD
SS
DD
REFOUT to AGND .........................................-0.3V, (V + 0.3V)
MAX53_ _C_ _ .....................................................0°C to +70°C
MAX53_ _E_ _ ..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10sec) .............................+300°C
DD
RFB .....................................................(V - 0.3V), (V + 0.3V)
SS
DD
BIPOFF................................................(V - 0.3V), (V + 0.3V)
SS
DD
V
OUT
(Note 1) ................................................................V , V
SS DD
Continuous Current, Any Pin................................-20mA, +20mA
Note 1: The output may be shorted to V , V , or AGND if the package power dissipation limit is not exceeded.
DD SS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—Single +5V Supply
(V = +5V ±10%, V = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), C
= 33µF
DD
SS
REFOUT
(MAX531), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.)
L
L
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
Bits
MAX53_AC/E
±0.5
18/MAX539
Relative Accuracy (Note 2)
INL
DNL
LSB
MAX53_BC/E
±1
±1
8
Differential Nonlinearity
Unipolar Offset Error
Unipolar Offset Tempco
Gain Error (Note 2)
Guaranteed monotonic
MAX53_ _C/E
LSB
LSB
V
OS
0
TCV
3
ppm/°C
LSB
OS
GE
MAX53_ _C/E
±1
1
Gain-Error Tempco
1
ppm/°C
Power-Supply Rejection Ratio
(Note 3)
PSRR
4.5V ≤ V ≤ 5.5V
0.4
LSB/V
DD
VOLTAGE OUTPUT (VOUT)
MAX531 (G = +1), MAX538
MAX531 (G = +2), MAX539
0
0
V
- 2
DD
Output Voltage Range
V
V
- 0.4
1
DD
Output Load Regulation
Short-Circuit Current
REFERENCE INPUT (REFIN)
Voltage Range
VOUT = 2V, R = 2kΩ
LSB
mA
L
I
SC
12
0
V
DD
- 2
V
Input Resistance
Code dependent, minimum at code 555 hex
Code dependent (Note 4)
40
10
kΩ
pF
dB
Input Capacitance
50
AC Feedthrough
REFIN = 1kHz, 2Vp-p
-80
2
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
ELECTRICAL CHARACTERISTICS—Single +5V Supply (continued)
(V = +5V ±10%, V = 0V, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531), C
= 33µF
DD
SS
REFOUT
(MAX531), R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.)
L
L
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE OUTPUT (REFOUT—MAX531 only)
T
= +25°C
2.024
2.017
2.013
2.048
2.072
2.079
2.083
50
A
Reference Output Voltage
Temperature Coefficient
V
= 5.0V
MAX531BC
MAX531BE
V
DD
MAX531AC/AE/AM/BM
MAX531BC/BE
(Note 5)
30
30
TC
ppm/°C
REFOUT
Resistance
R
0.5
2
Ω
REFOUT
Power-Supply Rejection Ratio
Noise Voltage
PSRR
4.5V ≤ V ≤ 5.5V
300
µV/V
µVp-p
DD
e
0.1Hz to 10kHz
400
n
Minimum Required External
Capacitor
C
3.3
2.4
µF
MIN
DIGITAL INPUTS (DIN, SCLK, CS, CLR)
Input High
V
V
V
IH
Input Low
V
0.8
±1
IL
Input Current
I
V
= 0V or V
DD
µA
pF
IN
IN
Input Capacitance
DIGITAL OUTPUT (DOUT)
Output High
C
8
IN
V
I
= 2mA
V
- 1
V
V
SOURCE
DD
OH
Output Low
V
I
= 2mA
0.4
OL
SINK
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
Digital Feedthrough
SR
T
= +25°C
0.15
0.25
25
5
V/µs
µs
A
To ±1/2LSB, VOUT = 2V
nV-s
CS = V , DIN = 100kHz
DD
REFIN = 1kHz, 2Vp-p (G = +1 or +2),
code = FFF hex
Signal-to-Noise plus Distortion
SINAD
68
dB
POWER SUPPLY
Positive Supply Voltage
V
4.5
5.5
400
300
V
DD
MAX531
,
260
140
All inputs = 0V or V
output = no load
DD
Power-Supply Current
I
DD
µA
MAX538, MAX539
SWITCHING CHARACTERISTICS
CS Setup Time
t
20
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSS
CSH0
CSH1
t
t
SCLK Fall to CS Fall Hold Time
SCLK Fall to CS Rise Hold Time
SCLK High Width
t
35
35
45
0
CH
SCLK Low Width
t
CL
DS
DH
DO
DIN Setup Time
t
DIN Hold Time
t
DOUT Valid Propagation Delay
CS High Pulse Width
t
C
= 50pF
80
L
t
20
25
50
CSW
t
CLR Pulse Width
CLR
t
CS Rise to SCLK Rise Setup Time
CS1
_______________________________________________________________________________________
3
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
ELECTRICAL CHARACTERISTICS—Dual Supplies (MAX531 Only)
(V = +5V ±10%, V = -5V ±10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, C = 33µF,
DD
SS
REFOUT
R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.)
MAX
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Resolution
N
12
Bits
MAX531AC/E
MAX531BC/E
±0.5
±1
Tested at V = 5V,
DD
Relative Accuracy
INL
LSB
V
= -5V
SS
Differential Nonlinearity
Bipolar Offset Error
DNL
Guaranteed monotonic
±1
LSB
LSB
V
OS
BIPOFF = REFIN, MAX531_C/E
BIPOFF = REFIN
±8
Bipolar Offset Tempco
TCV
3
ppm/°C
LSB
OS
Gain Error (Unipolar or Bipolar)
Gain-Error Tempco
GEU
MAX531_C/E
±1
1
1
ppm/°C
Power-Supply Rejection Ratio
(Note 3)
PSRR
4.5V ≤ V ≤ 5.5V, -5.5V ≤ V ≤ -4.5V
0.4
LSB/V
DD
SS
REFERENCE INPUT (REFIN)
Voltage Range
V
SS
+ 2
V
DD
- 2
V
Input Resistance
Code dependent, minimum at code 555 hex
Code dependent (Note 4)
40
kΩ
pF
dB
Input Capacitance
AC Feedthrough
10
50
REFIN = 1kHz, 2.0Vp-p
-80
REFERENCE OUTPUT (REFOUT—MAX531 only)
18/MAX539
T
= +25°C
2.024
2.017
2.013
2.048
2.072
2.079
2.083
50
A
MAX531BC
MAX531BE
Reference Output Voltage
Temperature Coefficient
V
= 5.0V
V
DD
MAX531AC/AE/AM/BM
MAX531BC/BE
(Note 5)
30
30
TC
ppm/°C
REFOUT
Resistance
R
0.5
2
Ω
REFOUT
PSRR
Power-Supply Rejection Ratio
Noise Voltage
4.5V ≤ V ≤ 5.5V
300
µV/V
µVp-p
DD
e
0.1Hz to 10kHz
400
n
Minimum Required External
Capacitor
C
3.3
2.4
µF
MIN
DIGITAL INPUTS (DIN, SCLK, CS)
Input High
V
V
V
IH
Input Low
V
0.8
±1
IL
Input Current
I
V
= 0V or V
DD
µA
pF
IN
IN
Input Capacitance
DIGITAL OUTPUT (DOUT)
Output High
C
8
IN
V
I
= 2mA
V - 1
DD
V
V
OH
SOURCE
Output Low
V
I
= 2mA
0.4
OL
SINK
4
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
ELECTRICAL CHARACTERISTICS—Dual Supplies (MAX531 Only) (continued)
(V = +5V ±10%, V = -5V ±10%, AGND = DGND = 0V, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, C = 33µF,
DD
SS
REFOUT
R = 10kΩ, C = 100pF, T = T
to T , unless otherwise noted.)
MAX
L
L
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VOLTAGE OUTPUT (VOUT)
MAX531 (G = +1)
MAX531 (G = +2)
V
+ 2
V
- 2
SS
DD
Output Voltage Range
V
V
SS
+ 0.4
V
DD
- 0.4
1
Output Load Regulation
Short-Circuit Current
VOUT = 2V, R = 2kΩ
LSB
mA
L
I
SC
12
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
Voltage-Output Settling Time
Digital Feedthrough
SR
0.15
0.25
25
5
V/µs
µs
To ±1/2LSB, VOUT = 2V
Step 000 hex to FFF hex
nV-s
REFIN = 1kHz, 2Vp-p, (G = +1)
REFIN = 1kHz, 2Vp-p, (G = +2)
68
68
Signal-to-Noise plus Distortion
SINAD
dB
POWER SUPPLY
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
SWITCHING CHARACTERISTICS
CS Setup Time
V
4.5
5.5
V
V
DD
V
SS
-5.5
0
I
DD
All inputs = 0V or V , no load
260
400
µA
µA
DD
I
SS
All inputs = 0V or V , no load
-120
-200
DD
t
20
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSS
t
t
SCLK Fall to CS Fall Hold Time
SCLK Fall to CS Rise Hold Time
SCLK High Width
CSH0
CSH1
t
35
35
45
0
CH
SCLK Low Width
t
CL
DS
DH
DO
DIN Setup Time
t
DIN Hold Time
t
DOUT Valid Propagation Delay
CS High Pulse Width
t
C
= 50pF
80
L
t
20
25
50
CSW
t
CLR Pulse Width
CLR
t
CS Rise to SCLK Rise Setup Time
CS1
Note 2: In single-supply operation, INL and GE calculated from code 11 to code 4095. Tested at V = +5V.
DD
Note 3: This specification applies to both gain-error power-supply rejection ratio and offset-error power-supply rejection ratio.
Note 4: Guaranteed by design.
Note 5: Tested at I
= 100µA. The reference can typically source up to 5mA (see Typical Operating Characteristics).
OUT
_______________________________________________________________________________________
5
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = +5V, V
= 2.048V, T = +25°C, unless otherwise noted.)
A
DD
REFIN
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (ALL CODES)
OUTPUT SINK CAPABILITY vs.
OUTPUT PULL-DOWN VOLTAGE
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (FIRST 12 CODES)
16
14
12
10
8
0.25
0
0.25
DUAL SUPPLIES
SINGLE SUPPLY
-0.25
-0.50
-0.75
-1.00
-1.25
0
6
4
2
0
-0.25
0
0.2
0.4
0.6
0.8
1.0
0
2
4
6
8
10
12
0
512 1024 1536 2048 2560 3072 3584 4095
DIGITAL INPUT CODE (DECIMAL)
OUTPUT PULL-DOWN VOLTAGE (V)
DIGITAL INPUT CODE (DECIMAL)
MAX531
REFERENCE VOLTAGE vs.
TEMPERATURE
ANALOG FEEDTHROUGH vs.
FREQUENCY
OUTPUT SOURCE CAPABILITY vs.
OUTPUT PULL-UP VOLTAGE
-110
-100
-90
2.055
2.050
0
CODE = 000 hex
5
1
2
3
4
5
-80
-70
-60
-50
-40
-30
-20
-10
6
7
8
2.045
0
-40
-60
-20
0
20 40
80 100
1
10
100
1k
10k 100k 1M
60
V
-5
V
-4
V
-3
V
-2
V
-1
V -0
DD
DD
DD
DD
DD
DD
TEMPERATURE (°C)
FREQUENCY (Hz)
OUTPUT PULL-UP VOLTAGE (V)
SUPPLY CURRENT vs.
TEMPERATURE
MAX531
GAIN vs. FREQUENCY
MAX531
AMPLIFIER SIGNAL-TO-NOISE RATIO
300
80
70
60
50
40
30
20
10
4
2
REFIN = 4Vp-p
REFIN = 4Vp-p
280
260
240
220
200
180
160
140
120
0
MAX531
-2
-4
-6
-8
-10
-12
MAX538/MAX539
0
-14
-60 -40 -20
0
20 40 60 80 100
10
100
1k
10k
100k
1
100
1k
FREQUENCY (Hz)
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
6
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = +5V, V
= 2.048V, T = +25°C, unless otherwise noted.)
A
DD
REFIN
MAX531
GAIN AND PHASE vs. FREQUENCY
MAX531 REFERENCE OUTPUT VOLTAGE
vs. REFERENCE LOAD CURRENT
20
10
2.0520
2.0515
180
RFB CONNECTED TO AGND (G=2)
RFB CONNECTED TO VOUT (G=1)
GAIN
2.0510
2.0505
2.0500
2.0495
2.0490
0
-10
-20
0
PHASE
-180
-30
1
10
100
800
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE LOAD CURRENT (mA)
FREQUENCY (kHz)
DIGITAL FEEDTHROUGH
A
B
2µs/div
CS = HIGH
A: DIN = 4Vp-p, 100kHz
B: VOUT, 10mV/div
NEGATIVE SETTLING TIME (MAX531)
POSITIVE SETTLING TIME (MAX531)
A
A
B
B
5µs/div
5µs/div
V
DD
= ±5V, V
= 2V, BIPOLAR CONFIGURATION
V
DD
= ±5V, V
= 2V, BIPOLAR CONFIGURATION
REFIN
REFIN
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
A: CS RISING EDGE, 5V/div
B: VOUT, NO LOAD, 1V/div
_______________________________________________________________________________________
7
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t
S e ria l 1 2 -Bit DACs
____________________P in De s c rip t io n
_______________De t a ile d De s c rip t io n
Ge n e ra l DAC Dis c u s s io n
PIN
The MAX531/MAX538/MAX539 use an “inverted” R-2R
ladder network with a single-supply CMOS op amp to con-
vert 12-bit digital data to analog voltage levels (see
Functional Diagram). The term “inverted” describes the
ladder network because the REFIN pin in current-output
DACs is the summing junction, or virtual ground, of an op
amp. However, such use would result in the output voltage
b e ing the inve rs e of the re fe re nc e volta g e . The
MAX531/MAX538/MAX539’s topology makes the output
the same polarity as the reference input.
NAME
FUNCTION
MAX538
MAX539
MAX531
Bipolar Offset/Gain
Resistor
—
1
BIPOFF
DIN
1
2
3
Serial Data Input
Clear. Asynchronously sets
DAC register to 000 hex.
—
CLR
An internal reset circuit forces the DAC register to reset to
000 hex on power-up. Additionally, a clear CLR pin, when
held low, sets the DAC register to 000 hex. CLR operates
asynchronously and independently from the chip-select
(CS) pin.
4
5
2
3
SCLK
Serial Clock Input
Chip Select, active low
CS
Serial Data Output for
daisy-chaining
6
4
DOUT
Bu ffe r Am p lifie r
7
8
9
—
5
DGND
AGND
REFIN
Digital Ground
Analog Ground
Reference Input
The output buffer is a unity-gain stable, rail-to-rail output,
BiCMOS op amp. Input offset voltage and CMRR are
trimmed to achieve better than 12-bit performance.
Settling time is 25µs to 0.01% of final value. The settling
time is considerably longer when the DAC code is initially
set to 000 hex, because at this code the op amp is com-
pletely debiased. Start from code 001 hex if necessary.
The output is short-circuit protected and can drive a 2kΩ
load with more than 100pF load capacitance.
6
18/MAX539
Reference Output,
2.048V
10
—
REFOUT
11
12
13
14
—
7
V
SS
Negative Power Supply
DAC Output
VOUT
8
V
DD
Positive Power Supply
Feedback Resistor
—
RFB
CS
t
t
CSH0
CSW
t
CH
t
t
CL
t
CSH1
CSS
SCLK
t
DH
t
CS1
t
DS
DIN
t
DO
DOUT
Figure 1. Timing Diagram
8
_______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
nite at code 000 hex. REFIN’s input capacitance is also
code dependent and has a 50pF maximum value at sever-
al codes. Because of the code-dependent nature of refer-
ence input impedances, a high-quality, low-output-imped-
ance amplifier (such as the MAX480 low-power, precision
op amp) should be used.
R
S
REFOUT
TOTAL
REFERENCE
NOISE
C
S
C
REFOUT
TEK 7A22
300
250
200
150
100
50
1.8
1.6
1.4
1.2
1.0
0.8
If an upgrade to the internal reference is required, the 2.5V
SINGLE-POLE ROLLOFF
MAX873A is suitable: ±15mV initial accuracy, TCV
=
OUT
7ppm/°C (max).
C
= 3.3µF
REFOUT
Logic Inte rfa c e
The MAX531/MAX538/MAX539 logic inputs are designed to
be compatible with TTL or CMOS logic levels. However, to
achieve the lowest power dissipation, drive the digital inputs
with rail-to-rail CMOS logic. With TTL logic levels, the power
requirement increases by a factor of approximately 2.
0.6
0.4
0.2
0
C
= 47µF
REFOUT
Se ria l Cloc k a nd Upda te Ra te
0
Figure 1 shows the MAX531/MAX538/MAX539 timing. The
0.1
1
10
100
1000
maximum serial clock rate is given by 1 / (t
+ t ),
CH
CL
FREQUENCY (kHz)
approximately 14MHz. The digital update rate is limited by
the chip-select period, which is 16 x (t + t ) + t
.
CSW
CH
CL
Figure 2. Reference Noise vs. Frequency
This equals a 1.14µs, or 877kHz, update rate. However, the
DAC settling time to 12 bits is 25µs, which may limit the
update rate to 40kHz for full-scale step transitions.
Inte rna l Re fe re nc e (MAX531 only)
The on-chip reference is lesser trimmed to generate 2.048V
at REFOUT. The output stage can source and sink current,
so REFOUT can settle to the correct voltage quickly in
response to code-dependent loading changes. Typically,
source current is 5mA and sink current is 100µA.
____________Applic a tions Inform a tion
Refer to Figures 3a and 3b for typical operating connec-
tions.
Se ria l Inte rfa c e
REFOUT connects the internal reference to the R-2R DAC
ladder at REFIN. The R-2R ladder draws 50µA maximum
load current. If any other connection is made to REFOUT,
ensure that the total load current is less than 100µA to
avoid gain errors.
The MAX531/MAX538/MAX539 use a three-wire serial
inte rfa c e tha t is c omp a tib le with SPI™, QSPI™
(CPOL = CPHA = 0), and Microwire™ standards as shown
in Figures 4 and 5. The DAC is programmed by writing two
8-bit words (see Figure 1 and the Functional Diagram).
Sixteen bits of serial data are clocked into the DAC MSB
first with the MSB preceded by four fill (dummy) bits. The
four dummy bits are not normally needed. They are
required only when DACs are daisy-chained. Data is
clocked in on SCLK’s rising edge while CS is low. The seri-
al input data is held in a 16-bit serial shift register. On CS’s
rising edge, the 12 least significant bits are transferred to
the DAC register and update the DAC. With CS high, data
cannot be clocked into the MAX531/MAX538/MAX539.
For applications requiring very low-noise performance,
connect a 33µF capacitor from REFOUT to AGND. If noise
is not a concern, a lower value capacitor (3.3µF min) may
be used. To reduce noise further, insert a buffered RC filter
between REFOUT and REFIN (Figure 2). The reference
bypass capacitor, C , is still required for reference
REFOUT
stability. In applications not requiring the reference, con-
nect REFOUT to V or use the MAX538 or MAX539 (no
DD
internal reference).
Exte rna l Re fe re nc e
The MAX531/MAX538/MAX539 input data in 16-bit blocks.
The SPI and Microwire interfaces output data in 8-bit
blocks, thereby requiring two write cycles to input data to
the DAC. The QSPI interface allows variable data input
from eight to 16 bits, and can be loaded into the DAC in
one write cycle.
An external reference in the range (V + 2V) to (V - 2V)
SS
DD
may be used with the MAX531 in dual-supply operation.
With the MAX538/MAX539 or the MAX531 in single-supply
use, the reference must be positive and may not exceed
V
DD
- 2V. The reference voltage determines the DAC’s full-
scale output. The DAC input resistance is code dependent
and is minimum (40kΩ) at code 555 hex and virtually infi-
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corp.
_______________________________________________________________________________________
9
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
DIN DOUT SCLK CS
REFIN
CLR
DIN SCLK CS DOUT
VOUT
REFIN
INVERTED
R-2R DAC
VOUT
INVERTED
R-2R DAC
REFOUT
2R
2R
2R
RFB
2.048V
MAX531
V
CONNECT BIPOFF
TO VOUT FOR G = 1,
TO AGND FOR G = 2,
OR TO REFIN FOR
BIPOLAR GAIN
BIPOFF
2R
MAX538
MAX539
AGND DGND
V
SS
MAX539
ONLY
DD
0.1µF
0.1µF
+5V
0V TO -5V
AGND
V
DD
33µF
+5V
0.1µF
Figure 3b. MAX538/MAX539 Typical Operating Circuit
Figure 3a. MAX531 Typical Operating Circuit
supplies in this mode. In this range, 1LSB = (2)(V
)
Da is y-Ch a in in g De vic e s
REFIN
-12
-11
(2 ) = (V
)(2 ). The MAX539 is internally config-
REFIN
The serial output, DOUT, allows cascading of two or
more DACs . The d a ta a t DIN a p p e a rs a t DOUT,
delayed by 16 clock cycles plus one clock width. For
low p owe r, DOUT is a CMOS outp ut tha t d oe s not
require an external pull-up resistor. DOUT does not go
into a high-impedance state when CS is high. DOUT
changes on SCLK’s falling edge when CS is low. When
CS is high, DOUT remains in the state of the last data
bit.
ured for unipolar gain = +2 operation.
18/MAX539
Bip o la r Co n fig u ra t io n
A bipolar range is set up by connecting BIPOFF to
REFIN a nd RFB to VOUT, a nd op e ra ting from d ua l
(±5V) supplies (Figure 8). Table 3 shows the DAC-latch
c onte nts (inp ut) vs . VOUT (outp ut). In this ra ng e ,
-11
1LSB = V
(2 ).
REFIN
Fo u r-Qu a d ra n t Mu lt ip lic a t io n
Any number of MAX531/MAX538/MAX539 DACs can
b e d a is y-c ha ine d b y c onne c ting the DOUT of one
device to the DIN of the next device in the chain. For
The MAX531 can be used as a four-quadrant multiplier
by connecting BIPOFF to REFIN and RFB to VOUT,
using (1) an offset binary digital code, (2) bipolar power
supplies, using dual power supplies, and (3) a bipolar
proper timing, ensure that t (CS low to SCLK high) is
CL
greater than t
+ t
.
DO
DS
analog input at REFIN within the range V + 2V to V
SS
DD
Un ip o la r Co n fig u ra t io n
The MAX531 is configured for a gain of +1 (0V to V
unipolar output) by connecting BIPOFF and RFB to
VOUT (Figure 6). The converter operates from either sin-
gle or dual supplies in this configuration. See Table 1 for
- 2V, as shown in Figure 9.
REFIN
In general, a 12-bit DAC’s output is (D) (V
where “G” is the gain (+1 or +2) and “D” is the binary
representation of the digital input divided by 2
4096. This formula is precise for unipolar operation.
However, for bipolar, offset binary operation, the MSB is
really a polarity bit. No resolution is lost, as there are
the same number of steps. The output voltage, howev-
er, has been shifted from a range of, for example, 0V to
4.096V (G = +2) to a range of -2.048V to +2.048V.
(G),
REFIN)
12
or
the DAC-latch contents (input) vs. the analog VOUT
-12
(outp ut). In this ra ng e , 1LSB = V
(2
). The
REFIN
MAX538 is internally configured for unipolar gain = +1
operation.
A gain of +2 (0V to 2V
unipolar output) is set up
REFIN
by connecting BIPOFF to AGND and RFB to VOUT
(Figure 7). Table 2 shows the DAC-latch contents vs.
VOUT. The MAX531 operates from either single or dual
Keep in mind that when using the DAC as a four-quad-
rant multiplier, the scale is skewed. Negative full scale
is -V
, while positive full scale is +V
- 1LSB.
REFIN
REFIN
10 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
SCLK
DIN
SCK
SCLK
DIN
SK
SO
MICROWIRE
PORT
SPI
PORT
MAX531
MAX538
MAX539
MOSI
MAX531
MAX538
MAX539
CS
I/O
CS
I/O
SI
DOUT
MISO
DOUT
CPOL = 0, CPHA = 0
THE DOUT-MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
THE DOUT-SI CONNECTION IS NOT REQUIRED FOR WRITING TO THE
DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER .
Figure 4. Microwire Connection
Figure 5. SPI/QSPI Connection
+5V
+5V
V
DD
V
DD
REFIN
REFIN
BIPOFF
REFOUT
REFOUT
33µF
33µF
MAX531
MAX531
BIPOFF
AGND
DGND
RFB
RFB
AGND
V
OUT
VOUT
VOUT
DGND
V
OUT
G = +2
V
SS
V
SS
G = +1
0V TO -5V
0V TO -5V
Figure 6. Unipolar Configuration (0V to +2.048V Output)
Figure 7. Unipolar Configuration (0V to +4.096V Output)
Table 1. Unipolar Binary Code Table
Table 2. Unipolar Binary Code Table
(0V to V
Output), Gain = +1
(0V to 2V
Output), Gain = +2
REFIN
REFIN
INPUT
OUTPUT
INPUT
OUTPUT
4095
4096
4095
4096
(V
)
1111 1111
1000 0000
1111
0001
REFIN
+2 (V
)
1111 1111
1111
0001
REFIN
2049
4096
2049
4096
(V
REFIN
)
1000 0000
1000 0000
0111 1111
+2 (V
+2 (V
)
REFIN
2048
4096
2048
4096
(V
)
= +V
/ 2
1000 0000
0111 1111
0000
1111
= +V
REFIN
REFIN
REFIN
)
REFIN
0000
1111
2047
4096
2047
4096
(V
REFIN
)
)
+2 (V
)
REFIN
1
4096
1
4096
0000 0000
0000 0000
(V
REFIN
0001
0000
0000 0000
0000 0000
+2 (V
)
0001
0000
REFIN
OV
OV
______________________________________________________________________________________ 11
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
Table 3. Bipolar (Offset Binary) Code
+5V
Table (-V
to +V
Output)
REFIN
REFIN
OUTPUT
INPUT
REFIN
BIPOFF
REFOUT
2047
2048
(+V
)
1111 1111
1111
0001
REFIN
33µF
MAX531
1
2048
RFB
1000 0000
(+V
)
REFIN
AGND
DGND
1000 0000
0111 1111
0000
1111
0V
V
OUT
VOUT
1
2048
(-V
)
)
REFIN
2047
2048
0000 0000
0000 0000
(-V
(-V
0001
0000
REFIN
-5V
2048
2048
)
= -V
REFIN
REFIN
Figure 8. Bipolar Configuration (-2.048V to +2.048V Output)
DGND and AGND should be connected together at the
chip. For the MAX531 in single-supply applications,
S in g le -S u p p ly Lin e a rit y
As with any amplifier, the MAX531/MAX538/MAX539’s
output buffer can be positive or negative. When the off-
set is positive, it is easily accounted for (Figure 10).
However, when the offset is negative, the buffer output
cannot follow linearly when there is no negative supply.
In that case, the amplifier output (VOUT) remains at
ground until the DAC voltage is sufficient to overcome
the offset and the output becomes positive.
connect V to AGND at the chip. The best ground
SS
18/MAX539
connection may be achieved by connecting the DAC’s
DGND and AGND pins together and connecting that
point to the system analog ground plane. If the DAC’s
DGND is connected to the system digital ground, digi-
tal noise may get through to the DAC’s analog portion.
Bypass V
(and V in dual-supply mode) with a
SS
DD
0.1µF ceramic capacitor, connected between V
and
DD
Normally, linearity is measured after accounting for
zero error and gain error. Since, in single-supply opera-
tion, the actual value of a negative offset is unknown, it
cannot be accounted for during test. Additionally, the
output buffer amplifier exhibits a nonlinearity near-zero
output when operating with a single supply. To account
for this nonlinearity in the MAX531/MAX538/MAX539,
linearity and gain error are measured from code 11 to
code 4095. The output buffer’s offset and nonlinear
behavior do not affect monotonicity, and these DACs
are guaranteed monotonic starting with code zero. In
dual-supply operation, linearity and gain error are mea-
sured from code 0 to 4095.
AGND (and between V and AGND). Mount with short
SS
leads close to the device. Ferrite beads may also be
used to further isolate the analog and digital power
supplies.
Fig ure s 11a a nd 11b illus tra te the g round ing a nd
bypassing scheme described.
S a vin g P o w e r
When the DAC is not being used by the system, mini-
mize power consumption by setting the appropriate
code to minimize load current. For example, in bipolar
mode, with a resistive load to ground, set the DAC
code to mid-scale (Table 3). If there is no output load,
minimize internal loading on the reference by setting
the DAC to all 0s (on the MAX531, use CLR). Under this
condition, REFIN is high impedance and the op amp
op e ra te s a t its minimum q uie s c e nt c urre nt. Due to
these low current levels, the output settling time for an
input code close to 0 typically increases to 60µs (no
more than 100µs).
P o w e r-S u p p ly Byp a s s in g a n d
Gro u n d Ma n a g e m e n t
Best system performance is obtained with printed cir-
c uit b oa rd s tha t us e s e p a ra te a na log a nd d ig ita l
ground planes. Wire-wrap boards are not recommend-
e d . The two g round p la ne s s hould b e c onne c te d
together at the low-impedance power-supply source.
12 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
CS CLR DIN DOUT REFOUT V
V
SS
DD
POSITIVE OFFSET
2.048V
SIGNAL
IN
REFIN
VOUT
4
3
2
1
0
INVERTED
R-2R DAC
NEGATIVE OFFSET
2R
2R
RFB
BIPOFF
MAX531
1
2
3
4
5
6 7 8
DAC CODE (LSB)
Figure 10. Single-Supply Offset
Figure 9. MAX531 Connected as Four-Quadrant Multiplier. The
unused REFOUT is connected to V
.
DD
AC Co n s id e ra t io n s
ANALOG GROUND PLANE
Digital Feedthrough
High-speed serial data at any of the digital input or output
pins may couple through the DAC package and cause
internal stray capacitance to appear at the DAC output as
noise, even though CS is held high (see Typical Operating
Characteristics). This digital feedthrough is tested by hold-
ing CS high, transmitting 555 hex from DIN to DOUT.
0.1µF
1
2
3
4
5
6
7
14
13
12
11
10
9
Analog Feedthrough
Because of internal stray capacitance, higher frequency
analog input signals may couple to the output as shown in
the Analog Feedthrough vs. Frequency graph in the
Typical Operating Characteristics. It is tested by holding
CS high, setting the DAC code to all 0s, and sweeping
REFIN.
0.1µF
8
(a) MAX531 BYPASSING
1
8
7
6
5
2
3
4
0.1µF
(b) MAX538/MAX539 BYPASSING
Figure 11. Power-Supply Bypassing
______________________________________________________________________________________ 13
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
__Ord e rin g In fo rm a t io n (c o n t in u e d )
____P in Co n fig u ra t io n s (c o n t in u e d )
ERROR
TOP VIEW
PART
TEMP. RANGE PIN-PACKAGE
(LSB)
±1/2
±1
MAX531AEPD -40°C to +85°C
MAX531BEPD -40°C to +85°C
MAX531AESD -40°C to +85°C
MAX531BESD -40°C to +85°C
14 Plastic DIP
14 Plastic DIP
14 SO
BIPOFF
RFB
1
2
3
4
5
6
7
14
13
12
11
10
9
±1/2
±1
DIN
CLR
V
DD
14 SO
MAX531
VOUT
MAX538ACPA
MAX538BCPA
MAX538ACSA
MAX538BCSA
MAX538BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
SCLK
CS
V
SS
±1/2
±1
REFOUT
REFIN
8 SO
DOUT
DGND
Dice*
±1
AGND
8
MAX538AEPA -40°C to +85°C
MAX538BEPA -40°C to +85°C
MAX538AESA -40°C to +85°C
MAX538BESA -40°C to +85°C
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
DIP/SO
±1/2
±1
8 SO
MAX539ACPA
MAX539BCPA
MAX539ACSA
MAX539BCSA
MAX539BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
___________________Ch ip To p o g ra p h y
±1/2
±1
8 SO
DIN
(BIPOFF)(RFB)
V
DD
Dice*
±1
18/MAX539
MAX539AEPA -40°C to +85°C
MAX539BEPA -40°C to +85°C
MAX539AESA -40°C to +85°C
MAX539BESA -40°C to +85°C
8 Plastic DIP
8 Plastic DIP
8 SO
±1/2
±1
±1/2
±1
8 SO
(CLR)
VOUT
*Dice are specified at T = +25°C only.
A
0.120"
(3.048mm)
SCLK
CS
(V
SS
)
(REFOUT)
REFIN
DOUT
(DGND) AGND
0.080"
(2.032mm)
( ) ARE FOR MAX531 ONLY.
TRANSISTOR COUNT: 922
SUBSTRATE CONNECTED TO V
DD
14 ______________________________________________________________________________________
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
18/MAX539
________________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
+5 V, Lo w -P o w e r, Vo lt a g e -Ou t p u t ,
S e ria l 1 2 -Bit DACs
__________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
18/MAX539
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX5400EKA
Digital Potentiometer, 1 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, BICMOS, PDSO8, SOT-23, 8 PIN
MAXIM
MAX5400EKA+T
Digital Potentiometer, 1 Func, 50000ohm, 2-wire Serial Control Interface, 256 Positions, BICMOS, PDSO8, SOT-23, 8 PIN
MAXIM
MAX5401EKA+
Digital Potentiometer, 1 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, BICMOS, PDSO8, SOT-23, 8 PIN
MAXIM
©2020 ICPDF网 联系我们和版权申明