MAX541ACSA+T [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 1us Settling Time, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8;
| 型号： | MAX541ACSA+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 1us Settling Time, PDSO8, 0.150 INCH, LEAD FREE, SOIC-8 |
| 文件： | 总12页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1082; Rev 2; 12/99
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
General Description
Features
The MAX541/MAX542 are serial-input, voltage-output,
16-bit digital-to-analog converters (DACs) that operate
from a single +5V supply. They provide 16-bit perfor-
mance ( 1ꢀLS ꢁIꢀ and DIꢀ) over temperature ꢂithout
any adjustments. The DAC output is unbuffered, result-
ing in a loꢂ supply current of 0.3mA and a loꢂ offset
error of 1ꢀLS.
ꢀ Full 16-Bit Performance Without Adjustments
ꢀ +5V Single-Supply Operation
ꢀ Low Power: 1.5mW
ꢀ 1µs Settling Time
ꢀ Unbuffered Voltage Output Directly Drives 60kΩ
Loads
The DAC output range is 0V to V
. For bipolar opera-
REF
ꢀ SPI/QSPI/MICROWIRE-Compatible Serial Interface
tion, matched scaling resistors are provided in the
MAX542 for use ꢂith an external precision op amp
(such as the MAX400), generating a
ꢀ Power-On Reset Circuit Clears DAC Output to 0V
V
output
REF
(unipolar mode)
sꢂing. The MAX542 also includes Kelvin-sense con-
nections for the reference and analog ground pins to
reduce layout sensitivity.
ꢀ Schmitt Trigger Inputs for Direct Optocoupler
Interface
A 16-bit serial ꢂord is used to load data into the DAC
latch. The 10MHz, 3-ꢂire serial interface is compatible
ꢂith LPꢁ™/QLPꢁ™/MꢁCROWꢁRE™, and it also interfaces
directly ꢂith optocouplers for applications requiring isola-
tion. A poꢂer-on reset circuit clears the DAC output to 0V
(unipolar mode) ꢂhen poꢂer is initially applied.
Ordering Information
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
MAX541ACPA
MAX541SCPA
MAX541CCPA
MAX541ACLA
MAX541SCLA
MAX541CCLA
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DꢁP
8 Plastic DꢁP
8 Plastic DꢁP
8 LO
1
2
4
1
2
4
The MAX541 is available in 8-pin plastic DꢁP and LO
packages. The MAX542 is available in 14-pin plastic
DꢁP and LO packages.
8 LO
Applications
High-Resolution Offset and Gain Adjustment
ꢁndustrial Process Control
8 LO
Ordering Information continued at end of data sheet.
Automated Test Equipment
Functional Diagrams
Data-Acquisition Lystems
V
DD
General Description
RFB
INV
TOP VIEW
MAX542
R
FB
R
INV
REFF
REFS
V
14
RFB
OUT
1
2
3
4
5
6
7
DD
16-BIT DAC
OUT
13 INV
MAX542
AGNDF
AGNDS
AGNDF
AGNDS
REFS
REFF
12 DGND
1
2
3
4
8
7
6
5
V
DD
OUT
AGND
REF
16-BIT DATA LATCH
CS
LDAC
SCLK
DIN
11
10
9
LDAC
DIN
DGND
DIN
CONTROL
LOGIC
MAX541
N.C.
SERIAL INPUT REGISTER
DGND
CS
SCLK
CS
8
SCLK
DIP/SO
DIP/SO
Functional Diagrams continued at end of data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
ABSOLUTE MAXIMUM RATINGS
V
to DGID ...........................................................-0.3V to +6V
14-Pin Plastic DꢁP (derate 10.00mW/°C above +70°C)...800mW
14-Pin LO (derate 8.33mW/°C above +70°C) ...............667mW
14-Pin Ceramic LS (derate 10.00mW/°C above +70°C ..800mW
Operating Temperature Ranges
DD
CS, LCꢀK, DꢁI, LDAC to DGID ..............................-0.3V to +6V
REF, REFF, REFL to AGID ........................-0.3V to (V + 0.3V)
AGID, AGIDF, AGIDL to DGID........................-0.3V to +0.3V
DD
OUT, ꢁIV to AGID, DGID ......................................-0.3V to V
RFS to AGID, DGID..................................................-6V to +6V
Maximum Current into Any Pin............................................50mA
Continuous Poꢂer Dissipation (T = +70°C)
A
8-Pin Plastic DꢁP (derate 9.09mW/°C above +70°C).....727mW
8-Pin LO (derate 5.88mW/°C above +70°C) .................471mW
MAX541 _C_ A/MAX542_C_D. .............................0°C to +70°C
MAX541 _E_ A/MAX542_E_D............................-40°C to +85°C
MAX542CMJD.................................................-55°C to +125°C
Ltorage Temperature Range.............................-65°C to +150°C
ꢀead Temperature (soldering, 10s) .................................+300°C
DD
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +5V 5ꢃ, V
= +2.5V, AGID = DGID = 0, T = T
A
to T
, unless otherꢂise noted.)
MAX
DD
REF
MꢁI
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Sits
STATIC PERFORMANCE—ANALOG SECTION (R = ∞)
Resolution
ꢀ
I
16
MAX54_A
0.5
0.5
0.5
0.5
1.0
2.0
4.0
1.0
1
ꢁntegral Ionlinearity
ꢁIꢀ
V
DD
= 5V
MAX54_S
MAX54_C
ꢀLS
Differential Ionlinearity
Zero-Code Offset Error
Zero-Code Tempco
Gain Error (Iote 1)
DIꢀ
ZLE
Guaranteed monotonic
ꢀLS
ꢀLS
T
A
T
A
T
A
T
A
T
A
= +25°C
= T
= T
to T
to T
2
MꢁI
MꢁI
MAX
MAX
ZL
0.05
ppm/°C
ꢀLS
TC
= +25°C
= T to T
5
10
MꢁI
MAX
Gain-Error Tempco
0.1
6.25
1.0
ppm/°C
DAC Output Resistance
R
OUT
(Iote 2)
MAX542
kΩ
R
/R
FS ꢁIV
Sipolar Resistor Matching
Sipolar Zero Offset Error
Ratio error
0.015
10
ꢃ
T
= +25°C
A
A
MAX542
ꢀLS
T
= T
to T
20
MꢁI
MAX
Sipolar Zero Tempco
SZL
MAX542
0.5
ppm/°C
ꢀLS
TC
Poꢂer-Lupply Rejection
PLR
4.75V ≤ V
≤ 5.25V
1.0
3.0
DD
REFERENCE INPUT
Reference ꢁnput Range
V
R
(Iote 3)
2.0
11.5
9.0
V
REF
Unipolar mode
Reference ꢁnput Resistance
(Iote 4)
kΩ
REF
MAX542, bipolar mode
DYNAMIC PERFORMANCE—ANALOG SECTION (R = ∞, unipolar mode)
ꢀ
Voltage-Output Lleꢂ Rate
LR
C = 10pF (Iote 5)
ꢀ
25
1
V/µs
µs
to 1/2ꢀLS of FL, C = 10pF
Output Lettling Time
ꢀ
2
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
ELECTRICAL CHARACTERISTICS (continued)
(V
= +5V 5ꢃ, V
= +2.5V, AGID = DGID = 0, T = T
A
to T
, unless otherꢂise noted.)
MAX
DD
REF
MꢁI
PARAMETER
SYMBOL
CONDITIONS
Major-carry transition
Code = 0000 hex; CS = V ; LDAC = 0;
MIN
TYP
MAX
UNITS
DAC Glitch ꢁmpulse
10
nVs
DD
Digital Feedthrough
10
nVs
LCꢀK, DꢁI = 0 to V
levels
DD
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dS Sandꢂidth
Reference Feedthrough
Lignal-to-Ioise Ratio
SW
Code = FFFF hex
1
1
MHz
mVp-p
dS
Code = 0000 hex, V
= 1Vp-p at 100kHz
REF
LIR
92
75
120
Code = 0000 hex
Code = FFFF hex
Reference ꢁnput Capacitance
C
ꢁI
pF
STATIC PERFORMANCE—DIGITAL INPUTS
ꢁnput High Voltage
ꢁnput ꢀoꢂ Voltage
ꢁnput Current
V
2.4
V
V
ꢁH
V
0.8
1
ꢁꢀ
ꢁ
ꢁI
V
= 0
µA
pF
V
ꢁI
ꢁnput Capacitance
Hysteresis Voltage
POWER SUPPLY
Positive Lupply Range
Positive Lupply Current
Poꢂer Dissipation
C
(Iote 6)
10
ꢁI
V
0.40
H
V
DD
4.75
5.25
1.1
V
ꢁ
0.3
1.5
mA
mW
DD
PD
TIMING CHARACTERISTICS
(V
= +5V 5ꢃ, V
= +2.5V, AGID = DGID = 0, CMOL inputs, T = T
to T
, unless otherꢂise noted.)
MAX
DD
REF
A
MꢁI
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
LCꢀK Frequency
f
10
CꢀK
LCꢀK Pulse Width High
LCꢀK Pulse Width ꢀoꢂ
CS ꢀoꢂ to LCꢀK High Letup
CS High to LCꢀK High Letup
LCꢀK High to CS ꢀoꢂ Hold
LCꢀK High to CS High Hold
DꢁI to LCꢀK High Letup
DꢁI to LCꢀK High Hold
LDAC Pulse Width
t
45
45
45
45
30
45
40
0
CH
t
Cꢀ
ns
t
t
t
ns
CLL0
CLL1
ns
(Iote 6)
MAX542
ns
CLH0
CLH1
t
ns
t
ns
DL
t
ns
DH
t
50
50
ns
LDAC
t
MAX542 (Iote 6)
ns
CS High to LDAC ꢀoꢂ Letup
ꢀDACL
V
High to CS ꢀoꢂ
DD
20
µs
(poꢂer-up delay)
Note 1: Gain Error tested at V
= 2.0V, 2.5V, and 3.0V.
REF
Note 2: R
tolerance is typically 20ꢃ.
OUT
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits ꢂill result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8555 hex.
Note 5: Lleꢂ-rate value is measured from 0ꢃ to 63ꢃ.
Note 6: Guaranteed by design. Iot production tested.
_______________________________________________________________________________________
3
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
__________________________________________Typical Operating Characteristics
(V
= 5V, V
= +2.5V, T = +25°C, unless otherꢂise noted.)
REF
A
DD
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
0.35
0.34
0.33
0.32
0.31
0.30
1.0
0.8
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0.29
0.28
-60
-40 -20
0
20
40
60
80 100
0
1
2
3
4
5
6
-20
20
60
100
140
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
1.0
0.8
1.0
0.8
1.0
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
+INL
+DNL
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-DNL
-INL
-60
-60
-60
-20
20
60
100
140
-20
20
60
100
140
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
REFERENCE CURRENT
vs. CODE
INTEGRAL NONLINEARITY
vs. CODE
DIFFERENTIAL NONLINEARITY
vs. CODE
200
160
120
80
1.00
1.00
0.75
0.75
0.50
0.25
0.50
0.25
0
0
-0.25
-0.25
-0.50
-0.50
-0.75
-1.00
40
-0.75
-1.00
0
0
10k 20k 30k 40k 50k 60k 70k
DAC CODE
0
10k 20k 30k 40k 50k 60k 70k
DAC CODE
0
10k 20k 30k 40k 50k 60k 70k
DAC CODE
4
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Typical Operating Characteristics (continued)
(V
= +5V, V
= +2.5V, T = +25°C, unless otherꢂise noted.)
REF
A
DD
FULL-SCALE STEP RESPONSE
FULL-SCALE STEP RESPONSE
(f = 20MHz)
(f
= 10MHz)
SCLK
SCLK
C = 10pF
L
L
C = 10pF
L
L
R = ∞
R = ∞
OUT
500mV/div
OUT
500mV/div
1µs/div
400ns/div
DIGITAL FEEDTHROUGH
MAJOR-CARRY OUTPUT GLITCH
CS
(5V/div)
SCLK
5V/div
OUT
OUT
(AC-COUPLED,
50mV/div)
(AC-COUPLED,
100mV/div)
2µs/div
2µs/div
CODE = 0000 hex
Pin Descriptions
MAX541
PIN
NAME
FUNCTION
1
2
3
4
5
6
7
8
OUT
AGID
REF
DAC Output Voltage
Analog Ground
Voltage Reference ꢁnput. Connect to external +2.5V reference.
Chip-Lelect ꢁnput
CS
LCꢀK
DꢁI
Lerial Clock ꢁnput. Duty cycle must be betꢂeen 40ꢃ and 60ꢃ.
Lerial Data ꢁnput
Digital Ground
DGID
V
DD
+5V Lupply Voltage
_______________________________________________________________________________________
5
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
________________________________________________Pin Descriptions (continued)
MAX542
PIN
1
NAME
RFS
FUNCTION
Feedback Resistor. Connect to external op amp’s output in bipolar mode.
DAC Output Voltage
2
OUT
3
AGIDF
AGIDL
REFL
REFF
CS
Analog Ground (force)
4
Analog Ground (sense)
5
Voltage Reference ꢁnput (sense). Connect REFL to external +2.5V reference.
Voltage Reference ꢁnput (force). Connect REFF to external +2.5V reference.
Chip-Lelect ꢁnput
6
7
8
LCꢀK
I.C.
Lerial Clock ꢁnput. Duty cycle must be betꢂeen 40ꢃ and 60ꢃ.
Io Connection. Iot internally connected.
Lerial Data ꢁnput
9
10
11
12
DꢁI
LDAC
DGID
LDAC ꢁnput. A falling edge updates the internal DAC latch.
Digital Ground
Junction of internal scaling resistors. Connect to external op amp’s inverting input in
bipolar mode.
13
14
ꢁIV
V
DD
+5V Lupply Voltage
t
t
CSH1
LDACS
CS
t
CSHO
t
CSS1
t
t
t
CL
CSSO
CH
SCLK
t
DH
t
DS
D15
D14
D0
DIN
LDAC*
t
LDAC
*MAX542 ONLY
Figure 1. Timing Diagram
6
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
+2.5V
10µF
+5V
0.1µF
0.1µF
MC68XXXX
V
REF (REFF) (REFS)
DD
UNIPOLAR
OUT
PCS0
MOSI
SCLK
CS
MAX495
EXTERNAL OP AMP
OUT
DIN
MAX541/MAX542
SCLK
(GND)
(LDAC)
DGND
AGND_
(
) ARE FOR MAX542 ONLY
Figure 2a. Typical Operating Circuit—Unipolar Output
+2.5V
10µF
+5V
0.1µF
0.1µF
REFF
+5V
RFB
MC68XXXX
V
REFS
DD
R
INV
PCS0
MOSI
SCLK
IC1
CS
R
INV
FB
BIPOLAR
OUT
EXTERNAL OP AMP
MAX400
DIN
OUT
SCLK
LDAC
DGND
MAX542
-5V
(GND)
AGNDF
AGNDS
Figure 2b. Typical Operating Circuit—Bipolar Output
major-carry transitions. ꢁt also loꢂers the DAC output
impedance by a factor of eight compared to a standard
R-2R ladder, alloꢂing unbuffered operation in medium-
load applications.
Detailed Description
The MAX541/MAX542 voltage-output, 16-bit digital-to-
analog converters (DACs) offer full 16-bit performance
ꢂith less than 1ꢀLS integral linearity error and less than
1ꢀLS differential linearity error, thus ensuring monoton-
ic performance. Lerial data transfer minimizes the num-
ber of package pins required.
The MAX542 provides matched bipolar offset resistors,
ꢂhich connect to an external op amp for bipolar output
sꢂings (Figure 2b). For optimum performance, the
MAX542 also provides a set of Kelvin connections to
the voltage-reference and analog-ground inputs.
The MAX541/MAX542 are composed of tꢂo matched
DAC sections, ꢂith a 12-bit inverted R-2R DAC forming
the 12 ꢀLSs and the 4 MLSs derived from 15 identically
matched resistors. This architecture alloꢂs the loꢂest
glitch energy to be transferred to the DAC output on
_______________________________________________________________________________________
7
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Digital Interface
The MAX541/MAX542’s digital interface is a standard
3-ꢂire connection compatible ꢂith LPꢁ/QLPꢁ/
MꢁCROWꢁRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DꢁI). ꢁmmediately folloꢂing CS’s high-to-loꢂ transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(LCꢀK). After 16 data bits have been loaded into the
serial input register, it transfers its contents to the DAC
latch on CS’s loꢂ-to-high transition (Figure 3a). Iote
that if CS is not kept loꢂ during the entire 16 LCꢀK
cycles, data ꢂill be corrupted. ꢁn this case, reload the
DAC latch ꢂith a neꢂ 16-bit ꢂord.
External Reference
The MAX541/MAX542 operate ꢂith external voltage ref-
erences from 2V to 3V. The reference voltage deter-
mines the DAC’s full-scale output voltage. Kelvin
connections are provided ꢂith the MAX542 for optimum
performance.
Power-On Reset
The MAX541/MAX542 have a poꢂer-on reset circuit to
set the DAC’s output to 0V in unipolar mode ꢂhen V
DD
is first applied. This ensures that unꢂanted DAC output
voltages ꢂill not occur immediately folloꢂing a system
poꢂer-up, such as after a loss of poꢂer. ꢁn bipolar
mode, the DAC output is set to -V
.
REF
Alternatively, for the MAX542, LDAC alloꢂs the DAC
latch to update asynchronously by pulling LDAC loꢂ
after CS goes high (Figure 3b). Hold LDAC high during
the data-loading sequence.
CS
DAC
UPDATED
SCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Figure 3a. MAX541/MAX542 3-Wire Interface Timing Diagram (LDAC = DGND for MAX542)
CS
SCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
LDAC
DAC
UPDATED
Figure 3b. MAX542 4-Wire Interface Timing Diagram
8
_______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Unbuffered Operation
Unbuffered operation reduces poꢂer consumption as
Applications Information
Reference and Analog Ground Inputs
The MAX541/MAX542 operate ꢂith external voltage ref-
erences from 2V to 3V, and maintain 16-bit performance
if certain guidelines are folloꢂed ꢂhen selecting and
applying the reference. ꢁdeally, the reference’s
temperature coefficient should be less than
0.4ppm/°C to maintain 16-bit accuracy to ꢂithin 1ꢀLS
over the 0°C to +70°C commercial temperature range.
Lince this converter is designed as an inverted R-2R
voltage-mode DAC, the input resistance seen by the volt-
age reference is code-dependent. The ꢂorst-case input-
resistance variation is from 11.5kΩ (at code 8555 hex) to
200kΩ (at code 0000 hex). The maximum change in load
current for a 2.5V reference is 2.5V / 11.5kΩ = 217µA;
therefore, the required load regulation is 7ppm/mA for a
maximum error of 0.1ꢀLS. This implies a reference
output impedance of less than 18mΩ. ꢁn addition, the
impedance of the signal path from the voltage
reference to the reference input must be kept loꢂ
because it contributes directly to the load-regulation
error.
ꢂell as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, alloꢂing 16-bit performance from +V
to AGID
REF
ꢂithout degradation at zero scale. The DAC’s output
impedance is also loꢂ enough to drive medium loads
(R > 60kΩ) ꢂithout degradation of ꢁIꢀ or DIꢀ; only
ꢀ
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
The requirements on the external output buffer amplifier
change ꢂhether the DAC is used in the unipolar or
bipolar mode of operation. ꢁn unipolar mode, the output
amplifier is used in a voltage-folloꢂer connection. ꢁn
bipolar mode (MAX542 only), the amplifier operates
ꢂith the internal scaling resistors (Figure 2b). ꢁn each
mode, the DAC’s output resistance is constant and is
independent of input code; hoꢂever, the output amplifi-
er’s input impedance should still be as high as possible
to minimize gain errors. The DAC’s output capacitance
is also independent of input code, thus simplifying sta-
bility requirements on the external amplifier.
The requirement for a loꢂ-impedance voltage reference
is met ꢂith capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor ꢂith short leads
betꢂeen REFF and AGIDF (MAX542), or REF and
AGID (MAX541), provides high-frequency bypassing.
A surface-mount ceramic chip capacitor is preferred
because it has the loꢂest inductance. An additional
10µF betꢂeen REFF and AGIDF (MAX542), or REF
and AGID (MAX541), provides loꢂ-frequency bypass-
ing. A loꢂ-ELR tantalum, film, or organic semiconductor
capacitor ꢂorks ꢂell. ꢀeaded capacitors are accept-
able because impedance is not as critical at loꢂer fre-
quencies. The circuit can benefit from even larger
bypassing capacitors, depending on the stability of the
external reference ꢂith capacitive loading. ꢁf separate
force and sense lines are not used, tie the appropriate
force and sense pins together close to the package.
ꢁn bipolar mode, a precision amplifier operating ꢂith
dual poꢂer supplies (such as the MAX400) provides
the
V
output range. ꢁn single-supply applications,
REF
precision amplifiers ꢂith input common-mode ranges
including AGID are available; hoꢂever, their output
sꢂings do not normally include the negative rail
(AGID) ꢂithout significant degradation of performance.
A single-supply op amp, such as the MAX495, is suit-
able if the application does not use codes near zero.
Lince the ꢀLSs for a 16-bit DAC are extremely small
(38.15µV for V
= 2.5V), pay close attention to the
REF
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2ꢀLS. Limilarly, the
input bias current multiplied by the DAC output resis-
tance (typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into con-
sideration. Over the 0°C to +70°C commercial tempera-
ture range, the offset voltage temperature coefficient
(referenced to +25°C) must be less than 0.42µV/°C to
add less than 1/2ꢀLS of zero-scale error. The external
amplifier’s input resistance forms a resistive divider ꢂith
the DAC output resistance, ꢂhich results in a gain error.
AGID must also be loꢂ impedance, as load-regulation
errors ꢂill be introduced by excessive AGID resis-
tance. As in all high-resolution, high-accuracy applica-
tions, separate analog and digital ground planes yield
the best results. Tie DGID to AGID at the AGID pin to
form the “star” ground for the DAC system. Alꢂays refer
remote DAC loads to this system ground for the best
possible performance.
_______________________________________________________________________________________
9
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
To contribute less than 1/2ꢀLS of gain error, the input
resistance typically must be greater than:
Unipolar Configuration
Figure 2a shoꢂs the MAX541/MAX542 configured for
unipolar operation ꢂith an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit.
1
2
1
16
6.25kΩ ÷
= 819MΩ
2
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Lettling time can be
significantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to ꢂithin
1/2ꢀLS of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance ꢂill
increase the settling time.
Bipolar Configuration
Figure 2b shoꢂs the MAX542 configured for bipolar
operation ꢂith an external op amp. The op amp is set
for unity gain ꢂith an offset of -1/2V
offset binary codes for this circuit.
. Table 2 lists the
REF
Power-Supply Bypassing and
Ground Management
For optimum system performance, use PC boards ꢂith
separate analog and digital ground planes. Wire-ꢂrap
boards are not recommended. Connect the tꢂo ground
planes together at the loꢂ-impedance poꢂer-supply
source. Connect DGID and AGID together at the ꢁC.
The best ground connection can be achieved by con-
necting the DAC’s DGID and AGID pins together and
connecting that point to the system analog ground
plane. ꢁf the DAC’s DGID is connected to the system
digital ground, digital noise may get through to the
DAC’s analog portion.
The external buffer amplifier’s gain-bandꢂidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of tꢂo cascaded systems,
each ꢂith a single time-constant response, is approxi-
mately the root square sum of the tꢂo time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. ꢁf the time
constant of an external amplifier ꢂith 1MHz bandꢂidth
is 1 / 2π (1MHz) = 159ns, then the effective time con-
stant of the combined system is:
Sypass V
ꢂith a 0.1µF ceramic capacitor connected
DD
DD
betꢂeen V
and AGID. Mount it ꢂith short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital poꢂer supplies.
2
2
83ns + 159ns
= 180ns
(
)
(
)
Table 1. Unipolar Code Table
DAC LATCH CONTENTS
ANALOG OUTPUT, V
OUT
This suggests that the settling time to ꢂithin 1/2ꢀLS of
the final output voltage, including the external buffer
amplifier, ꢂill be approximately 12 · 180ns = 2.15µs.
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
V
REF · (65,535 / 65,536)
1/
V
2
V
REF · (32,768 / 65,536) =
REF · (1 / 65,536)
0V
REF
Digital Inputs and Interface Logic
V
The digital interface for the 16-bit DAC is based on a
3-ꢂire standard that is compatible ꢂith LPꢁ, QLPꢁ, and
MꢁCROWꢁRE interfaces. The three digital inputs (CS,
DꢁI, and LCꢀK) load the digital input data serially into
the DAC. LDAC (MAX542) updates the DAC output
asynchronously.
Table 2. Bipolar Code Table
DAC LATCH CONTENTS
ANALOG OUTPUT, V
OUT
MSB
LSB
All of the digital inputs include Lchmitt-trigger buffers to
accept sloꢂ-transition interfaces. This means that opto-
couplers can interface directly to the MAX541/MAX542
ꢂithout additional external logic. The digital inputs are
compatible ꢂith TTꢀ/CMOL-logic levels.
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+VREF · (32,767 / 32,768)
+VREF · (1 / 32,768)
0V
-VREF · (1 / 32,768)
-VREF · (32,768 / 32,768) = -V
REF
10 ______________________________________________________________________________________
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
Ordering Information (continued)
Functional Diagrams (continued)
INL
(LSB)
PART
TEMP. RANGE
PIN-PACKAGE
V
DD
MAX541AEPA
MAX541SEPA
MAX541CEPA
MAX541AELA
MAX541SELA
MAX541CELA
MAX542ACPD
MAX542SCPD
MAX542CCPD
MAX542ACLD
MAX542SCLD
MAX542CCLD
MAX542SC/D
MAX542AEPD
MAX542SEPD
MAX542CEPD
MAX542AELD
MAX542SELD
MAX542CELD
-40°C to +85°C 8 Plastic DꢁP
-40°C to +85°C 8 Plastic DꢁP
-40°C to +85°C 8 Plastic DꢁP
-40°C to +85°C 8 LO
1
2
4
1
2
4
1
2
4
1
2
4
2
1
2
4
1
2
4
4
MAX541
REF
16-BIT DAC
OUT
AGND
-40°C to +85°C 8 LO
16-BIT DATA LATCH
SERIAL INPUT REGISTER
DGND
CS
DIN
SCLK
-40°C to +85°C 8 LO
CONTROL
LOGIC
0°C to +70°C 14 Plastic DꢁP
0°C to +70°C 14 Plastic DꢁP
0°C to +70°C 14 Plastic DꢁP
0°C to +70°C 14 LO
0°C to +70°C 14 LO
0°C to +70°C 14 LO
0°C to +70°C Dice*
-40°C to +85°C 14 Plastic DꢁP
-40°C to +85°C 14 Plastic DꢁP
-40°C to +85°C 14 Plastic DꢁP
-40°C to +85°C 14 LO
_____________________Chip Information
TRAILꢁLTOR COUIT: 2209
-40°C to +85°C 14 LO
LUSLTRATE COIIECTED TO DGID
-40°C to +85°C 14 LO
MAX542CMJD -55°C to +125°C 14 Ceramic LS**
*Dice are tested at T = +25°C, DC parameters only.
A
**Contact factory for availability.
______________________________________________________________________________________ 11
+5V, Serial-Input, Voltage-Output, 16-Bit DACs
________________________________________________________Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim ꢁntegrated Products
Printed ULA
is a registered trademark of Maxim ꢁntegrated Products.
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