MAX5442BCUB+ [MAXIM]
3V/5V, Serial-Input, Voltage-Output, 16-Bit DACs; 3V / 5V ，串行输入，电压输出， 16位DAC
| 型号： | MAX5442BCUB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 3V/5V, Serial-Input, Voltage-Output, 16-Bit DACs |
| 文件： | 总12页 (文件大小：245K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1846; Rev 3; 1/09
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
1–MAX54
General Description
Features
o Ultra-Small 3mm x 5mm 8-Pin µMAX Package
o Low 120µA Supply Current
o Fast 1µs Settling Time
The MAX5441–MAX5444 are serial-input, voltage-out-
put, 16-bit digital-to-analog converters (DACs) in tiny
®
µMAX packages, 50% smaller than comparable DACs
in 8-pin SOs. They operate from low +3V (MAX5443/
MAX5444) or +5V (MAX5441/MAX5442) single sup-
plies. They provide 16-bit performance ( 2ꢀSꢁ ꢂIꢀ and
1ꢀSꢁ DIꢀ) over temperature without any adꢃustments.
Unbuffered DAC outputs result in a low supply current
of 120µA and a low offset error of 2ꢀSꢁ.
o 25MHz SPI/QSPI/MICROWIRE-Compatible Serial
Interface
o V
Range Extends to V
DD
REF
o +5V (MAX5441/MAX5442) or +3V
(MAX5443/MAX5444) Single-Supply Operation
The DAC output ranges from 0 to V
. For bipolar
REF
o Full 16-Bit Performance Without Adjustments
operation, matched scaling resistors are provided in
the MAX5442/MAX5444 for use with an external preci-
sion op amp (such as the MAX400), generating a
o Unbuffered Voltage Output Directly Drives
60kΩ Loads
o Power-On Reset Circuit Clears DAC Output to
Code 0 (MAX5441/MAX5443) or Code 32768
(MAX5442/MAX5444)
V
REF
output swing.
A 16-bit serial word is used to load data into the DAC
latch. The 25MHz, 3-wire serial interface is compatible
with SPꢂ/QSPꢂ™/MꢂCROWꢂRE, and can interface directly
with optocouplers for applications requiring isolation. A
power-on reset circuit clears the DAC output to code 0
(MAX5441/MAX5443) or code 32768 (MAX5442
/MAX5444) when power is initially applied.
o Schmitt-Trigger Inputs for Direct Optocoupler
Interface
o Asynchronous CLR
Pin Configurations
A logic low on CLR asynchronously clears the DAC out-
put to code 0 (MAX5441/MAX5443) or code 32768
(MAX5442/MAX5444) independent of the serial interface.
TOP VIEW
+
+
The MAX5441/MAX5443 are available in 8-pin µMAX
packages. The MAX5442/MAX5444 are available in 10-
pin µMAX packages.
GND
REF
CS
1
2
3
4
5
10
9
GND
1
2
3
4
8
7
6
5
REF
CS
V
DD
V
DD
MAX5441
MAX5443
MAX5442
MAX5444
SCLK
DIN
8
RFB
INV
OUT
CLR
Applications
High-Resolution Offset and Gain Adꢃustment
ꢂndustrial Process Control
SCLK
DIN
7
CLR
OUT
6
µMAX-8
µMAX-10
Automated Test Equipment
Data-Acquisition Systems
Functional Diagrams appear at end of data sheet.
Ordering Information
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
8 µMAX
INL (LSB)
SUPPLY (V)
MAX5441ACUA+
MAX5441AEUA+
MAX5441ꢁCUA+
MAX5441ꢁEUA+
MAX5442ACUꢁ+
MAX5442AEUꢁ+
MAX5442ꢁCUꢁ+
MAX5442ꢁEUꢁ+
2
2
4
4
2
2
4
4
5
5
5
5
5
5
5
5
8 µMAX
8 µMAX
8 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: For leaded version, contact factory.
Ordering Information continued at end of data sheet.
µMAX is a registered trademark of Maxim ꢂntegrated Products, ꢂnc.
QSPꢂ is a trademark of Motorola, ꢂnc.
MꢂCROWꢂRE is a registered trademark of Iational Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
ABSOLUTE MAXIMUM RATINGS
V
to GND..............................................................-0.3V to +6V
Continuous Power Dissipation (T = +70°C)
A
DD
CS, SCLK, DIN, CLR to GND ...................................-0.3V to +6V
REF to GND................................................-0.3V to (V + 0.3V)
OUT, INV to GND .....................................................-0.3V to V
8-Pin µMAX (derate 4.5mW/°C above +70°C)...............362mW
10-Pin µMAX (derate 5.6mW/°C above +70°C) ..............444mW
Operating Temperature Ranges
DD
DD
RFB to INV...................................................................-6V to +6V
RFB to GND.................................................................-6V to +6V
Maximum Current Into Any Pin ...........................................50mA
MAX544 _ _CU_ ...................................................0°C to +70°C
MAX544 _ _EU_.................................................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Maximum Die Temperature..............................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
DD
(V
= +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), V
= +2.5V, C = 10pF, GND = 0, R = ∞, T = T
to T
,
MAX
REF
L
L
A
MIN
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
1–MAX54
Resolution
N
16
Bits
Differential Nonlinearity
DNL
Guaranteed monotonic
0.5
0.5
0.5
1
2
4
2
LSB
MAX544_A
MAX544_B
Integral Nonlinearity
INL
LSB
Zero-Code Offset Error
Zero-Code Tempco
Gain Error (Note 1)
ZSE
LSB
ppm/°C
LSB
ZS
0.05
TC
10
Gain-Error Tempco
DAC Output Resistance
0.1
6.2
1
ppm/°C
kΩ
R
(Note 2)
OUT
R
/R
FB INV
Bipolar Resistor Matching
%
Ratio error
0.015
20
Bipolar Zero Offset Error
Bipolar Zero Tempco
LSB
BZS
0.5
ppm/°C
TC
+2.7V ≤ V
+4.5V ≤ V
≤ +3.3V (MAX5443/MAX5444)
≤ +5.5V (MAX5441/MAX5442)
1
1
DD
Power-Supply Rejection
PSR
LSB
DD
REFERENCE INPUT
Reference Input Range
V
R
(Note 3)
2.0
10
6
V
V
REF
DD
Unipolar mode
Bipolar mode
Reference Input Resistance
(Note 4)
kΩ
REF
DYNAMIC PERFORMANCE—ANALOG SECTION
Voltage-Output Slew Rate
Output Settling Time
DAC Glitch Impulse
SR
(Note 5)
To 1/2LSB of FS
15
1
V/µs
µs
Major-carry transition
7
nV-s
Code = 0000 hex; CS = V
;
DD
Digital Feedthrough
0.2
nV-s
SCLK, DIN = 0 to V
levels
DD
2
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
1–MAX54
ELECTRICAL CHARACTERISTICS (continued)
(V
= +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), V
= +2.5V, C = 10pF, GND = 0, R = ∞, T = T
to T
,
MAX
DD
REF
L
L
A
MIN
unless otherwise noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
BW
Code = FFFF hex
1
1
MHz
Code = 0000 hex, V
= 1V
at 100kHz
mV
P-P
REF
P-P
SNR
92
70
170
dB
Code = 0000 hex
Code = FFFF hex
Reference Input Capacitance
C
INREF
pF
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
V
2.4
V
V
IH
V
0.8
1
IL
I
IN
µA
pF
V
Input Capacitance
Hysteresis Voltage
POWER SUPPLY
C
(Note 6)
3
10
IN
V
0.15
H
MAX5443/MAX5444
MAX5441/MAX5442
2.7
4.5
3.6
5.5
Positive Supply Range (Note 7)
Positive Supply Current
Power Dissipation
V
V
DD
I
All digital inputs at V
or GND
0.12
0.36
0.60
0.20
mA
mW
DD
DD
MAX5443/MAX5444
MAX5441/MAX5442
All digital inputs at
PD
V
DD
or GND
TIMING CHARACTERISTICS
(V
= +2.7V to +3.3V (MA5443/MAX5444) , V
= +4.5V to +5.5V (MAX5441/MAX5442), V
= +2.5V, GND = 0, CMOS inputs,
DD
DD
REF
T
A
= T
to T
, unless otherwise noted. Typical values are at T = +25°C.) (Figure 1)
MAX A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
25
CLK
SCLK Pulse Width High
SCLK Pulse Width Low
CS Low to SCLK High Setup
CSHigh to SCLKHigh Setup
SCLKHigh to CSLow Hold
SCLKHigh to CSHigh Hold
DIN to SCLKHigh Setup
DIN to SCLKHigh Hold
CLR Pulse Width Low
t
20
20
15
15
35
20
15
0
CH
t
CL
ns
t
t
t
ns
CSS0
CSS1
ns
(Note 6)
ns
CSH0
CSH1
t
ns
t
ns
DS
t
ns
DH
t
20
ns
CLW
V
High to CSLow
DD
20
µs
(power-up delay)
Note 1: Gain error tested at V
= +2.0V, +2.5V, and +3.0V (MAX5443/MAX5444) or V
= +2.0V, +2.5V, +3.0V, and +5.5V
REF
REF
(MAX5441/ MAX5442).
Note 2: R tolerance is typically 20%.
OUT
Note 3: Min/max range guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code-dependent, minimum at 8555hex in unipolar mode, 4555hex in bipolar mode.
Note 5: Slew-rate value is measured from 10% to 90%.
Note 6: Guaranteed by design. Not production tested.
Note 7: Guaranteed by power-supply rejection test and Timing Characteristics.
_______________________________________________________________________________________
3
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
__________________________________________Typical Operating Characteristics
(V
= +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), V
= +2.5V, GND = 0, R = ∞, T = T
to T
, unless other-
MAX
DD
REF
L
A
MIN
wise noted. Typical values are at T = +25°C.)
A
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
0.12
0.11
0.10
0.09
0.08
0.07
0.06
0.05
0.12
0.11
0.150
0.125
0.100
0.075
0.050
0.025
0
V
DD
= +5V
0.10
V
DD
= +3V
0.09
0.08
0.07
0.06
0.05
V
DD
= +5V
V
= +3V
DD
0
-40
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
REFERENCE VOLTAGE (V)
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-40
-40
-15
10
35
60
85
85
85
1–MAX54
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.8
0.6
0.4
0.2
0
0.2
0.1
0.4
0.3
0.2
0.1
0
+DNL
+INL
0
-0.1
-0.2
-0.3
-0.4
-INL
-DNL
-0.1
-0.2
-0.2
-0.4
-15
10
TEMPERATURE (°C)
35
60
85
-40
-15
10
35
60
85
-15
10
35
60
TEMPERATURE (°C)
TEMPERATURE (°C)
GAIN ERROR
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
INTEGRAL NONLINEARITY vs. CODE
0.125
0.100
0.075
0.050
0.025
0
0.25
0.20
0.15
0.10
0.05
0
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
-0.025
-0.050
-0.075
-0.05
-0.10
-0.15
-0.100
-0.125
-0.20
-0.25
-15
10
35
60
35k
35k
0
5k 15k 25k
45k 55k 66k
5k 15k 25k
45k 55k 66k
TEMPERATURE (°C)
CODE
CODE
4
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
1–MAX54
Typical Operating Characteristics (continued)
(V
= +3V (MAX5443/MAX5444) or +5V (MAX5441/MAX5442), V
= +2.5V, GND = 0, R = ∞, T = T
to T
, unless other-
MAX
DD
REF
L
A
MIN
wise noted. Typical values are at T = +25°C.)
A
FULL-SCALE STEP RESPONSE
(FALLING)
FULL-SCALE STEP RESPONSE
(RISING)
REFERENCE CURRENT
vs. DIGITAL INPUT CODE
140
MAX5441/44 toc11
120
100
80
60
40
20
0
CS
2V/div
CS
2V/div
A
OUT
A
OUT
1V/div
1V/div
C = 20pF
L
C = 20pF
L
400ns/div
0
10000 20000 30000 40000 50000 60000 70000
CODE
400ns/div
MAJOR-CARRY GLITCH
MAJOR-CARRY GLITCH
(FALLING)
(RISING)
CS
1V/div
CS
1V/div
A
OUT
20mV/div
A
OUT
20mV/div
C = 20pF
L
C = 20pF
L
200ns/div
200ns/div
INTEGRAL NONLINEARITY
vs. REFERENCE VOLTAGE
UNIPOLAR POWER-ON GLITCH
(REF = V
DIGITAL FEEDTHROUGH
)
DD
0.70
0.65
0.60
0.55
0.50
0.45
0.40
V
DD
2V/div
D
IN
2V/div
V
OUT
10mV/div
A
OUT
10mV/div
C = 112pF
L
50ns/div
2.0
2.5
3.0
3.5
4.0
4.5
5.0
50ms/div
REFERENCE VOLTAGE (V)
_______________________________________________________________________________________
5
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Pin Description
PIN
NAME
FUNCTION
MAX5441
MAX5443
MAX5442
MAX5444
1
2
3
4
1
2
3
4
REF
CS
Voltage Reference Input
Chip-Select Input
SCLK
DIN
Serial Clock Input. Duty cycle must be between 40% and 60%.
Serial Data Input
Clear Input. Logic low asynchronously clears the DAC to code 0 (MAX5441/MAX5443)
or code 32768 (MAX5442/MAX5444).
5
6
5
6
7
CLR
OUT
INV
DAC Output Voltage
Junction of Internal Scaling Resistors. Connect to external op amp’s inverting input in
bipolar mode.
—
—
7
8
9
RFB
Feedback Resistor. Connect to external op amp’s output in bipolar mode.
Supply Voltage. Use +3V for MAX5443/MAX5444 and +5V for MAX5441/MAX5442.
Ground
V
DD
1–MAX54
8
10
GND
t
CSH1
CS
t
CSHO
t
CSS1
t
t
t
CL
CSSO
CH
SCLK
DIN
t
DH
t
DS
D15
D14
D0
Figure 1. Timing Diagram
6
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
1–MAX54
+2.5V
MAX6166
+3V/+5V
1µF
0.1µF
0.1µF
V
REF
DD
MC68XXXX
UNIPOLAR
OUT
CS
PCS0
MOSI
MAX495
EXTERNAL OP AMP
MAX5441
MAX5442
MAX5443
MAX5444
OUT
DIN
SCLK
CLR
SCLK
IC1
(GND)
GND
Figure 2a. Typical Operating Circuit—Unipolar Output
+2.5V
MAX6166
+3V/+5V
1µF
0.1µF
0.1µF
+5V
RFB
MC68XXXX
V
DD
R
INV
PCS0
MOSI
SCLK
IC1
CS
R
INV
FB
BIPOLAR
OUT
EXTERNAL OP AMP
MAX400
DIN
OUT
SCLK
CLR
MAX5442
MAX5444
-5V
(GND)
GND
Figure 2b. Typical Operating Circuit—Bipolar Output
The MAX5441–MAX5444 are composed of two
matched DAC sections, with a 12-bit inverted R-2R
DAC forming the 12 LSBs and the four MSBs derived
from 15 identically matched resistors. This architecture
allows the lowest glitch energy to be transferred to the
DAC output on major-carry transitions. It also lowers the
DAC output impedance by a factor of eight compared
Detailed Description
The MAX5441–MAX5444 voltage-output, 16-bit digital-
to-analog converters (DACs) offer full 16-bit perfor-
mance with less than 2LSB integral linearity error and
less than 1LSB differential linearity error, thus ensuring
monotonic performance. Serial data transfer minimizes
the number of package pins required.
_______________________________________________________________________________________
7
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
to a standard R-2R ladder, allowing unbuffered opera-
tion in medium-load applications.
MAX5442/MAX5444 to code 32768 when V
is first
DD
applied. This ensures that unwanted DAC output volt-
ages will not occur immediately following a system
power-up, such as after a loss of power.
The MAX5442/MAX5444 provide matched bipolar offset
resistors, which connect to an external op amp for bipo-
lar output swings (Figure 2b).
Applications Information
Digital Interface
The MAX5441–MAX5444 digital interface is a standard
3-wire connection compatible with SPI/QSPI/
MICROWIRE interfaces. The chip-select input (CS)
frames the serial data loading at the data-input pin
(DIN). Immediately following CS’s high-to-low transition,
the data is shifted synchronously and latched into the
input register on the rising edge of the serial clock input
(SCLK). After 16 data bits have been loaded into the
serial input register, it transfers its contents to the DAC
latch on CS’s low-to-high transition (Figure 3). Note that
if CS is not kept low during the entire 16 SCLK cycles,
data will be corrupted. In this case, reload the DAC
latch with a new 16-bit word.
Reference and Ground Inputs
The MAX5441–MAX5444 operate with external voltage
references from 2V to V , and maintain 16-bit perfor-
DD
mance if certain guidelines are followed when selecting
and applying the reference. Ideally, the reference’s
temperature coefficient should be less than
0.1ppm/°C to maintain 16-bit accuracy to within 1LSB
over the -40°C to +85°C extended temperature range.
Since this converter is designed as an inverted R-2R volt-
age-mode DAC, the input resistance seen by the voltage
reference is code-dependent. In unipolar mode, the
worst-case input-resistance variation is from 11.5kΩ (at
code 8555hex) to 200kΩ (at code 0000hex). The maxi-
mum change in load current for a 2.5V reference is 2.5V /
11.5k Ω = 217µA; therefore, the required load regulation
is 7ppm/mA for a maximum error of 0.1LSB. This implies
a reference output impedance of less than 18mΩ. In
addition, the impedance of the signal path from the volt-
age reference to the reference input must be kept low
because it contributes directly to the load-regulation
error.
1–MAX54
Clearing the DAC
A 20ns (min) logic-low pulse on CLR asynchronously
clears the DAC buffer to code 0 in the MAX5441/
MAX5443 and to code 32768 in the MAX5442/ MAX5444.
External Reference
The MAX5441–MAX5444 operate with external voltage
references from 2V to V . The reference voltage
DD
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REF and GND provides high-frequency
bypassing. A surface-mount ceramic chip capacitor is
preferred because it has the lowest inductance. An
determines the DAC’s full-scale output voltage.
Power-On Reset
The power-on reset circuit sets the output of the
MAX5441/MAX5443 to code 0 and the output of the
CS
DAC
UPDATED
SCLK
SUB-BITS
DIN
D15 D14 D13 D12 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Figure 3. MAX5441–MAX5444 3-Wire Interface Timing Diagram
8
_______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
1–MAX54
additional 1µF between REF and GND provides low-fre-
add less than 1/2LSB of zero-scale error. The external
amplifier’s input resistance forms a resistive divider with
the DAC output resistance, which results in a gain error.
To contribute less than 1/2LSB of gain error, the input
resistance typically must be greater than:
quency bypassing. A low-ESR tantalum, film, or organic
semiconductor capacitor works well. Leaded capaci-
tors are acceptable because impedance is not as criti-
cal at lower frequencies. The circuit can benefit from
even larger bypassing capacitors, depending on the
stability of the external reference with capacitive loading.
17
6.25kΩ × 2 = 819MΩ
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be sig-
nificantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to within
1/2LSB of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance will
increase the settling time.
OUT, allowing 16-bit performance from +V
to GND
REF
without degradation at zero-scale. The DAC’s output
impedance is also low enough to drive medium loads
(R > 60kΩ) without degradation of INL or DNL; only
L
the gain error is increased by externally loading the
DAC output.
External Output Buffer Amplifier
The requirements on the external output buffer amplifier
change whether the DAC is used in the unipolar or bipo-
lar mode of operation. In unipolar mode, the output
amplifier is used in a voltage-follower connection. In
bipolar mode (MAX5442/MAX5444 only), the amplifier
operates with the internal scaling resistors (Figure 2b). In
each mode, the DAC’s output resistance is constant and
is independent of input code; however, the output ampli-
fier’s input impedance should still be as high as possible
to minimize gain errors. The DAC’s output capacitance is
also independent of input code, thus simplifying stability
requirements on the external amplifier.
The external buffer amplifier’s gain-bandwidth product
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approxi-
mately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time con-
stant of the combined system is:
In bipolar mode, a precision amplifier operating with
dual power supplies (such as the MAX400) provides
2
2
⎡
⎣
⎤
83ns + 159ns
=180ns
(
)
(
)
⎢
⎥
⎦
the
V
output range. In single-supply applications,
REF
precision amplifiers with input common-mode ranges
including GND are available; however, their output
swings do not normally include the negative rail (GND)
without significant degradation of performance. A sin-
gle-supply op amp, such as the MAX495, is suitable if
the application does not use codes near zero.
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
ꢀ
amplifier, will be approximately 12 180ns = 2.15µs.
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a
3-wire standard that is compatible with SPI, QSPI, and
MICROWIRE interfaces. The three digital inputs (CS,
DIN, and SCLK) load the digital input data serially into
the DAC.
Since the LSBs for a 16-bit DAC are extremely small
(38.15µV for V
= 2.5V), pay close attention to the
REF
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resis-
tance (typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into con-
sideration. Over the -40°C to +85°C extended tempera-
ture range, the offset voltage temperature coefficient
(referenced to +25°C) must be less than 0.24µV/°C to
A 20ns (min) logic-low pulse on CLR clears the data in
the DAC buffer.
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that opto-
couplers can interface directly to the MAX5441–
MAX5444 without additional external logic. The digital
inputs are compatible with TTL/CMOS-logic levels.
_______________________________________________________________________________________
9
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Unipolar Configuration
Table 1. Unipolar Code Table
Figure 2a shows the MAX5441–MAX5444 configured for
unipolar operation with an external op amp. The op amp
is set for unity gain, and Table 1 lists the codes for this
circuit. The bipolar MAX5442/MAX5444 can also be
used in unipolar configuration by connecting RFB and
INV to REF. This allows the DAC to power-up to mid-
scale.
DAC LATCH CONTENTS
MSB LSB
ANALOG OUTPUT, V
OUT
ꢀ
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
V
(65,535 / 65,536)
(32,768 / 65,536) =
(1 / 65,536)
REF
1/
V
REF
2
ꢀ
ꢀ
V
REF
V
0
REF
Bipolar Configuration
Figure 2b shows the MAX5442/MAX5444 configured for
bipolar operation with an external op amp. The op amp
Table 2. Bipolar Code Table
is set for unity gain with an offset of -1/2V
lists the offset binary codes for this circuit.
. Table 2
REF
DAC LATCH CONTENTS
ANALOG OUTPUT, V
OUT
MSB
LSB
Power-Supply Bypassing and
Ground Management
ꢀ
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
+V
+V
0
(32,767 / 32,768)
(1 / 32,768)
REF
REF
ꢀ
Bypass V
with a 0.1µF ceramic capacitor connected
DD
DD
between V
and GND. Mount the capacitor with short
leads close to the device (less than 0.25 inches).
ꢀ
-V
-V
(1 / 32,768)
X
REF
REF
ꢀ
(32,768 / 32,768) = -V
REF
10 ______________________________________________________________________________________
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
1–MAX54
Functional Diagrams
V
V
DD
DD
RFB
MAX5441
MAX5443
MAX5442
MAX5444
INV
REF
CS
REF
CS
OUT
OUT
16-BIT DAC
16-BIT DAC
16-BIT DATA LATCH
16-BIT DATA LATCH
SCLK
DIN
SCLK
DIN
CONTROL
LOGIC
CONTROL
LOGIC
SERIAL INPUT REGISTER
SERIAL INPUT REGISTER
CLR
CLR
GND
GND
Ordering Information (continued)
PART
TEMP RANGE
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
PIN-PACKAGE
8 µMAX
INL (LSB)
SUPPLY (V)
MAX5443ACUA+
MAX5443AEUA+
MAX5443BCUA+
MAX5443BEUA+
MAX5444ACUB+
MAX5444AEUB+
MAX5444BCUB+
MAX5444BEUB+
2
2
4
4
2
2
4
4
3
3
3
3
3
3
3
3
8 µMAX
8 µMAX
8 µMAX
10 µMAX
10 µMAX
10 µMAX
10 µMAX
+Denotes a lead(Pb)-free/RoHS-compliant package.
Note: For leaded version, contact factory.
_____________________Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
LAND
PATTERN NO.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
90-0092
90-0330
8 µMAX
U8+1
21-0036
21-0061
10 µMAX
U10+2
______________________________________________________________________________________ 11
+3V/+5V, Serial-Input,
Voltage-Output, 16-Bit DACs
Revision History
REVISION REVISION
DESCRIPTION
PAGES
CHANGED
NUMBER
DATE
0
2
3
10/00
10/07
1/09
Initial release
—
6
Changed timing diagram
Added lead-free notation in Ordering Information.
1, 11
1–MAX54
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 202
-
VISHAY
©2020 ICPDF网 联系我们和版权申明