MAX547BEQH+TD [MAXIM]
D/A Converter, 1 Func, Parallel, Word Input Loading, 5us Settling Time, PQCC44, PLASTIC, ROHS COMPLIANT, LCC-44;
| 型号： | MAX547BEQH+TD |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Parallel, Word Input Loading, 5us Settling Time, PQCC44, PLASTIC, ROHS COMPLIANT, LCC-44 |
| 文件： | 总16页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0257; Rev 3; 12/95
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t DAC
w it h P a ra lle l In t e rfa c e
MAX547
_________________Ge n e ra l De s c rip t io n
_____________________________Fe a t u re s
The MAX547 contains eight 13-bit, voltage-output digital-to-
analog converters (DACs). On-chip precision output ampli-
fiers provide the voltage outputs. The MAX547 operates
from a ±5V supply. Bipolar output voltages with up to ±4.5V
voltage swing can be achieved with no external compo-
nents. The MAX547 has four separate reference inputs;
each is connected to two DACs, providing different full-
scale output voltages for every DAC pair.
♦ Full 13-Bit Performance without Adjustments
♦ 8 DACs in One Package
♦ Buffered Voltage Outputs
♦ Calibrated Linearity
♦ Guaranteed Monotonic to 13 Bits
♦ ±5V Supply Operation
♦ Unipolar or Bipolar Outputs Swing to ±4.5V
♦ Fast Output Settling (5µs to ±1⁄2LSB)
♦ Double-Buffered Digital Inputs
The MAX547 features double-buffered interface logic with a
13-bit parallel data bus. Each DAC has an input latch and a
DAC latch. Data in the DAC latch sets the output voltage. The
eight input latches are addressed with three address lines.
♦ Asynchronous Load Inputs Load Pairs of DAC Latches
–——–
Data is loaded to the input latch with a single write instruction.
–——–
♦ Asynchronous CLR Input Resets DACs to Analog
An asynchronous load (LD_) input transfers data from the
–——–
Ground
input latch to the DAC latch. The four LD_ inputs each control
♦ Power-On Reset Circuit Resets DACs to Analog Ground
♦ Microprocessor and TTL/CMOS Compatible
two DACs, and all DAC latches can be updated simultane-
ously by asserting all LD_ pins. An asynchronous clear (CLR)
–——–
–——–
input resets the output of all eight DACs to AGND_. Asserting
–——–
________________Ord e rin g In fo rm a t io n
CLR resets both the DAC and the input latch to bipolar zero
(1000hex). On power-up, reset circuitry performs the same
–——–
INL
(LSBs)
function as CLR. All logic inputs are TTL/CMOS compatible.
PART
TEMP. RANGE
PIN-PACKAGE
The MAX547 is available in 44-pin plastic quad flat pack
and 44-pin PLCC packages.
________________________Ap p lic a t io n s
MAX547ACQH
MAX547BCQH
MAX547ACMH
MAX547BCMH
MAX547BC/D
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
44 PLCC
44 PLCC
±2
±4
±2
±4
±4
44 Plastic FP
44 Plastic FP
Dice*
Automatic Test Equipment
Minimum Component-Count Analog Systems
Digital Offset/Gain Adjustment
Arbitrary Function Generators
Industrial Process Controls
Ordering Information continued at end of data sheet.
*Contact factory for dice specifications.
Avionics Equipment
_______________________________________________________________P in Co n fig u ra t io n s
TOP VIEW
43
42 41 40
6
5
4
3
2
1
44
VOUTB
VOUTA
1
2
3
4
5
6
7
8
9
VOUTG
VOUTH
33
32
31
30
29
28
VOUTB
VOUTA
7
8
39 VOUTG
38 VOUTH
V
DD
V
DD
V
DD
9
37
V
DD
REFAB
AGNDAB
LDAB
REFGH
AGNDGH
GND
LDGH
LDEF
D0
10
36 REFGH
REFAB
AGNDAB 11
LDAB 12
LDCD 13
CS 14
35
34
33
32
31
30
29
AGNDGH
GND
LDGH
LDEF
D0
MAX547
MAX547
27
26
25
24
LDCD
CS
WR
A2
10
11
D1
WR 15
23
A1
D2
A2 16
D1
A1 17
D2
18 19 20 21 22 23 24 25 26 27 28
PLASTIC FP
PLCC
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
ABSOLUTE MAXIMUM RATINGS
DD
V
to GND ..............................................................-0.3V to +6V
to GND...............................................................-6V to +0.3V
Continuous Power Dissipation (T = +70°C)
A
V
PLCC (derate 13.33mW/°C above +70°C)...................1067mW
Plastic FP (derate 11.11mW/°C above +70°C )..............889mW
Operating Temperature Ranges
SS
Digital Input Voltage to GND ......................-0.3V to (V + 0.3V)
REF_ ..........................................(AGND_ - 0.3V) to (V + 0.3V)
DD
DD
MAX547 C H.........................................................0°C to +70°C
AGND_ .............................................(V - 0.3V) to (V + 0.3V)
SS
DD
– –
MAX547 E H......................................................-40°C to +85°C
– –
VOUT_ ........................................................................V to V
DD
SS
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
Maximum Current into REF_ Pin .......................................±10mA
Maximum Current into Any Other Signal Pin ....................±50mA
MAX547
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rat-
ings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, R = 10kΩ, C = 50pF, T = T
to T
, unless otherwise noted.
DD
SS
L
L
A
MIN
MAX
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION
Resolution
N
13
Bits
MAX547A
MAX547B
±0.5
±0.5
±2
±4
Relative Accuracy
INL
DNL
LSB
Differential Nonlinearity
Bipolar Zero-Code Error
Gain Error
Guaranteed monotonic
±1
LSB
LSB
LSB
±5
±20
±1
±8
∆Gain/∆V (Note 1)
±0.0025
±0.0025
DD
Power-Supply Rejection Ratio
Load Regulation
PSRR
%/%
LSB
∆Gain/∆V (Note 1)
SS
R = ∞ to 10kΩ
0.3
L
REFERENCE INPUT (Note 2)
Reference Input Range
REF
(Notes 2, 3)
V
AGND
5
V
DD
–
Reference Input Resistance
RREF
Each REF pin (Note 3)
–
kΩ
ANALOG OUTPUT
Maximum Output Voltage
Minimum Output Voltage
V
V
V
- 0.5
DD
V
SS
+ 0.5
DYNAMIC PERFORMANCE—ANALOG SECTION
Voltage-Output Slew Rate
3
5
5
5
V/µs
µs
1
±
Output Settling Time
Digital Feedthrough
Digital Crosstalk
To
⁄
LSB of full scale (Note 4)
2
nV-s
nV-s
DIGITAL INPUTS (V = 5V ±5%)
DD
Input Voltage High
Input Voltage Low
Input Current
V
2.4
V
V
IH
V
IL
0.8
1.0
10
I
IN
V
= 0V or V
DD
µA
pF
IN
Input Capacitance
C
(Note 5)
IN
2
_______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, R = 10kΩ, C = 50pF, T = T
to T
, unless otherwise noted.
DD
SS
L
L
A
MIN
MAX
Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
Positive Supply Range
Negative Supply Range
Positive Supply Current
Negative Supply Current
V
(Note 6)
(Note 6)
4.75
5.25
-4.75
44
V
V
DD
V
-5.25
SS
I
T
= T
= T
to T
14
11
mA
mA
A
MIN
MIN
MAX
DD
I
T
to T
40
A
MAX
SS
Note 1: PSRR is tested by changing the respective supply voltage by ±5%.
Note 2: For best performance, REF_ should be greater than AGND_ + 2V and less than V - 0.6V. The device operates with
DD
reference inputs outside this range, but performance may degrade. For further information on the reference, see the
Reference and Analog-Ground Inputs section in the Detailed Description.
Note 3: Reference input resistance is code dependent. See Reference and Analog-Ground Inputs section in the Detailed
Description.
Note 4: Typical settling time with 1000pF capacitive load is 10µs.
Note 5: Guaranteed by design. Not production tested.
Note 6: Guaranteed by supply-rejection test.
TIMING CHARACTERISTICS
(V = +5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, T = T
to T
, unless otherwise noted.)
DD
SS
A
MIN
MAX
PARAMETER
SYMBOL
CONDITIONS
MIN
50
50
50
100
0
TYP
MAX
UNITS
ns
–—–
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
CS Pulse Width Low
–—–
ns
WR Pulse Width Low
–——–
ns
LD Pulse Width Low
–
–——–
ns
CLR Pulse Width Low
–—–
–—–
ns
CS Low to WR Low
–—–
–—–
ns
0
CS High to WR High
–—–
ns
Data Valid to WR Setup
50
0
–—–
ns
Data Valid to WR Hold
–—–
ns
Address Valid to WR Setup
10
0
–—–
t
ns
10
Address Valid to WR Hold
_______________________________________________________________________________________
3
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = 5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, T = +25°C, unless otherwise noted.)
DD
SS
A
RELATIVE ACCURACY vs.
REFERENCE VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
RELATIVE ACCURACY
vs. DIGITAL INPUT CODE
0.5
20
15
10
5
3
2
0.4
0.3
0.2
0.1
0
I
DD
MAX547
1
0
0
-5
-0.1
-0.2
-0.3
-0.4
-0.5
I
SS
-10
-1
-2
-15
-20
5
-60 -40 -20
0
20 40 60 80 100 120 140
0
1
2
3
4
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
DIGITAL INPUT CODE (DECIMAL)
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
TOTAL HARMONIC DISTORTION
+ NOISE AT DAC OUTPUT
vs. REFERENCE FREQUENCY
SETTLING TIME
vs. LOAD CAPACITANCE
0.100
0.090
0.080
0.070
0.060
0.050
0.040
0.030
0.020
0.010
0
0.100
0.090
0.080
0.070
0.060
0.050
0.040
0.030
0.020
0.010
0
1000
100
REF = 4V
INPUT CODE = ALL 1s
REF = 2V
INPUT CODE = ALL 1s
p-p
p-p
–
–
10
1
1
10
100
1000
1
10
100
1000
0.01
0.1
1
10
100
FREQUENCY (kHz)
LOAD CAPACITANCE (nF)
FREQUENCY (kHz)
REFERENCE INPUT SMALL-SIGNAL
FREQUENCY RESPONSE
REFERENCE INPUT LARGE-SIGNAL
FREQUENCY RESPONSE
REFERENCE FEEDTHROUGH
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
2
0
6
0
-2
SINE WAVE AT REF
–
SINE WAVE AT REF_
2V ±2V
CODE ALL 1s
-6
-12
-18
-24
-30
-36
2V ±100mV
CODE ALL 1s
-6
-10
-14
-18
-22
SINE WAVE AT REF_
2V ±2V
0.1
1
10
100
1000
0.1
1
10
100
1000 10,000
0.1
1
10
100
1000 10,000
FREQUENCY (kHz)
FREQUENCY (kHz)
FREQUENCY (kHz)
4
_______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, T = +25°C, unless otherwise noted.)
DD
SS
A
POWER-SUPPLY REJECTION RATIO
vs. FREQUENCY
FULL-SCALE ERROR
vs. LOAD RESISTANCE
0
2.0
1.5
-10
-20
-30
-40
-50
-60
V
DD
= V = 5V ±200mV
SS
NEGATIVE
FULL-SCALE
NO LOAD
1.0
0.5
0
V
V
DD
SS
REF_ = 4.096V
-0.5
-1.0
-1.5
-2.0
POSITIVE
FULL-SCALE
-70
-80
0.01
0.1
1
10
100
1000
100
1
10
1000
FREQUENCY (kHz)
LOAD RESISTANCE (kΩ)
NEGATIVE SETTLING TIME TO FULL-SCALE STEP
(ALL BITS ON TO ALL BITS OFF)
POSITIVE SETTLING TIME TO FULL-SCALE STEP
(ALL BITS OFF TO ALL BITS ON)
DIGITAL
INPUTS
(5V/div)
DIGITAL
INPUTS
(5V/div)
OUTPUT
OUTPUT
(1mV/div)
(1mV/div)
2µs/div
2µs/div
REF = 4.096V, C = 100pF, R = 5kΩ
REF = 4.096V, C = 100pF, R = 5kΩ
L L
–
L
L
–
DYNAMIC RESPONSE
(ALL BITS OFF, ON, OFF)
DIGITAL FEEDTHROUGH
(GLITCH IMPULSE)
+5V
0V
DIGITAL
INPUTS
(5V/div)
10mV
0V
-10mV
OUTPUT
(2V/div)
200ns/div
2µs/div
TOP: DIGITAL TRANSITION ON ALL DATA BITS
BOTTOM: DAC OUTPUT WITH WR HIGH 10mV/div
REF = 4.096V, C = 100pF, R = 5kΩ
L
L
–
_______________________________________________________________________________________
5
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = 5V, V = -5V, REF_ = 4.096V, AGND_ = GND = 0V, T = +25°C, unless otherwise noted.)
DD
SS
A
ADJACENT-CHANNEL CROSSTALK
ADJACENT-CHANNEL CROSSTALK
A:
A
5V/div
5V/div
MAX547
B
B:
5mV/div
5mV/div
500ns/div
REF = 4.096V, C = 50pF, R = 10kΩ
500ns/div
L
L
REF = 4.096V, C = 50pF, R = 10kΩ
–
L
L
–
A: DIGITAL INPUTS, DAC A, DATA BITS from ALL Os to OAAAhex
B: OUTPUT, DAC B
A: DIGITAL INPUTS, DAC A, DATA BITS from OAAAhex to ALL Os
B: OUTPUT, DAC B
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
FLAT
PACK
PLCC
Clear Input (active low). Driving this asynchronous input low sets the content of all latches to
1000hex. All DAC outputs are reset to AGND_.
–——–
CLR
1
39
2
3
40
41
AGNDCD
REFCD
Analog Ground for DAC C and DAC D
Reference Voltage Input for DAC C and DAC D. Bypass to AGNDCD with a 0.1µF to 1µF capacitor.
Negative Power Supply, -5V (2 pins). Connect both pins to the supply voltage. Bypass each pin
to the system analog ground with a 0.1µF to 1µF capacitor.
4, 42
42, 36
V
SS
5
6
7
8
43
44
1
VOUTD
VOUTC
VOUTB
VOUTA
DAC D Output Voltage
DAC C Output Voltage
DAC B Output Voltage
DAC A Output Voltage
2
Positive Power Supply, 5V (2 pins). Connect both pins to the supply voltage. Bypass each pin to
the system analog ground with a 0.1µF to 1µF capacitor.
9, 37
3, 31
V
DD
10
11
4
5
REFAB
Reference Voltage Input for DAC A and DAC B. Bypass to AGNDAB with a 0.1µF to 1µF capacitor.
Analog Ground for DAC A and DAC B
AGNDAB
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
A and B to the respective DAC latches.
–———–
LDAB
12
13
6
7
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
C and D to the respective DAC latches.
–———–
LDCD
–—–
CS
14
15
8
9
Chip Select (active low)
–—–
–—–
–—–
WR
Write Input (active low). WR, along with CS, loads data into the DAC input latch selected by A0–A2.
6
_______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
_________________________________________________P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
FLAT
PACK
PLCC
16
17
10
11
A2
A1
Address Bit 2
Address Bit 1
Address Bit 0
Data Bits 12–0
18
12
A0
19–31
13–25
D12–D0
–———–
LDEF
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
E and F to the respective DAC latches.
32
33
26
27
–———–
LDGH
Load Input (active low). Driving this asynchronous input low transfers the contents of input latches
G and H to the respective DAC latches.
34
35
36
38
39
40
41
43
44
28
29
30
32
33
34
35
37
38
GND
AGNDGH
REFGH
VOUTH
VOUTG
VOUTF
VOUTE
REFEF
Digital Ground
Analog Ground for DAC G and DAC H
Reference Voltage Input for DAC G and DAC H. Bypass to AGNDGH with a 0.1µF to 1µF capacitor.
DAC H Output Voltage
DAC G Output Voltage
DAC F Output Voltage
DAC E Output Voltage
Reference Voltage Input for DAC E and DAC F. Bypass to AGNDEF with a 0.1µF to 1µF capaci-
Analog Ground for DAC E and DAC F
AGNDEF
_______________De t a ile d De s c rip t io n
An a lo g S e c t io n
The MAX547 c onta ins e ig ht 13-b it, volta g e -outp ut
DACs. These DACs are “inverted” R-2R ladder net-
works that convert 13-bit digital inputs into equivalent
analog output voltages, in proportion to the applied ref-
erence voltages. The MAX547 has one reference input
(REF_) and one analog-ground input (AGND_) for each
pair of DACs. The four REF_ inputs allow different full-
scale output voltages for each DAC pair, and the four
AGND_ inputs allow different offset voltages for each
DAC pair.
R
R
OUT
R
R
R
V
DAC
2R 2R
D0
2R
D10
2R
D11
2R
D12
REF
–
The DAC ladder outputs are buffered with op amps that
operate with a gain of two. The inverting node of the
a mp lifie r is c onne c te d to the re s p e c tive re fe re nc e
input, resulting in bipolar output voltages from -REF_ to
4095/4096 REF_. Figure 1 shows the simplified DAC
circuit.
AGND
–
Figure 1. DAC Simplified Circuit Diagram
_______________________________________________________________________________________
7
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
Reference and Analog-Ground Inputs
Table 1. MAX547 DAC Addressing
The REF_ inputs can range between AGND_ and VDD
.
A2
A1
A0
FUNCTION
However, the DAC outputs will operate to VDD - 0.6V
and VSS + 0.6V, due to the output amplifiers’ voltage-
swing limitations. The AGND_ inputs can be offset by
any voltage within the supply rails. The offset-voltage
potential must be lower than the reference-voltage
potential. For more information, refer to the Digital Code
and Analog Output Voltage section in the Applications
Information.
0
0
0
DAC A input latch
0
0
1
DAC B input latch
DAC C input latch
DAC D input latch
DAC E input latch
DAC F input latch
DAC G input latch
DAC H input latch
0
1
0
0
1
1
MAX547
1
0
0
1
0
1
The input impedance of the REF_ inputs is code depen-
dent. It is at its lowest value (5kΩ min) when the input
code of the referring DAC pair is 0 1010 1010 1010
(0AAAhex). Its maximum value, typically 50kΩ, occurs
when the code is 0000hex. When all reference inputs are
driven from the same source, the minimum load imped-
ance is 1.25kΩ. Since the input impedance at REF_ is
code dependent, load regulation of the reference used is
imp orta nt. For more informa tion, s e e Re fe re nc e
Selection in the Applications Information section.
1
1
0
1
1
1
TO INPUT LATCH OF DAC H
TO INPUT LATCH OF DAC G
TO INPUT LATCH OF DAC F
TO INPUT LATCH OF DAC E
TO INPUT LATCH OF DAC D
TO INPUT LATCH OF DAC C
TO INPUT LATCH OF DAC B
TO INPUT LATCH OF DAC A
A2
A1
A0
The input capacitance at REF_ is also code dependent,
and typically varies from 125pF to 300pF. Its minimum
value occurs when the code of the referring DAC pair is
set to all 0s. It is at its maximum value with all 1s on both
DACs.
Output Buffer Amplifiers
The MAX547’s voltage outputs are internally buffered
by precision gain-of-two amplifiers with a typical slew
rate of 3V/µs. With a full-scale transition at its output,
the typical settling time to ±1⁄2LSB is 5µs when loaded
with 10kΩ in parallel with 50pF, or 6µs when loaded
with 10kΩ in parallel with 100pF.
CS
WR
LDGH
TO DAC LATCHES OF DAC G AND DAC H
TO DAC LATCHES OF DAC E AND DAC G
TO DAC LATCHES OF DAC C AND DAC D
LDEF
LDCD
LDAB
CLR
Dig it a l In p u t s a n d In t e rfa c e Lo g ic
TO DAC LATCHES OF DAC C AND DAC B
TO ALL INPUT AND DAC LATCHES
All digital inputs are compatible with both TTL and
CMOS logic. The MAX547 interfaces with microproces-
sors using a data bus at least 13 bits wide. The inter-
face is double buffered, allowing simultaneous update
of all DACs. There are two latches for each DAC (see
Functional Diagram): an input latch that receives data
from the data bus, and a DAC latch that receives data
from the input latch. Address lines A0, A1, and A2
select which DAC’s input latch receives data from the
data bus, as shown in Table 1. Transfer data from the
input latches to the DAC latches by asserting the asyn-
c hronous LD_ s ig na l. Ea c h DAC’s a na log outp ut
reflects the data held in its DAC latch. All control inputs
are level triggered.
Figure 2. Input Control Logic
the DAC latch is transparent when LD_ is low. The
address lines (A0, A1, A2) must be valid throughout the
time CS and WR are low (Figure 3). Otherwise, the data
can be inadvertently written to the wrong DAC. Data is
latched within the input latch when either CS or WR is
high. Taking LD_ high latches data into the DAC latches.
If LD_ is brought low when WR and CS are low, it must
be held low for t3 or longer after WR and CS are high
(Figure 3).
Data can be latched or transferred directly to the DAC.
CS and WR control the input latch and LD_ transfers
information from the input latch to the DAC latch. The
input latch is transparent when CS and WR are low, and
Pulling the asynchronous CLR input low sets all DAC
outputs to a nominal 0V, regardless of the state of CS,
WR, and LD_. Taking CLR high latches 1000hex into
all input latches and DAC latches.
8
_______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
__________Ap p lic a t io n s In fo rm a t io n
Table 2. Interface Truth Table
–——– –——– –—–
–—–
CS
CLR LD
WR
FUNCTION
Mu lt ip lyin g Op e ra t io n
–
1
1
1
1
1
1
1
0
1
1
0
0
Both latches transparent
Both latches latched
Both latches latched
Input latch transparent
Input latch latched
The MAX547 can be used for multiplying applications.
Its reference accepts both DC and AC signals. The volt-
age at each REF_ input sets the full-scale output voltage
for its respective DACs. Since the reference inputs
accept only positive voltages, multiplying operation is
limited to two quadrants. Do not bypass the reference
inputs when applying AC signals to them. Refer to the
graphs in the Typical Operating Characteristics for
dynamic performance of the DACs and output buffers.
1
X
1
X
0
X
X
X
0
0
1
X
1
X
X
Input latch latched
X
DAC latch transparent
All input and DAC latches at
Dig it a l Co d e a n d An a lo g Ou t p u t Vo lt a g e
0
X
X
X
1000hex, outputs at AGND
–
The MAX547 uses offset binary coding. A 13-bit twos-
complement code can be converted to a 13-bit offset
binary code by adding 212 = 4096.
Bipolar Output Voltage Range (AGND_ = 0V)
For symmetrical bipolar operation, tie AGND_ to the
system ground. Table 3 shows the relationship between
digital code and output voltage. The following para -
graphs give a detailed explanation of this mode.
t
1
CS
t
5
t
6
The DAC ladder output voltage (VDAC) is multiplied by
2 and level shifted by the reference voltage, which is
internally connected to the output amplifiers (Figure 1).
Since the feedback resistors are the same size, the
amplifier’s output voltage is 2 times the voltage at its
noninverting input, minus the reference voltage.
t
2
WR
t
9
t
10
VOUT = 2(V
) − REF
–
DAC
A0–A2
where VDAC is the voltage at the amplifier’s noninvert-
ing input (DAC ladder output voltage), and REF_ is the
voltage applied to the reference input of the DAC.
t
7
t
8
With AGND_ connected to the system ground, the DAC
ladder output voltage is:
D0–D12
D
n
D
V
=
(REF ) =
(REF )
–
DAC
–
13
t
3
2
2
t
3
where D is the numeric value of the DAC’s binary input
code and n is the DAC’s resolution (13 bits). Replace
VDAC in the equation and calculate the output voltage.
LD
–
D
NOTES:
1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF
+5V. t = t = 5ns.
VOUT_ = 2
REF − REF
– –
(
)
13
2
r
f
D
D
= REF
–1 = REF
–1
2. MEASUREMENT REFERENCE LEVEL IS
(V + V )/2.
INH INL
–
–
12
4096
2
3. IF LD IS ACTIVATED WHILE WR IS LOW THEN LD MUST STAY LOW
D ranges from 0 (20) to 8191 (213 - 1).
–
–
FOR t OR LONGER AFTER WR GOES HIGH.
3
1
1LSB = REF
–
4096
Figure 3. Write-Cycle Timing
_______________________________________________________________________________________
9
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
Table 4. MAX547 Positive Unipolar Code Table
Table 3. MAX547 Bipolar Code Table
_
REF
2
(AGND_ =
)
(AGND_ = 0V)
INPUT
OUTPUT
INPUT
OUTPUT
4095
8191
1 1111 1111 1111
+REF_ ———
1 1111 1111 1111
+REF_ ———
(
)
)
(
)
4096
8192
1 0000 0000 0000
0 0000 0000 0000
+REF /2
–
1
1 0000 0000 0001
1 0000 0000 0000
0 1111 1111 1111
+REF_ ———
MAX547
(
4096
0V
0V
Customizing the Output Voltage Range
The AGND_ inputs can be offset by any voltage within the
supply rails if the voltage at the referring REF_ input is
higher than the voltage at the AGND_ input. Select the
reference voltage and the voltage at AGND_ so the
resulting output voltages do not come within ±0.6V of the
supply rails. Figure 4’s circuit shows one way to add posi-
tive offset to AGND_; make sure that the op amp used
has sufficient current-sink capability to take up the
remaining AGND_ current:
1
-REF_ ———
(
)
4096
4095
0 0000 0000 0001
0 0000 0000 0000
-REF_ ———
(
)
4096
-REF_
+5V
1µF
1µF
REF_ − AGND_
I
AGND_ =
V
DD
V
DD
5kΩ
REFAB
Another way is to digitally offset AGND_ by connecting
the output of one DAC to one or more AGND_ inputs. Do
not connect a DAC output to its own AGND_ input.
1µF
VOUTA
VOUTB
R1
R2
DAC A
DAC B
Table 5 summarizes the relationship between the refer-
ence and AGND_ potentials and the output voltage in
the different modes of operation.
AGNDAB
REF
P o w e r-S u p p ly S e q u e n c in g
The sequence in which the supply voltages come up is
not critical. However, we recommend that on power-up,
VSS comes up first, VDD next, followed by the reference
voltages. If you use other sequences, limit the current
into any reference pin to 10mA. Also, make sure that
VSS is never more than 300mV above ground. If there is
a ris k tha t this c a n oc c ur a t p owe r-up , c onne c t a
Schottky diode between VSS and GND, as shown in
Figure 5. We recommend that you not power up the
logic input pins before establishing the supply volt-
ages. If this is not possible and the digital lines can
drive more than 10mA, you should place current-limit-
ing resistors (e.g., 470Ω) in series with the logic pins.
MAX547
V
V
SS
SS
1µF
1µF
-5V
DIGITAL INPUTS NOT SHOWN.
NOT ALL DACS SHOWN.
Figure 4. Offsetting AGND
–
Positive Unipolar Output Voltage Range
(AGND_ = REF_/2)
For positive unipolar output operation, set AGND_ to
(REF_/2). For example, if you use Figure 4’s circuit with,
a 4.096V reference and offset AGND_ by 2.048V with
matched resistors (R1 = R2) and an op amp, it results in
a 0V to 4.0955V (nomina l) unip ola r outp ut volta g e ,
where 1LSB = 500µV. In general, the maximum current
flowing out of any AGND_ pin is given by:
Re fe re n c e S e le c t io n
If you want a ±2.5V full-scale output voltage swing, you
can use the MAX873 reference. It operates from a sin-
gle 5V supply and is specified to drive up to 10mA.
Therefore, it can drive all four reference inputs simulta-
neously. Because the maximum load impedance can
vary from 1.25kΩ to 12.5kΩ (four reference inputs in
parallel), the reference load current ranges from 2mA to
0.2mA (1.8mA maximum load step). The MAX873’s
REF_ − AGND_
I
AGND_ =
5kΩ
10 ______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
Table 5. Reference, AGND and Output Relationships
–
POSITIVE UNIPOLAR
OPERATION
(AGND_ = REF_/2)
BIPOLAR OPERATION
(AGND_ = 0V)
PARAMETER
CUSTOM OPERATION
Bipolar Zero Level, or
Unipolar Mid-scale,
(Code = 1000000000000)
_
REF
2
———
AGND_ (=0V)
AGND
AGND
–
=
–
(
)
Differential Reference Voltage
REF
–
REF /2
–
REF - AGND
–
–
(V
)
DR
Negative Full-scale Output
(Code = All 0s)
-REF
–
0V
AGND - V
DR
–
Positive Full-Scale Output
(Code = All 1s)
4095
8191
4095
———
——— REF_
——— REF_
V
DR
AGND _ +
(
4096 ) (
)
(
8192 ) (
)
( 4096 ) ( )
_
_
REF
REF
8192
VDR
———
———
———
LSB Weight
(
)
4096
4096
VOUT as a Function of
–
Digital Code (D, 0 to 8191)
D
D
D
——— - 1 REF_
——— REF_
—--—- - 1
(
V
DR
AGND _ +
(
) (
)
(
8192 ) (
)
) ( )
4096
4096
load regulation is specified to 20ppm/mA max over
temperature, resulting in a maximum error of 36ppm
(90µV). This corresponds to a maximum error caused
b y re fe re nc e loa d re g ula tion of only 0.147LSB
[0.147LSB = 90µV/(5V/8192)LSB] over temperature.
V
SS
V
SS
If you want a ±4.096V full-scale output swing (1LSB =
1mV), you can use the calibrated, low-drift, low-dropout
MAX676. Operating from a 5V supply, it is fully speci-
fied to drive two REF_ inputs with less than 60.4µV error
(0.0604LSB) over temperature, caused by the maxi-
mum load step.
MAX547
GND
1N5817
Re fe re n c e Bu ffe rin g
Another way to obtain high accuracy is to buffer a refer-
ence with an op amp. When driving all reference inputs
simultaneously, keep the closed-loop output imped-
ance of the op amp below 0.03Ω to ensure an error of
le s s tha n 0.1LSB. The op a mp mus t a ls o d rive the
capacitive load (typically 500pF to 1200pF).
SYSTEM GND
Figure 5. Optional Schottky Diode between V and GND
SS
Each reference input can also be buffered separately
by using the circuit in Figure 6. A reference load step
caused by a digital transition only affects the DAC pair
where the code transition occurs. It also allows the use
of re fe re nc e s with little d rive c a p a b ility. Ke e p the
closed-loop output impedance of each op amp below
0.12Ω, to ensure an error of less than 0.1LSB. Figure 6
shows the op amp’s inverting input directly connected
to the MAX547’s reference terminal. This eliminates the
influence of board lead resistance by sensing the volt-
age with a low-current path sense line directly at the
reference input.
Ad d ing fe e d b a c k re s is tors to ind ivid ua l re fe re nc e
buffer amplifiers enables different reference voltages to
be generated from a single reference.
______________________________________________________________________________________ 11
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
_Ord e rin g In fo rm a t io n (c o n t in u e d )
INL
(LSBs)
PART
TEMP. RANGE
PIN-PACKAGE
REFAB
REFCD
MAX547AEQH -40°C to +85°C 44 PLCC
MAX547BEQH -40°C to +85°C 44 PLCC
MAX547AEMH -40°C to +85°C 44 Plastic FP
MAX547BEMH -40°C to +85°C 44 Plastic FP
±2
±4
±2
±4
MAX547
MAX547
REFEF
+
-
REFGH
MAX494
Figure 6. Reference Buffering
P o w e r-S u p p ly Byp a s s in g a n d
Gro u n d Ma n a g e m e n t
For optimum performance, use a multilayer PC board
with an unbroken analog ground. For normal opera -
tion, when all AGND_ pins are at the same potential,
connect the four AGND_ pins directly to the ground
plane or connect them together in a “star” configura-
tion. The center of this star point is a good location to
connect the digital system ground with the analog
ground.
If you are using a single common reference voltage,
you can connect the reference inputs together using a
“star” configuration. If you are using DC reference volt-
ages, bypass each reference input with a 0.1µF to 1µF
capacitor to AGND_.
12 ______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
_________________________________________________________Fu n c t io n a l Dia g ra m
V
DD
REFAB REFCD REFEF REFGH
9, 37
10
3
43
36
8
VOUTA
INPUT
LATCH A
DAC
LATCH A
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
11
AGNDAB
7
VOUTB
INPUT
LATCH B
DAC
LATCH B
6
2
VOUTC
INPUT
LATCH C
DAC
LATCH C
AGNDCD
5
VOUTD
INPUT
LATCH D
DAC
LATCH D
D12–D0
DATA BUS
41
44
VOUTE
INPUT
LATCH E
DAC
LATCH E
AGNDEF
40
VOUTF
INPUT
LATCH F
DAC
LATCH F
39
35
VOUTG
INPUT
LATCH G
DAC
LATCH G
AGNDGH
38
VOUTH
INPUT
LATCH H
DAC
LATCH H
14
15
CS
WR
CONTROL
LOGIC
MAX547
34
4, 42
16, 18
A0–A2
12, 13
32, 33
1
V
SS
GND
LDAB
LDCD
LDEF
LDGH
CLR
Pin numbers shown for PLCC package.
______________________________________________________________________________________ 13
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
____________________________________________________________Ch ip To p o g ra p h y
VOUTB
VOUTA
VOUTG
VOUTH
MAX547
V
DD
V
DD
REFGH
REFAB
AGNDAB
AGNDGH
0. 242"
(6. 147mm)
GND
LDAB
LDCD
CS
LDGH
LDEF
D0
WR
A2
D1
D2
A1
0. 199"
(5. 055mm)
TRANSISTOR COUNT: 8987
SUBSTRATE CONNECTED TO V
DD
14 ______________________________________________________________________________________
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
________________________________________________________P a c k a g e In fo rm a t io n
INCHES
MILLIMETERS
DIM
MIN
0.165
MAX
0.180
0.110
0.156
–
MIN
4.19
2.54
3.68
0.51
0.33
0.66
0.23
17.40
16.51
14.99
MAX
4.57
2.79
3.96
–
A2
A
A1 0.100
A2 0.145
A3 0.020
C
B
0.013
0.021
0.032
0.011
0.695
0.655
0.630
0.53
0.81
0.28
17.65
16.64
16.00
B1 0.026
e
C
D
0.009
0.685
D1 0.650
D2 0.590
D1
D
D2
B1
D3
e
0.500 REF
0.050 REF
12.70 REF
B
1.27 REF
21-350A
A3
D3
D1
D
44-PIN PLASTIC
LEADED CHIP
CARRIER
A1
A
PACKAGE
______________________________________________________________________________________ 15
Oc t a l, 1 3 -Bit Vo lt a g e -Ou t p u t
DAC w it h P a ra lle l In t e rfa c e
MAX547
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1995 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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