MAX5490VB10000+ [MAXIM]
Array/Network Resistor, Divider, 0.5714W, 35ppm/Cel, Surface Mount, SOT-23, ROHS COMPLIANT;
| 型号： | MAX5490VB10000+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Array/Network Resistor, Divider, 0.5714W, 35ppm/Cel, Surface Mount, SOT-23, ROHS COMPLIANT 电阻器 |
| 文件： | 总16页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1206; Rev 0; 3/97
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
♦ +2.5V to +5.5V Single-Supply Operation
♦ ±1LSB (max) TUE
The MAX548A/MAX549A/MAX550A serial, 8-bit voltage-
output digital-to-analog converters (DACs) operate from
a single +2.5V to +5.5V supply. Their ±1LSB TUE spec-
ification is guaranteed over temperature. Operating cur-
rent (supply current plus reference current) is typically
♦ Power-On Reset Clears All Registers to Zero
♦ Low Operating Current:
75µA per DAC with V
= 2.5V. In shutdown, the DAC
DD
is disconnected from the reference, reducing current
drain to less than 1µA. The MAX548A/MAX549A allow
each DAC to be shut down independently.
150µA (MAX548A/MAX549A, V
= +2.5V)
REF
75µA (MAX550A, V
= +2.5V)
REF
♦ 1µA Shutdown Mode
The 10MHz, 3-wire serial interface is compatible with
SPI™/QSPI™ a nd Mic rowire ™ inte rfa c e s ta nd a rd s .
Double-buffered inputs provide flexibility when updat-
ing the DACs; the input and DAC registers can be
updated individually or simultaneously.
♦ 10MHz, 3-Wire Serial Interface Compatible with
SPI/QSPI and Microwire
♦ µMAX Package—50% Smaller than 8-Pin SO
♦ Independent Shutdown of DACs
The MAX548A is a dual DAC with an asynchronous
(MAX548A/MAX549A)
load input; it uses V
as the reference input. The
DD
MAX549A is a dual DAC with an external reference
input. The MAX550A is a single DAC with an external
reference input and an asynchronous load input.
The MAX548A/MAX549A/MAX550A’s low power con-
sumption and small µMAX and DIP packages make
these devices ideal for portable and battery-powered
applications.
______________Ord e rin g In fo rm a t io n
†
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 Plastic DIP
8 µMAX
MAX548ACPA
MAX548ACUA
MAX548AC/D
MAX548AEPA
MAX548AEUA
________________________Ap p lic a t io n s
Battery-Powered Systems
Dice*
8 Plastic DIP
8 µMAX
VCXO Control
Comparator-Level Settings
Ordering Information continued at end of data sheet.
*Dice are specified at T = +25°C, DC parameters only.
GaAs Amp Bias Control
A
†
Contact factory for availability of 8-pin SO package.
Digital Gain and Offset Control
_________________P in Co n fig u ra t io n s
_____________________S e le c t o r Gu id e
FEATURE
MAX548A
MAX549A
MAX550A
TOP VIEW
Number of DACs
DAC Reference
2
2
1
GND
OUTA
CS
1
2
3
4
8
7
6
5
V
DD
V
DD
External
External
OUTB
LDAC
SCLK
Asynchronous
Load DAC Input
√
√
—
√
√
MAX548A
µMAX Package
√
DIN
DIP/µMAX
SPI and QSPI are trademarks of Motorola Inc.
Microwire is a trademark of National Semiconductor Corp.
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Ranges
V
DD
, SCLK, DIN, CS, LDAC, OUT_ to GND ...............-0.3V to 6V
MAX5_ _AC_ A.....................................................0°C to +70°C
MAX5_ _AE_ A..................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
REF to GND................................................-0.3V to (V + 0.3V)
Maximum Current (any pin) .............................................±50mA
DD
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 9.09mW/°C above +70°C) .............727mW
µMAX (derate 4.10mW/°C above +70°C) .....................330mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2.5V to +5.5V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
8
Bits
MAX5_ _AEUA (Note 1)
±0.9
±0.9
±1
Guaranteed
monotonic
Differential Nonlinearity
Total Unadjusted Error
DNL
LSB
All others
MAX5_ _AEUA (Note 1)
All others
TUE
LSB
±1
Zero-Code Error
Full-Scale Error
ZCE
FSE
±1
LSB
LSB
±1
REFERENCE INPUT
Reference Input
Voltage Range
MAX549A/MAX550A for specified
performance
V
REF
2.5
V
DD
V
849/MX50A
MAX549A
MAX550A
16.7
33.3
330
150
165
75
Reference Input Resistance
DAC Code = 55 Hex (Note 2)
R
kΩ
REF
V
= V
= 5.5V
= 2.5V
= 5.5V
= 2.5V
550
250
275
125
DD
REF
MAX549A
MAX550A
V
DD
= V
REF
Reference Input Current
DAC Code = 55 Hex (Note 3)
I
µA
REF
V
DD
= V
REF
V
DD
= V
REF
DAC OUTPUT
MAX548A
0
0
V
DD
DAC Output Voltage Swing
DAC Output Resistance
V
kΩ
%
MAX549A/MAX550A
V
REF
R
33.3
±0.2
OUT
DAC Output Resistance
Matching
∆R
/
OUT
MAX548A/MAX549A
R
OUT
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
V
0.7V
V
V
IH
DD
V
IL
0.3V
DD
I
IN
V
IN
= 0V or V
DD
±1
10
µA
pF
Input Capacitance (Note 4)
C
IN
2
_______________________________________________________________________________________
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.5V to +5.5V, T = T
to T , unless otherwise noted. Typical values are at T = +25°C)
MAX A
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Digital Feedthrough and
Crosstalk
50
nV-sec
µs
CS = high, all digital inputs from 0V to V
DD
Voltage-Output Settling Time
To ±1/2LSB, C = 20pF
4
L
V
= 2.5V
= 5.5V
1.4
3.1
4
DD
Voltage-Output Slew Rate
C
C
= 20pF
= 20pF
V/µs
µs
L
L
V
DD
Wake-Up Time at Power-Up
POWER SUPPLIES
Supply Voltage Range
V
DD
Outputs unloaded, all inputs = GND or V
2.5
5.5
V
DD
Outputs unloaded,
all inputs = GND or
V
= 5.5V
= 2.5V
330
150
550
DD
Supply Current (MAX548A)
I
µA
DD
V
DD
250
10
V
DD
(Note 5)
Supply Current
(MAX549A/MAX550A)
Outputs unloaded, all inputs = GND or V
;
DD
I
DD
0.3
0.3
µA
µA
V
DD
= 5.5V
Shutdown Current
Shutdown mode
TIMING CHARACTERISTICS
(V = +2.5V to +5.5V, T = T
to T , unless otherwise noted. Digital inputs switching from 0V to V .) (Figure 3) (Note 4)
MAX DD
DD
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
40
40
30
0
TYP
MAX
UNITS
ns
SCLK Pulse Width High
SCLK Pulse Width Low
t
CH
t
ns
CL
DIN to SCLK High Setup
t
DS
ns
V
= 2.5V
= 5.5V
DD
DIN to SCLK High Hold
t
ns
DH
V
DD
10
30
30
10
10
20
40
80
50
50
5
t
t
ns
ns
ns
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold
CSS0
CSS1
CSH0
t
t
V
DD
= 2.5V
= 5.5V
ns
Delay, SCLK High to CS High
CSH1
V
DD
t
ns
ns
ns
ns
µs
CS Pulse Width High
SCLK Period
CSW
t
CP
t
MAX548A/MAX550A only
MAX548A/MAX550A only
LDAC Pulse Width Low
CS High to LDAC Low
LDAC
t
CSLD
V
DD
High to CS Low
Note 1: Cold temperature specifications (to -40°C) guaranteed by design using six sigma design limits.
Note 2: Worst-case input resistance at REF occurs at DAC code 55 hex.
Note 3: Worst-case reference input current occurs at DAC code 55 hex.
Note 4: Guaranteed by design. Not production tested.
Note 5: I measured with DACs loaded with worst-case DAC code 55 hex.
DD
_______________________________________________________________________________________
3
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V = V
= 2.5V, R = 1MΩ, C = 15pF, T = +25°C, unless otherwise noted.)
L L A
DD
REF
OPERATING CURRENT PER DAC
vs. TEMPERATURE
SHUTDOWN CURRENT
vs. TEMPERATURE
240
200
160
120
150.2
149.8
149.4
V
= V = 5.0V
DD REF
V
= V = 5.0V
DD REF
40
36
75.4
75.0
74.6
32
28
V
= V = 2.5V
DD REF
V
= V = 2.5V
DD REF
-60
-20
20
TEMPERATURE (°C)
60
100
-60
-20
20
60
100
TEMPERATURE (°C)
MAX549A/MAX550A
REFERENCE SMALL-SIGNAL
FREQUENCY RESPONSE
MAX549A/MAX550A
REFERENCE AC FEEDTHROUGH
vs. FREQUENCY
0
10
0
V
V
REF
= 2.5V
= 100mVp-p SINE WAVE
DD
-20
-40
-60
-80
-10
-20
-30
-40
849/MX50A
V
V
REF
= 5V
DD
= 2Vp-p SINE WAVE
V
REF
= 1Vp-p SINE WAVE
DAC CODE = 00 hex
DAC CODE = FF hex
10k 100k
FREQUENCY (Hz)
-50
-100
1k
1M
10M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
DIGITAL FEEDTHROUGH
SETTLING TIME (FALLING)
DAC CODE FF hex to 00 hex
SCLK, 5V/div
OUT, 1V/div
CS, 5V/div
OUT, 50mV/div
200ns/div
2µs/div
4
_______________________________________________________________________________________
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V = V
= 2.5V, R = 1MΩ, C = 15pF, T = +25°C, unless otherwise noted.)
L L A
DD
REF
SETTLING TIME (RISING)
OUTPUT GLITCH FILTERING
DAC CODE 00 hex to FF hex
CODE = 00 hex
OUT, 1V/div
CS, 5V/div
OUT, 50mV/div, C = 0pF
L
OUT, 50mV/div, C = 100pF
L
OUT, 50mV/div, C = 220pF
L
OUT, 50mV/div, C = 1000pF
L
CS, 5V/div
2µs/div
5µs/div
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
MAX548A
MAX549A
MAX550A
1
1
1
GND
OUTA
OUT
Ground
2
2
—
2
DAC A Output Voltage
DAC Output Voltage
—
—
Chip-Select Input. A logic low on CS enables serial data to be
clocked into the input shift register. Programming commands are
executed at CS’s rising edge.
3
3
3
CS
Serial-Data Input. Data is clocked into the 16-bit input shift register on
SCLK’s rising edge.
4
5
4
5
4
5
DIN
SCLK
Serial-Clock Input. Data is clocked in on SCLK’s rising edge.
Load DAC Input. After CS goes high and if programmed by the
control word, a falling edge on LDAC updates the DAC latch(es).
6
—
6
LDAC
Connect LDAC to V if unused.
DD
7
—
8
6
7
8
—
7
OUTB
REF
DAC B Output Voltage
External Reference Voltage Input for DAC(s)
Positive Power Supply (+2.5V to +5.5V)
8
V
DD
_______________________________________________________________________________________
5
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
The magnitude of the expected error is the ratio of the
DAC output resistance to the DC load resistance at the
_______________De t a ile d De s c rip t io n
An a lo g S e c t io n
The MAX548A/MAX549A/MAX550A are 8-bit, voltage-
outp ut d ig ita l-to-a na log c onve rte rs (DACs ). The
MAX548A/MAX549A are dual DACs, and the MAX550A
is a single DAC. Each DAC consists of an R-2R ladder
network that converts 8-bit digital inputs into equivalent
analog output voltages in proportion to the applied ref-
erence voltage (Figure 1).
output.
Typically, an energy pulse is coupled into the DAC out-
put on CS’s rising edge. Since each DAC output is
unbuffered, connecting a small capacitor (200pF to
1000pF) from the output to ground creates a lowpass
filter that effectively suppresses the pulse for sensitive
applications (see Typical Operating Characteristics).
Shutdown Mode
When the MAX548A/MAX549A/MAX550A are in shut-
down mode, the R-2R ladder disconnects from the refer-
ence source. The MAX549A/MAX550A supply current
does not change, but the REF input current decreases to
less than 1µA. This allows the externally applied system
re fe re nc e to re ma in a c tive with minima l p owe r
c ons ump tion. The MAX548A s up p ly c urre nt a ls o
decreases to less than 1µA in shutdown mode. When the
MAX548A/MAX549A/MAX550A exit shutdown mode,
recovery time is equivalent to the DAC’s settling time.
The DACs fe a ture d oub le -b uffe re d inp uts a nd
unbuffered outputs. The MAX549A/MAX550A require
an external reference. The MAX548A’s reference inputs
are internally connected to V . The power-supply
DD
range is from +2.5V to +5.5V.
Reference Input
The voltage applied at REF (V for the MAX548A) sets
DD
the full-scale output for all the DACs and may range
from +2.5V to V . The REF input resistance is code
DD
dependent, with the lowest value occurring with code
01010101 (55 hex). To minimize INL errors, the refer-
ence voltage source should have less than 3Ω output
impedance.
S e ria l In t e rfa c e
The serial interface is SPI/QSPI and Microwire compati-
ble. An active-low chip select (CS) enables the input
shift register to receive data from the serial input (DIN).
Data is clocked into the shift register on the rising edge
of the serial-clock signal (SCLK). The clock frequency
can be as high as 10MHz.
DAC Output
The MAX548A/MAX549A/MAX550A contain DACs with
unbuffered outputs; each output connects directly to an
R-2R ladder. Typical output impedance is 33.3kΩ. This
c onfig ura tion minimize s p owe r c ons ump tion a nd
reduces offset errors. For highest accuracy, apply high
resistive loads (1MΩ and up). Lower resistive loads can
be driven, but output loading increases full-scale error.
849/MX50A
Transmit data MSB first in one 16-bit word or two 8-bit
bytes. The write cycle can be segmented to allow two
8-bit-wide transfers when CS remains low. After all 16
bits are clocked into the input shift register, a rising
R
R
R
R
R
R
R
2R
2R
2R
2R
2R
2R
2R
2R
2R
REF
OUT_
GND
GND
LSB
MSB
DAC_ REGISTER
NOTE: SWITCH POSITIONS SHOWN FOR DAC CODE FF HEX.
Figure 1. DAC Simplified Circuit Diagram
6
_______________________________________________________________________________________
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
Serial-Input Data Format and Control Codes
The control byte determines which input registers/DAC
registers are updated (Table 1). The DAC input regis-
ters are updated on the rising edge of CS. The DAC
registers can be updated on CS’s rising edge or on
LDAC’s falling edge after CS goes high. Bit C0 of the
control byte determines how the DAC registers are
updated for the MAX548A/MAX550A. The MAX549A
has no LDAC pin; the DAC registers are always up-
dated on CS’s rising edge (C0 in the control byte has
no effect).
edge on CS programs the DAC. The input registers can
be loaded independently or simultaneously without
updating the DAC registers. This allows both DAC reg-
isters to be updated simultaneously with different digital
values. The DAC outputs reflect the data stored in the
DAC registers. LDAC can be used to asynchronously
up d a te the DAC re g is te rs ind e p e nd e ntly of CS
(MAX548A/MAX550A). With C1 set high, setting C0 in
the c ontrol word forc e s the DAC re g is te r(s ) to b e
updated on LDAC’s falling edge, rather than CS’s rising
edge (Table 1).
Tables 2, 3, and 4 list the serial-input command format
for the MAX548A, MAX549A, and MAX550A, respec-
tively. The 16-bit input word consists of an 8-bit control
byte and an 8-bit data byte. The control byte is not
d e c od e d inte rna lly. Eve ry c ontrol b it p e rforms one
Initialization
The MAX548A/MAX549A/MAX550A have an internal
power-on reset. At power-up, all internal registers are
reset to zero; therefore, an initialization write sequence
is not necessary.
Table 1. Control-Byte/Input-Word Bit Definitions
BIT NAME
STATE
OPERATION
UB1*
UB2
UB3
C2
X
X
X
0
Unassigned Bit 1
Unassigned Bit 2
Unassigned Bit 3
Power-Up Mode
Power-Down Mode
C2
1
C1
0
DAC Register Load Operation Disabled
DAC Register Load Operation Enabled
DAC Register Updated on CS’s Rising Edge
DAC Register Updated on LDAC’s Falling Edge (MAX549A = Don’t Care)
Do Not Address DAC B (MAX550A = Don’t Care)
Address DAC B (MAX550A = Don’t Care)
Do Not Address DAC A
CONTROL BYTE
C1
1
C0
0
C0
1
A1
0
A1
1
A0
0
A0
1
Address DAC A
D7
—
—
—
—
—
—
—
—
DAC Data Bit 7 (MSB)
D6
DAC Data Bit 6
D5
DAC Data Bit 5
D4
DAC Data Bit 4
DATA
BYTE
D3
DAC Data Bit 3
D2
DAC Data Bit 2
D1
DAC Data Bit 1
D0**
DAC Data Bit 0 (LSB)
X = Don’t care *Clocked in first **Clocked in last
_______________________________________________________________________________________
7
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
function. Data is clocked in starting with unassigned bit
1 (UB1), followed by the remaining control bits and the
DAC data byte. The data byte’s LSB (D0) is the last bit
clocked into the input register (Figure 2).
• Loads 80 hex (128 decimal) into the DAC input regis-
ter (DAC A for the MAX548A/MAX549A)
• Updates the DAC register(s) on CS’s rising edge.
Table 6 shows how to calculate the output voltage
based on the input code. Figure 3 gives detailed timing
information.
Table 5 is an example of a 16-bit input word that per-
forms the following functions:
INSTRUCTION
EXECUTED
CS
LDAC
MAX548A/
MAX550A
ONLY
OPTIONAL
PAUSE
1
8
9
16
SCLK
DIN
UB3
UB1 UB2
C2 C1 C0 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 2. Serial-Interface Timing Diagram
849/MX50A
t
LDAC
LDAC
CS
t
CSLD
t
CSW
t
CSH0
t
CSS0
t
CSH1
t
CH
SCLK
DIN
t
CL
t
DS
t
CSS1
t
DH
Figure 3. Detailed Serial-Interface Timing Diagram
_______________________________________________________________________________________
8
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
Table 2. MAX548A Serial-Interface Programming Commands
CONTROL BYTE
DATA BYTE
Loaded Last
D7........D0
LDAC
COMMAND
(Commands executed on CS’s rising edge)
Loaded First
UB1 UB2
UB3 C2 C1 C0 A1 A0
Pin 6
UNASSIGNED COMMANDS
X
X
X
X
X
X
0
1
0
X
X
0
0
0
0
XXXXXXXX
XXXXXXXX
X
X
Unassigned command
Unassigned operation
X
COMMANDS LOADING INPUT REGISTER(S) ONLY
Load DAC A input register. DAC B input register
and both DAC registers unchanged.
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
X
X
X
0
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X
X
X
Load DAC B input register. DAC A input register
and both DAC registers unchanged.
Load both DAC input registers. Both DAC regis-
ters unchanged.
COMMANDS UPDATING DAC REGISTER(S)
Update both DAC registers with current contents
of their input registers. Both input registers
unchanged.
X
X
X
0
1
0
0
0
XXXXXXXX
X
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X
X
X
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
Load both DAC input registers and update both
DAC registers.
Update both DAC registers with current contents
of their input registers. Both input registers
unchanged.
X
X
X
0
1
1
0
0
XXXXXXXX
0
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
0
0
0
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
Load both DAC input registers and update both
DAC registers.
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
After CS’s rising edge and on LDAC’s falling
edge, update both DAC registers with current
contents of their input registers. Both input regis-
ters unchanged.
X
X
X
0
1
1
0
0
XXXXXXXX
1
Load DAC A input register. After CS’s rising edge
and on LDAC’s falling edge, update both DAC
registers.
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
1
1
1
Load DAC B input register. After CS’s rising edge
and on LDAC’s falling edge, update both DAC
registers.
Load both DAC input registers. After CS’s rising
edge and on LDAC’s falling edge, update both
DAC registers.
_______________________________________________________________________________________
9
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
Table 2. MAX548A Serial-Interface Programming Commands (continued)
COMMANDS FOR POWERING DOWN
CONTROL BYTE
DATA BYTE
Loaded Last
D7........D0
LDAC
COMMAND
(Commands executed on CS’s rising edge)
Loaded First
UB1 UB2
UB3 C2 C1 C0 A1 A0
Pin 6
COMMANDS POWERING DOWN AND LOADING INPUT REGISTER(S) ONLY
Load DAC A input register and power down DAC
A. DAC B registers unchanged.
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
X
X
X
0
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X
X
X
Load DAC B input register and power down DAC
B. DAC A registers unchanged.
Load both DAC input registers and power down
both DACs. Both DAC registers unchanged
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER(S)
Load DAC A input register, power down DAC A,
and update both DAC registers. DAC B input
register unchanged.
X
X
X
1
1
0
0
1
8-Bit DAC Data
X
Load DAC B input register, power down DAC B,
and update both DAC registers. DAC A input
register unchanged.
X
X
X
X
X
X
X
X
X
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
X
X
0
Load both DAC input registers, power down both
DACs, and update both DAC registers.
Load DAC A input register, power down
DAC A, and update both DAC registers. DAC B
input register unchanged.
849/MX50A
Load DAC B input register, power down
DAC B, and update both DAC registers. DAC A
input register unchanged.
X
X
X
X
X
X
1
1
1
1
1
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
0
0
Load both DAC input registers and power down
both DACs. Update both DAC registers.
COMMANDS POWERING DOWN AND UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
Load DAC A input register and power down DAC
A. While powered down, on LDAC’s falling edge,
update both DAC registers. DAC B input register
unchanged.
X
X
X
1
1
1
0
1
8-Bit DAC Data
1
Load DAC B input register and power down DAC
B. While powered down, on LDAC’s falling edge,
update both DAC registers. DAC A input register
unchanged.
X
X
X
X
X
X
1
1
1
1
1
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
1
1
Load both DAC input registers and power down
both DACs. While powered down, on LDAC’s
falling edge, update both DAC registers.
X = Don’t care
10 ______________________________________________________________________________________
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
Table 3. MAX549A Serial-Interface Programming Commands
CONTROL BYTE
DATA BYTE
Loaded Last
D7........D0
COMMAND
(Commands executed on CS’s rising edge)
Loaded First
UB1 UB2
UB3 C2 C1 C0 A1 A0
UNASSIGNED COMMAND
X
X
X
X
0
X
0
0
XXXXXXXX
Unassigned command
COMMANDS LOADING INPUT REGISTER(S) ONLY
X
X
X
X
X
X
0
0
0
0
X
X
0
1
1
0
8-Bit DAC Data
8-Bit DAC Data
Load DAC A input register. DAC registers unchanged.
Load DAC B input register. DAC registers unchanged.
Load both DAC input registers. DAC registers
unchanged.
X
X
X
0
0
X
1
1
8-Bit DAC Data
COMMANDS UPDATING DAC REGISTER(S)
Update both DAC registers with current contents of their
input registers. Both input registers unchanged.
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
1
1
1
X
X
X
X
0
0
1
1
0
1
0
1
XXXXXXXX
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Load DAC A input register and update both DAC
registers. DAC B input register unchanged.
Load DAC B input register and update both DAC
registers. DAC A input register unchanged.
0
Load both DAC input registers and update both DAC
registers.
0
COMMANDS POWERING DOWN AND LOADING INPUT REGISTER(S) ONLY
Load DAC A input register and power down DAC A.
DAC B input register and both DAC registers unchanged.
X
X
X
X
X
X
X
X
X
1
1
1
0
0
0
X
X
X
0
1
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
8-Bit DAC Data
Load DAC B input register and power down DAC B.
DAC A input register and both DAC registers unchanged.
Load both DAC input registers and power down both
DACs. Both DAC registers unchanged.
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER(S)
Load DAC A input register, power down DAC A, and
update both DAC registers. DAC B input register
unchanged.
X
X
X
1
1
X
0
1
8-Bit DAC Data
Load DAC B input register, power down DAC B, and
update both DAC registers. DAC A input register
unchanged.
X
X
X
X
X
X
1
1
1
1
X
X
1
1
0
1
8-Bit DAC Data
8-Bit DAC Data
Load both DAC input registers, power down both DACs,
and update both DAC registers.
X = Don’t care
______________________________________________________________________________________ 11
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
Table 4. MAX550A Serial-Interface Programming Commands
CONTROL BYTE
DATA BYTE
Loaded Last
D7........D0
LDAC
COMMAND
(Commands executed on CS’s rising edge)
Loaded First
UB1
UB2
UB3 C2 C1 C0 A1 A0
Pin 6
UNASSIGNED COMMANDS
X
X
X
X
X
X
0
1
0
X
X
X
X
0
0
XXXXXXXX
XXXXXXXX
X
X
Unassigned command
Unassigned operation
X
COMMANDS LOADING INPUT REGISTER ONLY
X
X
X
0
0
X
X
1
8-Bit DAC Data
X
Load DAC input register. DAC register unchanged.
COMMANDS LOADING DAC REGISTER
Update DAC register with current contents of
input register. Input register unchanged.
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
X
X
X
X
0
1
0
1
XXXXXXXX
8-Bit DAC Data
XXXXXXXX
X
X
0
Load DAC input register and update DAC register.
Update DAC register with current contents of
input register. Input register unchanged.
8-Bit DAC Data
0
Load DAC input register and update DAC register.
COMMANDS UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
After CS’s rising edge and on LDAC’s falling
edge, update DAC register with current contents
of input register. Input register unchanged.
X
X
X
0
1
1
X
0
XXXXXXXX
1
1
Load DAC input register. After CS’s rising edge
and on LDAC’s falling edge, update DAC register.
X
X
X
0
1
1
X
1
8-Bit DAC Data
COMMAND POWERING DOWN AND LOADING INPUT REGISTER ONLY
X
X
X
1
0
X
X
1
8-Bit DAC Data
X
Load DAC input register and power down DAC.
849/MX50A
COMMANDS POWERING DOWN AND UPDATING DAC REGISTER
Load DAC input register, power down DAC, and
update DAC register.
X
X
X
X
X
X
1
1
1
1
0
1
X
X
1
1
8-Bit DAC Data
8-Bit DAC Data
X
0
Load DAC input register, power down DAC, and
update DAC register.
COMMAND POWERING DOWN AND UTILIZING THE ASYNCHRONOUS LOAD FUNCTION
Load DAC input register and power down DAC.
While powered down, on LDAC’s falling edge,
update DAC register.
X
X
X
1
1
1
X
1
8-Bit DAC Data
1
X = Don’t care
Table 5. Example Input Word
CONTROL BYTE
DATA BYTE
Loaded Last
Loaded First
UB1
X
UB2
X
UB3
X
C2
0
C1
1
C0
0
A1
0
A0
1
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
X = Don’t care
12 ______________________________________________________________________________________
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
Microprocessor Interfacing
The MAX548A/MAX549A/MAX550A serial interface is
SPI/QSPI and Microwire compatible. For SPI/QSPI, clear
the CPOL and CPHA bits (CPOL = 0 and CPHA = 0).
CPOL = 0 sets the clock idle state to zero, and CPHA =
0 changes data at SCLK’s falling edge. This is the
Microwire default condition. If a serial port is not avail-
able on your microprocessor, three bits of a parallel port
can be used to emulate a serial port by bit manipulation.
Operate the serial clock only when necessary, to mini-
mize digital feedthrough at the DAC registers.
Careful PC board layout minimizes crosstalk in DAC regis-
ters, the reference, and the digital inputs. Separate analog
traces by running ground traces between them. Make sure
that high-frequency digital lines are not routed parallel to
analog lines.
AC Co n s id e ra t io n s
Digital Feedthrough
High-speed data at any of the digital input pins can
couple through a DAC’s internal stray package capaci-
tance and cause noise (digital feedthrough) at the DAC
output, even though LDAC and/or CS are held high
(see Typical Operating Characteristics). Test digital
feedthrough by holding LDAC and/or CS high and tog-
gling the digital inputs from all 1s to all 0s.
__________Ap p lic a t io n s In fo rm a t io n
P o w e r-S u p p ly
a n d Gro u n d Co n s id e ra t io n s
Connect GND to the highest quality ground available.
Analog Feedthrough
Due to internal stray capacitance, higher frequency analog
input signals at REF can couple to the output, even when
the input digital code is all 0s. This condition is shown in
the MAX549A/MAX550A Reference AC Feedthrough vs.
Frequency graph in the Typical Operating Characteristics.
Test analog feedthrough by setting all DAC outputs to 0V
and sweeping REF.
Bypass V
with a 0.1µF to 0.22µF capacitor to GND.
DD
The reference input can be used without bypassing.
However, for optimum line/load-transient response and
noise performance, bypass the reference input with a
0.1µF to 4.7µF capacitor to GND.
Table 6. Analog Output vs. Code
DAC CONTENTS
ANALOG OUTPUT (V)
D0
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
1
1
0
1
1
0
+V (255 / 256)
REF
1
0
0
0
0
0
0
+V (129 / 256)
REF
1
0
0
0
0
0
0
+V (128 / 256) = +V
/ 2
REF
REF
0
1
1
1
1
1
1
+V (127 / 256)
REF
0
0
0
0
0
0
0
+V (1 / 256)
REF
0
0
0
0
0
0
0
0
Note: 1LSB = V
x 2-8 = V (1 / 256); ANALOG OUTPUT = +V (I / 256), where I = Integer Value of Digital Input.
REF REF
REF
_____________________________________________P in Co n fig u ra t io n s (c o n t in u e d )
TOP VIEW
GND
OUTA
CS
1
2
3
4
8
7
6
5
V
GND
OUT
CS
1
2
3
4
8
7
6
5
V
DD
DD
REF
REF
MAX549A
MAX550A
OUTB
SCLK
LDAC
SCLK
DIN
DIN
DIP/µMAX
DIP/µMAX
______________________________________________________________________________________ 13
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
_________________________________________________________Fu n c t io n a l Dia g ra m
V
DD
8
8
8
DAC A
INPUT
REGISTER
OUTA
REF
DAC A
REGISTER
DAC A
R-2R LADDER
DIN
SCLK
CS
INPUT
SHIFT
V
DD
MAX549A/
MAX550A
ONLY
MAX548A
ONLY
REGISTER
AND
LDAC
8
8
8
DAC B
INPUT
REGISTER
OUTB
DAC B
REGISTER
DAC B
R-2R LADDER
MAX548A/
MAX550A
ONLY
CONTROL
MAX548A/
MAX549A
ONLY
MAX548A
MAX549A
MAX550A
GND
849/MX50A
___________________Ch ip In fo rm a t io n
_Ord e rin g In fo rm a t io n (c o n t in u e d )
PART
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 Plastic DIP
8 µMAX
TRANSISTOR COUNT: 1562
MAX549ACPA
MAX549ACUA
MAX549AC/D
MAX549AEPA
MAX549AEUA
MAX550ACPA
MAX550ACUA
MAX550AC/D
MAX550AEPA
MAX550AEUA
Dice*
8 Plastic DIP
8 µMAX
8 Plastic DIP
8 µMAX
Dice*
8 Plastic DIP
8 µMAX
*Dice are specified at T = +25°C, DC parameters only.
A
14 ______________________________________________________________________________________
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
849/MX50A
________________________________________________________P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 15
+2 .5 V t o +5 .5 V, Lo w -P o w e r, S in g le /Du a l,
8 -Bit Vo lt a g e -Ou t p u t DACs in µMAX P a c k a g e
___________________________________________P a c k a g e In fo rm a t io n (c o n t in u e d )
849/MX50A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 (4 0 8 ) 7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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