MAX551BEUB+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 0.08us Settling Time, PDSO10, UMAX-10;
| 型号： | MAX551BEUB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 0.08us Settling Time, PDSO10, UMAX-10 转换器 数模转换器 |
| 文件： | 总12页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1260; Rev 0; 10/97
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
1/MAX52
_______________Ge n e ra l De s c rip t io n
____________________________Fe a t u re s
The MAX551/MAX552 are 12-bit, current-output, 4-quad-
rant multiplying digital-to-analog converters (DACs).
These devices are capable of providing unipolar or
bipolar outputs when operating from either a single +5V
(MAX551) or +3V (MAX552) power supply. An internal
p owe r-on-re s e t c irc uit c le a rs a ll DAC re g is te rs on
power-up, setting the DAC output voltage to 0V.
♦ Single-Supply Operation:
+4.5V to +5.25V (MAX551)
+2.7V to +3.6V (MAX552)
♦ 12.5MHz 3-Wire Serial Interface
♦ SPI/QSPI and Microwire Compatible
♦ Power-On Reset Clears DAC Output to Zero
The SPI™/QSPI™ and Microwire™-compatible 3-wire
serial interface saves board space and reduces power
dissipation compared with parallel-interface devices.
The MAX551/MAX552 feature double-buffered interface
logic with a 12-bit input register and a 12-bit DAC regis-
ter. Data in the DAC register sets the DAC output volt-
age. Data is loaded into the input register via the serial
interface. The LOAD input transfers data from the input
register to the DAC register, updating the DAC output
voltage.
♦ Asynchronous Clear Input Clears DAC Output
to Zero
♦ Voltage Mode or Bipolar Mode Operation with
a Single Power Supply
♦ Schmitt-Trigger Digital Inputs for Direct
Optocoupler Interface
♦ 0.4µA Supply Current
♦ 10-Pin µMAX Package
The MAX551/MAX552 are available in an 8-pin DIP
package or a space-saving 10-pin µMAX package. The
µMAX package provides an asynchronous clear (CLR)
input that clears all DAC registers when pulled to GND,
setting the output voltage to 0V.
______________Ord e rin g In fo rm a t io n
PIN-
PACKAGE
LINEARITY
(LSB)
PART
TEMP. RANGE
________________________Ap p lic a t io n s
Automatic Calibration
MAX551ACPA
MAX551BCPA
MAX551ACUB
MAX551BCUB
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
10 µMAX
±1/2
±1
Gain Adjustment
±1/2
±1
Transducer Drivers
10 µMAX
Process-Control I/O Boards
Digitally Controlled Filters
MAX551AEPA -40°C to +85°C
MAX551BEPA -40°C to +85°C
MAX551AEUB -40°C to +85°C
MAX551BEUB -40°C to +85°C
8 Plastic DIP
8 Plastic DIP
10 µMAX
±1/2
±1
Motion-Controlled Systems
µP-Controlled Systems
±1/2
±1
10 µMAX
Ordering Information continued at end of data sheet.
Programmable Amplifiers/Attenuators
_________________P in Co n fig u ra t io n s
________________Fu n c t io n a l Dia g ra m
REF
R
FB
TOP VIEW
RFB
12-BIT
D/A CONVERTER
OUT
AGND*
OUT
GND
1
2
3
4
8
7
6
5
RFB OUT
1
2
3
4
5
10 RFB
V
DD
AGND
REF
9
8
7
6
REF
CLR*
LOAD
MAX551
MAX552
12-BIT
DAC REGISTER
POWER-ON
RESET
MAX551
MAX552
GND
CLR
SCLK
DIN
GND
V
DD
SCLK
V
DD
LOAD
DIN
MAX551
MAX552
SCLK
12-BIT
SHIFT REGISTER
LOAD
µMAX
DIP
DIN
*µMAX PACKAGE ONLY
SPI and QSPI are trademarks of Motorola Inc. Microwire is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND..............................................................................6V
Operating Temperature Ranges
REF, RFB to GND.................................................................±12V
Digital Inputs (SCLK, DIN, LOAD, CLR)
to GND.....................................................................-0.3V to 6V
MAX55_ _C_ _......................................................0°C to +70°C
MAX55_ _E_ _...................................................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10sec) .............................+300°C
OUT to GND ...............................................-0.3V to (V + 0.3V)
DD
AGND to GND ............................................-0.3V to (V + 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
Plastic DIP (derate 9.09mW/°C above +70°C) .............727mW
µMAX (derate 5.60mW/°C above +70°C) .....................444mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—MAX551
1/MAX52
(V
= +4.5V to +5.25V, V
= 5V, OUT = AGND = GND, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
REF
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
Bits
MAX551A
MAX551B
MAX551A
MAX551B
MAX551A
MAX551B
±1/2
±1
Integral Nonlinearity
Differential Nonlinearity
Gain Error
INL
LSB
±1/2
±1
Guaranteed monotonic over
temperature
DNL
LSB
LSB
±1
Using internal feedback
resistor (R
)
FB
±2
Gain Tempco
(∆Gain/∆Temp)
Using internal feedback resistor (R
(Note 2)
)
FB
±0.2
0.08
±1
2
ppm/°C
ppm/%
Power-Supply Rejection
PSR
∆V = +5%, -10%
DD
DYNAMIC PERFORMANCE (Note 3)
T
A
= +25°C, to 1/2LSB, OUT load is
Current Settling Time
t
100Ω||13pF, DAC register alternately loaded
1
µs
S
with 1s and 0s
V
= 0V, OUT load is 100Ω||13pF, DAC
REF
Digital-to-Analog Glitch
AC Feedthrough at OUT
0.65
0.3
-85
13
20
1
nV-s
mVp-p
dB
register alternately loaded with 1s and 0s
V
= 5Vp-p at 10kHz, DAC register loaded
REF
with all 0s
V
= 6V at 1kHz, DAC register loaded
RMS
REF
Total Harmonic Distortion
THD
with all 1s
10Hz to 100kHz, measured between RFB and
OUT
Output Noise-Voltage Density
15
nV/√Hz
2
_______________________________________________________________________________________
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
1/MAX52
ELECTRICAL CHARACTERISTICS—MAX551 (continued)
(V
= +4.5V to +5.25V, V
= 5V, OUT = AGND = GND, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
REF
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE INPUT
Input Resistance
R
Measured between REF and OUT
7
11
6.5
725
15
kΩ
ppm/°C
kHz
REF
Input Resistance Tempco
Reference -3dB Bandwidth
ANALOG OUTPUT
BW
V
= 0.31V , R = 50Ω, code = full-scale
p-p
OUT
L
T
= +25°C
±0.15
±5
±25
20
A
DAC register loaded
with all 0s
OUT Leakage Current
OUT Capacitance
nA
pF
T
A
= T to T
MIN MAX
Code = zero scale (Note 2)
Code = full scale (Note 2)
14
20
C
OUT
30
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.4
V
V
IH
V
IL
0.8
HYST
156
18
mV
LOAD, CLR, DIN, and SCLK, V = 5V
DD
V
= V
±1
100
±1
8
CLR
DD
CLR
Input Leakage Current
I
IN
V
CLR
= 0V
µA
pF
Inputs at 0V or V
SCLK, LOAD, DIN
DD
Input Capacitance
C
Inputs at 0V or V (Note 2)
DD
IN
SWITCHING CHARACTERISTICS
SCLK Pulse Width High
SCLK Pulse Width Low
DIN Data to SCLK Setup
DIN Data to SCLK Hold
LOAD Pulse Width
t
t
25
25
15
15
20
0
ns
ns
ns
ns
ns
ns
ns
ns
CH
t
CL
DS
DH
t
t
LD
t
LSB SCLK to LOAD
LOAD High to SCLK
CLR Pulse Width
SL
t
15
20
LC
t
CLR
POWER SUPPLY
Supply Voltage
V
4.50
5.25
1.5
5
V
DD
0.5
0.4
mA
µA
All digital inputs at V or V CLR = V
DD
IL
IH,
Supply Current
I
DD
All digital inputs at 0V or V
CLR = V
DD
DD,
_______________________________________________________________________________________
3
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
ELECTRICAL CHARACTERISTICS —MAX552
(V
= +2.7V to +3.6V, V
= 2.5V, OUT = AGND = GND, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
REF
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
Resolution
N
12
Bits
MAX552A
MAX552B
MAX552A
MAX552B
MAX552A
MAX552B
±1/2
±1
Integral Nonlinearity
Differential Nonlinearity
Gain Error
INL
LSB
±1/2
±1
Guaranteed monotonic over
temperature
DNL
LSB
LSB
±1
Using internal feedback
resistor (R
)
FB
±2
Gain Tempco
(∆Gain/∆Temp)
Using internal feedback resistor (R
(Note 2)
)
FB
±0.3
0.12
±1
1
ppm/°C
ppm/%
1/MAX52
Power-Supply Rejection
PSR
∆V = +20%, -10%
DD
DYNAMIC PERFORMANCE (Note 3)
T
A
= +25°C, to 1/2LSB, OUT load is
Current Settling Time
t
100Ω||13pF, DAC register alternately loaded
1
µs
S
with 1s and 0s
V
= 0V, OUT load is 100Ω||13pF, DAC
REF
Digital-to-Analog Glitch
AC Feedthrough at OUT
0.6
0.2
-85
13
20
nV-s
mVp-p
dB
register alternately loaded with 1s and 0s
V
= 3Vp-p at 10kHz, DAC register loaded
REF
0.6
with all 0s
V
= 6V at 1kHz, DAC register loaded
RMS
REF
Total Harmonic Distortion
THD
with all 1s
10Hz to 100kHz, measured between RFB and
OUT
Output Noise-Voltage Density
15
15
nV/√Hz
REFERENCE INPUT
Input Resistance
R
Measured between REF and OUT
7
11
7.5
725
kΩ
ppm/°C
kHz
REF
Input Resistance Tempco
Reference -3dB Bandwidth
ANALOG OUTPUT
BW
V
OUT
= 0.31V , R = 50Ω, code = full-scale
p-p
L
T
= +25°C
±0.13
±5
A
DAC register loaded
with all 0s
OUT Leakage Current
OUT Capacitance
nA
pF
T
A
= T
to T
MAX
±25
MIN
Code = zero code (Note 2)
Code = full scale (Note 2)
14
20
20
30
C
OUT
4
_______________________________________________________________________________________
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
1/MAX52
ELECTRICAL CHARACTERISTICS —MAX552 (continued)
(V
= +2.7V to +3.6V, V
= 2.5V, VOUT = AGND = GND, T = T
to T , unless otherwise noted. Typical values are at
MAX
DD
REF
A
MIN
T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Hysteresis
V
2.1
V
V
IH
V
IL
0.6
HYST
135
12
mV
LOAD, CLR, DIN, and SCLK, V = 3V
DD
V
= V
±1
75
±1
8
CLR
DD
CLR
Input Leakage Current
I
IN
V
CLR
= 0V
µA
pF
Inputs at 0V or V
SCLK, LOAD, DIN
DD
Input Capacitance
C
Inputs at 0V or V (Note 2)
DD
IN
SWITCHING CHARACTERISTICS
SCLK Pulse Width High
SCLK Pulse Width Low
DIN Data to SCLK Setup
DIN Data to SCLK Hold
LOAD Pulse Width
t
t
40
40
15
15
30
0
ns
ns
ns
ns
ns
ns
ns
ns
CH
t
CL
DS
DH
t
t
LD
t
LSB SCLK to LOAD
LOAD High to SCLK
CLR Pulse Width
SL
LC
t
15
30
t
CLR
POWER SUPPLY
Supply Voltage
V
2.7
3.6
0.5
5
V
DD
0.1
mA
µA
All digital inputs at V or V CLR = V
DD
IL
IH,
Supply Current
I
DD
0.07
All digital inputs at 0V or V
CLR = V
DD
DD,
Note 1: AGND and CLR are for µMAX only.
Note 2: Guaranteed by design. Not subject to production testing.
Note 3: Parametric limits are provided for design guidance, and are not production tested.
_______________________________________________________________________________________
5
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(T = +25°C, unless otherwise noted.)
A
MAX551
TOTAL HARMONIC DISTORTION
MAX551
INL vs. REFERENCE VOLTAGE
SUPPLY CURRENT
vs. LOGIC INPUT VOLTAGE
vs. FREQUENCY
1.0
0.8
0.6
0.4
0.2
0
0.5
0.4
0
V
DD
= 5.25V
OUTPUT AMPLIFIER = MAX4166
1st 5 HARMONICS
= 0.42Vp-p, R = 50Ω
L
INPUT CODE = ALL 1s
V
AT DIN, SCLK, & LOAD
IN
CLR = V
DD
0.3
-20
V
REF
0.2
0.1
-40
-60
V
DD
= 5.0V
0
-0.1
-0.2
-0.3
-0.4
-0.5
V
DD
= 3.3V
-80
1/MAX52
V
DD
= 2.7V
3
-100
0
1
2
4
5
4.7
4.8
4.9
5.0
5.1
5.2
5.3
0.001
0.01
0.1
1
LOGIC INPUT VOLTAGE, V (V)
IN
REFERENCE VOLTAGE (V)
FREQUENCY (MHz)
MAX552
MAX551
MAX552
INL vs. REFERENCE VOLTAGE
DNL vs. REFERENCE VOLTAGE
DNL vs. REFERENCE VOLTAGE
0.5
0.4
0.5
0.4
0.5
0.4
V
DD
= 3.6V
V
DD
= 5.25V
V
DD
= 3.6V
0.3
0.3
0.3
0.2
0.2
0.2
0.1
0.1
0.1
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
2.2
2.3
2.4
2.5
2.6
2.7
2.8
4.7
4.8
4.9
5.0
5.1
5.2
5.3
2.2
2.3
2.4
2.5
2.6
2.7
2.8
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
REFERENCE AC FEEDTHROUGH
vs. FREQUENCY
MULTIPLYING FREQUENCY RESPONSE
-50
3
2
1
0
MAX551 OR MAX552
MAX551 OR MAX552
V
REF
= 0.31Vp-p, R = 50Ω
L
V
REF
= 0.31Vp-p, R = 50Ω
L
INPUT CODE = ALL 1s
OUTPUT AMPLIFIER = MAX4166
-60
-70
INPUT CODE = ALL 0s
OUTPUT AMPLIFIER = MAX4166
-1
-2
-3
-4
-5
-6
-7
-80
-90
-100
0.01
0.1
1
0.01
0.1
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
6
_______________________________________________________________________________________
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
1/MAX52
______________________________________________________________P in De s c rip t io n
PIN
NAME
FUNCTION
DIP
1
µMAX
1
2
3
4
OUT
AGND
GND
DAC Current Output
Analog Ground
—
2
Digital Ground. Also Analog Ground for DIP package.
Supply Voltage
3
V
DD
Active-Low Load DAC Input. Driving this asynchronous input low transfers the contents
of the input register to the DAC register.
4
5
LOAD
5
6
6
7
DIN
SCLK
CLR
REF
Serial-Data Input
Serial-Clock Input. The serial input data is clocked in on SCLK’s rising edge.
—
7
8
Clear DAC Input. Clears the DAC register. Tie to V or float if not used.
DD
9
Reference Input
8
10
RFB
Feedback Resistor
R
R
R
R
V
REF
R *
FB
2R
2R
2R
2R
2R
2R
RFB
OUT
AGND
D11
(MSB)
D10
D9
D1
DO
(LSB)
R * = R
FB
Figure 1. MAX551/MAX552 Simplified Circuit
_______________________________________________________________________________________
7
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
DIN
BIT 11
MSB
BIT 0
LSB
BIT 10
BIT 1
t
DS
t
DH
1
2
11
t
CH
t
CL
SCLK
LOAD SERIAL DATA INTO INPUT REGISTER
t
LC
t
SL
t
LD
LOAD
CLR
1/MAX52
t
CLR
Figure 2. Write-Cycle Timing Diagram
internal feedback resistor (R ) to minimize gain varia-
FB
tion with temperature.
De t a ile d De s c rip t io n
The MAX551/MAX552 digital-to-analog converter (DAC)
circuits consist of a laser-trimmed, thin-film R-2R resis-
tor a rra y with NMOS c urre nt s witc he s (Fig ure 1).
Binary-weighted currents are switched to either OUT or
AGND, depending on the status of each input data bit.
Although the currents at OUT and AGND depend on
the digital input code, the sum of the two output cur-
rents is always equal to the input current at REF.
The internal feedback resistor (R ) is compensated
FB
with an NMOS switch that matches the NMOS switches
used in the R-2R array, resulting in excellent supply
rejection and gain-temperature coefficient.
The OUT p in outp ut c a p a c ita nc e (C
) is c od e
OUT
dependent. C
at FFFhex.
is typically 14pF at 000hex and 20pF
OUT
The output current (I
) can be converted into a volt-
OUT
S e ria l In t e rfa c e
age by adding an external output amplifier (Figure 3).
The REF input accepts a wide range of signals, includ-
ing fixed and time-varying voltage or current inputs. If a
current source is used at the reference input, use a
low-tempco, external feedback resistor in place of the
The MAX551/MAX552 serial interface is compatible
with the SPI/QSPI and Microwire serial-interface stan-
d a rd s . The s e d e vic e s a c c e p t s e ria l c loc ks up to
12.5MHz (50% duty cycle). If the SCLK input is not
Table 1. Unipolar Binary-Code Table
for Circuit of Figure 3
+5V (+3V)
V
REF
R1
100Ω
DIGITAL INPUT
REF
V
DD
ANALOG OUTPUT
R2
50Ω
MSB
LSB
DIN
RFB
4095
4096
1 1 1 1
1 1 1 1
0000
0 0 0 0
0 0 0 0
1 1 1 1
−V
REF
C1
15pF
MAX551
MAX552
2
3
OUT
SCLK
LOAD
2048
V
REF
2
1000
0 0 0 0
0 0 0 0
0000
0 0 0 1
0 0 0 0
−V
= −
6
REF
4096
V
OUT
GND
1
−V
REF
4096
AGND
( ) ARE FOR MAX552
0
Figure 3. Unipolar Operation
8
_______________________________________________________________________________________
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
1/MAX52
R4
20k
R2
50Ω
+5V (+3V)
R5
20k
C1
33pF
V
DD
RFB
R3
10k
OUT
V
REF
REF
MAX551
MAX552
AGND
R1
100Ω
GND
V
OUT
SCLK LOAD DIN
( ) ARE FOR MAX552
Figure 4. Bipolar Operation
Table 2. Offset Binary-Code Table
for Circuit of Figure 4
Un ip o la r Op e ra t io n
Figure 3 shows the MAX551/MAX552’s basic applica-
tion. This circuit is used for unipolar operation or 2-
quadrant multiplication. The code table for this mode is
given in Table 1. Note that the output’s polarity is the
opposite of the reference voltage polarity.
DIGITAL INPUT
ANALOG OUTPUT
MSB
LSB
2047
1 1 1 1
1 1 1 1
0000
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
In many applications the gain accuracy is sufficient and
gain adjustment is not necessary. In these cases, resis-
tors R1 and R2 in Figure 3 can be omitted. If the gain is
trimmed and the DAC is operated over a wide tempera-
ture range, use low-tempco (<300ppm/°C) resistors for
R1 and R2. Capacitor C1 provides phase compensa-
tion a nd re d uc e s ove rs hoot a nd ring ing whe n fa s t
amplifiers are used at the DAC’s output.
+V
REF
2048
1
1000
1 0 0 0
0 1 1 1
0 0 0 0
0001
0 0 0 0
1 1 1 1
0 0 0 0
+V
REF
2048
0
1
−V
REF
Bip o la r Op e ra t io n
Figure 4 shows the MAX551/MAX552 operating in bipo-
lar (or 4-quadrant multiplying) mode. Matched resistors
R3, R4, and R5 must be of the same material (prefer-
ably metal film or wire-wound) for good temperature-
tra c king c ha ra c te ris tic s (< 15p p m/°C) a nd s hould
match to 0.01% for 12-bit performance. The output
code is offset binary, as listed in Table 2.
2048
2048
2048
−V
REF
symmetrical, then the clock signal used must meet the
a nd t re q uire me nts g ive n in the Ele c tric a l
t
CH
CL
Characteristics.
To adjust the circuit, load the DAC with a code of 1000
0000 0000 and trim R1 for a 0V output. With R1 and R2
omitted, an alternative zero trim is needed to adjust the
ratio of R3 and R4 for 0V out. Trim full scale by loading
Figure 2 shows the MAX551/MAX552 timing diagram.
The most significant bit (MSB) is always loaded first on
SCLK’s rising edge. When all data is shifted into the
input register, the DAC register is loaded by driving the
LOAD signal low. The DAC register is transparent when
LOAD is low a nd la tc he d whe n LOAD is hig h. The
MAX551/MAX552 digital inputs are compatible with
CMOS logic levels. The MAX551’s inputs are also com-
patible with TTL logic.
the DAC with all 0s or 1s and adjusting the V
ampli-
REF
tude or varying R5 until the desired positive or negative
output is obtained. In applications where gain trim is
not required, omit resistors R1 and R2. If gain trim is
desired and the DAC is operated over a wide tempera-
_______________________________________________________________________________________
9
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
ture range, then low-tempco (<300ppm/°C) resistors
should be used.
+5V
__________Ap p lic a t io n s In fo rm a t io n
Ou t p u t Am p lifie r
V
DD
For best linearity, terminate OUT and GND at exactly
0V. In mos t a p p lic a tions , OUT is c onne c te d to a n
inverting op amp’s summing junction. The amplifier’s
input offset voltage can degrade the DAC’s linearity by
causing OUT to be terminated to a nonzero voltage.
The resulting error is:
REFERENCE
VOLTAGE
V
OUT
OUT
REF
MAX551
GND
DIN
SCLK LOAD
Error Voltage = V (1 + R / R )
OS
FB
O
Figure 5. Single-Supply, Voltage Mode Operation
whe re V
= is the op a mp ’s offs e t a nd R is the
O
OS
1/MAX52
internal feedback resistor, R . Its value depends on
FB
DAC’s output resistance, which is code dependent.
The maximum error voltage (Ro = R ) is 2V ; the
minimum error voltage (R = ∞) is V . To minimize this
error, use a low-offset amplifier such as the MAX4166
(unip ola r outp ut) or the MAX427 (b ip ola r outp ut).
Otherwise, the amplifier offset must be trimmed to zero.
the type of op amp used but typically ranges from 14pF
to 30pF. Too small a value causes output ringing, while
excess capacitance overdamps the output. C1’s size
can be minimized and the output voltage settling time
improved by keeping the circuit-board trace short and
stray capacitance at OUT as low as possible.
FB
OS
O
OS
A good guide rule is that V should be no more than
OS
1/10LSB.
S in g le -S u p p ly Op e ra t io n
The output amplifier’s input bias current (I ) can also
limit performance, since I x R
error. Choose an op amp with an I much less than
(e.g., one-tenth) the DAC’s 1LSB output current (typi-
B
Reference Voltage
The MAX551/MAX552 are true 4-quadrant DACs, mak-
ing them ideal for multiplying applications. The refer-
ence input accepts both AC and DC signals within a
voltage range of ±6V. The R-2R ladder is implemented
with thin-film resistors, enabling the use of unipolar or
bipolar reference voltages with only a single power
generates an offset
B
FB
B
cally 111nA when V
= 5V, and 55.5nA when V
=
REF
REF
2.5V). Offset and linearity can also be impaired if the
outp ut a mp lifie r’s noninve rting inp ut is g round e d
throug h a b ia s -c urre nt c omp e ns a tion re s is tor. This
resistor adds to the offset at this pin and thus should
not be used. For best performance, connect the nonin-
verting input directly to ground.
supply for the DAC. The voltage at the V
input sets
REF
the DAC’s full-scale output voltage.
If the reference is too noisy, it should be bypassed to
GND (AGND on the 10-p in µMAX p a c ka g e ) with a
0.1µF ceramic capacitor located as close to the REF
pin as possible.
In static or DC applications, the output amplifier’s char-
acteristics are not critical. In higher speed applications
in which either the reference input is an AC signal or
the DAC outp ut mus t q uic kly s e ttle to a ne w p ro-
grammed value, the output op amp’s AC parameters
must be considered.
Voltage Mode (MAX551)
The MAX551 c a n b e c onve nie ntly us e d in volta g e
mode, single-supply operation with OUT biased at any
volta g e b e twe e n GND a nd V . OUT mus t not b e
allowed to go 0.3V lower than GND or 0.3V higher than
A compensation capacitor, C1, may be required when
the DAC is used with a high-speed output amplifier.
The purpose of the capacitor is to cancel the pole
DD
V
DD
. Otherwise, internal diodes will turn on, causing a
high current flow that could damage the device.
formed by the DAC output capacitance, C
, and the
OUT
10 ______________________________________________________________________________________
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
1/MAX52
+5V (+3V)
+5V
(+3V)
10k
10k
C1
V
RFB
DD
OUT
AC
REFERENCE
INPUT
V
DD
OUT
REF
MAX551
MAX552
MAX4167
V
OUT
REF
MAX4166
MAX551
MAX552
AGND
DGND
GND
+1.43V TO +12.6V
OUT
( ) ARE FOR MAX552
MAX4167
Figure 7. Single-Supply AC Reference Input Circuit
scale). With 2.45V applied to REF, the output can be
p rog ra mme d from 1.23V (ze ro c od e ) to 0.01V (full
scale).
106M
MAX6160
ADJ
The MAX4166 op amp that drives AGND maintains the
1.23V bias as AGND’s impedance changes with the
DAC’s digital code, from high impedance (zero code)
to 7kΩ minimum (full scale).
( ) ARE FOR MAX552
Figure 6. Single-Supply, Current Mode Operation
Us in g a n AC Re fe re n c e
In applications where reference voltage has AC signal
components, the MAX551/MAX552 have multiplying
capability within the reference input range of ±6V. If the
DAC and the output amplifier are operated with a single
supply voltage, then an AC reference input can be off-
set with the circuit shown in Figure 7 to prevent the
DAC output voltage from exceeding the output amplifi-
er’s negative output rail. The reference input’s typical
-3dB bandwidth is greater than 700kHz, as shown in
the Typical Operating Characteristics graphs.
Figure 5 shows the MAX551 connected as a voltage
output DAC. In this mode of operation, the OUT pin is
connected to the reference-voltage source, and the
GND pin is connected to the PCB ground plane. The
DAC output now appears at the REF pin, which has a
constant resistance equal to the reference input resis-
tance (11kΩ typ). This output should be buffered with
an op amp when a lower output impedance is required.
The RFB pin is not used in this mode. The reference
input (OUT) impedance is code dependent, and the
c irc uit’s re s p ons e time d e p e nd s on the re fe re nc e
source’s behavior with changing load conditions.
Offs e t t in g AGND
The MAX551/MAX552 provide separate AGND and
GND inputs in the µMAX package. With this package,
AGND can be biased above GND to provide an arbi-
tra ry nonze ro outp ut volta g e for a “0” inp ut c od e
(Figure 8).
An advantage of voltage mode operation is that a neg-
ative reference is not required for a positive output.
Note that the reference input (OUT) must always be
positive and is limited to no more than 2V when V is
5V. The unipolar and bipolar circuits in Figures 3 and 4
can be converted to voltage mode.
DD
La yo u t , Gro u n d in g , a n d Byp a s s in g
Bypass V with a 0.1µF capacitor, located as close to
DD
Current Mode
Figure 6 shows the MAX551/MAX552 in a current out-
put configuration in which the output amplifier is pow-
ered from a single supply, and AGND is biased to
1.23V. With 0V applied to the REF input, the output can
be programmed from 1.23V (zero code) to 2.46V (full
V
DD
and GND as possible. The ground pins (AGND
and GND) should be connected in a star configuration
to the highest quality ground available, which should be
located as close to the MAX551/MAX552 as possible.
Since OUT and the output amplifier’s noninverting input
are sensitive to offset voltage, nodes that are to be
______________________________________________________________________________________ 11
+3 V/+5 V, 1 2 -Bit , S e ria l, Mu lt ip lyin g DACs
in 1 0 -P in µMAX P a c k a g e
tice, connect active inputs to V or GND through high-
DD
value resistors (1MΩ) to prevent static charge accumu-
lation if the pins are left floating, such as when a circuit
card is left unconnected.
V
IN
The CLR input on the µMAX device has an internal pull-
up resistor with a typical value of 125kΩ. If the CLR
REF
V
DD
AGND
OUT
input is not used, tie it to V
to minimize supply cur-
DD
MAX551
MAX552
rent.
GND
V
BIAS
Figure 8. AGND Bias Current
_Ord e rin g In fo rm a t io n (c o n t in u e d )
grounded should be connected directly to a single-
point ground through a separate, low-resistance (less
than 0.2Ω) connection. The current at OUT and AGND
varies with input code, creating a code-dependent
error if these terminals are connected to ground (or vir-
tual ground) through a resistive path.
PIN-
PACKAGE
LINEARITY
(LSB)
1/MAX52
PART
TEMP. RANGE
MAX552ACPA
MAX552BCPA
MAX552ACUB
MAX552BCUB
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
8 Plastic DIP
8 Plastic DIP
10 µMAX
±1/2
±1
±1/2
±1
10 µMAX
Parasitic coupling of the signal from REF to OUT is an
error source in dynamic applications. This coupling is
normally a function of board layout and pin-to-pin pack-
age capacitance. Minimize digital feedthrough with
guard traces between digital inputs, REF, and OUT
pins.
MAX552AEPA -40°C to +85°C
MAX552BEPA -40°C to +85°C
MAX552AEUB -40°C to +85°C
MAX552BEUB -40°C to +85°C
8 Plastic DIP
8 Plastic DIP
10 µMAX
±1/2
±1
±1/2
±1
10 µMAX
The MAX551/MAX552 ha ve hig h-impe d a nc e dig ita l
inputs. To minimize noise pick-up, tie them to either
___________________Ch ip In fo rm a t io n
V
or GND when they are not in use. As a good prac-
DD
TRANSISTOR COUNT: 887
SUBSTRATE CONNECTED TO V
DD
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ___________________Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0
© 1997 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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