MAX5541CSA+ [MAXIM]
D/A Converter, 1 Func, Serial Input Loading, 1us Settling Time, PDSO8, 0.150 INCH, SOIC-8;
| 型号： | MAX5541CSA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | D/A Converter, 1 Func, Serial Input Loading, 1us Settling Time, PDSO8, 0.150 INCH, SOIC-8 |
| 文件： | 总8页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1572; Rev 0; 12/99
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
General Description
Features
The MAX5541 serial-input, voltage-output, 16-bit
monotonic digital-to-analog converter (DAC) operates
from a single +5V supply. The DAC output is
unbuffered, resulting in low 0.3mA supply current and
low 1LSB offset error. The DAC output range is 0V to
ꢀ Full 16-Bit Performance Without Adjustments
ꢀ +5V Single-Supply Operation
ꢀ Low Power: 1.5mW
ꢀ 1µs Settling Time
V
. The DAC latch accepts a 16-bit serial word. A
power-on reset circuit clears the DAC output to 0V
(unipolar mode) when power is initially applied.
REF
ꢀ Unbuffered Voltage Output Directly Drives 60kΩ
Loads
ꢀ SPI/QSPI/MICROWIRE-Compatible Serial Interface
The 10MHz 3-wire serial interface is SPI™/QSPI™/
MICROWIRE™ compatible and interfaces directly with
optocouplers for applications requiring isolation. The
MAX5541 is available in an 8-pin SO package.
ꢀ Power-On Reset Circuit Clears DAC Output to 0V
(unipolar mode)
ꢀ Schmitt Trigger Inputs for Direct Optocoupler
Interface
Applications
High-Resolution Offset and Gain Adjustment
Industrial Process Control
Ordering Information
PART
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
8 SO
MAX5541CSA
MAX5541ESA
-40°C to +85°C
8 SO
Automated Test Equipment
Data Acquisition Systems
Pin Configuration
Functional Diagram
TOP VIEW
V
DD
MAX5541
REF
16-BIT DAC
OUT
1
2
3
4
8
7
6
5
V
OUT
AGND
REF
DD
DGND
DIN
AGND
MAX5541
16-BIT DATA LATCH
SERIAL INPUT REGISTER
DGND
CS
DIN
SCLK
CONTROL
LOGIC
CS
SCLK
SO
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 1-800-835-8769.
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
ABSOLUTE MAXIMUM RATINGS
DD
V
to DGND............................................................-0.3V to +6V
Operating Temperature Ranges
CS, SCLK, DIN to DGND..........................................-0.3V to +6V
REF to AGND, DGND..................................-0.3V to (V +0.3V)
AGND to DGND.....................................................-0.3V to +0.3V
MAX5541CSA .....................................................0°C to +70°C
MAX5541ESA ..................................................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
DD
OUT to AGND, DGND..............................................-0.3V to V
DD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin SO (derate 5.88mW/°C above +70°C)................471mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +5V 5ꢀ, V
= +2.5V, V
= V
= 0, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
REF
AGND
DGND
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE—ANALOG SECTION (R = ∞)
L
Resolution
N
16
Bits
Bits
LSB
Differential Nonlinearity
Integral Nonlinearity
DNL
INL
Guaranteed monotonic
= 5V
0.5
4
1.0
16
1
V
DD
T
A
T
A
T
A
T
A
T
A
= +25°C
Zero-Code Offset Error
Zero-Code Tempco
Gain Error (Note 1)
ZSE
LSB
ppm/°C
LSB
= T
= T
to T
to T
2
MIN
MIN
MAX
ZS
0.05
TC
MAX
= +25°C
= T to T
5
10
MIN
MAX
Gain-Error Tempco
0.1
ppm/°C
kΩ
DAC Output Resistance
Power-Supply Rejection
REFERENCE INPUT
Reference Input Range
R
(Note 2)
6.25
OUT
PSR
4.75V ≤ V
≤ 5.25V
1.0
3.0
LSB
DD
V
R
(Note 3)
2.0
V
REF
Reference Input Resistance
(Note 4)
11.5
kΩ
REF
DYNAMIC PERFORMANCE—ANALOG SECTION (R = ∞)
L
Voltage-Output Slew Rate
Output Settling Time
SR
C = 10pF (Note 5)
L
To 1/2LSB of FS, C = 10pF
25
1
V/µs
µs
L
2
_______________________________________________________________________________________
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
ELECTRICAL CHARACTERISTICS (continued)
(V = +5V 5ꢀ, V
= +2.5V, V
= V
= 0, T = T
to T , unless otherwise noted. Typical values are at T = +25°C.)
MAX A
DD
REF
AGND
DGND
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC Glitch Impulse
Major-carry transition
10
nVs
Code = 0000 hex, CS = V
,
DD
Digital Feedthrough
10
nVs
SCLK = V
= 0 to V
levels
DIN
DD
DYNAMIC PERFORMANCE—REFERENCE SECTION
Reference -3dB Bandwidth
Reference Feedthrough
Signal-to-Noise Ratio
BW
Code = FFFF hex
1
1
MHz
mVp-p
dB
Code = 0000 hex, V
= 1Vp-p at 100kHz
REF
SNR
92
75
120
Code = 0000 hex
Code = FFFF hex
Reference Input Capacitance
C
IN
pF
STATIC PERFORMANCE—DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
V
2.4
V
V
IH
V
0.8
1
IL
I
IN
V
= 0
µA
pF
V
IN
Input Capacitance
Hysteresis Voltage
POWER SUPPLY
Positive Supply Range
Positive Supply Current
Power Dissipation
C
(Note 6)
10
IN
V
0.40
H
V
DD
4.75
5.25
1.1
V
I
0.3
1.5
mA
mW
DD
PD
TIMING CHARACTERISTICS
(V
= +5V 5ꢀ, V
= +2.5V, V
= V
= 0, CMOS inputs, T = T
to T
, unless otherwise noted.)
MAX
DD
REF
AGND
DGND
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
ns
SCLK Frequency
f
10
CLK
SCLK Pulse Width High
SCLK Pulse Width Low
CS Low to SCLK High Setup
CS High to SCLK High Setup
SCLK High to CS Low Hold
SCLK High to CS High Hold
DIN to SCLK High Setup
DIN to SCLK High Hold
t
45
45
45
45
30
45
40
0
CH
t
CL
ns
t
t
t
ns
CSS0
CSS1
ns
(Note 6)
ns
CSH0
CSH1
t
ns
t
ns
DS
t
ns
DH
V
High to CS Low
DD
20
µs
(power-up delay)
Note 1: Gain Error tested at V
= +2.0V, +2.5V, and +3.0V.
REF
Note 2: R
tolerance is typically 20ꢀ.
OUT
Note 3: Min/Max ranges guaranteed by gain-error test. Operation outside min/max limits will result in degraded performance.
Note 4: Reference input resistance is code dependent, minimum at 8555 hex.
Note 5: Slew-rate value is measured from 0ꢀ to 63ꢀ.
Note 6: Guaranteed by design. Not production tested.
_______________________________________________________________________________________
3
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
Typical Operating Characteristics
(V
= +5V, V
= +2.5V, T = +25°C, unless otherwise noted.)
REF
A
DD
SUPPLY CURRENT
vs. REFERENCE VOLTAGE
ZERO-CODE OFFSET ERROR
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
0.35
0.34
0.33
0.32
0.31
0.30
1.0
0.8
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
0.29
0.28
-60
-40 -20
0
20
40
60
80 100
0
1
2
3
4
5
6
-20
20
60
100
140
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. TEMPERATURE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
GAIN ERROR
vs. TEMPERATURE
1.0
0.8
1.0
0.8
1.0
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
+INL
+DNL
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-DNL
-INL
-60
-60
-60
-20
20
60
100
140
-20
20
60
100
140
-20
20
60
100
140
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY
vs. CODE
DIFFERENTIAL NONLINEARITY
vs. CODE
REFERENCE CURRENT
vs. CODE
200
160
120
80
1.00
1.00
0.75
0.75
0.50
0.25
0.50
0.25
0
0
-0.25
-0.25
-0.50
-0.50
-0.75
-1.00
40
-0.75
-1.00
0
0
0
0
10k 20k 30k 40k 50k 60k 70k
DAC CODE
10k 20k 30k 40k 50k 60k 70k
DAC CODE
10k 20k 30k 40k 50k 60k 70k
DAC CODE
4
_______________________________________________________________________________________
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
Typical Operating Characteristics (continued)
(V
= +5V, V
= +2.5V, T = +25°C, unless otherwise noted.)
DD
REF
A
FULL-SCALE STEP RESPONSE
FULL-SCALE STEP RESPONSE
(f = 20MHz)
(f
= 10MHz)
SCLK
SCLK
OUT
500mV/div
OUT
500mV/div
1µs/div
400ns/div
C = 13pF, R = ∞
C = 13pF, R = ∞
L
L
L
L
MAJOR-CARRY OUTPUT GLITCH
DIGITAL FEEDTHROUGH
CS
5V/div
SCLK
5V/div
OUT
AC-COUPLED
100mV/div
OUT
AC-COUPLED
50mV/div
2µs/div
2µs/div
CODE = 0000 hex
______________________________________________________________Pin Description
PIN
1
NAME
OUT
FUNCTION
DAC Output Voltage
Analog Ground
2
AGND
REF
3
Voltage Reference Input. Connect to external +2.5V reference.
4
Chip-Select Input
CS
5
SCLK
DIN
Serial-Clock Input. Duty cycle must be between 40ꢀ and 60ꢀ.
6
Serial-Data Input
Digital Ground
7
DGND
8
V
DD
+5V Supply Voltage
_______________________________________________________________________________________
5
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
synchronously and latched into the input register on the
Detailed Description
rising edge of the serial-clock input (SCLK). After 16
data bits have been loaded into the serial input regis-
ter, it transfers its contents to the DAC latch on CS’s
low-to-high transition (Figure 2). Note that if CS does
not remain low during the entire 16 SCLK cycles, data
will be corrupted. In this case, reload the DAC latch
with a new 16-bit word.
The MAX5541 voltage-output, 16-bit digital-to-analog
converter (DAC) offers 16-bit monotonicity with less
than 1LSB differential linearity error. Serial-data transfer
minimizes the number of package pins required.
The MAX5541 is composed of two matched DAC sec-
tions, with a 12-bit inverted R-2R DAC forming the 12
LSBs and the 4 MSBs derived from 15 identically
matched resistors. This architecture allows the lowest
glitch energy to be transferred to the DAC output on
major-carry transitions. It also decreases the DAC out-
put impedance by a factor of eight compared to a stan-
dard R-2R ladder, allowing unbuffered operation in
medium-load applications. Figure 1 is the Timing
Diagram.
External Reference
The MAX5541 operates with external voltage refer-
ences from 2V to 3V. The reference voltage determines
the DAC’s full-scale output voltage.
Power-On Reset
The MAX5541 has a power-on reset circuit to set the
DAC’s output to 0V in unipolar mode when V
is first
DD
applied. This ensures that unwanted DAC output volt-
ages will not occur immediately following a system
power-up, such as after power loss. In bipolar mode,
Digital Interface
The MAX5541 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE inter-
faces. The chip-select input (CS) frames the serial data
loading at the data input pin (DIN). Immediately follow-
ing CS’s high-to-low transition, the data is shifted
the DAC output is set to -V
.
REF
t
CSH1
CS
t
CSHO
t
CSS1
t
t
t
CL
CSSO
CH
SCLK
DIN
t
DH
t
DS
D15
D14
D0
Figure 1. Timing Diagram
CS
DAC
UPDATED
SCLK
DIN
D15 D14 D13 D12 D11 D10 D9 D8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Figure 2. 3-Wire Interface Timing Diagram
6
_______________________________________________________________________________________
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
(R > 60kΩ) without degradation of INL or DNL; only
L
Applications Information
the gain error is increased by externally loading the
DAC output.
Reference and Analog Ground Inputs
The MAX5541 operates with external voltage references
from 2V to 3V, and maintains 16-bit performance with
proper reference selection and application. Ideally, the
reference’s temperature coefficient should be less than
0.4ppm/°C to maintain 16-bit accuracy to within 1LSB
over the commercial (0°C to +70°C) temperature range.
Since this converter is designed as an inverted R-2R
voltage-mode DAC, the input resistance seen by the
voltage reference is code dependent. The worst-case
input-resistance variation is from 11.5kΩ (at code 8555
hex) to 200kΩ (at code 0000 hex). The maximum
change in load current for a 2.5V reference is 2.5V/
11.5kΩ = 217µA; therefore, the required load regulation
is 7ppm/mA for a maximum error of 0.1LSB. This implies
a reference output impedance of <18mΩ. In addition,
the impedance of the signal path from the voltage refer-
ence to the reference input must be kept low because it
contributes directly to the load-regulation error.
External Output Buffer Amplifier
In unipolar mode, the output amplifier is used in a volt-
age-follower connection. The DAC’s output resistance
is constant and is independent of input code; however,
the output amplifier’s input impedance should still be as
high as possible to minimize gain errors. The DAC’s
output capacitance is also independent of input code,
thus simplifying stability requirements on the external
amplifier.
In single-supply applications, precision amplifiers with
input common-mode ranges including AGND are avail-
able; however, their output swings do not normally
include the negative rail (AGND) without significant per-
formance degradation. A single-supply op amp, such
as the MAX495, is suitable if the application does not
use codes near zero.
Since the LSBs for a 16-bit DAC are extremely small
The requirement for a low-impedance voltage reference
is met with capacitor bypassing at the reference inputs
and ground. A 0.1µF ceramic capacitor with short leads
between REF and AGND provides high-frequency
bypassing. A surface-mount ceramic chip capacitor is
preferred because it has the lowest inductance. An
additional 10µF between REF and AGND provides low-
frequency bypassing. A low-ESR tantalum, film, or
organic semiconductor capacitor works well. Leaded
capacitors are acceptable because impedance is not
as critical at lower frequencies. The circuit can benefit
from even larger bypassing capacitors, depending on
the stability of the external reference with capacitive
loading. If separate force and sense lines are not used,
connect the appropriate force and sense pins together
close to the package.
(38.15µV for V
= 2.5V), pay close attention to the
REF
external amplifier’s input specification. The input offset
voltage can degrade the zero-scale error and might
require an output offset trim to maintain full accuracy if
the offset voltage is greater than 1/2LSB. Similarly, the
input bias current multiplied by the DAC output resis-
tance (typically 6.25kΩ) contributes to the zero-scale
error. Temperature effects also must be taken into con-
sideration. Over the commercial temperature range, the
offset voltage temperature coefficient (referenced to
+25°C) must be less than 0.42µV/°C to add less than
1/2LSB of zero-scale error. The external amplifier’s
input resistance forms a resistive divider with the DAC
output resistance, which results in a gain error. To con-
tribute less than 1/2LSB of gain error, the input resis-
tance typically must be greater than:
AGND must also be low impedance, as load-regulation
errors will be introduced by excessive AGND resis-
tance. As in all high-resolution, high-accuracy applica-
tions, separate analog and digital ground planes yield
the best results. Connect DGND to AGND at the AGND
pin to form the “star” ground for the DAC system. For
the best possible performance, always refer remote
DAC loads to this system ground.
1
1
6.25kΩ /
= 205MΩ
14
2
2
The settling time is affected by the buffer input capaci-
tance, the DAC’s output capacitance, and PC board
capacitance. The typical DAC output voltage settling
time is 1µs for a full-scale step. Settling time can be sig-
nificantly less for smaller step changes. Assuming a
single time-constant exponential settling response, a
full-scale step takes 12 time constants to settle to within
1/2LSB of the final output voltage. The time constant is
equal to the DAC output resistance multiplied by the
total output capacitance. The DAC output capacitance
is typically 10pF. Any additional output capacitance will
increase the settling time.
Unbuffered Operation
Unbuffered operation reduces power consumption as
well as offset error contributed by the external output
buffer. The R-2R DAC output is available directly at
OUT, allowing 16-bit performance from +V
to AGND
REF
without degradation at zero-scale. The DAC’s output
impedance is also low enough to drive medium loads
_______________________________________________________________________________________
7
Low-Cost, +5V, Serial-Input,
Voltage-Output, 16-Bit DAC
The external buffer amplifier’s gain-bandwidth product
Table 1. Unipolar Code Table
is important because it increases the settling time by
adding another time constant to the output response.
The effective time constant of two cascaded systems,
each with a single time-constant response, is approxi-
mately the root square sum of the two time constants.
The DAC output’s time constant is 1µs / 12 = 83ns,
ignoring the effect of additional capacitance. If the time
constant of an external amplifier with 1MHz bandwidth
is 1 / 2π (1MHz) = 159ns, then the effective time con-
stant of the combined system is:
DAC LATCH CONTENTS
ANALOG OUTPUT, V
OUT
MSB LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
V
•
(65,535 / 65,536)
(32,768 / 65,536) =
(1 / 65,536)
REF
1/
V
REF
2
V
REF
•
V
REF
•
0V
Power-Supply Bypassing and
Ground Management
2
2
For optimum system performance, use PC boards with
separate analog and digital ground planes. Wire-wrap
boards are not recommended. Connect the two ground
planes together at the low-impedance power-supply
source. Connect DGND and AGND together at the IC.
The best ground connection can be achieved by con-
necting the DAC’s DGND and AGND pins together and
connecting that point to the system analog ground
plane. If the DAC’s DGND is connected to the system
digital ground, digital noise may get through to the
DAC’s analog portion.
96ns + 159ns
=186ns
This suggests that the settling time to within 1/2LSB of
the final output voltage, including the external buffer
amplifier, will be approximately 12 180ns = 2.15µs.
•
Digital Inputs and Interface Logic
The digital interface for the 16-bit DAC is based on a 3-
wire standard that is SPI/QSPI/MICROWIRE compati-
ble. The three digital inputs (CS, DIN, and SCLK) load
the digital input data serially into the DAC.
Bypass V
with a 0.1µF ceramic capacitor connected
DD
DD
All of the digital inputs include Schmitt-trigger buffers to
accept slow-transition interfaces. This means that opto-
couplers can interface directly to the MAX5541 without
additional external logic. The digital inputs are TTL/
CMOS-logic compatible.
between V
and AGND. Mount it with short leads
close to the device. Ferrite beads can also be used to
further isolate the analog and digital power supplies.
Chip Information
Unipolar Configuration
Figure 3 shows the MAX5541 configured for unipolar
operation with an external op amp. The op amp is set for
unity gain, and Table 1 shows the codes for this circuit.
TRANSISTOR COUNT: 2209
SUBSTRATE CONNECTED TO DGND
+2.5V
+5V
10µF
0.1µF
0.1µF
MC68XXXX
V
REF
(REFS)
DD
UNIPOLAR
OUT
PCS0
MOSI
SCLK
CS
MAX495
OUT
DIN
MAX5541
EXTERNAL OP AMP
SCLK
DGND
AGND_
Figure 3. Typical Operating Circuit
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 1999 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX5541CSA+T
D/A Converter, 1 Func, Serial Input Loading, 1us Settling Time, PDSO8, 0.150 INCH, SOIC-8
MAXIM
MAX5541ESA+
D/A Converter, 1 Func, Serial Input Loading, 1us Settling Time, PDSO8, 0.150 INCH, SOIC-8
MAXIM
©2020 ICPDF网 联系我们和版权申明