MAX5661GCB+ [MAXIM]
Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules; 一个16位DAC，提供电流和电压输出，适用于工业模拟输出模块
| 型号： | MAX5661GCB+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Single 16-Bit DAC with Current and Voltage Outputs for Industrial Analog Output Modules |
| 文件： | 总40页 (文件大小：4693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-ꢀ741; Rev 1; 5/ꢀ9
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
General Description
Features
♦ 10-Bit Programmable Full-Scale Output
The MAX5661 single 16-bit DAC with precision high-
voltage amplifiers provides a complete solution for pro-
grammable current and voltage-output applications.
The output amplifiers swing to industry-standard levels
of 1ꢀ0 ꢁvoltage outputꢂ or source from ꢀmA ꢁor from
4mAꢂ to 2ꢀmA ꢁcurrent outputꢂ. The voltage output
ꢁOUT0ꢂ drives resistive loads greater than 2kΩ and
capacitive loads of up to 1.2µF. 0oltage-output force-
sense connections compensate for series protection
resistors and field-wiring resistance. Short-circuit pro-
tection on the voltage output limits output current to
1ꢀmA ꢁtypꢂ sourcing or -11.5mA ꢁtypꢂ sinking. The cur-
rent output ꢁOUTIꢂ drives resistive loads up to 37.50
ꢁmaxꢂ and inductive loads up to 1H.
Adjustment for Up to ±±25 Oꢀer ꢁange
♦ Programmable Voltage Output
Unipolar ꢁange: 0 to +10.±4V ±±25
Bipolar ꢁange: ±10.±4V ±±25
♦ Programmable Current Output
Unipolar Low ꢁange: 0 to ±0.42mA
Unipolar High ꢁange: 3.97mA to ±0.42mA
♦ Flexible Analog Supplies (See Table 16)
±13.4ꢂV to ±12.72V for Voltage Output
+13.4ꢂV to +40V for Current Output
♦ Force-Sense Connections (Voltage Output)
The MAX5661 provides either a current output or a volt-
age output. Only one output is active at any given time,
regardless of the configuration. The MAX5661 voltage
output operates with 13.4ꢃ0 to 15.750 supplies
for Differential Voltage-Output ꢁemote Sensing
♦ Voltage-Output Current Limit
♦ Dropout Detector Senses Out-of-ꢁegulation
ꢁ0
, 0
ꢂ and the current output operates with a
SS0
DD0
Current Output
single +13.4ꢃ0 to +4ꢀ0 supply ꢁ0
+5.250 digital supply ꢁ0 ꢂ powers the rest of the inter-
ꢂ. A +4.750 to
DDI
♦ CLR and LDAC Inputs for Asynchronous DAC
CC
nal circuitry. A buffered reference input accepts an
external +4.ꢀ960 reference voltage.
Updates
♦ CLR Input ꢁesets Output to Programmed Value or
Update the DAC outputs using software commands or
the asynchronous LDAC input. An asynchronous CLR
input sets the DAC outputs to the value stored in the
clear register or to zero. The FAULT output asserts
when the DAC’s current output is an open circuit, the
DAC’s voltage output is a short circuit, or when the CLR
input is low.
Zero Code
♦ FAULT Output Indicates Open-Circuited Current
Output, Short-Circuited Voltage Output, or Clear
State
♦ Temperature Drift
Voltage Output: ±0.4ppm FSꢁR/C
Current Output: ±7.9ppm FSꢁR/C
The MAX5661 communicates through a 4-wire 1ꢀMHz
SPI™-/QSPI™-/MICROWIRE™-compatible serial inter-
face. The DOUT output allows daisy chaining of multi-
ple devices. The MAX5661 is available in a 1ꢀmm x
1ꢀmm, 64-pin, LQFP package and operates over the
-4ꢀ°C to +1ꢀ5°C temperature range.
♦ Small 64-Pin LQFP Package (10mm x 10mm)
SPI and QSPI are trademarks of Motorola, Inc.
Ordering Information
MICROWIRE is a trademark of National Semiconductor Corp.
PAꢁT
TEMP ꢁANGE
PIN-PACKAGE
MAX5661GCB+
-4ꢀ°C to +1ꢀ5°C
64 LQFP
Applications
Industrial Analog Output Modules
Industrial Instrumentation
+Denotes a leadꢁPbꢂ-free/RoHS-compliant package.
Programmable Logic Controls/Distributed
Control Systems
Process Control
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing deliꢀery, and ordering information please contact Maxim Direct at 1-ꢂꢂꢂ-6±9-464±,
or ꢀisit Maxim’s website at www.maxim-ic.com.
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
OUT0, S0P, S0N, COMP0 to 0
OUTI, COMPI, OUTI4/0 to AGND..............-ꢀ.30 to ꢁ0
Maximum Current into Any Pin ....................................... 1ꢀꢀmA
Continuous Power Dissipation ꢁT = +7ꢀ°Cꢂ
64-Pin, 1ꢀmm x 1ꢀmm TQFP ꢁderate 25mW/°C
above +7ꢀ°Cꢂ............................................................ 2ꢀꢀꢀmW
Junction-to-Ambient Thermal Resistance
...........-ꢀ.30 to ꢁ0
DD0
+ ꢀ.30ꢂ
+ ꢀ.30ꢂ
SS0
DDI
A
DACGNDS to AGND ............................................-ꢀ.30 to +60
Digital Inputs ꢁCS, DIN, SCLK, CLR, LDAC,
in Still Air ꢁθ ꢂ...………………………………………….4ꢀ°C/W
JA
Junction-to-Case Thermal Resistance ꢁθ ꢂ...................... ꢃ°C/W
5
JC
Operating Temperature Range .........................-4ꢀ°C to +1ꢀ5°C
Junction Temperature......................................................+15ꢀ°C
Storage Temperature Range.............................-65°C to +15ꢀ°C
Lead Temperature ꢁsoldering,1ꢀsꢂ ..................................+3ꢀꢀ°C
CNF_ꢂ to DGND .....................................-ꢀ.30 to ꢁ0
+ ꢀ.30ꢂ
CC
Digital Outputs ꢁDOUT, FAULTꢂ to DGND....................................
...............................-ꢀ.30 to the lesser of ꢁ0 + ꢀ.30ꢂ or +60
CC
REF to AGND............................................................-ꢀ.30 to +60
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTꢁICAL CHAꢁACTEꢁISTICS
ꢁ0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960, 0
= 0
= 0
=
DUTGND
CC
COMPI
DD0
DDCORE
SS0
DDI
REF
AGND
DGND
0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = -4ꢀ°C to +1ꢀ5°C,
DACGND
SERIES A
unless otherwise noted. Typical values are at T = +25°C. See the Typical Operating Circuit.ꢂ ꢁNote 1ꢂ
A
PAꢁAMETEꢁ
STATIC PEꢁFOꢁMANCE
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
16
Bits
0
ꢀ.2
6
4
OUT
I
, 0
= 4ꢀ0,
= ꢀ
DD0
OUT DDI
4–2ꢀmA
0
= 0
SS0
ꢀ to 2ꢀmA
4–2ꢀmA
1ꢀ
ꢁNote 2ꢂ
Integral Nonlinearity
INL
LSB
I
, 0
= 0
DD0
OUT DDI
2
6
= +150, 0
ꢁNote 2ꢂ
= -150
SS0
ꢀ to 2ꢀmA
Differential Nonlinearity
Zero-Scale 0oltage Error
DNL
Guaranteed monotonic ꢁNote 3ꢂ
-1.ꢀ
+1.ꢀ
3
LSB
m0
Unipolar
ꢀ.ꢀ1
2.ꢀ
0
OUT0
ZSE
Bipolar
1ꢀ
T
T
T
T
T
T
T
T
= +25°C
-45
-6ꢀ
-3ꢀ
-3ꢀ
3.97
3.97
2.ꢀ
-15
ꢀ
A
A
A
A
A
A
A
A
ꢀ to 2ꢀmA mode
4–2ꢀmA mode
ꢀ to 2ꢀmA mode
4–2ꢀmA mode
OUT0
µA
= T
to T
Zero-Scale Current
ꢁNote 4ꢂ
MIN
MAX
MAX
MAX
MAX
= +25°C
= T to T
3.955
3.94
-15
3.9ꢃ5
4.ꢀꢀ
+15
+3ꢀ
+15
+3ꢀ
mA
MIN
= +25°C
= T to T
-3ꢀ
2.ꢀ
Zero-Scale Current Error
ꢁNote 4ꢂ
MIN
I
µA
ZSE
= +25°C
= T to T
-15
3.ꢀ
-3ꢀ
7.ꢀ
MIN
Unipolar
Bipolar
ꢀ.5
ppm of
FSR/oC
0oltage-Offset Error Drift
TC0
OS
ꢀ.2
±
________________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
ELECTꢁICAL CHAꢁACTEꢁISTICS (continued)
ꢁ0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960, 0
= 0
= 0
=
DUTGND
CC
COMPI
DD0
DDCORE
SS0
DDI
REF
AGND
DGND
0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = -4ꢀ°C to +1ꢀ5°C,
DACGND
SERIES A
unless otherwise noted. Typical values are at T = +25°C. See the Typical Operating Circuit.ꢂ ꢁNote 1ꢂ
A
PAꢁAMETEꢁ
SYMBOL
TCI
CONDITIONS
ꢀ to 2ꢀmA
MIN
TYP
4
MAX
UNITS
ppm of
FSR/oC
Current-Offset Error Drift
OUTI
OUT0
OUTI
OUT0
OUTI
OS
4–2ꢀmA
Unipolar
Bipolar
4
2.5
4.5
ꢃ.ꢀ
4ꢀ
1ꢀ
2ꢀ
m0
µA
Gain Error
GE
T
A
T
A
= +25°C
7ꢀ
= T
to T
13ꢀ
MIN
MAX
Unipolar
Bipolar
ꢀ.4
ꢀ.4
-7.9
-ꢃ.6
ppm of
FSR/oC
Gain-Error Drift
TCGE
PSRR
ꢀ to 2ꢀmA
4–2ꢀmA
OUT0, unipolar output, full-scale code,
from +13.4ꢃ0 to +15.750
2ꢀ
2ꢀ
2ꢀꢀ
2ꢀꢀ
5
0
DD0
µ0/0
µA/0
OUT0, bipolar output, zero-scale code,
from -13.4ꢃ0 to -15.750
0
SS0
Power-Supply Rejection Ratio
OUTI, full-scale code, 0
from +13.4ꢃ0 to
DDI
ꢀ.ꢀ13
ꢀ.ꢀ17
+4ꢀ0, 0
= -15.750, 0
= +15.750
DD0
SS0
OUTI, full-scale code, 0
from +13.4ꢃ0 to
DDI
5
+4ꢀ0, 0
= 0
= ꢀ
SS0
DD0
ꢁEFEꢁENCE INPUT
Reference Input Current
Reference Input 0oltage Range
DYNAMIC PEꢁFOꢁMANCE
I
ꢀ.ꢀ5ꢀ
4.ꢀ96
1
µA
0
REF
0
4.ꢀ
4.2
REF
Unipolar output, 0
= +1ꢀ.4ꢃ0
23ꢀ
3ꢀꢀ
132
12ꢀ
OUT0
Output-0oltage Noise at 1ꢀkHz
Output-Current Noise at 1ꢀkHz
e
n0/√Hz
pA/√Hz
0/µs
n
Bipolar output, 0
ꢀ to 2ꢀmA range
4–2ꢀmA range
=
1ꢀ.4ꢃ0
OUT0
i
n
C
= 1ꢀꢀpF, R
= 2kΩ,
OUT0
OUT0
0oltage-Output Slew Rate
Current-Output Slew Rate
ꢀ.1
step = 2ꢀ0, C
= ꢀnF
EXT
L
= ꢀ, R
= 5ꢀꢀΩ, step = 2ꢀmA
ꢀ.15
1
mA/µs
µ0•s
OUTI
OUTI
OUT0
From code 7FFFh
to code ꢃꢀꢀꢀh
Major Code Transition Glitch
ꢀ to 2ꢀmA
OUTI
2.ꢀ
2.ꢀ
nA•s
n0•s
pA•s
4–2ꢀmA
Outputs set to
zero scale, all
digital inputs from
OUT0
ꢀ.1
ꢀ.2
Digital Feedthrough
ꢀ0 to 0
and
CC
OUTI, R = 5ꢀꢀΩ
L
back to ꢀ0
_______________________________________________________________________________________
3
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
ELECTꢁICAL CHAꢁACTEꢁISTICS (continued)
ꢁ0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960, 0
= 0
= 0
=
DUTGND
CC
COMPI
DD0
DDCORE
SS0
DDI
REF
AGND
DGND
0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = -4ꢀ°C to +1ꢀ5°C,
DACGND
SERIES A
unless otherwise noted. Typical values are at T = +25°C. See the Typical Operating Circuit.ꢂ ꢁNote 1ꢂ
A
PAꢁAMETEꢁ
SETTLING TIME
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
C
R
= 1nF,
= 2kΩ
OUT0
3
Bipolar output,
= 3.3nF,
to ꢀ.1%
MAX561
OUT0
C
ms
µs
COMP0
C
= 1.2µF,
= 2kΩ
OUT0
5.44
R
OUT0
Bipolar output,
= ꢀnF,
C
= 1ꢀꢀpF,
= 2kΩ
OUT0
C
244
COMP0
R
OUT0
to ꢀ.1%
0oltage-Output Settling Time
C
= 1nF,
= 2kΩ
OUT0
1.ꢃ
Unipolar output,
= 3.3nF,
R
OUT0
C
ms
µs
COMP0
C
= 1.2µF,
= 2kΩ
OUT0
to ꢀ.1%
3.64
R
OUT0
Unipolar output,
= ꢀnF,
C
= 1ꢀꢀpF,
= 2kΩ
OUT0
C
13ꢀ
COMP0
R
OUT0
to ꢀ.1%
R
OUTI
= 5ꢀꢀΩ
1.5
L
L
L
= 1mH
= 1ꢀmH
= 1H
1.66
1.66
1.97
1.43
1.5ꢃ
1.5ꢃ
1.73
ꢀ to 2ꢀ.45mA
range to ꢀ.1%
OUTI
OUTI
OUTI
Current-Output Settling Time
ms
R
= 5ꢀꢀΩ
= 1mH
= 1ꢀmH
= 1H
OUTI
OUTI
OUTI
OUTI
3.97mA to
2ꢀ.45mA range
to ꢀ.1%
L
L
L
4
________________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
ELECTꢁICAL CHAꢁACTEꢁISTICS (continued)
ꢁ0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960, 0
= 0
= 0
=
DUTGND
CC
COMPI
DD0
DDCORE
SS0
DDI
REF
AGND
DGND
0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = -4ꢀ°C to +1ꢀ5°C,
DACGND
SERIES A
unless otherwise noted. Typical values are at T = +25°C. See the Typical Operating Circuit.ꢂ ꢁNote 1ꢂ
A
PAꢁAMETEꢁ
OUTV OUTPUT
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT0 Linear Output 0oltage
Range
0
+
0
-
SS0
3.ꢀ
DD0
3.ꢀ
0
0
0
Unipolar, 0
= +13.4ꢃ0, 0 = -13.4ꢃ0
SS0
ꢀ
+1ꢀ.4ꢃ
+1ꢀ.4ꢃ
Default OUT0 Output 0oltage
Ranges ꢁꢀ0 to Full Scaleꢂ
DD0
0
0
0
OUT
OUT
OUT
Bipolar, 0
Unipolar
Bipolar
= +13.4ꢃ0, 0
= -13.4ꢃ0
-1ꢀ.4ꢃ
DD0
SS0
+7.6ꢃ
7.6ꢃ
+12.ꢃ
12.ꢃ
ꢀ.1
Minimum OUT0 Output 0oltage
Range ꢁFS to ADJꢂ
Unipolar
Bipolar
Maximum OUT0 Output 0oltage
Range ꢁFS to ADJꢂ
0
Ω
DC Output Impedance
OUT0 off or disabled,
output leakage current from OUT0 to AGND
OUT0 Off-State Leakage Current
2.5
1ꢀ
µA
Sourcing
7
1ꢀ
-11.5
2
13
OUT0 Short-Circuit Output
Current
I
mA
SC
Sinking
-1ꢃ.ꢀ
-9.ꢀ
Minimum OUT0 Resistive Load
R
C
Full-scale code
kΩ
µF
nF
OUT0
OUT0
C
C
= 3.3nF
= ꢀnF
1.2
1
COMP0
COMP0
Maximum OUT0 Capacitive Load
OUTI OUTPUT
OUTI 0oltage Compliance
Full-scale output, R
= 15ꢀꢀΩ ꢁNote 5ꢂ
0
- 2.5
DDI
0
OUTI
ꢀ to 2ꢀmA mode includes FS calibration
ꢁNote 4ꢂ
ꢀ
2ꢀ.45
2ꢀ.45
OUTI Output Current Range
mA
4–2ꢀmA mode includes FS calibration
OUTI = full scale
3.97
DC Output Impedance
45
ꢀ.1
1.3
MΩ
µA
0
OUTI off or disabled,
OUTI Off-State Leakage Current
1ꢀ
ꢀ0 < 0
< 0
DDI
OUTI
Current-Mode Dropout Detection
0
0
- 0
, FAULT does not assert
DDI
SS0
OUTI
FEEDBACK SENSE BUFFEꢁ INPUTS
Input Current
+ 1.70 < S0P, S0N < 0
- 1.70
ꢀ.ꢀ5
1
µA
0
DD0
0
0
DD0
- 1.7
SS0
+ 1.7
Input 0oltage Range
S0P, S0N
DIGITAL INPUTS
Input High 0oltage
Input Low 0oltage
Input Capacitance
Input Leakage Current
DIGITAL OUTPUTS
Output High 0oltage
0
0
0
= 4.750 to 5.250
= 4.750 to 5.250
2.4
0
0
IH
CC
CC
0
ꢀ.ꢃ
+1
IL
IN
IN
C
1ꢀ
pF
µA
I
0
= ꢀ0 or 0
-1
IN
CC
0
I
= 4ꢀꢀµA, except FAULT
0 - ꢀ.5
CC
0
0
OH
SOURCE
I
= 1.6mA
ꢀ.4
1
SINK
SINK
Output Low 0oltage
0
0
= 4.750
CC
OL
I
= 1ꢀmA
_______________________________________________________________________________________
2
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
ELECTꢁICAL CHAꢁACTEꢁISTICS (continued)
ꢁ0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960, 0
= 0
= 0
=
DUTGND
CC
COMPI
DD0
DDCORE
SS0
DDI
REF
AGND
DGND
0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = -4ꢀ°C to +1ꢀ5°C,
DACGND
SERIES A
unless otherwise noted. Typical values are at T = +25°C. See the Typical Operating Circuit.ꢂ ꢁNote 1ꢂ
A
PAꢁAMETEꢁ
SYMBOL
CONDITIONS
MIN
TYP
ꢀ.1
MAX
UNITS
µA
Output High Leakage Current
Three-State Output Leakage Current
POWEꢁ SUPPLIES (see Table 16)
FAULT only
2
2
DOUT only
ꢀ.1
µA
MAX561
0
Supply Range
0
+4.75
+5.25
0
0
CC
CC
Only OUT0 powered
+13.4ꢃ
+15.75
0
Supply Range
0
Only OUTI powered
AGND
AGND
DD0
SS0
DDI
DD0
Both OUT0 and OUTI powered
Only OUT0 powered
+13.4ꢃ
-15.75
+15.75
-13.4ꢃ
0
0
0
Supply Range
Supply Range
0
Only OUTI powered
0
0
0
SS0
Both OUT0 and OUTI powered
Only OUT0 powered
-15.75
-13.4ꢃ
0
DD0
0
Only OUTI powered
+13.4ꢃ
+4ꢀ.ꢀꢀ
+4ꢀ
DDI
Both OUT0 and OUTI powered
Only OUT0 powered
0
DD0
0
DD0
Supply Range
0
Only OUTI powered
0
DDI
DDCORE
DDCORE
Both OUT0 and OUTI powered
0
DD0
I
I
+
+
0DD0
4.5
6.5
0DDI
OUT0 powered, 0
= 0
= 0
DDI DDCORE
DD0
I
I
0DDCORE
Analog and Digital Supply
Currents ꢁOUT0 Activeꢂ
= +15.750, 0
OUT0 unloaded, all ditgital inputs at 0 or
CC
DGND
= -15.750, 0
= +5.250,
CC
SS0
mA
mA
mA
I
-5
-2.5
-1.6
ꢀ.ꢀ3
0SS0
I
-3.ꢀ
AGND
I
ꢀ.2
5.5
0CC
I
I
+
+
0DD0
2.ꢃ
0DDI
Analog and Digital Supply
Currents ꢁOUTI Activeꢂ, ꢀ to
2ꢀmA Mode
OUTI powered, 0
= 0
= AGND,
SS0
DD0
0DDCORE
0
= 0
= +120 to +4ꢀ0, 0
CC
=
DDI
DDCORE
I
-1.ꢀ
-4.ꢀ
-ꢀ.ꢀ3
-2.1
0SS0
+5.250, zero code
I
AGND
I
ꢀ.ꢀ3
ꢀ.2
9.5
0CC
I
I
+
+
0DD0
6.ꢃ
0DDI
Analog and Digital Supply
Currents ꢁOUTI Activeꢂ, 4–2ꢀmA
Mode
OUTI powered, 0
= 0
= AGND,
SS0
DD0
I
I
0DDCORE
0
= 0
= +120 to +4ꢀ0, 0
=
DDI
DDCORE
CC
I
-1.ꢀ
-4.ꢀ
-ꢀ.ꢀ3
-2.1
0SS0
+5.250, zero code
I
AGND
I
ꢀ.ꢀ3
ꢀ.2
6
0CC
I
+
0DD0
4.2
Both OUT0 and OUTI powered, 0
=
DD0
0DDCORE
0
= +15.750, 0
= -15.750, 0
=
DDCORE
SS0
DDI
I
-4.ꢀ
-4.ꢀ
2.6
-2.ꢀ
ꢀ.ꢀ3
1.3
0SS0
Analog and Digital Supply
Currents ꢁEither OUT0 or OUTI
Activeꢂ
+4ꢀ0, 0 = +5.250, OUT0 unloaded at zero
CC
I
mA
AGND
code, all ditgital inputs at 0
or DGND
CC
I
ꢀ.2
2
0CC
I
ꢀ to 2ꢀmA at zero code
4–2ꢀmA at zero code
0DDI
0DDI
I
5.3
6.5
6
________________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
TIMING CHAꢁACTEꢁISTICS
ꢁ0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960, AGND = DGND = DUTGND =
CC
COMPI
DD0
DDCORE
SS0
DDI
REF
DACGND = ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = -4ꢀ°C to +1ꢀ5°C,
SERIES
A
unless otherwise noted. Typical values are at T = +25°C. See Figure 1.ꢂ ꢁNotes 1, 6ꢂ
A
PAꢁAMETEꢁ
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Rise or Fall to CS Fall
Setup Time
t
45
ns
CSO
CS Fall to SCLK Rise or Fall
Setup Time
t
4ꢀ
ns
CSS
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIN to SCLK High Setup Time
DIN to SCLK High Hold Time
SCLK Period
t
45
45
ns
ns
ns
ns
ns
ns
CH
t
CL
DS
DH
t
4ꢀ
t
ꢀ
t
1ꢀꢀ
1ꢀꢀ
CP
CS Pulse-Width High
t
CSW
CS High to SCLK High or Low
Setup Time
t
45
45
ns
ns
ns
CS1
CSH
SCLK High to CS Hold Time
t
SCLK Fall to DOUT 0alid
Propagation Delay
t
C
C
= 1ꢀꢀpF
1ꢀꢀ
1ꢀꢀ
DO
DOUT
DOUT
CS Transitions to DOUT
Enable/Disable Delay
t
= 1ꢀꢀpF
ns
ns
D0
SCLK Fall or Rise to CS Rise
Time
t
15
SCS
LDAC Pulse-Width Low
t
4ꢀ
ꢃꢀ
ns
ns
LDL
CS Rise to LDAC Rise Time
t
CSLD
Note 1: Devices are 1ꢀꢀ% production tested at T = +25°C and +1ꢀ5°C. Operation to -4ꢀ°C is guaranteed by design.
A
Note ±: I
Note 3: I
INL 1ꢀꢀ% production tested from ꢀ to 2ꢀmA only.
OUT
OUT
DNL guaranteed by 0
DNL.
OUT
Note 4: ꢀ to 2ꢀmA zero-scale current extrapolated by interpolation from full scale and code 192. See the Measuring Zero-Code
Current ꢁꢀ to 2ꢀmA Modeꢂ section.
Note 2: OUTI voltage compliance measured at 0
= +33.220.
DDI
Note 6: When updating the DAC registers, allow 5µs before sending the next command.
_______________________________________________________________________________________
7
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
CS
t
CSO
t
t
CSW
CSH
t
t
CH
CL
t
CP
MAX561
t
t
SCS
CSS
SCLK
DIN
t
DH
t
DS
t
CS1
t
DO
t
t
DV
DV
DOUT
LDAC
t
LDL
t
CSLD
Figure 1. Serial-Interface Timing Diagram
Typical Operating Characteristics
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
INL vs. DIGITAL INPUT CODE
INL vs. DIGITAL INPUT CODE
INL vs. DIGITAL INPUT CODE
1.0
0.8
1.0
0.8
5
4
BIPOLAR VOLTAGE OUTPUT
UNIPOLAR VOLTAGE OUTPUT
0.6
0.6
3
0.4
0.4
0.2
0.2
2
0
0
1
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
-1
-2
0 TO 20mA CURRENT OUTPUT
0
16,384
32,768
49,152
65,536
0
16,384
32,768
49,152
65,536
0
16,384
32,768
49,152
65,536
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIGITAL INPUT CODE
ꢂ
________________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
INL vs. DIGITAL INPUT CODE
INL vs. DIGITAL INPUT CODE
INL vs. DIGITAL INPUT CODE
3
10
5
4
9
8
2
1
0
7
3
6
5
2
4
1
3
2
-1
-2
-3
0
1
0 TO 20mA CURRENT OUTPUT
4–20mA CURRENT OUTPUT
V
V
= V
= +40V
V
V
= V
= +40V
0
DDI
DDCORE
DDI
DDCORE
-1
-2
= V = 0V
= V = 0V
DDV
SSV
DDV
SSV
-1
-2
4–20mA CURRENT OUTPUT
0
16,384
32,768
49,152
65,536
0
16,384
32,768
49,152
65,536
0
16,384
32,768
49,152
65,536
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DIGITAL INPUT CODE
INL vs. TEMPERATURE
INL vs. TEMPERATURE
DNL vs. DIGITAL INPUT CODE
0.5
0.4
0.4
0.3
0.5
0.4
0.3
0.2
0.1
ALL MODES
MAX INL
0.3
0.2
0.1
0.2
MAX INL
0.1
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
-0.5
MIN INL
-0.1
-0.2
-0.3
-0.4
MIN INL
BIPOLAR VOLTAGE OUTPUT
UNIPOLAR VOLTAGE OUTPUT
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
0
16,384
32,768
49,152
65,536
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL INPUT CODE
INL vs. TEMPERATURE
INL vs. TEMPERATURE
INL vs. TEMPERATURE
7.0
6.5
6.0
5.5
5.0
4.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
1.5
1.0
0.5
0 to 20mA CURRENT OUTPUT
= V = +40V
0 TO 20mA CURRENT OUTPUT
4–20mA CURRENT OUTPUT
V
DDI
DDCORE
V
DDV
= V = 0V
SSV
4.0
3.5
MAX INL
MAX INL
3.0
2.5
2.0
1.5
1.0
0.5
0
MAX INL
MIN INL
MIN INL
0
-0.5
-1.0
MIN INL
-0.5
-1.0
-0.5
-1.0
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
AGND
DGND
SERIES
A
ZERO-SCALE ERROR
vs. TEMPERATURE
INL vs. TEMPERATURE
DNL vs. TEMPERATURE
0.4
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3
2
4–20mA CURRENT OUTPUT
= V = +40V
ALL MODES
V
0.3
0.2
0.1
0
DDI
DDCORE
MAX561
V
DDV
= V = 0V
SSV
CURRENT OUTPUT = 0 TO 20mA
1
0
MAX DNL
MIN DNL
MAX INL
-1
-2
-3
-4
-5
-0.1
-0.2
UNIPOLAR VOLTAGE OUTPUT
BIPOLAR VOLTAGE OUTPUT
MIN INL
-0.3
-0.4
-0.5
-1.0
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
CURRENT-OUTPUT FULL-SCALE CURRENT
vs. TEMPERATURE
VOLTAGE-OUTPUT FULL-SCALE VOLTAGE
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
(UNIPOLAR VOLTAGE OUTPUT)
20.60
20.55
20.50
20.45
20.40
20.35
20.30
10.4850
4.0
CURRENT OUTPUT = 0 TO 20mA
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
UNIPOLAR VOLTAGE OUTPUT
10.4825
10.4800
10.4775
10.4750
I
I
I
VDDCORE
VSSV
VDDV
BIPOLAR VOLTAGE OUTPUT
I
VDDI
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY CURRENT vs. TEMPERATURE
(BIPOLAR VOLTAGE OUTPUT)
SUPPLY CURRENT vs. TEMPERATURE
(0 TO 20mA CURRENT OUTPUT)
SUPPLY CURRENT vs. TEMPERATURE
(4–20mA CURRENT OUTPUT)
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
5.5
5.0
I
I
I
VDDCORE
VSSV
VDDV
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
VDDI
I
I
I
VDDCORE
VSSV
VDDV
I
VSSV
I
I
VDDV
VDDCORE
I
= 4mA
OUTI
L
I
I
VDDI
VDDI
R = 500Ω
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
-50 -25
0
25
50
75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
10 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
SUPPLY CURRENT vs. TEMPERATURE
(0 TO 20mA CURRENT OUTPUT)
SUPPLY CURRENT vs. TEMPERATURE
(4–20mA CURRENT OUTPUT)
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
38
36
34
32
30
28
26
24
22
20
18
4.0
3.6
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
6.0
5.5
5.0
4.5
4.0
I
VDDCORE
I
VDDCORE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
I
I
VDDI
VDDI
I
V
= 0mA
= V
I
V
= 4mA
= V
OUTI
V
= +5.25V
OUTI
CC
= +40V
25
= +40V
25
DDI
DDCORE
ALL INPUTS CONNECTED TO V
DDI
DDCORE
CC
-50 -25
0
50
75 100 125
-50 -25
0
50
75 100 125
-50 -25
0
25
50
75
100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
UNIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
UNIPOLAR VOLTAGE-OUTPUT,
UNIPOLAR VOLTAGE-OUTPUT,
ZS-TO-FS TRANSITION vs. C (C
ZS-TO-FS TRANSITION vs. C (C
= 3.3nF)
= 0nF)
COMP
MAX5661 toc20
COMP
L
COMP
L
MAX5661 toc21
MAX5661 toc22
CS
5V/div
CS
5V/div
CS
5V/div
C = 100pF
L
C = 100pF
L
C = 100nF
L
OUTV
2V/div
C = 0.47µF
L
C = 0.47µF
L
OUTV
100mV/div
OUTV
2V/div
C = 1µF
L
C = 1µF
L
C = 1.8µF
L
C = 1.8µF
L
C = 100pF
L
C = 100nF
L
R = 2kΩ
ZS-TO-FS TRANSITION
L
R = 2kΩ
L
R = 2kΩ
L
400µs/div
400µs/div
100μs/div
UNIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
UNIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 3.3nF)
UNIPOLAR VOLTAGE-OUTPUT,
FS-TO-ZS TRANSITION (C = 0nF)
COMP
COMP
COMP
MAX5661 toc25
MAX5661 toc24
MAX5661 toc23
R = 2kΩ
L
CS
5V/div
CS
5V/div
CS
5V/div
OUTV
OUTV
100mV/div
100mV/div
C = 100nF
L
OUTV
2V/div
C = 100pF
L
C = 0.47μF
L
C = 1μF
L
C = 1μF
L
C = 1μF
R = 2kΩ
L
L
C = 1.8μF
L
R = 2kΩ
L
ZS-TO-FS TRANSITION
ZS-TO-FS TRANSITION
400μs/div
400μs/div
400μs/div
______________________________________________________________________________________ 11
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
UNIPOLAR VOLTAGE-OUTPUT,
FS-TO-ZS TRANSITION (C = 3.3nF)
UNIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 3.3nF)
UNIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
COMP
COMP
COMP
MAX5661 toc28
MAX5661 toc26
MAX5661 toc27
CS
CS
CS
MAX561
5V/div
5V/div
5V/div
C = 100pF
L
C = 100pF
L
C = 1μF
L
R = 2kΩ
L
OUTV
2V/div
OUTV
100mV/div
C = 100pF
L
OUTV
100mV/div
C = 0.47µF
L
C = 100nF
L
C = 1µF
L
R = 2kΩ
R = 2kΩ
FS-TO-ZS
L
L
C = 1.8µF
L
FS-TO-ZS
TRANSITION
TRANSITION
400μs/div
400µs/div
100μs/div
UNIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
BIPOLAR VOLTAGE-OUTPUT,
ZS-TO-FS TRANSITION (C = 0nF)
BIPOLAR VOLTAGE-OUTPUT,
ZS-TO-FS TRANSITION (C
= 3.3nF)
COMP
COMP
COMP
MAX5661 toc29
MAX5661 toc30
MAX5661 toc31
CS
CS
CS
5V/div
5V/div
5V/div
C = 1μF
C = 100nF
C = 100pF
L
L
L
OUTV
5V/div
OUTV
5V/div
R = 2kΩ
L
C = 0.47µF
L
C = 0.47µF
L
FS-TO-ZS TRANSITION
C = 1µF
L
C = 1µF
L
OUTV
100mV/div
C = 1.8µF
L
C = 1.8µF
L
R = 2kΩ
L
R = 2kΩ
L
400μs/div
1.0ms/div
1.0ms/div
BIPOLAR VOLTAGE-OUTPUT
BIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
BIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
SETTLING TIME (C
= 3.3nF)
COMP
COMP
COMP
MAX5661 toc33
MAX5661 toc32
MAX5661 toc34
CS
CS
CS
5V/div
5V/div
5V/div
C = 100pF
L
OUTV
OUTV
100mV/div
100mV/div
C = 100pF
L
OUTV
100mV/div
C = 100nF
L
C = 1μF
L
C = 1μF
L
R = 2kΩ
ZS-TO-FS TRANSITION
L
R = 2kΩ
L
R = 2kΩ
L
ZS-TO-FS TRANSITION
1.0ms/div
1.0ms/div
100μs/div
1± _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
AGND
DGND
SERIES
A
BIPOLAR VOLTAGE-OUTPUT
BIPOLAR VOLTAGE-OUTPUT,
BIPOLAR VOLTAGE-OUTPUT,
FS-TO-ZS TRANSITION (C = 0nF)
SETTLING TIME (C
= 0nF)
FS-TO-ZS TRANSITION (C
= 3.3nF)
COMP
COMP
COMP
MAX5661 toc35
MAX5661 toc37
MAX5661 toc36
CS
CS
CS
5V/div
5V/div
5V/div
C = 100pF
L
C = 100pF
L
C = 100pF
L
C = 100nF
L
OUTV
5V/div
OUTV
5V/div
C = 0.47µF
C = 0.47μF
L
L
C = 1μF
L
C = 1µF
L
OUTV
100mV/div
C = 1.8μF
L
C = 1.8µF
L
R = 2kΩ
FS-TO-ZS TRANSITION
L
R = 2kΩ
L
R = 2kΩ
L
1.0ms/div
1.0ms/div
100μs/div
BIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 0nF)
BIPOLAR VOLTAGE-OUTPUT
SETTLING TIME (C = 3.3nF)
0 TO 20mA CURRENT-OUTPUT,
ZS-TO-FS TRANSITION vs. INDUCTIVE LOAD
COMP
COMP
MAX5661 toc39
MAX5661 toc38
MAX5661 toc40
CS
5V/div
CS
5V/div
CS
5V/div
OUTI
4mA/div
L = 1H
L
C = 1μF
L
R = 2kΩ
FS-TO-ZS TRANSITION
L
C = 100pF
L
L = 0mH, L = 100mH
L
L
C = 1μF
L
OUTV
OUTV
100mV/div
100mV/div
R = 2kΩ
L
FS-TO-ZS TRANSITION
1.0ms/div
1.0ms/div
400µs/div
0 TO 20mA CURRENT-OUTPUT,
ZS-TO-FS SETTLING TIME
0 TO 20mA CURRENT-OUTPUT,
FS-TO-ZS TRANSITION vs. INDUCTIVE LOAD
0 TO 20mA CURRENT-OUTPUT,
FS-TO-ZS SETTLING TIME
MAX5661 toc42b
MAX5661 toc41
MAX5661 toc42a
CS
CS
CS
5V/div
5V/div
5V/div
OUTI
4mA/div
OUTI
200µA/div
L = 0mH
L
OUTV
200µA/div
L = 100mH
L
L = 0mH, L = 100mH
L
L
L = 0mH
L
L = 1H
L
L = 1H
L
L = 100mH
L
L = 1H
L
400µs/div
2ms/div
2ms/div
______________________________________________________________________________________ 13
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
0 TO 20mA CURRENT-OUTPUT,
ZS-TO-FS TRANSITION vs. INDUCTIVE LOAD
0 TO 20mA CURRENT-OUTPUT,
ZS-TO-FS SETTLING TIME
0 TO 20mA CURRENT-OUTPUT,
FS-TO-ZS TRANSITION vs. INDUCTIVE LOAD
MAX5661 toc43a
MAX5661 toc43b
MAX5661 toc43c
CS
CS
CS
MAX561
5V/div
5V/div
5V/div
V
V
= V
= +40V
DDI
DDCORE
SSV
L = 1H
L
L = 0mH, 100mH
L
= V = 0V
DDV
L = 1H
L
OUTI
4mA/div
OUTI
200µA/div
OUTI
4mA/div
L = 1H
L
L = 100mH
L
L = 0mH, L = 100mH
L
L
L = 0mH
L
V
V
= V
= +40V
V
V
= V
= +40V
DDI
DDCORE
SSV
DDI
DDCORE
SSV
= V = 0V
= V = 0V
DDV
DDV
400µs/div
400µs/div
2ms/div
OUTV OUTPUT VOLTAGE
vs. LOAD CURRENT (SINKING)
0 TO 20mA CURRENT-OUTPUT,
FS-TO-ZS SETTLING TIME
OUTV OUTPUT VOLTAGE
vs. LOAD CURRENT (SOURCING)
MAX5661 toc43d
100
80
60
40
20
0
10.484
10.482
10.480
10.478
10.476
10.474
10.472
UNIPOLAR OUTV MODE
CS
5V/div
L = 0mH
L
L = 100mH
L
BIPOLAR OUTV MODE
OUTI
200µA/div
L = 1H
L
V
V
= V
DDCORE
= +40V
DDI
= V = 0V
SSV
UNIPOLAR OUTV MODE
DDV
-20
2ms/div
-12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1
SINK CURRENT (mA)
0
1
2
3
4
5
6
7
8
9 10
11
0
SOURCE CURRENT (mA)
OUTI OUTPUT CURRENT
vs. OUTPUT VOLTAGE
OUTI OUTPUT CURRENT
vs. OUTPUT VOLTAGE
UNIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR
CARRY TRANSITION GLITCH (C
= 3.3nF)
COMP
MAX5661 toc48
25
20
15
10
5
25
20
15
10
5
CS
5V/div
OUTV
1mV/div
V
= V = +24V
DDI
V
= V = +40V
DDCORE DDI
DDCORE
0
0
100µs/div
0
5
10
15
20
25
0
5
10 15 20 25 30 35 40 45
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
14 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
UNIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR
BIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR
BIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR
CARRY TRANSITION GLITCH (C
= 3.3nF)
CARRY TRANSITION GLITCH (C
= 3.3nF)
CARRY TRANSITION GLITCH (C
= 3.3nF)
COMP
MAX5661 toc51
COMP
COMP
MAX5661 toc49
MAX5661 toc50
CS
5V/div
CS
5V/div
CS
5V/div
OUTV
1mV/div
OUTV
1mV/div
OUTV
1mV/div
100µs/div
100µs/div
100µs/div
UNIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR
BIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR
UNIPOLAR VOLTAGE-OUTPUT, POSITIVE MAJOR
CARRY TRANSITION GLITCH (C
= 0nF)
CARRY TRANSITION GLITCH (C
= 0nF)
COMP
MAX5661 toc54
CARRY TRANSITION GLITCH (C
= 0nF)
COMP
COMP
MAX5661 toc53
MAX5661 toc52
CS
5V/div
CS
5V/div
CS
5V/div
OUTV
50mV/div
OUTV
50mV/div
OUTV
50mV/div
4µs/div
4µs/div
4µs/div
BIPOLAR VOLTAGE-OUTPUT, NEGATIVE MAJOR
0 TO 20mA CURRENT-OUTPUT, POSITIVE
0 TO 20mA CURRENT-OUTPUT, NEGATIVE
CARRY TRANSITION GLITCH (C
= 0nF)
MAJOR CARRY TRANSITION GLITCH
MAJOR CARRY TRANSITION GLITCH
COMP
MAX5661 toc55
MAX5661 toc56
MAX5661 toc57
CS
CS
CS
5V/div
5V/div
5V/div
OUTV
50mV/div
OUTI
2µA/div
OUTI
2µA/div
4µs/div
100µs/div
100µs/div
______________________________________________________________________________________ 12
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
4–20mA CURRENT-OUTPUT, POSITIVE
4–20mA CURRENT-OUTPUT, NEGATIVE
V
SUPPLY CURRENT
CC
MAJOR CARRY TRANSITION GLITCH
MAJOR CARRY TRANSITION GLITCH
vs. DIGITAL INPUT VOLTAGE
MAX5661 toc58
MAX5661 toc59
10,000
1000
100
V
= 5.25V
CC
CS
5V/div
CS
5V/div
MAX561
OUTI
2µA/div
OUTI
2µA/div
10
100µs/div
100µs/div
0
1
2
3
4
5
6
DIGITAL INPUT VOLTAGE (V)
UNIPOLAR VOLTAGE-OUTPUT
DIGITAL FEEDTHROUGH
BIPOLAR VOLTAGE-OUTPUT
DIGITAL FEEDTHROUGH
MAX5661 toc61
MAX5661 toc62
CS = V
CS = V
CC
CC
DIN = SCLK
f = 1MHz
DIN = SCLK
f = 1MHz
DIN, SCLK
5V/div
DIN, SCLK
5V/div
OUTV
2mV/div
OUTV
1mV/div
200ns/div
200ns/div
CURRENT-OUTPUT
DIGITAL FEEDTHROUGH
FULL-SCALE CURRENT vs. FULL-SCALE
OUTPUT CURRENT TRIM CODE
MAX5661 toc63
27
26
25
24
23
22
21
CS = V
DIN = SCLK
f = 1MHz
CC
DIN, SCLK
5V/div
20
19
18
17
16
15
OUTI
2µA/div
14
200ns/div
0
256
512
768
1024
CODE
16 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Typical Operating Characteristics (continued)
ꢁTypical Operating Circuit, 0
= +50, C
= 22nF, 0
= 0
= +150, 0
= -150, 0
= +240, 0
= +4.ꢀ960,
REF
CC
COMPI
DD0
DDCORE
SS0
DDI
0
= 0
= ꢀ0, R
= 47Ω, OUT0 loaded with 2kΩ || 1ꢀꢀpF to AGND, OUTI loaded with 5ꢀꢀΩ to AGND, T = +25°C.ꢂ
SERIES A
AGND
DGND
NEGATIVE FULL-SCALE VOLTAGE
vs. FULL-SCALE OUTPUT TRIM CODE
POSITIVE FULL-SCALE VOLTAGE
vs. FULL-SCALE OUTPUT TRIM CODE
-6
-7
-8
-9
14
13
12
11
-10
-11
-12
-13
-14
10
9
8
7
UNIPOLAR OR BIPOLAR MODE
6
0
256
512
768
1024
0
256
512
768
1024
CODE
CODE
Pin Description
PIN
NAME
N.C.
FUNCTION
1, 3, 5, 7, ꢃ,
1ꢀ, 15–2ꢀ,
29–34, 36, 3ꢃ,
42, 44, 46–52,
5ꢃ, 61–64
No Connection. Not internally connected.
2
OUTI
DAC Current-Source Output. OUTI sources either from ꢀ to 2ꢀmA or from 4–2ꢀmA.
DAC Current-Output Positive Supply. Connect 0 to a power supply between +13.4ꢃ0 and
DDI
4
0
+4ꢀ0 to power the DAC current-output ꢁOUTIꢂ buffer. Bypass 0 with a ꢀ.1µF capacitor to
DDI
DDI
AGND, as close as possible to the device.
OUTI Noise-Limiting Capacitor Connection. Connect a 22nF capacitor from COMPI to 0
reduce transient noise at OUTI.
to
DDI
6
9
COMPI
Current-Output Range Selection Input. Connect OUTI4/0 to AGND to select the ꢀ to 2ꢀmA OUTI
current-output range. Connect OUTI4/0 to 0 to select the 4–2ꢀmA OUTI current-output range.
DDI
OUTI4/0
The OUTI current range can also be set by software. When using software to set the OUTI current
range, connect OUTI4/0 to AGND.
Buffered 0oltage Reference Input. Connect an external +4.ꢀ960 voltage reference to REF. Bypass
REF with a ꢀ.1µF capacitor to DACGND, as close as possible to the device. Use a 1kΩ resistor in
series to the reference input for optimum performance.
11
REF
DAC Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a
low-noise ground plane with a star connection.
12
13
14
21
DACGND
DACGNDS
CNF1
DAC Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together
on a low-noise ground plane with a star connection.
0oltage/Current Configuration Input. CNF1 and CNFꢀ control the OUT0 and OUTI outputs. See
Tables 13 and 14.
0oltage/Current Configuration Input. CNFꢀ and CNF1 control the OUT0 and OUTI outputs. See
Tables 13 and 14.
CNFꢀ
______________________________________________________________________________________ 17
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Pin Description (continued)
PIN
22
NAME
DIN
FUNCTION
Serial-Data Input. Data is clocked into the serial interface on the rising edge of SCLK.
Serial-Clock Input
23
SCLK
Active-Low Chip-Select Input. Drive CS low to enable the serial interface. Drive CS high to disable
the serial interface. DOUT is high impedance when CS is high.
24
25
26
CS
DGND
Digital Ground
MAX561
Digital Power Supply. Connect 0
to a power supply between +4.750 and +5.250. Bypass 0
CC
CC
0
CC
with a ꢀ.1µF capacitor to DGND, as close as possible to the device.
Active-Low Asynchronous Load DAC Input. Drive LDAC low to transfer the contents of the input
27
2ꢃ
LDAC
register to the DAC register to immediately update the output. Connect LDAC to 0 if unused.
CC
Active-Low Open-Drain Fault Output. FAULT asserts low for an OUTI open-circuit condition, an
OUT0 short-circuit condition, or when the CLR input is low ꢁsee Table 12 and Figure 9ꢂ. Ignore the
FAULT pin function in single supply mode.
FAULT
Serial Data Output. Data transitions at DOUT on SCLK’s falling edge. DOUT is high impedance
when CS is high. Use DOUT to read the shift register contents or for daisy chaining multiple
MAX5661 devices.
35
37
DOUT
Active-Low Clear Input. Drive CLR low to set the DAC code to the value stored in the clear
register, to ꢀ0 in voltage mode, or ꢀmA/4mA depending on the output current mode. Program the
contents of the clear register through the serial interface. Enable and disable the CLR input
through the control register’s CLREN bit ꢁsee Table 4ꢂ.
CLR
DAC Core Positive Supply. Connect 0
with a ꢀ.1µF capacitor to AGND, as close as possible to the device.
to 0
or 0
ꢁsee Table 16ꢂ. Bypass 0
DD0 DDCORE
DDCORE
DDI
39
4ꢀ
41
0
DDCORE
DUT Analog Sense Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together
on a low-noise ground plane with a star connection.
DUTGNDS
DUTGND
DUT Analog Ground. Connect DACGND, DACGNDS, DUTGND, and DUTGNDS together on a
low-noise ground plane with a star connection.
OUT0 Amplifier Compensation Feedback Node. Connect a 3.3nF capacitor from OUT0 to COMP0
when OUT0 drives capacitive loads of up to 1.2µF. Leave COMP0 open for faster response time.
43
45
COMP0
AGND
S0P
Analog Ground
Remote Ground Sense Input. Connect S0P to the bottom terminal of R
. See the Typical
OUT0
53
Operating Circuit.
54, 59
55
I.C.
Internal Connection. Leave unconnected.
DAC 0oltage-Output Negative Power Supply. Always connect 0
to a power supply between -13.4ꢃ0
SS0
0
SS0
and -15.750. Bypass 0
with a ꢀ.1µF capacitor to AGND, as close as possible to the device.
SS0
DAC Unipolar/Bipolar 0oltage Output. OUT0 provides ꢀ to +1ꢀ.4ꢃ0 in unipolar mode and -1ꢀ.4ꢃ0
to +1ꢀ.4ꢃ0 in bipolar mode.
56
OUT0
DAC 0oltage-Output Positive Power Supply. Connect 0
to a power supply between +13.4ꢃ0
DD0
57
6ꢀ
0
DD0
and +15.750. Bypass 0
with a ꢀ.1µF capacitor to AGND, as close as possible to the device.
DD0
S0N
Remote 0oltage Sense Input. Connect to the top terminal of R
. See the Typical Operating Circuit.
OUT0
1ꢂ _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
microcontroller ꢁµCꢂꢂ runs in master mode to generate
Detailed Description
the serial-clock signal. Set the SCLK frequency to
The MAX5661 single 16-bit DAC with precision high-volt-
1ꢀMHz or less, and set the clock polarity ꢁCPOLꢂ and
age amplifiers provides a complete solution for program-
phase ꢁCPHAꢂ in the µC control registers to the same
mable current and voltage-output applications. The
value. The MAX5661 operates with SCLK idling high or
programmable output amplifiers swing to industry-stan-
low, and thus operates with CPOL = CPHA = ꢀ ꢁsee
dard voltage levels of 1ꢀ0 or current levels from ꢀmA
Figure 2ꢂ or CPOL = CPHA = 1 ꢁsee Figure 3ꢂ. Force
ꢁor from 4mAꢂ to 2ꢀmA. The OUT0 voltage output drives
CS low to input data at DIN on the rising edge of SCLK.
resistive loads greater than 2kΩ and capacitive loads up
Output data at DOUT updates on the falling edge of
to 1.2µF. Force and sense connections on the voltage
SCLK ꢁsee Figure 1ꢂ.
output compensate for series protection resistors and
A high-to-low transition on CS initiates the 24-bit data
input cycle. Once CS is low, write an ꢃ-bit command
byte ꢁMSB firstꢂ at DIN to send data to the appropriate
internal register ꢁsee Tables 1, 2, and 3ꢂ. C7 is the MSB
of the command byte and Cꢀ is the LSB. Following the
command byte, write 2 data bytes containing bits
D15–Dꢀ. D15 is the MSB of the 2 data bytes and Dꢀ is
the LSB ꢁsee Figure 4 and the Register Descriptions sec-
tionꢂ. Data loads into the shift register 1 bit at a time.
field wiring resistance. Short-circuit protection on the
voltage output limits output current. The OUTI current
output drives resistive loads from ꢀΩ and higher, up to a
compliance voltage of ꢁ0
- 2.50ꢂ. The OUTI current
DDI
output also drives inductive loads up to 1H.
The MAX5661 provides a current output or a voltage
output, with only one output active at any given time.
The MAX5661 operates with 13.4ꢃ0 to 15.750 dual
supplies ꢁ0
, 0
ꢂ for the voltage output and a
SS0
DD0
Write the data as one continuous 24-bit stream, always
keeping CS low throughout the entire 24-bit word. The
MAX5661 stores the 24 most recent bits received,
including bits from previous transmissionꢁsꢂ. Ensure
SCLK has 24 rising and falling edges between CS
falling low to CS returning high. Data loads into the shift
register on the rising edge of SCLK. Once CS returns
high, data transfers from the shift register into the
appropriate internal register.
+13.4ꢃ0 to +4ꢀ0 single supply ꢁ0
ꢂ for the current
DDI
output ꢁsee Table 16ꢂ. The +4.750 to +5.250 digital sup-
ply ꢁ0 ꢂ powers the digital circuitry and 0 pow-
CC
DDCORE
ers the rest of the internal analog circuitry. A buffered
reference input accepts a +4.ꢀ960 reference voltage.
The LDAC and CLR inputs asynchronously update the
DAC outputs. CLR sets the DAC code to the value
stored in the clear register ꢁsoftware clearꢂ, or to zero
scale ꢁhardware clearꢂ. The FAULT output asserts for
an open-circuit current output, a short-circuit voltage
output, or a clear state condition when CLR is low. The
power-on reset circuitry guarantees the outputs remain
off at power-up and all register bits are set to zero to
ensure a glitchless power-up sequence.
When reading data, write an ꢃ-bit command byte and
16 data bits at DIN. On the following 24-bit sequence,
read out the shift register’s contents ꢁcommand byte
and the 16 data bitsꢂ at DOUT ꢁsee Figure 5ꢂ. Data tran-
sitions at DOUT on the falling edge of SCLK. While
reading data at DOUT on the second 24-bit sequence,
load another command byte and 2 data bytes at DIN or
write a no-operation command. DOUT three-states
when CS is high. The DAC outputs update on the rising
edge of CS after writing to the DAC register or by
pulling LDAC low.
A 1ꢀMHz SPI-/QSPI-/MICROWIRE-compatible serial
interface programs the DAC outputs and configures the
device. The DOUT output allows shift-register reads or
daisy chaining of several devices. The double-buffered
interface includes an input register and a DAC register.
Use software commands or the asynchronous LDAC
input to transfer the input register contents to the DAC
register and update the DAC outputs.
Daisy chain multiple devices by connecting the first
DOUT to the second DIN, and so forth. Daisy chaining
allows communication with multiple MAX5661 devices
using single CS and SCLK signals. See the Daisy
Chaining Multiple MAX5661 Devices section.
4-Wire SPI-Compatible Serial Interface
The MAX5661 communicates through a serial interface
compatible with SPI, QSPI, and MICROWIRE devices.
For SPI, ensure that the SPI bus master ꢁtypically a
______________________________________________________________________________________ 19
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
CS
SCLK
MAX561
DIN
C7
c7
C6
C5
C4
D3
D2
D1
D0
DOUT
c6
c5
c4
d3
d2
d1
d0
C7
BITS WITH CAPITAL LETTERS REPRESENT DATA BEING WRITTEN TO THE SHIFT REGISTER.
BITS WITH LOWERCASE LETTERS REPRESENT DATA IN THE SHIFT REGISTER FROM THE PREVIOUS 24-BIT CYCLE.
Figure 2. MICROWIRE- or SPI-Interface Timing Diagram ꢁCPOL = CPHA = ꢀꢂ
CS
SCLK
DIN
C7
C6
C5
C4
D3
D2
D1
D0
DOUT
p
c7
c6
c5
c4
d3
d2
d1
d0
p IS DATA LEFT FROM THE PREVIOUS INSTRUCTION CYCLE.
BITS WITH CAPITAL LETTERS REPRESENT DATA BEING WRITTEN TO THE SHIFT REGISTER.
BITS WITH LOWERCASE LETTERS REPRESENT DATA IN THE SHIFT REGISTER FROM THE PREVIOUS 24-BIT CYCLE.
Figure 3. SPI-Interface Timing Diagram ꢁCPOL = CPHA = 1ꢂ
±0 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Table 1. Input Command Bits
±4-BIT SEꢁIAL INPUT WOꢁD
COMMAND BYTE
DATA BITS
MSB
LSB
C7 C6 C5 C4 C3 C2 C1 Cꢀ D15 D14 D13 D12 D11 D1ꢀ D9 Dꢃ D7 D6 D5 D4 D3 D2 D1 Dꢀ
Table ±. ꢁegister Description
COMMAND BITS
OPEꢁATION
C7
X
C6
X
C2
X
C4
X
C3
ꢀ
C±
ꢀ
C1
ꢀ
C0
ꢀ
No operation. Transfer shift register’s data to DOUT.
Write control register.
X
X
X
X
ꢀ
ꢀ
ꢀ
1
X
X
X
X
ꢀ
ꢀ
1
ꢀ
Read control register.
X
X
X
X
ꢀ
ꢀ
1
1
Load input register. DAC register unchanged.
Load DAC and input register.
X
X
X
X
ꢀ
1
ꢀ
ꢀ
Load DAC register. Transfer input register data to DAC
register. DAC outputs update on CS’s rising edge.
X
X
X
X
ꢀ
1
ꢀ
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ꢀ
ꢀ
1
1
1
1
1
ꢀ
ꢀ
1
1
1
ꢀ
ꢀ
1
ꢀ
1
ꢀ
1
1
Write clear register.
Read input register.
Read DAC register.
Read clear register.
No operation. Transfer shift register’s data to DOUT.
X = Don’t care. All other commands are reserved for factory use. Do not use.
ꢁegister Descriptions
The MAX5661 communicates between its internal regis-
ters and the external bus lines through the 4-wire
SPI-/QSPI-/MICROWIRE-compatible serial interface.
Table 1 details the command bits ꢁC7–Cꢀꢂ and the data
bits ꢁD15–Dꢀꢂ of the serial input word. Tables 2 and 3
detail the command byte and the subsequent register
accessed. Tables 4–ꢃ detail the various read/write
internal registers and their power-on reset states. When
updating the DAC register, allow 2µs before sending
the next command.
mode, and set the current-output range. The control
register also initializes the clear and fault modes. Set
the command byte to ꢀxꢀ1 to write to the control regis-
ter. Set the command byte to ꢀxꢀ2 to read from the
control register. Write or read data bits D15–D5. D4–Dꢀ
are don’t-care bits for a write operation. D4, D3, and D2
are read-only bits. D1 and Dꢀ are don’t-care bits for a
read operation ꢁsee Table 4ꢂ.
Set the OUT0ON bit ꢁD15ꢂ to 1 to enable the OUT0
DAC voltage output. Set the OUTION bit ꢁD14ꢂ to 1 to
enable the OUTI DAC current output. Always set bit
D13 to ꢀ. Set the B/U bit ꢁD12ꢂ to determine whether the
OUT0 output operates in bipolar mode ꢁB/U = ꢀꢂ or
unipolar mode ꢁB/U = 1ꢂ.
Control ꢁegister (ꢁeadRWrite)
Write to the control register to enable the current or volt-
age output, set the voltage output for unipolar or bipolar
______________________________________________________________________________________ ±1
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Table 3. ꢁegister Bit Descriptions
COMMAND BYTE
1STDATA BYTE
2NDDATA BYTE
OPERATION
DESCRIPTION
C7
C6
C5
C4
C3
C2
C1
C0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data in shift register
before CS driven high and
command executed
X
X
X
X
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
No operation.
Transfer shift-
register data
to DOUT.
Data in shift register
after CS driven high and
command executed
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
X
X
X
X
X
X
X
X
1
0
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAX561
No operation.
Transfer shift-
register data
to DOUT.
Data in shift register
after CS driven high and
command executed
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
X
X
X
X
X
X
0
0
0
0
1
1
1
0
1
0
X
X
Write control
register
Data in shift register
after CS driven high and
command executed
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
Read control
register
Data in shift register
after CS driven high and
command executed
Same as line above.
Data in shift register
before CS driven high and
command executed
X
X
0
MSB <-- 16-Bit DAC Data --> LSB
Load input
register from shift
register. DAC
Data in shift register
after CS driven high and
command executed
register unchanged.
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
MSB <-- 16-Bit DAC Data --> LSB
X
X
X
X
X
X
X
X
0
0
1
1
0
0
0
1
Load input
register and DAC
register from shift
register.
Data in shift register
after CS driven high and
command executed
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Load DAC register
from input
Data in shift register
after CS driven high and
command executed
register
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
X
X
X
X
X
X
X
X
0
0
1
1
1
1
0
1
MSB <-- 16-Bit Clear-Register Data --> LSB
Write clear
register
Data in shift register
after CS driven high and
command executed
Same as line above. Shift-register data not changed by this operation.
Data in shift register
before CS driven high and
command executed
X
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Read input register
Data in shift register
after CS driven high and
command executed
Same as line above.
MSB <-- 16-Bit Input-Register Data --> LSB
Data in shift register
before CS driven high and
command executed
X
X
X
X
X
X
X
X
1
0
0
0
0
0
1
0
1
0
X
X
X
X
X
Read DAC
register
Data in shift register
after CS driven high and
command executed
Same as line above.
MSB <-- 16-Bit DAC-Register Data --> LSB
Data in shift register
before CS driven high and
command executed
X
X
1
X
X
X
X
X
Read clear
register
Data in shift register
after CS driven high and
command executed
Same as line above.
MSB <-- 16-Bit DAC Clear Register Data --> LSB
Data in shift register
before CS driven high and
command executed
X
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
Write full-scale
output trim
register
Data in shift register
after CS driven high and
command executed
Same as line above.
X
±± _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
DIN CLOCKED IN ON THE
SCLK RISING EDGE
WRITE COMMAND EXECUTED
CS
SCLK
DIN
C7
C6
C5
C4
C0
D15
D14
D13
D0
Figure 4. Write Timing
READ COMMAND EXECUTED
CS
SCLK
DIN
C7
C6
C5
C4
C0
D15
D14
D13
D0
DOUT
DOUT READY
CS
SCLK
DIN
X
X
X
X
X
X
X
X
X
DOUT
C7
C6
C5
C4
C0
D15
D14
D13
D0
DOUT TRANSITIONS ON THE FALLING SCLK EDGE
X = DON'T CARE.
Figure 5. Read Timing
functionality. Set the CLRFLAGEN bit ꢁD5ꢂ high to acti-
vate the FAULT output when the MAX5661 is in the
clear state.
Set the OUTI4/0EN bit ꢁD11ꢂ low to enable the OUTI4/0
hardware input. Set the I4TO2ꢀBIT bit ꢁD1ꢀꢂ high to
select the current-output range through the software.
Set the CLREN bit ꢁD9ꢂ low to enable the CLR hardware
input. Set the CLRMODE bit ꢁDꢃꢂ high to force the out-
put to the value in the clear register or the zero state
when the CLR hardware input is pulled low. Set the
RCLR bit ꢁD7ꢂ high to remain in the clear state. Set the
FAULTEN bit ꢁD6ꢂ high to enable the FAULT output
Bits D4, D3, and D2 are read-only bits. The FAULT0 bit
ꢁD4ꢂ is set to 1 when OUT0 is short circuited. The
FAULTI bit ꢁD3ꢂ is set to 1 when OUTI is open circuited.
The CLEARST bit ꢁD2ꢂ is set to 1 when the MAX5661 is
in the clear state.
______________________________________________________________________________________ ±3
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Table 4. Control ꢁegister (ꢁeadRWrite)
DATA
BIT
ꢁESET
STATE
BIT NAME
FUNCTION
OUT0ON
OUTION
—
D15
D14
D13
ꢀ
ꢀ
ꢀ
DAC OUT0 output enable bit. Set to 1 to enable the OUT0 output.
DAC OUTI output enable bit. Set to 1 to enable the OUTI output.
Reserved. Always set to ꢀ.
0oltage-output unipolar/bipolar mode select bit. Set to ꢀ ꢁdefault power-up stateꢂ to select the
bipolar output range ꢁ 1ꢀ.4ꢃ0ꢂ. Set to 1 to select the unipolar output range ꢁꢀ to +1ꢀ.4ꢃ0ꢂ.
MAX561
B/U
D12
ꢀ
OUTI4/0 enable bit. Set to ꢀ ꢁdefault power-up stateꢂ to enable the OUTI4/0 hardware input. Set
to 1 to disable the OUTI4/0 hardware input, thereby controlling the current-output range
through software commands.
OUTI4/0EN
D11
ꢀ
OUTI current range bit. Set to ꢀ to set the OUTI current range from ꢀ to 2ꢀmA. Set to 1 to set
the OUTI current range from 4–2ꢀmA.
I4TO2ꢀBIT
D1ꢀ
D9
ꢀ
ꢀ
Clear enable bit. Set to ꢀ to enable the external CLR input. Set to 1 to disable the external CLR
input.
CLREN
Clear mode bit. Set to 1 and drive the external CLR input low to force the DAC output to the
value stored in the clear register. Set to ꢀ and drive the external CLR input low to force the DAC
output to ꢀ0 in voltage mode or ꢀmA/4mA depending on output-current mode.
CLRMODE
RCLR
Dꢃ
D7
ꢀ
ꢀ
Remain in clear bit. Set to 1 to remain in the clear state. The RCLR bit determines the steps
required to exit the clear state. See the CLR Input section.
Fault output enable. Set to 1 to enable the FAULT output functionality. Set to ꢀ to disable the
FAULT output functionality. In single supply mode, set to ꢀ to disable the FAULT pin function.
FAULTEN
D6
D5
ꢀ
ꢀ
CLRFLAGEN
Clear flag enable. Set to 1 to enable the FAU LT output to report when the device is in the clear state.
Output voltage fault bit ꢁread onlyꢂ. The FAULT0 bit is set to 1 when FAULT triggers due to an
OUT0 short-circuit condition. The FAULT0 bit is a don’t-care bit for control-register write
commands. In single supply mode, FAULT0 = 1 must be ignored.
FAULT0
FAULTI
D4
D3
ꢀ
ꢀ
Output-current fault bit ꢁread onlyꢂ. The FAULTI bit is set to 1 when FAULT triggers due to an
OUTI open-circuit condition. The FAULTI bit is a don’t-care bit for the control register write
commands. In single supply mode, monitor the FAULTI bit for any FAULTI condition.
Clear state bit ꢁread onlyꢂ. The CLEARST bit is set to 1 when CLR is low and CLREN = ꢀ. The CLRST
bit is a don’t-care bit for control register write commands.
CLEARST
X
D2
ꢀ
ꢀ
D1, Dꢀ
Not used.
±4 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Input ꢁegister (ꢁeadRWrite)
Write to the input register to store the DAC code.
Transfer the value written to the input register to the
DAC register by pulling the LDAC input low or by writ-
ing to the load DAC register ꢁꢀxꢀ5ꢂ. Set the command
byte to ꢀxꢀ3 to write to the input register. Set the com-
mand byte to ꢀxꢀ7 to read from the input register. Bits
D15–Dꢀ contain the straight binary data ꢁsee Table 5ꢂ.
put. Set the command byte to ꢀxꢀ5 to write to the load
DAC register. Bits D15–Dꢀ are don’t-care bits.
Clear ꢁegister (ꢁeadRWrite)
Write to the clear register to set the DAC output value
when the CLR hardware input is pulled low ꢁforcing the
MAX5661 into the clear stateꢂ. Set the command byte to
ꢀxꢀ6 to write to the clear register. Set the command
byte to ꢀxꢀ9 to read the clear register. Bits D15–Dꢀ
contain the straight binary data ꢁsee Table 7ꢂ.
DAC ꢁegister (ꢁeadRWrite)
Write to the DAC register to update the OUT0 and OUTI
outputs after CS returns high. Set the command byte to
ꢀxꢀ4 to write to the DAC register. Set the command
byte to ꢀxꢀꢃ to read from the DAC register. Bits
D15–Dꢀ contain the straight binary data ꢁsee Table 6ꢂ.
No Operation
Set the command byte to ꢀxꢀF or ꢀxꢀꢀ to perform a no-
operation command. After writing the command byte
and 2 data bytes ꢁ16 don’t-care bitsꢂ, read out the shift
register’s contents on the following 24-bit cycle.
Load DAC ꢁegister (Write)
Write to the load DAC register to transfer the input reg-
ister data to the DAC register and update the DAC out-
Table 2. Input ꢁegister (ꢁeadRWrite)
BIT NAME
DATA BIT
ꢁESET STATE
FUNCTION
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢁunipolar/currentꢂ
1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢁbipolarꢂ
IN15–INꢀ
D15–Dꢀ
IN15 is the MSB and INꢀ is the LSB. Data format is straight binary.
Table 6. DAC ꢁegister (ꢁeadRWrite)
BIT NAME
DATA BIT
ꢁESET STATE
FUNCTION
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢁunipolar/currentꢂ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢁbipolarꢂ
DAC15 is the MSB and DACꢀ is the LSB. Data format is straight
binary.
DAC15–DACꢀ
D15–Dꢀ
Table 7. Clear ꢁegister (ꢁeadRWrite)
BIT NAME
DATA BIT
ꢁESET STATE
FUNCTION
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢁunipolar/currentꢂ
1ꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢁbipolarꢂ
CLR15 is the MSB and CLRꢀ is the LSB. Data format is straight
binary.
CLR15–CLRꢀ
D15–Dꢀ
Table ꢂ. Full-Scale Output Trim ꢁegister (Write)
BIT NAME
DATA BIT
ꢁESET STATE
FUNCTION
FS_EN +
FS_BIT9–
FS_BITꢀ
FS_EN ꢁD15ꢂ enables the full-scale output adjustment feature. D9
is the MSB and Dꢀ is the LSB. D9 is straight binary, Dꢃ–Dꢀ are
inverted binary.
D9–Dꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ
______________________________________________________________________________________ ±2
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Full-Scale Output
Current Trim Register (Write)
Write to the full-scale output trim register to adjust the
output voltage or current 25%. Set command bits to
ꢀxꢀ6 to write to the output trim register. Bit 15 enables
the output trim register. Bits D9–Dꢀ program the 1ꢀ-bit
trim DAC ꢁTable ꢃꢂ.
MAX561
Table 9. N to D: Full-Scale Output Trim ꢁegister Bits Map
N9
Nꢂ
N7
N6
N2
N4
N3
N±
N1
N0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 10. Full-Scale Output Variation ꢀs.
N and B
BITS (B) TO NUMERICAL (N)
TRANSFER FUNCTION
MAX5661 fig06
1100
1000
900
800
700
600
500
400
300
200
100
0
DECIMAL
VALUE (N)
BIT DECIMAL
VALUE (B)
+25%
5 CHANGE
ꢀ
511
255
ꢀ
-25
-12.5
ꢀ-
+12.5%
0%
256
511
512
767
1ꢀ23
1ꢀ23
76ꢃ
512
ꢀ+
+12.5
+25
-12.5%
-25%
0
100 200 300 400 500 600 700 800 9001000 1100
BITS (B)
Figure 6. Transfer Function of Bits ꢁBꢂ to Numerical ꢁNꢂ
Representation
±6 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
LDAC
SOFTWARE
LOAD DAC
CONTROL
REGISTER
FULL-SCALE
OUTPUT ADJUST
FULL-SCALE
ADJUST
CS
REGISTER
INPUT
REGISTER
SCLK
SHIFT
REGISTER
OUTI
DAC
REGISTER
TO OUTPUT
CIRCUITRY
DAC
DIN
OUTV
2-TO-1
MUX
DOUT
CLEAR
REGISTER
MAX5661
Figure 7. Functional Diagram
Reference Input
Connect an external voltage reference in the +40 to
+4.20 range through a 1kΩ series resistor to
the buffered REF input. Use a high-accuracy, low-
noise +4.ꢀ960 voltage reference such as the
MAX6126AASA41 ꢁ3ppm/°C temperature drift and
ꢀ.ꢀ2% initial accuracyꢂ for best 16-bit static accuracy.
REF does not accept AC signals. See Table 17 for a list-
ing of +4.ꢀ960 references.
t
LDL
LDAC
± 2 LSB
LDAC Input
The MAX5661 features an active-low load DAC ꢁLDACꢂ
logic input that allows asynchronous updates to the
t
DELAY
OUT_
DAC outputs. Drive LDAC high to 0
during normal
CC
operation while controlling the MAX5661 using only the
serial interface. Drive LDAC low to update the DAC out-
put with the input register data. Hold LDAC low to make
the input register transparent and immediately update
the DAC output with the input register data. Figure ꢃ
shows the LDAC timing with respect to OUT_.
Figure ꢃ. LDAC Timing
______________________________________________________________________________________ ±7
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
With the RCLR bit set to ꢀ, exit the clear state one of
three ways:
1ꢂ Set the CLREN bit high.
CLR Input
The active-low external CLR input asynchronously sets
the DAC code to the value in the clear register ꢁsoftware
clearꢂ or to the zero state ꢁhardware clearꢂ, depending
on the control register’s CLRMODE bit setting ꢁsee
Tables 4 and 11ꢂ. Set the CLRMODE bit to 1 and drive
external CLR low to force the output to the value stored
in the clear register. Set the CLRMODE bit to ꢀ and
drive the external CLR input low to force the output to
the zero state. The zero state value is ꢀmA in ꢀ to 2ꢀmA
current mode, 3.97mA in 4–2ꢀmA current mode, or ꢀ0
in voltage mode ꢁunipolar or bipolarꢂ.
2ꢂ Pull the external CLR input high.
3ꢂ Initiate a power-on reset ꢁPORꢂ.
FAULT Output
The open-drain active-low FAULT output asserts low for
a current-output open circuit or dropout condition, for a
voltage-output short circuit, or when the MAX5661 is in
the clear state ꢁsee the CLR Input sectionꢂ.
MAX561
Enable and disable the FAULT output with the control
register’s FAULTEN and CLRFLAGEN bits ꢁsee Tables
4, 12, and Figure 9ꢂ. Set the FAULTEN bit to 1 to enable
the FAULT output to report fault conditions on OUT0
and OUTI. Set FAULTEN to ꢀ to disable the FAULT out-
put for fault conditions on OUT0 and OUTI. Set the
CLRFLAGEN bit to 1 to enable the FAULT output
to report when the device is in the clear state. Set
CLRFLAGEN to ꢀ to disable a hardware indication
of the clear state. The FAULT output asserts low if
CLRFLAGEN = 1 and CLEARST = 1.
Disable the external CLR input functionality by setting
the control register’s CLREN bit to 1. Set the CLREN bit
to ꢀ to enable the external CLR input functionality.
After setting the CLREN bit to ꢀ, force the external CLR
input low to set the MAX5661 into the clear state. The
control register’s read-only CLEARST bit is set to 1 while
in the clear state. The RCLR ꢁremain in clearꢂ bit deter-
mines the steps required to exit the clear state.
With the RCLR bit set to 1, exit the clear state in one of
three ways:
1ꢂ Pull the external CLR input high and then write to
the DAC register ꢁꢀxꢀ4ꢂ or the load DAC register
ꢁꢀxꢀ5ꢂ or force LDAC low.
Read the control register to determine the source of
a FAULT output condition. The FAULT0 read-only bit
is set to 1 when the voltage output ꢁOUT0ꢂ is short-
circuited. The FAULTI bit is set to 1 when the current
output ꢁOUTIꢂ is open circuited or in a dropout condition
2ꢂ Pull the external CLR input high and set the RCLR
bit low.
ꢁ0
- 0
at 1.30 typꢂ. The FAULT output asserts
OUTI
DDI
low if FAULTEN is set to 1 and either the FAULT0 bit or
FAULTI bit is set to 1.
3ꢂ Initiate a power-on reset ꢁPORꢂ to reset the RCLR bit
to ꢀ.
Table 11. Hardware-Clear and Software-Clear Truth Table
CLEAꢁST BIT
(ꢁEAD)
CLꢁMODE BIT
(ꢁEADRWꢁITE)
HAꢁDWAꢁE CLEAꢁ
SOFTWAꢁE CLEAꢁ
ꢀ ꢁnot in clear stateꢂ
1 ꢁin clear stateꢂ
1 ꢁin clear stateꢂ
X
ꢀ
1
X
X
DAC code set to zero state*
—
—
DAC code set by clear register data
X = Don’t care.
*Zero state is ꢀ0 in unipolar voltage mode, -1ꢀ.4ꢃ0 in bipolar voltage mode, and ꢀmA/4mA depending on output-current mode.
±ꢂ _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
FAULT_AT_
OUTPUT
INTERNAL
FAULT SIGNAL
FAULTEN BIT
X
0
1
0
X
1
0
0
1
INTERNAL FAULT SIGNAL
FAULTEN BIT
FAULT
OUTPUT
FAULT_AT_OUTPUT
(INTERNALLY
GENERATED,
INTERNAL
FAULT SIGNAL
CLEAR_
FLAG
FAULT
OUTPUT
FAULTI BIT
FAULTV BIT
1
X
0
X
0
0
1
CANNOT BE READ)
1
0
FAULT_AT_
OUTPUT
FAULTV BIT
FAULTI BIT
1
X
0
X
1
0
1
1
0
CLEAR_FLAG
(INTERNALLY GENERATED,
CANNOT BE READ)
CLRFLAGEN
CLEAR_
FLAG
CLRFLAGEN
BIT
CLEARST
BIT
CLEARST BIT
0
X
1
X
0
1
0
0
1
X = DON'T CARE.
Figure 9. FAULT Output Logic Diagram
Table 1±. FAULT Output Truth Table
OUTV SHOꢁT
CIꢁCUITED
OUTI OPEN CIꢁCUITED
Oꢁ IN DꢁOPOUT
CLEAꢁST
BIT
FAULTEN BIT
CLꢁFLAGEN BIT
FAULT OUTPUT
No
No
X
No
No
X
ꢀ
X
1
ꢀ
X
X
X
X
X
X
ꢀ
1
ꢀ
1
X
ꢀ
1
X
X
ꢀ
X
High
High
Low
High
Low
High
Low
X
X
No
X
Yes
X
Yes
No
X = Don’t care. Only one output ꢁOUT0 or OUTIꢂ is active at a time.
______________________________________________________________________________________ ±9
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
The 0
digital supply powers the CNF1, CNFꢀ, and
Output Configurations
The CNFꢀ, CNF1, and OUTI4/0 hardware inputs deter-
mine whether the hardware or software controls the
MAX5661 DAC outputs ꢁsee Table 13ꢂ. The CNFꢀ and
CNF1 inputs enable and disable the DAC outputs or
allow software control of the outputs ꢁsee Table 14ꢂ.
The OUTI4/0 input sets the current range of the OUTI
output. Hardware inputs take precedence over the soft-
ware commands.
CC
OUTI4/0 inputs. If 0
= ꢀ0, the DAC outputs enter the
CC
zero state and all register bits are set to ꢀ. The zero
state of the voltage output ꢁOUT0ꢂ is ꢀ0. The zero state
of the current output ꢁOUTIꢂ is ꢀmA when OUTI4/0 =
AGND or 4mA when OUTI4/0 = 0
.
DDI
MAX561
Table 13. Output Configuration
CONTꢁOL
SIGNAL
HAꢁDWAꢁE
INPUTRSOFTWAꢁE BIT
DESCꢁIPTION
DETAILS
CNF1, CNFꢀ:
ꢀꢀ = both outputs disabled
ꢀ1 = OUTI active, set to ꢀ to 2ꢀmA range
1ꢀ = OUT0 active, set to bipolar mode
11 = outputs controlled by serial interface
CNF1
CNFꢀ
Hardware input
Hardware input
Enables/disables the DAC
OUT0 and OUTI outputs.
Set the OUTI4/0EN bit to ꢀ ꢁdefault power-up stateꢂ to enable
the OUTI4/0 hardware input. Connect the OUTI4/0 hardware
input to AGND to set the OUTI current range to ꢀ to 2ꢀmA.
OUTI4/0
Hardware input
Sets the OUTI current range.
Connect the OUTI4/0 hardware input to 0
to set the OUTI
DDI
current range to 4–2ꢀmA. Set the OUTI4/0EN bit to 1 to
disable the OUT14/0 hardware input. Connect OUTI4/0 to
AGND when controlling the current output through software.
Set the OUTI4/0EN bit to ꢀ ꢁdefault power-up stateꢂ to
enable the OUTI4/0 hardware input. Set to 1 to disable the
OUTI4/0 hardware input.
Enables and disables the
OUTI4/0EN
Software bit
Software bit
OUTI4/0 input.
When the CNF1 and CNFꢀ hardware inputs are high, the
OUTION and OUT0ON bits control the DAC output OUTI
and OUT0 settings.
OUT0ON, OUTION:
ꢀꢀ = both outputs powered down
ꢀ1 = OUTI active
OUT0ON
Enables and disables the
DAC OUT0 and OUTI
outputs.
OUTION
Software bit
1ꢀ = OUT0 active
11 = both outputs powered down
Sets the voltage output to
unipolar mode or bipolar
mode.
Set B/U to ꢀ to set the OUT0 output to bipolar mode
ꢁ 1ꢀ.4ꢃ0ꢂ. Set B/U to 1 to set the OUT0 output to unipolar
mode ꢁꢀ to +1ꢀ.4ꢃ0ꢂ.
B/U
Software bit
Software bit
Set I4TO2ꢀBIT to ꢀ to set the OUTI current range from ꢀ to
2ꢀmA. Set I4TO2ꢀBIT to 1 to set the OUTI current range
from 4–2ꢀmA.
Sets the OUTI current range
through software.
I4TO2ꢀBIT
30 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
CNF0RCNF1 Hardware Inputs
The CNFꢀ and CNF1 inputs enable the DAC’s voltage
ꢁOUT0ꢂ or current ꢁOUTIꢂ outputs. Drive CNFꢀ and
CNF1 low to disable both the OUT0 and OUTI outputs.
Drive CNFꢀ high and CNF1 low to enable the OUTI out-
put. Drive CNFꢀ low and CNF1 high to enable the
OUT0 output. Drive CNFꢀ and CNF1 high to control the
OUT0 and OUTI outputs through the serial interface.
Table 14 summarizes the output behavior when pro-
grammed by the CNFꢀ/CNF1 hardware inputs.
OUTV Voltage-Output Configuration
Drive CNFꢀ low and CNF1 high to enable the OUT0
output through the hardware ꢁsee Table 14ꢂ.
Alternatively, drive CNFꢀ and CNF1 high to control
OUT0 with the serial interface. With CNF1 and CNFꢀ
high, the control register’s OUT0ON bit enables the
OUT0 output. Set OUT0ON to 1 to enable the OUT0
output. Set OUT0ON to ꢀ ꢁdefault power-up stateꢂ to
disable the OUT0 output.
The OUT0 output derives power from 0
, 0
, and
DD0 SS0
ꢁ+13.4ꢃ0 to
DD0
0
. Connect 0
to 0
DDCORE
DDCORE
OUTI Current-Output Configuration
Drive CNFꢀ high and CNF1 low to enable the OUTI out-
put through the hardware. Alternatively, drive CNFꢀ and
CNF1 high to control OUTI with the serial interface. With
CNF1 and CNFꢀ high, the control register’s
OUTION bit enables the OUTI output. Set OUTION to 1
to enable the OUTI output. Set OUTION to ꢀ ꢁdefault
power-up stateꢂ to disable the OUTI output.
+15.750ꢂ when using the OUT0 output. Always connect
a negative supply to 0
Table 16ꢂ.
ꢁ-13.4ꢃ0 to -15.750ꢂ ꢁsee
SS0
The control register’s B/U bit sets OUT0 for bipolar or
unipolar mode. Set B/U to ꢀ ꢁdefault power-up stateꢂ to
select the bipolar output range ꢁ 1ꢀ.4ꢃ0ꢂ. Set B/U to 1
to select the unipolar output range ꢁꢀ to +1ꢀ.4ꢃ0ꢂ.
The OUTI current output derives power from 0
and
DDI
Output Transfer Functions
The DAC output voltage/current is a function of the vari-
ous hardware control inputs and digital inputs in the
control register ꢁsee Table 13ꢂ. The transfer functions
below assume that the outputs are on, and a reference
voltage of +4.ꢀ960 is applied to the reference input. For
the voltage output, the sense input is at the same
potential as the DAC output ꢁOUT0 = S0P and AGND =
S0Nꢂ. Table 15a details the bipolar output voltage
transfer function. Table 15b details the unipolar output
voltage transfer function. Table 15c details the ꢀ to
2ꢀmA current-range transfer function. Table 15d details
the 4mA to 2ꢀmA current-range transfer function.
0
0
ꢁ+13.4ꢃ0 to +4ꢀ0ꢂ. Connect 0
to
DDCORE
DDCORE
when using the OUTI output.
DDI
The control register’s OUTI4/0EN bit ꢁsee Tables 4 and
13ꢂ determines whether the OUTI4/0 hardware input or
the control register’s I4TO2ꢀBIT bit controls the OUTI
current range. Set the OUTI4/0EN bit to ꢀ ꢁdefault
power-up stateꢂ to control the current range through the
OUTI4/0 hardware input. Connect the OUTI4/0 hard-
ware input to AGND to select the ꢀ to 2ꢀmA mode.
Connect the OUTI4/0 hardware input to 0
to select
DDI
the 4–2ꢀmA mode.
Set the OUTI4/0EN bit to 1 to allow software control of
the OUTI current range through the I4TO2ꢀBIT bit ꢁsee
Table 13ꢂ. Set I4TO2ꢀBIT to ꢀ to select the ꢀ to 2ꢀmA
mode. Set I4TO2ꢀBIT to 1 to select the 4–2ꢀmA mode.
Table 14. CNF1RCNF0 Hardware Settings
CNF1
DGND
DGND
CNF0
OUTV, OUTI SETTING
DGND
Both DAC outputs disabled.
OUTI enabled. OUT0 disabled.
OUT0 enabled. OUTI disabled.
0
CC
0
0
DGND
CC
CC
0
DAC outputs controlled by the serial interface.
CC
______________________________________________________________________________________ 31
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Table 12a. Bipolar Voltage Output
DAC CODE (DECIMAL VALUE)
OUTPUT VOLTAGE (V)
1ꢀ.479ꢃ4
1ꢀ.234ꢃ5
1ꢀ.23453
1ꢀ.23421
5.1175ꢃ5
5.117266
5.116946
1.ꢀ23773
1.ꢀ23453
1.ꢀ23133
ꢀ.ꢀꢀꢀ32
ꢁANGE
65535
64769
6476ꢃ
64767
4ꢃ769
4ꢃ76ꢃ
4ꢃ767
35969
3596ꢃ
35967
32769
3276ꢃ
32767
29569
2956ꢃ
29567
16769
1676ꢃ
16767
769
Overrange
Overrange
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Underrange
MAX561
ꢀ
-ꢀ.ꢀꢀꢀ32
-1.ꢀ2313
-1.ꢀ2345
-1.ꢀ2377
-5.11695
-5.11727
-5.11759
-1ꢀ.2342
-1ꢀ.2345
-1ꢀ.2349
-1ꢀ.4ꢃꢀ2
76ꢃ
767
ꢀ
Underrange
Table 12b. Unipolar Voltage Output
DAC CODE (DECIMAL VALUE)
OUTPUT VOLTAGE (V)
1ꢀ.4ꢃ
ꢁANGE
65535
64ꢀꢀ1
64ꢀꢀꢀ
32ꢀꢀ1
32ꢀꢀꢀ
31999
64ꢀ1
64ꢀꢀ
6399
1
Overrange
1ꢀ.23469
1ꢀ.23453
5.117425
5.117266
5.1171ꢀ6
1.ꢀ23613
1.ꢀ23453
1.ꢀ23293
ꢀ.ꢀꢀꢀ16
Overrange
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
ꢀ
ꢀ
3± _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Table 12c. 0 to ±0mA Current Output
EXTENSION OF OUTPUT
CUꢁꢁENT LINEAꢁ ꢁANGE
(mA)
ACTUAL OUTPUT CUꢁꢁENT
DAC CODE (DECIMAL)
ꢁANGE
(mA)
65535
64ꢀꢀ1
64ꢀꢀꢀ
63999
32ꢀꢀ1
32ꢀꢀꢀ
31999
12ꢃꢀ1
12ꢃꢀꢀ
12799
97
2ꢀ.4496ꢃꢃ
19.97ꢀ313
19.97ꢀꢀꢀꢀ
19.9696ꢃꢃ
9.97ꢀ313
9.97ꢀꢀꢀꢀ
9.9696ꢃꢃ
3.97ꢀ313
3.97ꢀꢀꢀꢀ
3.9696ꢃꢃ
ꢀ.ꢀꢀꢀ313
ꢀ.ꢀꢀꢀꢀꢀꢀ
ꢀ.ꢀꢀꢀꢀꢀꢀ
ꢀ.ꢀꢀꢀꢀꢀꢀ
ꢀ.ꢀꢀꢀꢀꢀꢀ
ꢀ.ꢀꢀꢀꢀꢀꢀ
ꢀ.ꢀꢀꢀꢀꢀꢀ
ꢀ.ꢀꢀꢀꢀꢀꢀ
Overrange
Overrange
2ꢀ.4496ꢃꢃ
19.97ꢀ313
19.97ꢀꢀꢀꢀ
19.9696ꢃꢃ
9.97ꢀ313
9.97ꢀꢀꢀꢀ
9.9696ꢃꢃ
3.97ꢀ313
3.97ꢀꢀꢀꢀ
3.9696ꢃꢃ
ꢀ.ꢀꢀꢀ313
ꢀ.ꢀꢀꢀꢀꢀꢀ
-ꢀ.ꢀꢀꢀ313
-ꢀ.ꢀꢀ5ꢀꢀꢀ
-ꢀ.ꢀ1125ꢀ
-ꢀ.ꢀ175ꢀꢀ
-ꢀ.ꢀ2ꢀ625
-ꢀ.ꢀ3ꢀꢀꢀꢀ
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Underrange
96
95
ꢃꢀ
Underrange
6ꢀ
Underrange
4ꢀ
Underrange
3ꢀ
Underrange
ꢀ
Underrange
Table 12d. 4–±0mA Current Output
DAC CODE (DECIMAL)
OUTPUT CUꢁꢁENT (mA)
ꢁANGE
65535
64ꢀꢀꢀ
63634
6ꢀꢀꢀꢀ
5ꢀꢀꢀꢀ
4ꢀꢀꢀꢀ
3ꢀꢀꢀꢀ
2ꢀꢀꢀꢀ
16ꢀꢀꢀ
5ꢀꢀꢀ
5ꢀꢀ
2ꢀ.4496ꢃꢃ
2ꢀ.ꢀ6369ꢀ
19.971655
19.ꢀ57ꢃ35
16.543196
14.ꢀ2ꢃ556
11.513917
ꢃ.99927ꢃ
7.993423
5.22732ꢀ
4.ꢀ95732
4.ꢀ29ꢃ4ꢃ
4.ꢀ2ꢀ293
3.97ꢀꢀꢀꢀ
3.97ꢀꢀꢀꢀ
3.97ꢀꢀꢀꢀ
3.97ꢀꢀꢀꢀ
3.97ꢀꢀꢀꢀ
Overrange
Overrange
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Nominal range
Underrange
Underrange
Underrange
Underrange
Underrange
Underrange
23ꢃ
2ꢀꢀ
1ꢀꢀ
ꢃꢀ
6ꢀ
3ꢀ
ꢀ
______________________________________________________________________________________ 33
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Measuring Zero-Code Current
(0 to 20mA Mode)
Daisy Chaining Multiple MAX5661 Devices
In standard SPI-/QSPI-/MICROWIRE-compatible sys-
tems, a microcontroller ꢁµCꢂ communicates with its
slave devices through a 3- or 4-wire serial interface.
The typical interface includes a chip select signal ꢁCSꢂ,
a serial clock ꢁSCLKꢂ, a data input signal ꢁDINꢂ, and
sometimes a data signal output ꢁDOUTꢂ. In this system,
the µC allots an independent chip-select signal to each
slave device so that they can be addressed individually
ꢁsee Figure 1ꢀꢂ. Only the slaves with their CS inputs
asserted low acknowledge and respond to the activity
on the serial clock and data lines. This is simple to
implement when there are very few slave devices in the
system. An alternative programming method is daisy
chaining. Daisy chaining, in serial-interface applica-
tions, is a method of propagating commands through
multiple devices connected in series ꢁsee Figure 11ꢂ.
Daisy chaining reduces CS and DIN line routing, and
saves board space when using the MAX5661.
After setting the MAX5661 for ꢀ to 2ꢀmA current-range
mode, determine the LSB size as follows:
1ꢂ Measure I
at full scale ꢁFSꢂ.
OUT
2ꢂ Measure I
at code 192.
OUT
3ꢂ Measure I
at code 193:
OUT
MAX561
I
at FS − I
at 192
OUT
OUT
I
LSB =
16
ꢁ2 − 1ꢂ − 192
If I
ꢁcode 193ꢂ - I
ꢁcode 192ꢂ is inside the linear region of the I
fer curve.
ꢁcode 192ꢂ > ꢀ.5 I , I
LSB OUT
OUT
OUT
trans-
OUT
Obtain the straight-line equation from I
ꢁFSꢂ and
OUT
I
ꢁ192ꢂ and substituting code ꢀ for I
ꢁzero scaleꢂ
OUT
in the equation:
OUT
Daisy chain multiple MAX5661 devices by connecting
the DOUT of one device to the DIN of the next. Connect
the SCLK of all devices to a common clock and connect
the CS from all devices to a common chip-select line.
Data shifts out of DOUT 24.5 clock cycles after it is shift-
ed into DIN on the falling edge of SCLK. Hold CS low
until each slave in the chain receives its 24-bit word ꢁꢃ
command bits and 16 data bitsꢂ. In this configuration,
the µC only needs three signals ꢁCS, SCLK, and DINꢂ to
control all the slaves in the network. The SPI-/QSPI-
/MICROWIRE-compatible serial interface normally works
at up to 1ꢀMHz, but must be slowed to 6MHz if daisy
chaining. DOUT is high impedance when CS is high.
⎛
⎞
atFS −I at192
OUT
I
OUT
ꢁI−I
OUT
at192ꢂ =
x ꢁcode −192ꢂ
⎟
⎜
65535 −192
⎝
⎠
I
at ZS = ꢁI
OUT
at192 − I
OUT
at FSꢂ x ꢀ.ꢀꢀ293ꢃ3 +I
at192
OUT
OUT
The expected current is -3ꢀµA ꢁtypꢂ.
Applications Information
Power-Supply Sequencing and Bypassing
After connecting all ground inputs, apply the analog
supply voltages 0
first followed by the most positive
SS0
supply, the second most positive supply, etc. Before
applying power, connect the 0 supply to either
, as shown in Table 16, depending on
whether the current output or voltage output is used. Do
DDCORE
DD0 SS0 DDI
ꢁTable 16ꢂ. Ensure that there are no unconnected
power-supply connections when powering the
DDCORE
Figure 1ꢀ details a method of controlling multiple
MAX5661 devices using separate CS lines. This
method allows writes to and reads from each device
without shifting data through the other device’s shift
register. Figure 1ꢀ shows the FAULT outputs shorted
together. This configuration requires a read from each
device to determine which one has the fault condition
and saves an optocoupler in isolated applications. It is
not necessary to short the FAULT outputs together.
0
or 0
DD0
DDI
not apply 0
separate from the main supply
ꢂ in the preferred configuration
ꢁ0
/0
or 0
MAX5661. If 0
cannot be powered first, connect a
Schottky diode between 0
SS0
and AGND.
SS0
Table 16. Application Modes and Supply-Voltage Limits
APPLICATION MODE
0oltage from OUT0
V
V
V
V
DDCOꢁE
DDV
SSV
DDI
+13.4ꢃ0 to +15.750
-13.4ꢃ0 to -15.750
0
0
DD0
DD0
Current from OUTI
ꢁSingle Supplyꢂ
AGND
AGND
+13.4ꢃ0 to +4ꢀ0
to +4ꢀ0
0
DDI
0oltage from OUT0 and Current
from OUTI*
+13.4ꢃ0 to +15.750
-13.4ꢃ0 to -15.750
0
0
DD0
DD0
*On-the-fly switching. Only one output is active at a time.
34 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Figure 11 shows a method of daisy chaining multiple
MAX5661 devices using a single CS and SCLK line with
the FAULT outputs shorted together. Connect DOUT
from IC1 to DIN of IC2, and DOUT from IC2 to DIN of
IC3. Hold CS low for three 24-bit write cycles to load
data into all three devices. Due to the latency of read-
ing and writing to the different devices, using separate
lines for each FAULT output does not save time.
MAX5661
IC1
CS1
DIN
CS
DIN
SCLK
LDAC
CLR
SCLK
LDAC
CLR
FAULT
DOUT
MAX5661
IC2
CS2
CS
DIN
SCLK
LDAC
CLR
FAULT
DOUT
DOUT
FAULT
Figure 1ꢀ. Address Two MAX5661 Devices Through Separate CS Lines
Driving Inductive Loads from I
OUT
When driving inductive loads > 275µH with the current
output ꢁI ꢂ, connect a 1nF capacitor between 0
OUT
DDI
and I
for optimal performance.
OUT
______________________________________________________________________________________ 32
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX5661
IC1
CS
DIN
CS
DIN
SCLK
LDAC
CLR
SCLK
LDAC
CLR
MAX561
FAULT
DOUT
MAX5661
IC2
CS
DIN
SCLK
LDAC
CLR
FAULT
DOUT
MAX5661
IC3
CS
DIN
SCLK
LDAC
CLR
FAULT
DOUT
DOUT
FAULT
Figure 11. Address Three MAX5661 Devices Through Separate CS Lines
36 _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Table 17. +4.096V ꢁeference Selector Guide
INITIAL
ACCUꢁACY
(5)
SUPPLY VOLTAGE
ꢁANGE (V)
TEMPEꢁATUꢁE
DꢁIFT (ppmR°C max)
PAꢁT
FEATUꢁES
MAX6341
MAX6241
+ꢃ to +36
+ꢃ to +36
1
3
ꢀ.ꢀ2
ꢀ.ꢀ2
Ultra-low drift, 2.4µ0
output noise
P-P
Low drift, 2.4µ0
output noise
P-P
High-precision reference with temperature
sensor
MAX6174
+4.3 to +4ꢀ
3
ꢀ.ꢀ6
MAX6133_41
MAX6126_41
MAX6ꢀ43_41
MAX6143_41
MAX6ꢀ33_41
MAX6ꢀ41
+4.3 to +12.6
+4.3 to +12.6
+6 to +4ꢀ
3
ꢀ.ꢀ4
ꢀ.ꢀ2
ꢀ.ꢀ5
ꢀ.1
Ultra-low drift, µMAX®
3
Ultra-low noise, µMAX
3
High voltage, low drift
+6 to +4ꢀ
ꢃ
High precision
+4.3 to +12.6
+4.3 to +12.6
+4.3 to +12.6
+ꢃ to +4ꢀ
1ꢀ
2ꢀ
2ꢀ
2ꢀ
25
3ꢀ
3ꢀ
ꢀ.ꢀ4
ꢀ.2
1ꢀmA output current, ultra-low drift, SOT23
Low power, low drift, low dropout
5mA current output, precision SOT23
-4ꢀ°C to +125°C, 15mA output
SOT23 with shutdown
MAX6ꢀ64
ꢀ.2
MAX622ꢀ
ꢀ.1
MAX6ꢀ37_41
MAX6ꢀ34_41
MAX6ꢀ29
+4.3 to +5.5
+4.3 to +5.5
+4.3 to +12.6
ꢀ.2
ꢀ.2
Low supply current in SC7ꢀ
Ultra-low supply current, SOT23
ꢀ.15
Chip Information
PROCESS: BiCMOS
Pin Configuration
TOP VIEW
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
N.C.
OUTI
N.C.
1
2
3
4
5
6
7
8
9
48 N.C.
+
47 N.C.
46 N.C.
V
45 AGND
44 N.C.
DDI
N.C.
COMPI
N.C.
43 COMPV
42 N.C.
N.C.
41 DUTGND
40 DUTGNDS
MAX5661
OUTI4/0
N.C. 10
REF 11
39 V
DDCORE
38 N.C.
37 CLR
36 N.C.
35 DOUT
34 N.C.
33 N.C.
DACGND 12
DACGNDS 13
CNF1 14
N.C. 15
N.C. 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LQFP
µMAX is a registered trademark of Maxim Integrated Products, Inc.
______________________________________________________________________________________ 37
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Typical Operating Circuit
V
OR V
DDI
+13.48V TO +15.75V
-13.48V TO -15.75V
DDV
+4.75V TO +5.25V
+13.48V TO +40V
V
V
V
V
SSV
CC
DDCORE
DDV
DOUT
DIN
MAX561
UNIPOLAR CURRENT BLOCK
(SOURCE ONLY)
SERIAL
INTERFACE*
SCLK
V
DDI
CS
DETAIL OF
OPTIONAL
SURGE PROTECTION
22nF
CLR
MICROCONTROLLER
V
DDV
LDAC
COMPI
OUTI4/0
CNF0
16-BIT
DAC
V
DDI
V
SSV
CNF1
R
I
DAC
FAULT
OUTI
AGND
FULL-SCALE
OUTPUT
ADJUST
VOLTAGE-
TO-CURRENT
CONVERTER
L
*
OUTI
+5V
R
1kΩ
REFERENCE
BUFFER
REF
+4.096V
REFERENCE
UNIPOLAR OR BIPOLAR
VOLTAGE BLOCK
R
OPTIONAL
SURGE
PROTECTION
SVN
R
R
2.5R
COMPV
OUTV
C
V
COMPV
DDV
3.3nF**
OPTIONAL
SURGE
PROTECTION
V
SSV
MAX5661
OPTIONAL
SURGE
PROTECTION
SVP
R
R
DAC
DACGNDS
DACGND
DUTGND
DUTGNDS
* SEE THE DAC FUNCTIONAL DIAGRAM IN FIGURE 7.
DGND
AGND
** REQUIRED TO DRIVE C
< 1nF.
OUTV
3ꢂ _______________________________________________________________________________________
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
MAX561
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.comRpackages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
±1-00ꢂ3
64 LQFP
C64-ꢃ
______________________________________________________________________________________ 39
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Revision History
ꢁEVISION
NUMBEꢁ
ꢁEVISION
DATE
PAGES
CHANGED
DESCꢁIPTION
ꢀ
1
ꢃ/ꢀꢃ
5/ꢀ9
Initial release
Clarified how the part operates in single supply mode
—
1ꢃ, 24
MAX561
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