MAX5705BATB+T [MAXIM]
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output Voltage DACs with Internal Reference and SPI Interface;
| 型号： | MAX5705BATB+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output Voltage DACs with Internal Reference and SPI Interface |
| 文件： | 总26页 (文件大小：3348K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
General Description
Benefits and Features
The MAX5703/MAX5704/MAX5705 single-channel, low-
power, 8-/10-/12-bit, voltage-output digital-to-analog
converters (DACs) include output buffers and an internal
reference that is selectable to be 2.048V, 2.500V, or
4.096V. The MAX5703/MAX5704/MAX5705 accept a
wide supply voltage range of 2.7V to 5.5V with extremely
low power (< 1mW) consumption to accommodate most
low-voltage applications. A precision external reference
input allows rail-to-rail operation and presents a 100kI
(typ) load to an external reference.
S Single High-Accuracy DAC Channel
12-Bit Accuracy Without Adjustments
1 LSB INL Buffered Voltage Output
Monotonic Over All Operating Conditions
S Three Precision Selectable Internal References
2.048V, 2.500V, or 4.096V
S Internal Output Buffer
Rail-to-Rail Operation with External Reference
6.3µs Settling Time
Output Directly Drives 2kI Loads
The MAX5703/MAX5704/MAX5705 have a 50MHz,
3-wire SPI/QSPI™/MICROWIRE®/DSP-compatible serial
interface. The DAC output is buffered and has a low
supply current of 155FA (typical at 3V) and a low offset
error of Q0.5mV (typical). On power-up, the MAX5703/
MAX5704/MAX5705 reset the DAC outputs to zero,
providing additional safety for applications that drive
valves or other transducers which need to be off on
power-up. The internal reference is initially powered
down to allow use of an external reference.
S Small, 10-Pin, 2mm x 3mm TDFN and 3mm x 5mm
µMAX Packages
S Wide 2.7V to 5.5V Supply Range
S Flexible 1.8V to 5.5V V
DDIO
S 50MHz, 3-Wire, SPI/QSPI/MICROWIRE/DSP-
Compatible Serial Interface
S Power-On-Reset to Zero-Scale DAC Output
S User-Configurable Asynchronous I/O Functions:
CLR, LDAC, GATE
The MAX5703/MAX5704/MAX5705 include
a
user-
configurable active-low asynchronous input, AUX for
additional flexibility. This input can be programmed to
asynchronously clear (CLR) or temporarily gate (GATE) the
DAC output to a user-programmable value. A dedicated
active-low asynchronous LDAC input is also included. This
allows simultaneous output updates of multiple devices.
S Three Software-Selectable Power-Down Output
Impedances: 1kI, 100kI, or High Impedance
S Low 155µA DAC Supply Current at 3V
Functional Diagram
The MAX5703/MAX5704/MAX5705 are available in 10-pin
TDFN/µMAX packages and are specified over the -40NC
V
DDIO
V
DD
REF
M
to +125NC temperature range
.
MAX5703
MAX5704
MAX5705
INTERNAL REFERENCE /
EXTERNAL BUFFER
Applications
CS
8-/10-/
12-BIT
DAC
CODE
DAC
Programmable Voltage and Current Sources
Gain and Offset Adjustment
SCLK
REGISTER
LATCH
OUT
BUFFER
SPI
SERIAL
INTERFACE
DIN
AUX
Automatic Tuning and Optical Control
Power Amplifier Control and Biasing
Process Control and Servo Loops
Portable Instrumentation
CLEAR/
RESET
CLEAR /
RESET
CODE
LOAD GATE
LDAC
100kI 1kI
POWER
DOWN
DAC CONTROL LOGIC
POR
Data Acquisition
GND
QSPI is a trademark of Motorola, Inc.
Ordering Information appears at end of data sheet.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
For related parts and recommended products to use with this part,
refer to: www.maximintegated.com/MAX5703.related
µMAX is a registered trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6463; Rev 3; 11/14
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ABSOLUTE MAXIMUM RATINGS
V
V
to GND.............................................................-0.3V to +6V
Maximum Continuous Current into Any Pin .................... 50mA
Operating Temperature Range........................ -40NC to +125NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
DD
to GND .........................................................-0.3V to +6V
DDIO
OUT, REF to GND ........-0.3V to lower of (V
+ 0.3V) and +6V
DD
CS, SCLK, DIN, AUX, LDAC to GND......................-0.3V to +6V
Continuous Power Dissipation (T = +70NC)
A
TDFN (derate 14.9mW/NC above +70NC)...............1188.7mW
µMAX (derate 8.8mW/NC above +70NC) ..................707.3mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (θ ) .......67.3NC/W
JA
µMAX
Junction-to-Ambient Thermal Resistance (θ ) .....113.1NC/W
JA
Junction-to-Ambient Thermal Resistance (θ )...........36NC/W
JC
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegated.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
DD
DDIO
GND
L
L
A
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Bits
DC PERFORMANCE (Note 3)
MAX5703
MAX5704
MAX5705
8
10
Resolution and Monotonicity
N
12
MAX5703, 8 bits
MAX5704, 10 bits
MAX5705, 12 bits
MAX5703, 8 bits
MAX5704, 10 bits
MAX5705, 12 bits
-0.25
-0.5
-1
0.05
0.2
0. 5
0.05
0.1
0.2
0.5
10
+0.25
+0.5
+1
Integral Nonlinearity (Note 4)
INL
LSB
-0.25
-0.5
-1
+0.25
+0.5
+1
Differential Nonlinearity (Note 4)
DNL
OE
LSB
Offset Error (Note 5)
Offset Error Drift
-5
+5
mV
FV/NC
%FS
Gain Error (Note 5)
GE
-1.0
0.1
+1.0
ppm of
FS/NC
Gain Temperature Coefficient
With respect to V
With respect to V
2.5
REF
Zero-Scale Error
Full-Scale Error
0
+10
mV
-0.5
+0.5
%FS
REF
Maxim Integrated
2
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
DD
DDIO
GND
L
L
A
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC OUTPUT CHARACTERISTICS
No load
2kI load to GND
2kI load to V
0
0
V
DD
V
-
DD
Output Voltage Range (Note 6)
V
0.2
0.2
V
DD
DD
V
= 3V Q10%,
| P 5mA
DD
300
300
0.3
|I
OUT
Load Regulation
V
= V /2
FV/mA
OUT
OUT
FS
V
= 5V Q10%,
| P 10mA
DD
|I
OUT
V
= 3V Q10%,
| P 5mA
DD
|I
OUT
I
DC Output Impedance
V
= V /2
FS
V
= 5V Q10%,
| P 10mA
DD
0.3
|I
OUT
Capacitive Load Handling
Resistive Load Handling
C
500
pF
L
R
2
kI
L
Sourcing (output
short to GND)
30
40
Short-Circuit Output Current
V
= 5.5V
mA
DD
Sinking (output
shorted to V
)
DD
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
Positive and negative
2.0
2.8
5.2
6.3
5.0
V/Fs
Fs
¼ scale to ¾ scale, to P 1 LSB, MAX5703
¼ scale to ¾ scale, to P 1 LSB, MAX5704
¼ scale to ¾ scale, to P 1 LSB, MAX5705
Major code transition
Voltage-Output Settling Time
DAC Glitch Impulse
Digital Feedthrough
nV·s
nV·s
Code = 0, all digital inputs from 0V to
0.5
V
DDIO
Startup calibration time (Note 7)
From power-down mode
200
60
Fs
Fs
Power-Up Time
DC Power-Supply Rejection
V
= 3V Q10% or 5V Q10%
100
FV/V
DD
Maxim Integrated
3
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
DD
DDIO
GND
L
L
A
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
88
MAX
UNITS
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
External reference
79
108
98
2.048V internal
reference
Output Voltage-Noise Density
(DAC Output at Midscale)
nV/√Hz
117
110
152
145
10
2.5V internal
reference
4.096V internal
reference
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 1kHz
External reference
72
298
11
2.048V internal
reference
89
370
12
Integrated Output Noise
(DAC Output at Midscale)
FV
P-P
2.5V internal
reference
99
355
13
4.096V internal
reference
128
400
113
100
172
157
195
180
279
258
12
External reference
f = 10kHz
f = 1kHz
2.048V internal
reference
f = 10kHz
Output Voltage-Noise Density
(DAC Output at Full Scale)
nV/√Hz
f = 1kHz
2.5V internal
reference
f = 10kHz
f = 1kHz
4.096V internal
reference
f = 10kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
External reference
88
280
14
2.048V internal
reference
135
530
15
Integrated Output Noise
(DAC Output at Full Scale)
FV
P-P
2.5V internal
reference
160
550
23
4.096V internal
reference
220
610
Maxim Integrated
4
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
DD
DDIO
GND
L
L
A
(Note 2)
PARAMETER
REFERENCE INPUT
SYMBOL
CONDITIONS
MIN
1.24
75
TYP
MAX
UNITS
Reference Input Range
Reference Input Current
Reference Input Impedance
REFERENCE OUPUT
V
V
V
REF
DD
I
V
= V
= 5.5V
55
75
FA
kI
REF
REF
DD
R
100
REF
REF
V
V
V
= 2.048V, T = +25NC
2.043
2.494
4.086
2.048
2.500
2.053
2.506
4.106
REF
REF
REF
A
Reference Output Voltage
V
= 2.5V, T = +25NC
V
A
= 4.096V, T = +25NC
4.096
129
122
158
151
254
237
12
A
f = 1kHz
V
V
V
= 2.048V
= 2.500V
= 4.096V
REF
REF
REF
f = 10kHz
f = 1kHz
f = 10kHz
f = 1kHz
f = 10kHz
Reference Output Noise Density
nV/√Hz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
f = 0.1Hz to 10Hz
f = 0.1Hz to 10kHz
f = 0.1Hz to 300kHz
V
V
V
= 2.048V
= 2.500V
= 4.096V
110
390
15
REF
REF
REF
Integrated Reference Output
Noise
129
430
20
FV
P-P
205
525
4
MAX5705A
12
25
Reference Temperature
Coefficient (Note 8)
ppm/NC
MAX5703/MAX5704/MAX5705B
External load
10
25
Reference Drive Capacity
kI
Reference Capacitive Load
Handling
200
pF
Reference Load Regulation
Reference Line Regulation
I
= 0 to 500FA
1.0
0.1
mV/mA
mV/V
SOURCE
Maxim Integrated
5
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
DD
DDIO
GND
L
L
A
(Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
V
= 4.096V
4.5
2.7
1.8
5.5
5.5
REF
Supply Voltage
V
V
V
DD
All other options
I/O Supply Voltage
V
5.5
DDIO
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 3V
= 5V
135
165
190
205
250
215
225
275
155
200
205
220
275
225
240
300
90
190
225
265
280
340
300
315
375
210
265
280
300
375
310
330
410
135
135
150
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
External reference
= 2.048V
= 2.5V
Internal reference,
reference pin
undriven
Supply Current (DAC Output at
Midscale) (Note 9)
I
FA
DD
= 4.096V
= 2.048V
= 2.5V
Internal reference,
reference pin driven
= 4.096V
= 3V
External reference
= 5V
= 2.048V
= 2.5V
Internal reference,
reference pin
undriven
Supply Current (DAC Output at
Full Scale) (Note 9)
I
I
FA
FA
DD
DD
= 4.096V
= 2.048V
= 2.5V
Internal reference,
reference pin driven
= 4.096V
= 2.048V
= 2.5V
Power-Down Mode Supply
Current (DAC Powered Down,
Reference Remains Active)
(Note 9)
Internal reference,
reference pin driven
93
= 4.096V
100
Power-Down Mode Supply
Current (Note 9)
I
External reference, V
= V
0.4
2
FA
FA
PD
DD
REF
Digital Supply Current (Note 9)
I
1.0
DDIO
DIGITAL INPUT CHARACTERISTICS (CS, SCLK, DIN, LDAC, AUX)
0.7 x
2.2V < V
1.8V < V
2.2V < V
1.8V < V
< 5.5V
< 2.2V
< 5.5V
< 2.2V
DDIO
DDIO
DDIO
DDIO
V
DDIO
Input High Voltage
Input Low Voltage
V
V
V
IH
0.8 x
V
DDIO
0.3 x
V
DDIO
V
IL
0.2 x
V
DDIO
Maxim Integrated
6
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
DD
DDIO
GND
L
L
A
(Note 2)
PARAMETER
Hysteresis Voltage
SYMBOL
CONDITIONS
MIN
TYP
0.15
0.1
3
MAX
UNITS
V
V
H
Input Leakage Current (Note 9)
Input Capacitance
I
1
FA
IN
C
pF
IN
SPI TIMING CHARACTERISTICS (CS, SCLK, DIN, LDAC, AUX) (Note 10)
2.7V ≤ V
1.8V ≤ V
2.7V ≤ V
1.8V ≤ V
≤ 5.5V
< 2.7V
≤ 5.5V
< 2.7V
0
0
50
33
DDIO
DDIO
DDIO
DDIO
SCLK Frequency
SCLK Period
MHz
ns
20
30
8
t
SCLK
SCLK Pulse Width High
SCLK Pulse Width Low
t
ns
ns
CH
t
8
CL
2.7V ≤ V
1.8V ≤ V
≤ 5.5V
< 2.7V
8
To first SCLK
falling edge
DDIO
CS Fall to SCLK Fall Setup Time
t
ns
CSS0
12
DDIO
Applies to inactive SCLK falling edge
preceding the first SCLK falling edge
CS Fall to SCLK Fall Hold Time
CS Rise to SCLK Fall Hold Time
CS Rise to SCLK Fall
t
t
0
0
ns
ns
ns
CSH0
CSH1
Applies to the 24th SCLK falling edge
Applies to the 24th SCLK falling edge,
aborted sequence
t
12
CSA
SCLK Fall to CS Fall
t
Applies to 24th SCLK falling edge
100
20
5
ns
ns
ns
ns
ns
ns
ns
ns
CSF
CS Pulse Width High
t
CSPW
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CLR Pulse Width Low
t
DS
t
4.5
20
20
20
20
DH
t
t
CLPW
CLR Rise to CS Fall
t
Required for command to be executed
Applies to 24th SCLK falling edge
CSC
LDPW
LDAC Pulse Width Low
LDAC Fall to SCLK Fall Hold
t
LDH
Maxim Integrated
7
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
(Note 2)
= 2.7V to 5.5V, V
= 1.8V to 5.5V, V
= 0V, C = 200pF, R = 2kI , T = -40NC to +125NC, unless otherwise noted.)
GND L L
A
DD
DDIO
Note 2: Electrical specifications are production tested at T = +25°C. Specifications over the entire operating temperature range
A
are guaranteed by design and characterization. Typical specifications are at T = +25°C.
A
Note 3: DC Performance is tested without load.
Note 4: Linearity is tested with unloaded outputs to within 20mV of GND and V
DD.
Note 5: Gain and offset calculated from measurements made with V
= V
at code 30 and 4065 for MAX5705, code 8 and
REF
DD
1016 for MAX5704, and code 2 and 254 for MAX5703.
Note 6: Subject to zero and full-scale error limits and V
settings.
REF
Note 7: On power-up, the device initiates an internal 200Fs (typ) calibration sequence. All commands issued during this time will
be ignored.
Note 8: Specification is guaranteed by design and characterization.
Note 9: Static logic inputs with V = V
and V = V
.
IL
GND
GND
IH
DDIO
Note 10: All timing is tested with V = V
and V = V
.
IL
IH
DDIO
DIN
SCLK
CS
D
1
23
D
22
D
3
21
IN
D
4
20
D
5
19
IN
D
18
IN
D
17
IN
D
16
IN
D
15
IN
D
14
IN
D
1
D
0
IN
D
23’
IN
IN
IN
IN
IN
t
t
SCLK
6
t
DH
DS
2
7
8
9
10
23
24
1
t
t
t
CH
t
CSH1
CSH0
CSA
t
t
CL
CSS0
t
t
CSF
CSPW
t
t
CSC
CLPW
CLR
t
t
LDH
LDPW
LDAC
Figure 1. SPI Serial Interface Timing Diagram
Maxim Integrated
8
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics
(MAX5705, 12-bit performance, T = +25NC, unless otherwise noted.)
A
INL vs. CODE
INL vs. CODE
DNL vs. CODE
1.0
0.8
1.0
0.8
0.5
0.4
V
= V = 3V
V
= V = 5V
V
= V = 3V
DD REF
DD
REF
DD
REF
NO LOAD
NO LOAD
NO LOAD
0.6
0.6
0.3
0.4
0.4
0.2
0.2
0.2
0.1
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.1
-0.2
-0.3
-0.4
-0.5
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
DNL vs. CODE
INL AND DNL vs. SUPPLY VOLTAGE
INL AND DNL vs. TEMPERATURE
0.5
0.4
1.0
0.8
1.0
0.8
V
= V = 5V
V
= V
REF
V = V = 3V
DD REF
DD
REF
DD
NO LOAD
0.3
0.6
0.6
MAX INL
MAX INL
MAX DNL
MIN INL
MAX DNL
0.2
0.4
0.4
0.1
0.2
0.2
0
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
MIN DNL
MIN DNL
MIN INL
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OFFSET AND ZERO-SCALE ERROR
vs. SUPPLY VOLTAGE
OFFSET AND ZERO-SCALE ERROR
vs. TEMPERATURE
FULL-SCALE ERROR AND GAIN ERROR
vs. SUPPLY VOLTAGE
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
1.0
0.8
-0.02
-0.03
-0.04
-0.05
-0.06
-0.07
-0.08
-0.09
-0.10
V
= 2.5V (EXTERNAL)
REF
NO LOAD
V
= 2.5V (EXTERNAL)
REF
NO LOAD
0.6
ZERO-SCALE ERROR
0.4
FULL-SCALE ERROR
GAIN ERROR
OFFSET ERROR
0.2
0
OFFSET ERROR (V = 3V)
DD
-0.2
-0.4
-0.6
-0.8
-1.0
OFFSET ERROR (V = 5V)
DD
ZERO-SCALE ERROR
V
= 2.5V (EXTERNAL)
REF
NO LOAD
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
Maxim Integrated
9
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, T = +25NC, unless otherwise noted.)
A
FULL-SCALE ERROR AND GAIN ERROR
vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
(PIN UNDRIVEN FOR INTERNAL REF MODES)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(2.048V INTERNAL REFERENCE)
300
250
200
150
100
50
380
340
300
260
220
180
140
100
0.12
0.10
0.08
0.06
0.04
0.02
0
DAC ON
REFERENCE PAD DRIVEN
V
= 2.5V (EXTERNAL)
REF
V
V
= V
DDIO
DD
V
= 4.096V,
REF
V
NO LOAD
= FULL SCALE
DAC_
= 5V
DD
DAC ENABLED
NO LOAD
GAIN ERROR (V = 5V)
DD
FULL-SCALE ERROR
V
= 2.048V,
REF
DAC OFF
REFERENCE
V
= 3V
DAC ON
DD
V
REF
= 2.5V, V = 3V
DD
REFERENCE PAD
UNDRIVEN
OUTPUT ONLY
GAIN ERROR (V = 3V)
DD
V
= V = 5V
DD
REF
V
V
= V
DDIO
DD
= FULL SCALE
DAC
NO LOAD
V
= V = 3V
DD
REF
0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
TEMPERATURE (°C)
POWER-DOWN MODE CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(2.500V INTERNAL REFERENCE)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
(4.096V INTERNAL REFERENCE)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
300
250
200
150
100
50
400
350
300
250
200
150
100
50
DAC ON
REFERENCE PAD DRIVEN
DAC ON REFERENCE PAD DRIVEN
V
= V
REF
DD
(EXTERNAL, ACTIVE)
T = +85°C
A
DAC ON
REFERENCE PAD UNDRIVEN
DAC ON
DAC OFF
REFERENCE PAD
REFERENCE
T = +125°C
A
UNDRIVEN
OUTPUT ONLY
DAC ON EXT REFERENCE = 2.5V
V
V
= V
DDIO
DD
V
V
= V
T = -40°C
A
DD
DDIO
DAC OFF
REFERENCE
OUTPUT ONLY
T = +25°C
A
= FULL SCALE
DAC
= FULL SCALE
DAC
NO LOAD
NO LOAD
0
0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
SUPPLY VOLTAGE (V)
4.00 4.25 4.50 4.75 5.00 5.25 5.50
SUPPLY VOLTAGE (V)
SUPPLY CURRENT vs. CODE
(FOR INTERNAL REF, PIN IS UNDRIVEN)
I
(EXTERNAL) vs. CODE
REF
60
55
50
45
40
35
30
25
20
350
300
250
200
150
100
50
V
= V
DD REF
NO LOAD
V
= 5V,
= 2.5V
DD
V
= 5V,
= 4.096V
V
= 5V,
= 2.048V
DD
DD
V
REF(INT)
V
V
REF(INT)
REF(INT)
V
= 5V
REF
V
= 3V
REF
V
= V = 5V
REF(EXT)
DD
V
= V
= 3V
REF(EXT)
DD
NO LOAD, T = +25°C
A
0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
0
512 1024 1536 2048 2560 3072 3584 4096
CODE (LSB)
Maxim Integrated
10
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, T = +25NC, unless otherwise noted.)
A
SETTLING TO ±± LSꢀ
SETTLING TO ±± LSꢀ
(V = V = 5V, R = 2kI, C = 200pF)
DD REF
(V = V
DD
= 5V, R = 2kI, C = 200pF)
L L
MAX5703 toc18
REF
L
L
MAX5703 toc19
ZOOMED
V
OUT
6.3µs
1 LSB/div
5.9µs
ZOOMED
V
OUT
1 LSB/div
V
OUT
V
OUT
2V/div
2V/div
3/4 SCALE TO 1/4 SCALE
1/4 SCALE TO 3/4
SCALE
TRIGGER
PULSE
TRIGGER
PULSE
10V/div
10V/div
2µs/div
2µs/div
MAJOR CODE TRANSITION GLITCH ENERGY
MAJOR CODE TRANSITION GLITCH ENERGY
(V = V
= 5V, R = 2kI, C = 200pF)
(V = V
= 5V, R = 2kI, C = 200pF)
DD
REF
L
L
DD
REF
L
L
MAX5703 toc20
MAX5703 toc21
1 LSB CHANGE
(MIDCODE TRANSITION
0x800 TO 0x7FF)
GILTCH IMPULSE = 5nV*S
ZOOMED
ZOOMED
V
OUT
V
OUT
1.25mV/div
1.25mV/div
1 LSB CHANGE
(MIDCODE TRANSITION
0x7FF TO 0x800)
GILTCH IMPULSE = 5nV*S
TRIGGER
PULSE
5V/div
TRIGGER
PULSE
5V/div
2µs/div
2µs/div
V
vs. TIME TRANSIENT
OUT
EXITING POWER-DOWN
POWER-ON RESET TO 0V
MAX5703 toc22
MAX5703 toc23
V
DD
2V/div
V
CLK
5V/div
V
= V = 5V
REF
DD
10kI LOAD TO V
0V
DD
24TH EDGE
0V
0V
V
OUT
1V/div
V
= 5V, V = 2.5V
REF
DD
EXTERNAL
V
OUT
2V/div
0V
20µs/div
40µs/div
Maxim Integrated
11
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, T = +25NC, unless otherwise noted.)
A
OUTPUT LOAD REGULATION
DIGITAL FEEDTHROUGH
3
2
(V = V
= 5V, R = 2kI, C = 200pF)
L L
MAX5703 toc24
DD
REF
V
= V
DD REF
MIDSCALE
V
= V = 5V
DD REF
DAC AT MIDSCALE
1
V
= 3V
DD
V
OUT
125µV/div
0
V
DD
= 5V
-1
-2
-3
DIGITAL FEEDTHROUGH = 0.1nV·s
-30 -20 -10
0
10
20
30
40
I
(mA)
1µs/div
OUT
HEADROOM AT RAILS
vs. OUTPUT CURRENT (V = V
NOISE-VOLTAGE DENSITY
vs. FREQUENCY (DAC AT MIDSCALE)
OUTPUT CURRENT LIMITING
)
REF
DD
500
400
300
200
100
0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
350
300
250
200
150
100
50
V
DD
= V
REF
MIDSCALE
V
= 5V, V = 4.096V
DD REF
(INTERNAL)
V
= 5V, SOURCING
DD
FULL SCALE
V
= 5V
DD
V
= 5V, V = 2.5V
REF
DD
(INTERNAL)
V
= 5V, V = 2.048V
REF
DD
(INTERNAL)
V
= 3V, SOURCING
DD
FULL SCALE
-100
-200
-300
-400
-500
V
= 3V
DD
V
= 3V AND 5V SINKING
DD
ZERO SCALE
V
= 5V, V = 5V
REF
DD
(EXTERNAL)
0
-40 -30 -20 -10
0
10 20 30 40 50
(mA)
0
1
2
3
4
I
5
6
7
8
9
10
100
1k
10k
100k
I
(mA)
OUT
OUT
FREQUENCY (Hz)
0.1Hz TO 10Hz OUTPUT NOISE, EXTERNAL
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V
= 4.5V)
REFERENCE (V = 5V, V
= 2.048V)
REF
MAX5703 toc30
DD
REF
DD
MAX5703 toc29
MIDSCALE UNLOADED
MIDSCALE UNLOADED
V
= 10µV
V
= 11µV
P-P
P-P
V
V
OUT
5µV/div
OUT
5µV/div
4s/div
4s/div
Maxim Integrated
12
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Characteristics (continued)
(MAX5705, 12-bit performance, T = +25NC, unless otherwise noted.)
A
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
0.1Hz TO 10Hz OUTPUT NOISE, INTERNAL
REFERENCE (V = 5V, V
= 2.500V)
REFERENCE (V = 5V, V
= 4.096V)
REF
MAX5703 toc32
DD
REF
DD
MAX5703 toc31
MIDSCALE UNLOADED
MIDSCALE UNLOADED
V
= 12µV
V
= 13µV
P-P
P-P
V
V
OUT
OUT
5µV/div
5µV/div
4s/div
4s/div
V
REF
DRIFT vs. TEMPERATURE
REFERENCE LOAD REGULATION
45
40
35
30
25
20
15
10
5
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
V
= 5V
DD
INTERNAL REFERENCE
V
V
= 2.7V
= 2.5V
DD
REF
BOX METHOD
V
= 2.048V, 2.5V, 4.096V
REF
0
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
TEMPERATURE COEFFICIENT (ppm/°C)
0
100
200
300
400
500
REFERENCE OUTPUT CURRENT (µA)
INTERNAL REFERENCE NOISE
DENSITY vs. FREQUENCY
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
450
400
350
300
250
200
150
100
50
2000
1800
1600
1400
1200
1000
800
V
= 5V
DD
V
= 4.096V
REF
ALL I/O PINS SWEPT
V
= 5V
V
= 2.5V
DDIO
REF
V
= 3V
600
DDIO
400
V
DDIO
= 1.8V
V
= 2.048V
1k
REF
200
0
0
100
10k
100k
0
1
2
3
4
5
FREQUENCY (Hz)
INPUT LOGIC VOLTAGE (V)
Maxim Integrated
13
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Pin Configurations
TOP VIEW
+
AUX
LDAC
CS
1
2
3
4
5
10
9
REF
AUX
LDAC
CS
1
2
3
4
5
10 REF
OUT
GND
9
8
7
6
OUT
GND
MAX5703
MAX5704
MAX5705
MAX5703
MAX5704
MAX5705
8
SCLK
DIN
V
DD
V
7
SCLK
DIN
DD
*EP
V
DDIO
V
DDIO
6
TDFN
µMAX
*CONNECTED TO GND
Pin Description
PIN
NAME
FUNCTION
Active-Low Auxilliary Asynchronous Input. User configurable, see Table 7. If not using the AUX
functions, connect this input to V
1
AUX
.
DDIO
2
3
LDAC
CS
Dedicated Active-Low Asynchronous Load DAC
SPI Chip-Select Input
4
SCLK
DIN
SPI Interface Clock Input
5
SPI Interface Data Input
6
V
Digital Interface Power-Supply Input
DDIO
7
V
Supply Voltage Input. Bypass V with a 0.1FF capacitor to GND.
DD
DD
8
GND
OUT
REF
EP
Ground
9
Buffered DAC Output
Reference Voltage Input/Output
10
—
Exposed Pad (TDFN Only). Connect to ground.
Maxim Integrated
14
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Within the device there is a CODE register followed by
a DAC Latch register (see the Functional Diagram).
Detailed Description
The contents of the CODE register hold pending DAC
output settings which can later be loaded into the DAC
registers. The CODE register can be updated using both
CODE and CODE_LOAD user commands. The contents
of the DAC register hold the current DAC output settings.
The DAC register can be updated directly from the serial
interface using the CODE_LOAD commands or can
upload the current contents of the CODE register using
LOAD commands or the LDAC input.
The MAX5703/MAX5704/MAX5705 are single-channel,
low-power, 8-/10-/12-bit voltage-output digital-to-analog
converters (DACs) with an internal output buffer. The
wide supply voltage range of 2.7V to 5.5V and low power
consumption accommodate low-power and low-voltage
applications. The devices present a 100kI (typ) load to
the external reference. The internal output buffer allows
rail-to-rail operation. An internal voltage reference is
available with software selectable options of 2.048V,
2.500V, or 4.096V. The devices feature a 50MHz, 3-wire
SPI/QSPI/MICROWIRE/DSP-compatible serial interface
to save board space and reduce complexity in isolated
applications. The MAX5703/MAX5704/MAX5705 include
a serial-in/parallel-out shift register, internal CODE and
DAC registers, a power-on-reset (POR) circuit to initialize
the DAC output to code zero, and control logic. A user-
configurable AUX pin is available to asynchronously
clear or gate the device output independent of the serial
interface.
The contents of both CODE and DAC registers are
maintained during all software power-down states, so that
when the DAC is returned to a normal operating mode, it
returns to its previously stored output settings. Any CODE
or LOAD commands issued during software power-down
states continue to update the register contents. The
SW_CLEAR command clears the contents of the CODE
and DAC registers to the user-programmable default
values. The SW_RESET command resets all configuration
registers to their power-on default states, while resetting
the CODE and DAC registers to zero scale.
DAC Output (OUT)
The MAX5703/MAX5704/MAX5705 include an internal
buffer on the DAC output. The internal output buffer
provides improved load regulation for the DAC output.
The output buffer slews at 1V/Fs (typ) and drives up to
2kI in parallel with 500pF. The analog supply voltage
Internal Reference
The MAX5703/MAX5704/MAX5705 include an internal
precision voltage reference that is software selectable to
be 2.048V, 2.500V, or 4.096V. When an internal reference
is selected, that voltage is available on the REF pin
for other external circuitry (see the Typical Operating
Circuits) and can drive a 25kI load.
(V ) determines the maximum output voltage range
DD
of the devices as V
powers the output buffer. Under
DD
no-load conditions, the output buffer drives from GND to
, subject to offset and gain errors. With a 2kI load
External Reference
The external reference input features a typical input
impedance of 100kI and accepts an input voltage
V
DD
to GND, the output buffer drives from GND to within and
200mV of V . With a 2kIload to V , the output buffer
DD
DD
DD
from +1.24V to V . Connect an external voltage
DD
drives from V
to within 200mV of GND.
supply between REF and GND to apply an external
reference. The MAX5703/4/5 power up and reset to
external reference mode. Visit www.maximintegated.
com/products/references for a list of available external
voltage-reference devices.
The DAC ideal output voltage is defined by:
D
V
= V
×
REF
OUT
N
2
Where D = code loaded into the DAC register, V
reference voltage, N = resolution.
=
REF
AUX Input
The MAX5703/MAX5704/MAX5705 provide an asynchro-
nous AUX (active-low) input. Use the CONFIG command
to program the device to use the input in one of the fol-
lowing modes: CLR (default), GATE, or disabled. If not
Internal Register Structure
The user interface is separated from the DAC logic to
minimize digital feedthrough. Within the serial interface
is an input shift register, the contents of which can
be routed to control registers or the DAC itself, as
determined by the user command.
using the AUX functions, connect this input to V
.
DDIO
Maxim Integrated
15
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
CLR Mode
In CLR mode, the AUX input performs an asynchronous
level sensitive CLEAR operation when pulled low. If
CLR is configured and asserted, all CODE and DAC
data registers are cleared to their default/return values
as defined by the configuration settings. Other user-
configuration settings are not affected.
V
Input
DDIO
The MAX5703/MAX5704/MAX5705 feature a separate
supply pin (V ) for the digital interface (1.8V to 5.5V).
DDIO
DDIO
Connect V
to the I/O supply of the host processor.
SPI Serial Interface
The MAX5703/MAX5704/MAX5705 3-wire serial interface
is compatible with MICROWIRE/SPI/QSPI and DSPs. The
interface provides three inputs: SCLK, CS, and DIN. The
chip-select input (CS, active-low) frames the data loaded
through the serial data input (DIN). Following a CS input
high-to-low transition, the data is shifted in synchronously
and latched into the input register on each falling edge of
the serial clock input (SCLK). Each serial operation word
is 24-bits long. The DAC data is left justified as shown in
Table 1. The serial input register transfers its contents to
the destination registers after loading 24 bits of data on
the 24th SCLK falling edge. To initiate a new SPI opera-
tion, drive CS high and then low to begin the next opera-
tion sequence, being sure to meet all relevant timing
requirements. During CS high periods, SCLK is ignored,
allowing communication to other devices on the same
bus. SPI operations consisting of more than 24 SCLK
cycles are executed on the 24th SCLK falling edge, using
the first three bytes of data available. SPI operations con-
sisting of less than 24 SCLK cycles will not be executed.
The content of the SPI operation consists of a command
byte followed by a two byte data word.
Some SPI interface commands are gated by CLR activity
during the transfer sequence. If CLR is issued during a
command write sequence, any gated commands within
the sequence are ignored. Any non-gated commands
appearing in the transfer sequence are executed. For
the gating condition to be removed, drive CLR high,
satisfying the t
requirements.
CSC
GATE Mode
Use of the GATE mode provides a means of momentarily
holding the DAC in a user-selectable default/return state,
returning the DAC to the last programmed state upon
removal. The MAX5703/MAX5704/MAX5705 also feature
a software-accessible GATE command. While asserted
in GATE mode, the AUX pin does not interfere with
RETURN, CODE, or DAC register updates and related
load activity.
LDAC Input
The MAX5703/MAX5704/MAX5705 provide a dedicated
asynchronous LDAC (active-low) input. The LDAC input
performs an asynchronous level sensitive LOAD operation
when pulled low. Use of the LDAC input mode provides
a means of updating multiple devices together as a
group. Users wishing to control the DAC update instance
independently of the I/O instruction should hold LDAC
high during programming cycles. Once programming
is complete, LDAC may be strobed and the new CODE
register content is loaded into the DAC latch output.
Users wishing to load new DAC data in direct response
to I/O CODE register activity should connect LDAC
permanently low; in this configuration, the MAX5703/
MAX5704/MAX5705 DAC output updates in response to
each completed I/O CODE instruction update edge. A
software LOAD command is also provided.
Figure 1 shows the timing diagram for the complete
3-wire serial interface transmission. The DAC code
settings (D) for the MAX5703/MAX5704/MAX5705 are
accepted in an offset binary format (see Table 1).
Otherwise, the expected data format for each command
is listed in Table 2.
SPI User-Command Register Map
This section lists the user-accessible commands and
registers for the MAX5703/MAX5704/MAX5705.
Table 2 provides detailed information about the SPI
Command Registers.
The LDAC operation does not interact with the user
interface directly. However, in order to achieve the best
possible glitch performance, timing with respect to the
interface update edge should follow t
when issuing CODE commands.
specifications
LDH
Maxim Integrated
16
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
CODE Command
The CODE command (B[23:20] = 1000) updates the
CODE register content for the DAC. Changes to the
µC
CSB1
SCLK
MOSI
CS
CODE register content based on this command will not
affect the DAC output directly unless the LDAC input
is in a low state. Otherwise, a subsequent hardware
or software LOAD operation will be required to move
this content to the active DAC latch. This command is
gated when CLR is asserted, updates to this register are
ignored while the register is being cleared. See Table
1 and Table 2.
SCLK
DIN
MAX5703
MAX5704
MAX5705
*
CSB2
CS
SCLK
DIN
LOAD Command
The LOAD command (B[23:20] = 1001) updates the DAC
latch register content by uploading the current contents
of the CODE register. This command is gated when CLR
is asserted, updates to this register are ignored while the
register is being cleared. See Table 2.
MISO
CSB3
DOUT
*
CS
SCLK
DIN
CODE_LOAD Command
The CODE_LOAD command (B[23:20] = 1010 and 1011)
updates the CODE register contents as well as the DAC
register content of the DAC. This command is gated
when CLR is asserted, updates to these registers are
ignored while the register is being cleared. See Table 1
and Table 2.
*ADDITIONAL SPI DEVICE
Figure 2. Typical SPI Application Circuit
Table 1. DAC Data Bit Positions
PART
B15 B14 B13 B12 B11 B10
B9
D1
D3
D5
B8
D0
D2
D4
B7
X
B6
X
B5
X
B4
X
B3
X
B2
B1
X
B0
X
MAX5703
MAX5704
MAX5705
D7
D9
D6
D8
D5
D7
D9
D4
D6
D8
D3
D5
D7
D2
D4
D6
X
X
X
D1
D3
D0
D2
X
X
X
X
X
D11 D10
D1
D0
X
X
X
Maxim Integrated
17
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Maxim Integrated
18
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
1 = A l w a y s O N
0 = D e f a u l t
1 = D r i v e P i n
0 = N o D r i v e
Maxim Integrated
19
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
REF Command
The REF (B[23:20] = 0010) command updates the global
reference setting used for the DAC. Set B[17:16] = 00 to
use an external reference for the DAC or set B[17:16] to
01, 10, or 11 to select either the 2.5V, 2.048V, or 4.096V
internal reference, respectively.
SOFTWARE Commands
The SOFTWARE (B[23:20] = 0011) commands provide
a means of issuing several flexible software actions. See
Table 4.
The SOFTWARE Command Action Mode is selected by
B[18:16]:
If RF3 (B19) is set to zero (default) in the REF command,
the REF I/O will not be driven by the internal reference
circuit, saving current. If RF3 is set to one, the REF I/O
will be driven by the internal reference circuit, consuming
an additional 25FA (typ) of current when the reference is
powered; when the reference is powered down, the REF
I/O will be high-impedance.
END (000):
Used to end any active gate operation,
returning to normal operation (default).
DAC contents will be gated to their
DEFAULT selected values until the gate
condition is removed.
GATE (001):
CLEAR (100): All CODE and DAC contents will be
cleared to their DEFAULT selected
values.
If RF2 (B18) is set to zero (default) in the REF command,
the reference will be powered down any time the DAC
is powered down (in STANDBY mode). If RF2 (B18) is
set to one, the reference will remain powered even if the
DAC is powered down, allowing continued operation of
external circuitry. In this mode, the 1FA shutdown state is
not available. See Table 3.
RESET (101):
All CODE, DAC, RETURN, and
configuration registers reset to their
power-up defaults (including REF,
POWER, and CONFIG settings),
simulating a power cycle reset.
OTHER:
No effect.
Table 3. REF (0010) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
0
RF3 RF2 RF1 RF0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Ref Mode:
00 = EXT
01 = 2.5V
10 = 2.0V
11 = 4.0V
REF COMMAND
Don’t Care
Don’t Care
DEFAULT VALUES
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Table 4. SOFTWARE (0011) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
X
SW2 SW1 SW0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Mode:
000: END
001: GATE
100: CLR
101: RST
Other: No
Effect
SOFTWARE
COMMANDS
Don’t Care
Don’t Care
DEFAULT VALUES
X
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Maxim Integrated
20
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
mode, the DAC register retains its value so that the
output is restored when the device powers up. The serial
interface remains active in power-down mode with all
registers accessible.
POWER Command
The MAX5703/MAX5704/MAX5705 feature a software-
controlled POWER mode command (B[23:20] = 0100).
In power-down, the DAC output is disconnected from
the buffer and is grounded with either one of the two
selectable internal resistors or set to high impedance.
See Table 5 and Table 6 for the selectable internal
resistor values in power-down mode. In power-down
In power-down mode, the internal reference can be
powered down or it can be set to remain powered-on for
external use. Also, in power-down mode, parts using the
external reference do not load the REF pin. See Table 5.
Table 5. POWER (0100) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
PD1 PD0
X
X
X
X
X
X
Power
Mode:
00 =
POWER
COMMAND
Normal
01 = 1kI
10 =
Don’t Care
Don’t Care
Don’t Care
100kI
11 = Hi-Z
DEFAULT VALUES
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
X
X
X
X
X
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Table 6. Selectable DAC Output Impedance in Power-Down Mode
PD1 (B7)
PD0 (B6)
OPERATING MODE
0
0
1
1
0
1
0
1
Normal operation
Power-down with internal 1kIpulldown resistor to GND.
Power-down with internal 100kIpulldown resistor to GND.
Power-down with high-impedance output.
Maxim Integrated
21
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
CONFIG Command
The CONFIG command (B[23:20] = 0101) updates the
function of the AUX input enabling its gate, load, or clear
(default) operation mode. See Table 7.
DEFAULT Command
DEFAULT (0110): The DEFAULT command selects the
default value for the DAC. These default values are used
for all future clear and gate operations. The new default
setting is determined by bits DF[2:0]. See Table 8.
AUX Config settings are written by B[5:3]:
Available default values are:
GATE (011):
AUX functions as a GATE. DAC code is
gated to DEFAULT value input when pin
is low.
POR (000):
DAC defaults to power-on reset value
(default).
ZERO (001):
MID (010):
FULL (011):
DAC defaults to zero scale.
DAC defaults to midscale.
DAC defaults to full scale.
CLEAR (110): AUX functions as a CLR input (default).
CODE and DAC content is cleared to
DEFAULT value if pin is low.
RETURN (100): DAC defaults to value specified by the
RETURN register
NONE (111):
OTHER:
AUX functions are disabled.
AUX function is not altered.
OTHER:
No effect, the default setting remains
unchanged.
Note: CONFIG should not be programmed with the AUX
pin asserted (low) or unexpected behavior could result.
Note: The selected default values do not apply to resets
initiated by SW_RESET commands or supply cycling,
both of which return the DACs to the power-on reset state
(zero scale).
Table 7. CONFIG (0101) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
AB2 AB1 AB0
X
X
X
AUXB Mode:
011 = GATE
110 = CLEAR
111 = NONE
Other = No
Effect
Don’t
Care
CONFIG COMMAND
Don’t Care
Don’t Care
Don’t Care
DEFAULT VALUES
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
0
X
X
X
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Table 8. DEFAULT (0110) Command Format
B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
1
1
0
X
X
X
X
X
X
X
X
X
X
X
X
DF2 DF1 DF0
X
X
X
X
X
Default Values:
000: POR
001: ZERO
010: MID
011: FULL
100: RETURN
Other: No
Effect
DEFAULT
COMMAND
Don’t Care
Don’t Care
Don’t Care
DEFAULT VALUES
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
X
X
X
X
X
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Maxim Integrated
22
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
RETURN Command
The RETURN command (B[23:20] = 0111) updates the
RETURN register content for the DAC. If the DEFAULT
configuration register is set to RETURN mode, the DAC
will be cleared or gated to the RETURN register value in
the event of a SW or HW CLEAR or GATE condition. It is
not necessary to program this register if the DEFAULT =
RETURN mode will not be used. The data format for the
RETURN register is identical to that used for CODE and
LOAD operations. See Table 1 and Table 2.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step height and
the ideal value of 1 LSB. If the magnitude of the DNL P
1 LSB, the DAC guarantees no missing codes and is
monotonic. If the magnitude of the DNL R1 LSB, the DAC
output may still be monotonic.
Offset Error
Offset error indicates how well the actual transfer function
matches the ideal transfer function. The offset error is
calculated from two measurements near zero code and
near maximum code.
Applications Information
Gain Error
Gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
Power-On Reset (POR)
When power is applied to V , the DAC output is
DD
set to zero scale. To optimize DAC linearity, wait until
the supplies have settled and the internal setup and
calibration sequence completes (200Fs, typ).
Power Supplies and Bypassing
Considerations
Zero-Scale Error
Zero-scale error is the difference between the DAC
output voltage when set to code zero and ground. This
includes offset and other die level nonidealities.
Bypass V
with high-quality ceramic capacitors to
DD
a low-impedance ground as close as possible to the
device. Minimize lead lengths to reduce lead inductance.
Connect GND to the analog ground plane.
Full-Scale Error
Full-scale error is the difference between the DAC output
voltage when set to full scale and the reference voltage.
This includes offset, gain error, and other die level
nonidealities.
Layout Considerations
Digital and AC transient signals on GND can create noise
at the output. Connect GND to form the star ground for
the DAC system. Refer remote DAC loads to this system
ground for the best possible performance. Use proper
grounding techniques, such as a multilayer board with
a low-inductance ground plane, or star connect all
ground return paths back to the MAX5703/MAX5704/
MAX5705 GND. Carefully layout the traces between
channels to reduce AC cross-coupling. Do not use wire-
wrapped boards and sockets. Use shielding to maximize
noise immunity. Do not run analog and digital signals
parallel to one another, especially clock signals. Avoid
routing digital lines underneath the MAX5703/MAX5704/
MAX5705 package.
Settling Time
The settling time is the amount of time required from the
start of a transition, until the DAC output settles to the new
output value within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the amount of noise that appears
on the DAC output when the DAC digital control lines are
toggled.
Digital-to-Analog Glitch Impulse
A major carry transition occurs at the midscale point
where the MSB changes from low to high and all other
bits change from high to low, or where the MSB changes
from high to low and all other bits change from low to
high. The duration of the magnitude of the switching
glitch during a major carry transition is referred to as the
digital-to-analog glitch impulse.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function
from a straight line drawn between two codes once offset
and gain errors have been nullified.
The digital-to-analog power-up glitch is the duration of
the magnitude of the switching glitch that occurs as the
device exits power-down mode.
Maxim Integrated
23
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Typical Operating Circuits
100nF
100nF
4.7µF
V
V
DDIO
DAC
DD
OUT
REF
V
= -V to +V
REF REF
OUT
CS
MICRO -
CONTROLLER
SCLK
DIN
MAX5703
MAX5704
MAX5705
LDAC
R1
R2
AUX
R1 = R2
GND
NOTE: BIPOLAR OPERATION SHOWN
100nF
4.7µF
100nF
V
V
DD
DDIO
V
= 0V to V
REF
OUT
OUT
REF
DAC
CS
SCLK
DIN
MICRO -
CONTROLLER
MAX5703
MAX5704
MAX5705
LDAC
AUX
GND
NOTE: UNIPOLAR OPERATION SHOWN
Maxim Integrated
24
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Ordering Information
PART
MAX5703ATB+T
MAX5703AUB+
MAX5704ATB+T
MAX5704AUB+
MAX5705AAUB+
MAX5705BATB+T
MAX5705BAUB+
PIN-PACKAGE
10 TDFN-EP*
10 FMAX
RESOLUTION (BIT)
INTERNAL REFERENCE TEMPCO (ppm/NC)
10 (typ), 25 (max)
8
8
10 (typ), 25 (max)
10 TDFN-EP*
10 FMAX
10
10
12
12
12
10 (typ), 25 (max)
10 (typ), 25 (max)
10 FMAX
4 (typ), 12 (max)
10 TDFN-EP*
10 FMAX
10 (typ), 25 (max)
10 (typ), 25 (max)
Note: All devices are specified over the -40°C to +125°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Chip Information
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 TDFN-EP
T1032N+1
U10+2
21-0429
21-0061
90-0082
90-0330
10 FMAX
Maxim Integrated
25
MAX5703/MAX5704/MAX5705
Ultra-Small, Single-Channel, 8-/10-/12-Bit Buffered Output
Voltage DACs with Internal Reference and SPI Interface
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
11/12
2/13
0
1
2
3
Initial release
—
2–8, 25
25
Released MAX5703/MAX5704. Updated the Electrical Characteristics.
Released the MAX5703/MAX5704/MAX5705 TDFN packages.
Added details to AUX input description
6/13
11/14
14, 15, 22
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
26
©
2014 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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