MAX5811MEUT-T [MAXIM]
10-Bit, Low-Power, 2-Wire Interface, Serial, Voltage-Output DAC; 10位，低功耗， 2线接口，串行，电压输出DAC
| 型号： | MAX5811MEUT-T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10-Bit, Low-Power, 2-Wire Interface, Serial, Voltage-Output DAC |
| 文件： | 总13页 (文件大小：417K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2270; Rev 0; 1/02
10-Bit, Low-Power, 2-Wire Interface, Serial,
Voltage-Output DAC
General Description
Features
The MAX5811 is a single, 10-bit voltage-output digital-to-
analog converter (DAC) with an I2C™-compatible 2-wire
interface that operates at clock rates up to 400kHz. The
device operates from a single 2.7V to 5.5V supply and
ꢀ Ultra-Low Supply Current
100µA at V
130µA at V
= 3.6V
= 5.5V
DD
DD
ꢀ 300nA Low-Power Power-Down Mode
ꢀ Single 2.7V to 5.5V Supply Voltage
draws only 100µA at V
= 3.6V. A low-power power-
DD
down mode decreases current consumption to less than
1µA. The MAX5811 features three software-selectable
power-down output impedances: 100kΩ, 1kΩ, and high
impedance. Other features include an internal precision
ꢀ Fast 400kHz I2C-Compatible 2-Wire Serial
Interface
®
Rail-to-Rail output buffer and a power-on reset (POR)
ꢀ Schmitt-Trigger Inputs for Direct Interfacing
circuit that powers up the DAC in the 100kΩ power-down
to Optocouplers
mode.
The MAX5811 features a double-buffered I2C-compatible
serial interface that allows multiple devices to share a sin-
gle bus. All logic inputs are CMOS-logic compatible and
buffered with Schmitt triggers, allowing direct interfacing
to optocoupled and transformer-isolated interfaces. The
MAX5811 minimizes digital noise feedthrough by discon-
necting the clock (SCL) signal from the rest of the device
when an address mismatch is detected.
ꢀ Rail-to-Rail Output Buffer Amplifier
ꢀ Three Software-Selectable Power-Down Output
Impedances
100kΩ, 1kΩ, and High Impedance
ꢀ Read-Back Mode for Bus and Data Checking
ꢀ Power-On Reset to Zero
ꢀ Miniature 6-Pin SOT23 Package
The MAX5811 is specified over the extended temperature
range of -40°C to +85°C and is available in a space-sav-
ing 6-pin SOT23 package. Refer to the MAX5812 data
sheet for the 12-bit version.
Ordering Information
PIN-
PACKAGE
TOP
MARK
PART
TEMP RANGE
Applications
MAX5811LEUT-T
-40°C to +85°C
6 SOT23-6
6 SOT23-6
6 SOT23-6
6 SOT23-6
AAYS
AAYU
AAYW
AAYY
Digital Gain and Offset Adjustments
Programmable Voltage and Current Sources
Programmable Attenuation
MAX5811MEUT-T -40°C to +85°C
MAX5811NEUT-T
MAX5811PEUT-T
-40°C to +85°C
-40°C to +85°C
VCO/Varactor Diode Control
Functional Diagram appears at end of data sheet.
Low-Cost Instrumentation
Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.
I2C is a trademark of Philips Corp.
Battery-Operated Equipment
Typical Operating Circuit
Pin Configuration
V
DD
V
DD
TOP VIEW
µC
SCL
SDA
R
R
P
P
R
S
1
2
3
6
5
4
V
OUT
ADD
SCL
DD
SCL
SDA
V
DD
R
S
MAX5811
MAX5811
GND
SDA
MAX5811
OUT
R
S
SCL
SDA
V
DD
R
SOT23
S
OUT
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
ABSOLUTE MAXIMUM RATINGS
DD
OUT, ADD to GND........................................-0.3V to V
Maximum Current into Any Pin............................................50mA
V
, SCL, SDA to GND............................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
+ 0.3V
DD
Continuous Power Dissipation (T = +70°C)
A
6-Pin SOT23 (derate 9.1mW above +70°C).................727mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
V
= +2.7V to +5.5V, GND = 0, R = 5kΩ, C = 200pF, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
L
L
A
MIN
= +5V, T = +25°C.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC ACCURACY (Note 2)
Resolution
N
10
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
Zero-Code Error
INL
DNL
ZCE
(Note 3)
0.5
4
Guaranteed monotonic (Note 3)
0.5
40
LSB
Code = 000 hex, V
Code = 3FF hex
= 2.7V
6
2.3
mV
ppm/°C
DD
Zero-Code Error Tempco
Gain Error
GE
-0.8
0.26
-3
%FS
ppm/°C
Gain-Error Tempco
DAC OUTPUT
Output Voltage Range
DC Output Impedance
No load (Note 4)
Code = 200 hex
0
V
V
DD
1.2
42.2
15.1
8
Ω
V
V
V
V
= 5V, V
= 3V, V
= 5V
= full scale (short to GND)
= full scale (short to GND)
DD
DD
DD
DD
OUT
OUT
Short-Circuit Current
Wake-Up Time
mA
µs
= 3V
8
Power-down mode = high impedance,
DAC Output Leakage Current
DIGITAL INPUTS (SCL, SDA)
Input High Voltage
0.1
1
µA
V
= 5.5V, V
= V
or GND
DD
OUT
DD
0.7 x
V
V
V
V
IH
V
DD
0.3 x
Input Low Voltage
Input Hysteresis
V
IL
V
DD
0.05 x
V
DD
Input Leakage Current
Digital inputs = 0 or V
0.1
6
1
µA
pF
DD
DD
Input Capacitance
DIGITAL OUTPUT (SDA)
Output Logic Low Voltage
Three-State Leakage Current
Three-State Output Capacitance
V
I
= 3mA
SINK
0.4
1
V
OL
I
Digital inputs = 0 or V
0.1
6
µA
pF
L
2
_______________________________________________________________________________________
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (continued)
(V
V
= +2.7V to +5.5V, GND = 0, R = 5kΩ, C = 200pF, T = T
to T
, unless otherwise noted. Typical values are at
MAX
DD
L
L
A
MIN
= +5V, T = +25°C.) (Note 1)
A
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC PERFORMANCE
Voltage-Output Slew Rate
SR
0.5
4
V/µs
µs
To 1/2LSB code 100 hex to 300 hex or 300
hex to 100 hex (Note 5)
Voltage-Output Settling Time
Digital Feedthrough
12
Code = 000 hex, digital inputs from 0 to V
0.2
12
nV-s
nV-s
DD
Major-carry transition (code = 1FF hex to 200
hex and 200 hex to 1FF hex)
Digital-to-Analog Glitch Impulse
POWER SUPPLIES
Supply Voltage Range
V
2.7
5.5
170
190
1
V
DD
All digital inputs at 0 or V
All digital inputs at 0 or V
= 3.6V
= 5.5V
100
130
0.3
DD
DD
Supply Current with
No Load
Power-Down Supply Current
All digital inputs at 0 or V = 5.5V
DD
µA
TIMING CHARACTERISTICS (Figure 1)
Serial Clock Frequency
f
0
400
kHz
µs
SCL
Bus-Free Time Between STOP
and START Conditions
t
1.3
BUF
START Condition Hold Time
SCL Pulse Width Low
SCL Pulse Width High
Repeated START Setup Time
Data Hold Time
t
t
0.6
1.3
0.6
0.6
0
µs
µs
µs
µs
µs
ns
HD,STA
t
LOW
t
HIGH
SU,STA
HD,DAT
t
0.9
Data Setup Time
t
100
SU,DAT
SDA and SCL Receiving
Rise Time
t
r
t
f
t
f
(Note 5)
(Note 5)
(Note 5)
0
300
300
250
ns
ns
ns
SDA and SCL Receiving
Fall Time
0
20 +
0.1C
SDA Transmitting Fall Time
b
STOP Condition Setup Time
Bus Capacitance
t
0.6
µs
SU,STO
C
(Note 5)
400
50
pF
b
Maximum Duration of
Suppressed Pulse Widths
t
0
ns
SP
Note 1: All devices are 100% production tested at T = +25°C and are guaranteed by design for T = T
to T
.
MAX
A
A
MIN
Note 2: Static specifications are tested with the output unloaded.
Note 3: Linearity is guaranteed from codes 29 to 995.
Note 4: Offset and gain error limit the FSR.
Note 5: Guaranteed by design. Not production tested.
_______________________________________________________________________________________
3
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Typical Operating Characteristics
(V
= +5V, R = 5kΩ, T = +25°C.)
L A
DD
INTEGRAL NONLINEARITY
vs. INPUT CODE
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
INTEGRAL NONLINEARITY
vs. TEMPERATURE
1.00
0.75
0.50
0.25
0
1.25
1.00
0.75
0.50
0.25
0
1.25
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
256
512
768
1024
1024
5.5
2.7
3.4
4.1
4.8
5.5
-40
-15
10
35
60
85
INPUT CODE
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
DIFFERENTIAL NONLINEARITY
vs. SUPPLY VOLTAGE
DIFFERENTIAL NONLINEARITY
vs. INPUT CODE
DIFFERENTIAL NONLINEARITY
vs. TEMPERATURE
0
-0.1
-0.2
-0.3
-0.4
-0.5
1.00
0.75
0.50
0.25
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.25
-0.50
-0.75
-1.00
2.7
3.4
4.1
4.8
5.5
0
256
512
768
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
INPUT CODE
TEMPERATURE (°C)
ZERO-CODE ERROR
vs. TEMPERATURE
ZERO-CODE ERROR
vs. SUPPLY VOLTAGE
GAIN ERROR
vs. SUPPLY VOLTAGE
10
8
10
8
-2.0
-1.6
-1.2
-0.8
-0.4
0
6
6
4
4
2
2
NO LOAD
NO LOAD
60
NO LOAD
4.8
0
0
2.7
3.4
4.1
4.8
2.7
3.4
4.1
5.5
-40
-15
10
35
85
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Typical Operating Characteristics (continued)
(V
= +5V, R = 5kΩ, T = +25°C.)
L A
DD
DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT (NOTE 6)
DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT (NOTE 6)
GAIN ERROR vs. TEMPERATURE
6
5
4
3
2
1
0
-2.0
-1.6
-1.2
-0.8
-0.4
0
2.5
2.0
1.5
1.0
0.5
0
CODE = 100 hex
CODE = 3FF hex
NO LOAD
0
2
4
6
8
10
-40
-15
10
35
60
85
0
2
4
6
8
10
OUTPUT SOURCE CURRENT (mA)
TEMPERATURE (°C)
OUTPUT SINK CURRENT (mA)
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. INPUT CODE
100
100
90
80
70
60
50
120
100
80
60
40
20
0
95
90
85
80
NO LOAD
CODE = 3FF hex
CODE = 3FF hex
NO LOAD
NO LOAD
-40
-15
10
35
60
85
2.5
3.5
4.5
5.5
0
256
512
768
1024
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
INPUT CODE
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
EXITING SHUTDOWN
POWER-UP GLITCH
MAX5811 toc18
MAX5811 toc17
500
400
300
200
100
0
5V
V
DD
T
= -40°C
A
T
= +25°C
A
OUT
500mV/div
0
10mV/div
OUT
T
= +85°C
A
Z
= HIGH IMPEDANCE
OUT
NO LOAD
2µs/div
100µs/div
2.7
3.4
4.1
4.8
5.5
C
= 200pF
CODE = 200 hex
LOAD
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
5
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Typical Operating Characteristics (continued)
(V
= +5V, R = 5kΩ, T = +25°C.)
L A
DD
SETTLING TIME
(POSITIVE)
MAJOR-CARRY TRANSITION
(POSITIVE)
MAJOR-CARRY TRANSITION
(NEGATIVE)
MAX5811 toc21
MAX5811 toc19
MAX5811 toc20
5V
V
DD
0
OUT
500mV/div
OUT
5mV/div
10mV/div
OUT
2µs/div
2µs/div
CODE = 200 hex to 1FF hex
100µs/div
C = 200pF
LOAD
CODE = 100 hex to 300 hex
C
L
= 200pF
LOAD
R = 5kΩ
SETTLING TIME
(NEGATIVE)
DIGITAL FEEDTHROUGH
MAX5811 toc22
MAX5811 toc23
OUT
500mV/div
2µs/div
C
= 200pF
= 12kHz
CODE = 000 hex
LOAD
C
= 200pF
CODE = 300 hex to 100 hex
LOAD
f
SCL
Note 6: The ability to drive loads less than 5kΩ is not implied.
6
_______________________________________________________________________________________
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Pin Description
PIN
1
NAME
FUNCTION
V
Power Supply and DAC Reference Input
Ground
DD
2
GND
SDA
SCL
ADD
OUT
3
Bidirectional Serial Data I/O
Serial Clock Line
4
5
Address Select. A logic high sets the address LSB to 1, a logic low sets the address LSB to 0.
Analog Output
6
buffer output swings rail-to-rail, and is capable of dri-
Detailed Description
ving 5kΩ in parallel with 200pF. The output settles to
The MAX5811 is a 10-bit, voltage-output DAC with an
I2C/SMBus-compatible 2-wire interface. The device
consists of a serial interface, power-down circuitry,
input and DAC registers, a 10-bit resistor string DAC,
unity-gain output buffer, and output resistor network.
The serial interface decodes the address and control
bits, routing the data to either the input or DAC register.
Data can be directly written to the DAC register imme-
diately updating the device output, or can be written to
the input register without changing the DAC output.
Both registers retain data as long as the device is pow-
ered.
0.5LSB within 4µs.
Power-On Reset
The MAX5811 features an internal POR circuit that ini-
tializes the device upon power-up. The DAC registers
are set to zero scale and the device is powered-down
with the output buffer disabled and the output pulled to
GND through the 100kΩ termination resistor. Following
power-up, a wake-up command must be initiated
before any conversions are performed.
Power-Down Modes
The MAX5811 has three software-controlled low-power
power-down modes. All three modes disable the output
DAC Operation
The MAX5811 uses a segmented resistor string DAC
architecture, which saves power in the overall system
and guarantees output monotonicity. The MAX5811’s
input coding is straight binary, with the output voltage
given by the following equation:
buffer and disconnect the DAC resistor string from V
,
DD
reducing supply current draw to 300nA. In power-down
mode 0, the device output is high impedance. In
power-down mode 1, the device output is internally
pulled to GND by a 1kΩ termination resistor. In power-
down mode 2, the device output is internally pulled to
GND by a 100kΩ termination resistor. Table 1 shows
the power-down mode command words.
V
×(D)
REF
V
=
OUT
N
2
Upon wake-up, the DAC output is restored to its previ-
ous value. Data is retained in the input and DAC regis-
ters during power-down mode.
where N = 10 (bits), and D = the decimal value of the
input code (0 to 1023).
Output Buffer
The MAX5811 analog output is buffered by a precision,
unity-gain follower that slews at about 0.5V/µs. The
Digital Interface
The MAX5811 features an I2C/SMBus-compatible 2-
wire interface consisting of a serial data line (SDA) and
Table 1. Power-Down Command Bits
POWER-DOWN
COMMAND BITS
MODE/FUNCTION
PD1
PD0
0
0
1
1
0
1
0
1
Power-up device. DAC output restored to previous value.
Power-down mode 0. Power-down device with output floating.
Power-down mode 1. Power-down device with output terminated with 1kΩ to GND.
Power-down mode 2. Power-down device with output terminated with 100kΩ to GND.
_______________________________________________________________________________________
7
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
SDA
t
SU, STA
t
BUF
t
SU, DAT
t
HD, STA
t
t
SP
SU, STO
t
LOW
t
HD, DAT
SCL
t
HIGH
t
HD, STA
t
t
F
R
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. 2-Wire Serial lnterface Timing Diagram
S
S
r
P
a serial clock line (SCL). The MAX5811 is SMBus com-
patible within the range of V = 2.7V to 3.6V. SDA and
DD
SCL
SDA
SCL facilitate bidirectional communication between the
MAX5811 and the master at rates up to 400kHz. Figure
1 shows the 2-wire interface timing diagram. The
MAX5811 is a transmit/receive slave-only device, rely-
ing upon a master to generate a clock signal. The mas-
ter (typically a microcontroller) initiates data transfer on
the bus and generates SCL to permit that transfer.
A master device communicates to the MAX5811 by
transmitting the proper address followed by command
and/or data words. Each transmit sequence is framed
Figure 2. START/STOP Conditions
by a START (S) or REPEATED START (S ) condition and
r
a STOP (P) condition. Each word transmitted over the
bus is 8 bits long and is always followed by an
acknowledge clock pulse.
SCL
SDA
The MAX5811 SDA and SCL drivers are open-drain
outputs, requiring a pullup resistor (500Ω or greater) to
generate a logic high voltage (see Typical Operating
STOP
START
LEGAL STOP CONDITION
Circuit). Series resistors R are optional. These series
S
resistors protect the input stages of the MAX5811 from
high-voltage spikes on the bus lines, and minimize
crosstalk and undershoot of the bus signals.
SCL
SDA
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high are control signals (see START and
STOP Conditions). SDA and SCL idle high when the
I2C bus is not busy.
ILLEGAL
START
STOP
ILLEGAL EARLY STOP CONDITION
Figure 3. Early STOP Condition
START and STOP Conditions
When the serial interface is inactive, SDA and SCL idle
high. A master device initiates communication by issu-
ing a START condition. A START condition is a high-to-
8
_______________________________________________________________________________________
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
low transition on SDA with SCL high. A STOP condition
2
Table 2. MAX5811 I C Slave Addresses
is a low-to-high transition on SDA while SCL is high
(Figure 2). A START condition from the master signals
the beginning of a transmission to the MAX5811. The
master terminates transmission by issuing a not
acknowledge followed by a STOP condition (see
Acknowledge Bit). The STOP condition frees the bus. If
a repeated START condition (Sr) is generated instead of
a STOP condition, the bus remains active. When a
STOP condition or incorrect address is detected, the
MAX5811 internally disconnects SCL from the serial
interface until the next START condition, minimizing digi-
tal noise and feedthrough.
DEVICE ADDRESS
PART
V
ADD
(A ...A )
6
0
MAX5811L
MAX5811L
MAX5811M
MAX5811M
MAX5811N
MAX5811N
MAX5811P
MAX5811P
GND
0010 000
0010 001
0010 010
0010 011
0110 100
0110 101
1010 100
1010 101
V
DD
GND
V
DD
GND
V
DD
GND
V
DD
Early STOP Conditions
The MAX5811 recognizes a STOP condition at any point
during transmission except if a STOP condition occurs in
the same high pulse as a START condition (Figure 3).
This condition is not a legal I2C format; at least one
clock pulse must separate any START and STOP condi-
tions.
S
A6
A5
A4
A3
A2
A1
A0
R/W
Figure 4. Slave Address Byte Definition
Repeated START Conditions
A REPEATED START (S ) condition may indicate a
r
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
C3
C2
C1
C0
D9
D8
D7
D6
read operation. S may also be used when the bus
r
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX5811 ser-
ial interface supports continuous write operations with
Figure 5. Command Byte Definition
value bit by bit, allowing the interface to power down
immediately if an incorrect address is detected. The
LSB of the address word is the Read/Write (R/W) bit.
R/W indicates whether the master is writing to or read-
ing from the MAX5811 (R/W = 0 selects the write condi-
tion, R/W = 1 selects the read condition). After
receiving the proper address, the MAX5811 issues an
ACK by pulling SDA low for one clock cycle.
or without an S condition separating them. Continuous
r
read operations require S conditions because of the
r
change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. ACK is always generated by the
receiving device. The MAX5811 generates an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX5811 waits for the receiving device to generate
an ACK. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master should reattempt communica-
tion at a later time.
The MAX5811 has eight different factory/user-pro-
grammed addresses (Table 2). Address bits A6
through A1 are preset, while A0 is controlled by ADD.
Connecting ADD to GND sets A0 = 0. Connecting ADD
sets A0 = 1. This feature allows up to eight
MAX5811s to share the same bus.
to V
DD
Write Data Format
In write mode (R/W = 0), data that follows the address
byte controls the MAX5811 (Figure 5). Bits C3–C0 con-
figure the MAX5811 (Table 3). Bits D9–D0 are DAC
data. Bits S1 and S0 are sub-bits and are always zero.
Input and DAC registers update on the falling edge of
SCL during the acknowledge bit. Should the write cycle
be prematurely aborted, data is not updated and the
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by the 7-
bit slave address (Figure 4). When idle, the MAX5811
waits for a START condition followed by its slave
address. The serial interface compares each address
_______________________________________________________________________________________
9
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Table 3. Command Byte Definitions
SERIAL DATA INPUT
FUNCTION
C3
C2
C1
C0
D9/PD1*
D8/PD0*
D7-D6
Load DAC with new data from the following data byte and
update DAC output simultaneously as soon as data is
available from the serial bus. The DAC and input registers
are updated with the new data.
DAC
DATA
DAC
DATA
DAC
DATA
1
1
0
0
DAC
DATA
DAC
DATA
DAC
DATA
Load input register with data from the following data byte.
DAC output remains unchanged.
1
1
1
1
1
1
0
1
1
1
0
1
DAC
DATA
DAC
DATA
DAC
DATA
Load input register with data from the following data byte.
Update DAC output to the previously stored data.
Update DAC output from input register. The device
ignores any new data.
X
X
XX
Read data request. Data bits are ignored. The contents of
the DAC register are available on the bus.
1
0
0
0
1
1
X
X
X
X
X
X
X
0
0
X
0
1
XX
XX
XX
Power up the device.
Power-down mode 0. Power down device with output
floating.
Power-down mode 1. Power down device with output
terminated with 1kΩ to GND.
0
0
1
1
X
X
X
X
1
1
0
1
XX
XX
Power-down mode 2. Power down device with output
terminated with 100kΩ to GND.
*When C3 = 0 and C2 = 1, data bits D9 and D8 write to the power-down registers (PD1 and PD0).
X = Don’t care.
MSB
S
LSB
R/W
MSB
C3
LSB
D6
A6
A5
A4
D4
A4
A3
D3
A3
A2
D2
A2
A1
D1
A1
A0
ACK
C2
C1
C0
D9
D8
D7
ACK
MSB
D5
LSB
S0
D0
S1
ACK
P
EXAMPLE WRITE DATA SEQUENCE
MSB
S
LSB
R/W
MSB
C3
LSB
X
A6
A5
A0
ACK
C2
X
X
PD1
PD0
X
ACK
P
EXAMPLE WRITE TO POWER-DOWN REGISTER SEQUENCE
Figure 6. Example Write Command Sequences
write cycle must be repeated. Figure 6 shows two
example write data sequences.
Read Data Format
In read mode (R/W = 1), the MAX5811 writes the con-
tents of the DAC register to the bus. The direction of
10 ______________________________________________________________________________________
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
MSB
A6
LSB
MSB
C3
LSB
X
R/W
= 0
S
A4
A3
A2
A1
A0
C2
X
X
X
X
ACK
A5
X
ACK
DATA BYTES GENERATED BY MASTER DEVICE
MSB
A6
LSB
MSB
X
LSB
D6
R/W
= 1
ACK
Sr
A4
A3
A2
A1
A0
ACK
X
PD0
D9
D8
D7
A5
PD1
ACK GENERATED BY
MASTER DEVICE
DATA BYTES GENERATED BY MAX5811
LSB
MSB
D5
D4
D3
D2
D1
D0
X
X
ACK
P
Figure 7. Read Word Data Sequence
Digital Feedthrough Suppression
IN
OUT
When the MAX5811 detects an address mismatch, the
serial interface disconnects the SCL signal from the
core circuitry. This minimizes digital feedthrough
caused by the SCL signal on a static output. The serial
interface reconnects the SCL signal once a valid
START condition is detected.
V
DD
OUT
MAX6030/
MAX5811
MAX6050
GND
GND
Applications Information
Figure 8. Powering the MAX5811 from an External Reference
Powering the Device from an
External Reference
data flow reverses following the address acknowledge
by the MAX5811. The device transmits the first byte of
data, waits for the master to acknowledge, then trans-
mits the second byte. Figure 7 shows an example read
data sequence.
The MAX5811 uses the V
as the DAC voltage refer-
DD
ence. Any power-supply noise is directly coupled to the
device output. The circuit in Figure 8 uses a precision
voltage reference to power the MAX5811, isolating the
device from any power-supply noise. Powering the
MAX5811 in such a manner greatly improves overall
performance, especially in noisy systems. The
MAX6030 (3V, 75ppm/°C) or the MAX6050 (5V,
75ppm/°C) precision voltage references are ideal
choices due to the low power requirements of the
MAX5811.
2
I C Compatibility
The MAX5811 is compatible with existing I2C systems.
SCL and SDA are high-impedance inputs; SDA has an
open drain that pulls the data line low during the ninth
clock pulse. The Typical Operating Circuit shows a typ-
ical I2C application. The communication protocol sup-
ports the standard I2C 8-bit communications. The
general call address is ignored. The MAX5811 address
is compatible with the 7-bit I2C addressing protocol
only. No 10-bit address formats are supported.
Digital Inputs and Interface Logic
The MAX5811 2-wire digital interface is I2C and SMBus
compatible. The two digital inputs (SCL and SDA) load
the digital input serially into the DAC. Schmitt-trigger
buffered inputs allow slow-transition interfaces such as
______________________________________________________________________________________ 11
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Functional Diagram
V
DD
INPUT
REGISTER
MUX AND DAC
REGISTER
10-BIT
DAC
OUT
RESISTOR
NETWORK
SERIAL
INTERFACE
POWER-DOWN
CIRCUITRY
MAX5811
SDA ADD SCL
GND
optocouplers to interface directly to the device. The
digital inputs are compatible with CMOS logic levels.
Selector Guide
PART
ADDRESS
0010 00X
0010 01X
0110 10X
1010 10X
Power-Supply Bypassing and
Ground Management
Careful PC board layout is important for optimal system
performance. Keep analog and digital signals separate
to reduce noise injection and digital feedthrough. Use a
ground plane to ensure that the ground return from
GND to the power-supply ground is short and low
MAX5811LEUT
MAX5811MEUT
MAX5811NEUT
MAX5811PEUT
Chip Information
impedance. Bypass V
with a 0.1µF capacitor to
DD
TRANSISTOR COUNT: 7172
ground as close to the device as possible.
PROCESS: BiCMOS
12 ______________________________________________________________________________________
10-Bit Low Power 2-Wire Interface Serial,
Voltage-Output DAC
Package Information
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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