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MAX5938AEEE [MAXIM]

-48V Hot-Swap Controller with VIN Step Immunity, No RSENSE, and Overvoltage Protection;
MAX5938AEEE
型号： MAX5938AEEE
厂家： MAXIM INTEGRATED PRODUCTS    MAXIM INTEGRATED PRODUCTS
描述：

-48V Hot-Swap Controller with VIN Step Immunity, No RSENSE, and Overvoltage Protection
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19-3320; Rev 1; 1/05  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
General Description  
Features  
The MAX5938 is a hot-swap controller for -10V to -80V  
rails. The MAX5938 allows circuit line cards to be safely  
hot-plugged into a live backplane without causing a  
glitch on the power supply. It integrates an adjustable  
♦ -10V to -80V Operation  
♦ No External R Required  
SENSE  
♦ Drives Large Power MOSFETS  
circuit-breaker function requiring no R  
.
SENSE  
♦ Eliminates Inrush Current Spikes During Hot Plug  
The MAX5938 provides a controlled turn-on for circuit  
cards, which limits inrush current and prevents both  
glitches on the power-supply rail and damage to board  
connectors and components. Before startup, the  
MAX5938 performs a Load Probe™ test to detect the  
presence of a short-circuit condition. If a short-circuit  
condition does not exist, the device limits the inrush cur-  
rent drawn by the load by gradually turning on the exter-  
nal MOSFET. Once the external MOSFET is fully  
enhanced, the MAX5938 provides overcurrent and short-  
circuit protection by monitoring the voltage drop across  
into Powered Backplane  
♦ Eliminates Inrush Current Spikes and Dropping of  
Load During Large V Steps  
IN  
♦ Adjustable Circuit-Breaker Threshold with  
Temperature Compensation  
♦ Circuit-Breaker Fault with Transient Rejection  
♦ Shorted Load Detection (Load Probe) Before  
Power MOSFET Turn-On  
the R  
of the external power MOSFET. The  
DS(ON)  
♦ Programmable Load-Voltage Slew Rate Controls  
MAX5938 integrates a 400mA fast GATE pulldown to  
guarantee that the external MOSFET is rapidly turned off  
in the event of an overcurrent or short-circuit condition.  
Inrush Current  
♦ ±±2.4 Accuracꢀy Programmable Turn-OnꢁOff  
Voltage (UVLO)  
The MAX5938 also protects the system against input  
voltage (V ) steps. During an input voltage step, the  
IN  
♦ Overvoltage Fault Protection with Transient  
device limits the current drawn by the load to a safe level  
without shutting down the load. The device also includes  
ON/OFF control, selectable PGOOD output polarity,  
undervoltage (UV) and overvoltage (OV) protection.  
Rejection  
♦ Autoretrꢀ and Latched Fault Management  
Available  
The device offers latched (MAX5938L) or autoretry  
(MAX5938A) fault management. Both the MAX5938A  
and MAX5938L are available in a 16-pin QSOP package  
and are specified for the extended (-40°C to +85°C)  
temperature range.  
♦ Low Quiescent Current (1mA)  
Ordering Information  
PART  
TEMP RANGE  
-40°C to +85°C  
-40°C to +85°C  
PIN-PACKAGE  
16 QSOP  
MAX5938AEEE  
MAX5938LEEE  
Applications  
16 QSOP  
Servers  
Telecom Line Cards  
Network Switches  
Solid-State Circuit Breakers  
Network Routers  
Pin Configuration  
TOP VIEW  
GND  
1
2
3
4
5
6
7
8
16 PGOOD  
15 N.C.  
N.C.  
OFF  
ON  
14  
V
OUT  
MAX5938  
13 N.C.  
OV  
12 CB_ADJ  
11 GATE  
10 N.C.  
STEP_MON  
POL_SEL  
Typical Operating Circuit appears at end of data sheet.  
V
9
LP  
EE  
Load Probe is a trademark of Maxim Integrated Products, Inc.  
QSOP  
________________________________________________________________ Maxim Integrated Products  
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at  
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
ABSOLUTE MAXIMUM RATINGS  
EE OUT  
V
, V  
, PGOOD, LP,  
GATE (during 2V clamp, continuous) .............................50mA  
GATE (during gate pulldown, continuous)......................50mA  
STEP_MON to GND............................................+0.3V to -85V  
PGOOD to V .....................................................-0.3V to +85V  
Continuous Power Dissipation (T = +70°C)  
OUT  
A
V
, LP, STEP_MON to V .................................-0.3V to +85V  
16-Pin QSOP (derate 8.3mW/°C above +70°C)...........667mW  
Operating Temperature Range ...........................-40°C to +85°C  
Junction Temperature .....................................................+150°C  
Storage Temperature Range ............................-65°C to +150°C  
Lead Temperature (soldering, 10s) ................................+300°C  
OUT  
EE  
GATE to V ...........................................................-0.3V to +20V  
ON, OFF, OV, POL_SEL, CB_ADJ to V ................-0.3V to +6V  
Input Current  
EE  
EE  
LP (internally duty-cycle limited)..........................................1A  
PGOOD (continuous)......................................................80mA  
GATE (during 15V clamp, continuous) ...........................30mA  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional  
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to  
absolute maximum rating conditions for extended periods may affect device reliability.  
ELECTRICAL CHARACTERISTICS  
(V = -10V to -80V, V = (GND - V ), V  
= V , R = 200Ω, V  
= V  
A
= 2V, V = V  
= V , POL_SEL open, T  
CB_ADJ EE  
A
IN  
EE  
ON  
OFF  
OV  
EE  
STEP_MON  
EE LP  
= -40°C to +85°C, unless otherwise noted. Typical values are at V = -48V, T = +25°C.) (Notes 1, 2)  
EE  
PARAMETER  
Operating Voltage Range  
Operating Supply Current  
ONꢁOFFy OV  
SYMBOL  
CONDITIONS  
Referenced to GND  
MIN  
TYP  
MAX  
-10  
UNITS  
V
-80  
V
EE  
I
0.95  
1.4  
mA  
CC  
ON Reference Threshold Rising  
ON Reference Threshold Falling  
ON Glitch Rejection (Note 3)  
OFF Reference Threshold  
ON/OFF/OV Input Bias Current  
OV Reference Threshold, Rising  
OV Reference Threshold, Falling  
OV Transient Rejection  
V
V
V
V
increasing  
1.219  
1.069  
0.80  
1.219  
-25  
1.25  
1.125  
1.5  
1.281  
1.181  
2.25  
V
V
ON_REF,R  
ON  
ON  
ON  
V
decreasing  
decreasing  
ON_REF,F  
t
ms  
V
REJ  
V
1.25  
1.281  
+25  
OFF_REF  
I
nA  
V
BIAS  
V
V
V
V
increasing  
decreasing  
1.219  
1.069  
0.80  
80  
1.25  
1.125  
1.5  
1.281  
1.181  
2.25  
OV_REF,R  
OV_REF,F  
OV  
OV  
V
t
OV increasing  
ms  
ms  
OVREJ  
Power-Up Delay (Note 4)  
t
220  
380  
ONDLY  
V
= V = -80V, V  
= GND,  
OUT  
OFF  
EE  
V
to V Leakage Current  
0.01  
1
µA  
OUT  
EE  
PGOOD open  
LP to V Leakage Current  
V
= V = -80V, LP = GND  
0.01  
-34  
1
µA  
µA  
EE  
OFF  
EE  
POL_SEL to V Input Current  
EE  
POL_SEL = V  
-50  
-20  
EE  
GATE DRIVE  
V
= 10V  
6.5  
8.1  
6.8  
10  
7.2  
IN  
External Gate-Drive Voltage  
V
V
- V  
EE  
V
V
GS  
GATE  
14V < V < 80V  
12.8  
IN  
I
I
I
I
= 9mA  
= 20mA  
= 1mA  
= 10mA  
13.5  
16  
CLAMP  
CLAMP  
CLAMP  
CLAMP  
MOSFET fully  
enhanced  
17  
19.5  
2.55  
2.93  
-35  
GATE to V Clamp Voltage  
EE  
2.1  
2.5  
-52  
9.0  
7.5  
9.0  
Power-off,  
V
V
V
= GND  
EE  
Open-Loop Gate Charge Current  
I
= V , V = GND  
EE OUT  
-66  
2.4  
µA  
mA  
G,ON  
GATE  
V
V
> 10V  
14.1  
12.5  
14.8  
IN  
IN  
GATE Pulldown Switch  
On-Resistance  
- V  
EE  
=
GATE  
R
G,OFF  
500mV  
> 14V  
Output-Voltage Slew Rate  
SR  
l dV  
/dt l, C  
OUT  
= 0  
V/ms  
SLEW  
±
_______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
ELECTRICAL CHARACTERISTICS (continued)  
(V = -10V to -80V, V = (GND - V ), V  
= V , R = 200Ω, V  
= V  
A
= 2V, V = V  
= V , POL_SEL open, T  
CB_ADJ EE  
A
IN  
EE  
ON  
OFF  
OV  
EE  
STEP_MON  
EE LP  
= -40°C to +85°C, unless otherwise noted. Typical values are at V = -48V, T = +25°C.) (Notes 1, 2)  
EE  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
CIRCUIT BREAKER AND SHORT CIRCUIT  
T
T
T
T
T
T
T
T
T
T
= +85°C  
= +25°C  
= -40°C  
= +85°C  
= +25°C  
= -40°C  
= +85°C  
= +25°C  
= -10°C  
= -40°C  
55  
39  
72  
50  
89  
61  
A
A
A
A
A
CB_ADJ Bias Current  
I
CB_ADJ = V  
CB_ADJ = V  
µA  
CB_ADJ  
EE  
33  
59  
41  
72  
85  
59  
50  
EE  
33  
A
A
A
A
A
Circuit-Breaker Threshold  
V
mV  
123  
85  
144  
100  
82  
165  
115  
98  
CB  
R
= 2kΩ  
CB_ADJ  
66  
66  
I
Temperature Coefficient  
-40°C < T < +85°C  
6000  
1.2  
144  
100  
82  
ppm/°C  
ms  
CB_ADJ  
A
Circuit-Breaker Glitch Rejection  
t
1.0  
112  
75  
1.6  
176  
125  
114  
CB_DLY  
T
= +85°C  
= +25°C  
= -10°C  
= -40°C  
= +85°C  
= +25°C  
= -10°C  
A
A
A
A
A
A
A
T
T
T
T
T
T
CB_ADJ = V  
EE  
50  
66  
Short-Circuit Threshold (Note 5)  
V
mV  
ns  
SC  
224  
159  
108  
288  
200  
164  
352  
241  
220  
R
= 2kΩ  
CB_ADJ  
T
A
= -40°C  
= 0,  
132  
150mV overdrive, C  
to GATE below 1V  
LOAD  
Short-Circuit Response Time  
330  
500  
INPUT-VOLTAGE STEP PROTECTION  
Input-Voltage-Step Detection  
Threshold  
STEP  
1.219  
-10.8  
1.25  
-10  
1.281  
-9.2  
V
TH  
Input-Voltage-Step Threshold  
Offset Current  
I
µA  
STEP_OS  
LOAD-PROBE CIRCUIT  
Load-Probe Switch On-Resistance  
Load-Probe Timeout  
V
- V = 1V  
7.5  
220  
16 x  
11  
Ω
LP  
EE  
t
80  
380  
ms  
LP  
Load-Probe Retry Time  
t
s
LP_OFF  
t
LP  
Shorted Load Detection Voltage  
Threshold  
V
Referenced to GND  
-220  
-200  
-180  
mV  
TH_LP  
_______________________________________________________________________________________  
3
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
ELECTRICAL CHARACTERISTICS (continued)  
(V = -10V to -80V, V = (GND - V ), V  
= V , R = 200Ω, V  
= V  
A
= 2V, V = V  
= V , POL_SEL open, T  
CB_ADJ EE  
A
IN  
EE  
ON  
OFF  
OV  
EE  
STEP_MON  
EE LP  
= -40°C to +85°C, unless otherwise noted. Typical values are at V = -48V, T = +25°C.) (Notes 1, 2)  
EE  
PARAMETER  
SYMBOL  
CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
LOGIC AND FAULT MANAGEMENT  
16 x  
Autoretry Delay  
t
s
RETRY  
t
LP  
0.74  
x V  
|V  
- V | falling  
EE  
OUT  
CB  
PGOOD Assertion Threshold  
mV  
ms  
0.26  
x V  
Hysteresis  
CB  
PGOOD Assertion Delay Time  
(Note 6)  
t
0.70  
1.26  
1.85  
PGOOD  
I
V
= 1mA, referenced to V  
< (GND - 5V )  
SINK  
OUT,  
PGOOD Low Voltage  
V
0.05  
0.01  
0.4  
1
V
OL  
OUT  
PGOOD Open-Drain Leakage  
I
V
= -80V, PGOOD = GND  
EE  
µA  
L
Note 1: All currents into pins are positive and all currents out of pins are negative. All voltages referenced to V , unless otherwise  
EE  
specified.  
Note ±: All limits are 100% tested at +25°C and +85°C. Limits at -40°C and -10°C are guaranteed by characterization.  
Note 3: V  
drops below the V  
threshold are ignored during this time.  
ON  
ON_REF,F  
Note .: Delay time from a valid on condition until the load-probe test begins.  
Note 5: The short-circuit threshold is V = 2 x V  
.
CB  
SC  
Note 6: The time when PGOOD condition is met until PGOOD signal is asserted.  
Typical Operating Characteristics  
(V = -48V, GND = 0V, V = GND - V , POL_SEL = floating, all voltages are referenced to V , unless otherwise noted. T = +25°C,  
EE  
IN  
EE  
EE  
A
unless otherwise noted.)  
SUPPLY CURRENT  
vs. INPUT VOLTAGE  
SUPPLY CURRENT  
vs. TEMPERATURE  
GATE-DRIVE VOLTAGE  
vs. INPUT VOLTAGE  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
10.5  
V
= 72V  
IN  
10.0  
9.5  
9.0  
8.5  
8.0  
7.5  
7.0  
6.5  
6.0  
V
= 48V  
IN  
V
= 12V  
IN  
10  
20  
30  
40  
50  
60  
70  
80  
-40  
-15  
10  
35  
60  
85  
10  
20  
30  
40  
50  
60  
70  
80  
INPUT VOLTAGE (V)  
TEMPERATURE (°C)  
INPUT VOLTAGE (V)  
.
_______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Typical Operating Characteristics (continued)  
(V = -48V, GND = 0V, V = GND - V , POL_SEL = floating, all voltages are referenced to V , unless otherwise noted. T = +25°C,  
EE  
IN  
EE  
EE  
A
unless otherwise noted.)  
GATE PULLDOWN CURRENT  
vs. GATE VOLTAGE  
RETRY TIME  
vs. TEMPERATURE  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
4.0  
3.9  
3.8  
3.7  
3.6  
3.5  
3.4  
3.3  
3.2  
3.1  
3.0  
C
= 0, C  
= 100µF  
GATE  
LOAD  
0
0
1
2
3
4
5
6
7
8
9
10  
-40  
-15  
10  
35  
60  
85  
V
(V)  
GATE  
TEMPERATURE (°C)  
SHORT-CIRCUIT EVENT  
CIRCUIT-BREAKER EVENT  
STARTUP WAVEFORM  
MAX5938 toc08  
MAX5938 toc07  
MAX5938 toc06  
V
= 48V  
V
V
= 48V  
IRFR1310  
= 2kΩ  
IN  
IN  
IN  
50V/div  
R
V
V
CB_ADJ  
GATE  
GATE  
POL_SEL = OPEN  
10V/div  
10V/div  
V
GATE  
10V/div  
V
V
V
OUT  
OUT  
OUT  
50V/div  
50V/div  
50V/div  
V
PGOOD  
50V/div  
V
PGOOD  
V
PGOOD  
50V/div  
50V/div  
IRFR1310  
R
R
= 2kΩ  
CB_ADJ  
I
I
IN  
IN  
= 48Ω  
LOAD  
R
C
= 48Ω  
= 100µF  
LOAD  
LOAD  
10A/div  
2A/div  
I
IN  
POL_SEL = OPEN  
2A/div  
400ns/div  
1ms/div  
40ms/div  
V
SLEW RATE  
NORMALIZED CIRCUIT-BREAKER  
THRESHOLD vs. TEMPERATURE  
OUT  
vs. TEMPERATURE  
10.0  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
C
= 0, C  
= 100µF  
GATE  
LOAD  
9.5  
9.0  
8.5  
8.0  
7.5  
7.0  
6.5  
6.0  
5.5  
5.0  
V
= 72V  
IN  
V
= 48V  
IN  
V
= 12V  
IN  
-40  
-15  
10  
35  
60  
85  
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
_______________________________________________________________________________________  
5
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Typical Operating Characteristics (continued)  
(V = -48V, GND = 0V, V = GND - V , POL_SEL = floating, all voltages are referenced to V , unless otherwise noted. T = +25°C,  
EE  
IN  
EE  
EE  
A
unless otherwise noted.)  
INPUT VOLTAGE STEP TO  
FAULT MANAGEMENT  
INPUT VOLTAGE STEP EVENT (NO FAULT)  
MAX5938 toc11  
MAX5938 toc12  
V
IN  
V
IN  
50V/div  
50V/div  
V
GATE  
V
10V/div  
GATE  
10V/div  
V
OUT  
V
OUT  
50V/div  
100V/div  
CIRCUIT-BREAKER  
THRESHOLD  
V
PGOOD  
V
PGOOD  
50V/div  
100V/div  
ALL VOLTAGES REFERENCED TO V  
EE  
I
IN  
I
IN  
1A/div  
2A/div  
4ms/div  
4ms/div  
IRFR1310  
IRFR1310  
R
R
= 2kΩ  
CB_ADJ  
R
R
= 2kΩ  
CB_ADJ  
= 80Ω  
LOAD  
= 20Ω  
LOAD  
OVERVOLTAGE TRANSIENT TO  
FAULT MANAGEMENT  
OVERVOLTAGE TRANSIENT (NO FAULT)  
MAX5938 toc14  
MAX5938 toc13  
V
GND  
V
IN  
50V/div  
50V/div  
V
GATE  
V
GATE  
10V/div  
10V/div  
V
OUT  
V
50V/div  
OUT  
50V/div  
V
PGOOD  
t
OVREJ  
50V/div  
V
PGOOD  
50V/div  
2ms/div  
4ms/div  
GATE TO V CLAMP VOLTAGE AT  
EE  
GATE TO V CLAMP VOLTAGE MOSFET  
EE  
POWER-OFF vs. GATE SINK CURRENT  
FULLY ENHANCED vs. GATE SINK CURRENT  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
18  
17  
16  
15  
14  
13  
12  
11  
10  
9
V
= -48V, V = V = 2V  
ON OFF  
V
= GND = 0V  
EE  
EE  
8
0
2
4
6
8
10 12 14 16 18 20  
(mA)  
0
2
4
6
8
10 12 14 16 18 20  
(mA)  
I
I
SINK  
SINK  
6
_______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Pin Description  
PIN  
NAME  
FUNCTION  
1
GND  
Ground. The high supply connection for a negative rail hot-swap controller.  
2, 10,  
13, 15  
N.C.  
OFF  
No Connection. Not internally connected. Leave open.  
Off Control Input. Referenced to V . Drive OFF and ON above 1.25V (typ) to turn on the MAX5938. When the  
EE  
ON input low requirements are met and OFF falls below 1.25V (typ), the MAX5938 turns off.  
3
4
On Control Input. Referenced to V . Drive ON and OFF above the 1.25V rising thresholds to turn on the  
EE  
MAX5938. When the voltage at OFF falls below its 1.25V (typ) threshold and the voltage at ON falls below  
1.125V for longer than the ON 1.5ms glitch rejection period, the MAX5938 turns off.  
ON  
OV  
Overvoltage Control Input. Referenced to V . When the voltage at OV rises above the 1.25V rising threshold,  
EE  
5
6
GATE pulls to V until OV falls below the 1.125V falling threshold. If the overvoltage condition remains longer  
EE  
than 1.5ms, fault management initiates and PGOOD deasserts (see the Detailed Description).  
Input Voltage Step Monitor. Connect a resistor between STEP_MON and V to set the step sensitivity.  
Connect a capacitor from GND to STEP_MON to adjust the step response relative to a negative step at V to  
eliminate false circuit-breaker and short-circuit faults. Connect to V to disable the step immunity function.  
EE  
See the Selecting Resistor and Capacitor Values for Step Monitor section in the Applications Information.  
EE  
EE  
STEP_MON  
POL_SEL  
PGOOD Output Polarity Select. Leave POL_SEL open for an active-low PGOOD assertion. Connect POL_SEL  
to V for an active-high open-drain PGOOD assertion.  
EE  
7
8
V
Negative Input Voltage  
EE  
Load-Probe Detect. Connect a resistor from LP to V  
to set the load-probe test current. Limit load-probe  
OUT  
9
LP  
test current to 1A2 Connect to V to disable load-probe function.  
EE  
11  
GATE  
Gate-Drive Output. Connect to the gate of the external n-channel MOSFET.  
Circuit-Breaker Adjust. Connect a resistor from CB_ADJ to V to adjust the circuit-breaker threshold. Short  
EE  
12  
14  
16  
CB_ADJ  
CB_ADJ to V for the default circuit-breaker 50mV (typ) threshold. Leave CB_ADJ open to disable circuit-  
EE  
breaker and short-circuit fault detection.  
Output Voltage Sense. V  
MOSFET.  
is the negative rail of the load. Connect to the drain of the external n-channel  
OUT  
V
OUT  
Power-Good Open-Drain Output. Referenced to V  
. PGOOD asserts high (POL_SEL = V ) or low  
OUT EE  
PGOOD  
(POL_SEL open) when V  
is within limits and there is no fault condition. PGOOD is deasserted when  
OUT  
ON and OFF are cycled low.  
The MAX5938 controls an external n-channel power  
Detailed Description  
The MAX5938 hot-swap controller incorporates over-  
current and overvoltage fault management and is  
intended for negative-supply-rail applications. The  
MOSFET placed in the negative supply path of an  
external load. When no power is applied, the GATE out-  
put of the MAX5938 clamps the V of the MOSFET to 2V  
GS  
keeping the MOSFET turned off (Figure 2). When power  
is applied to the MAX5938, the 2V clamp at the GATE  
output is replaced by a strong pulldown device, which  
MAX5938 eliminates the need for an external R  
SENSE  
and includes V input step protection and load probe,  
IN  
which prevents powering up into a shorted load. It is  
intended for negative 48V telecom power systems  
where low cost, flexibility, multifault management, and  
compact size are required. The MAX5938 is ideal for  
the widest range of systems from those requiring low  
current with small MOSFETs to high-current systems  
requiring large power MOSFETs and low on-resistance.  
pulls GATE to V  
and the V  
of the MOSFET to 0.  
GS  
EE  
As shown in Figure 2, this transition enables the  
MAX5938 to keep the power MOSFET continually off  
during the board insertion phase when the circuit board  
first makes contact with the backplane. Without this  
clamp, the GATE output of a powered-down controller  
would be floating and the MOSFET reverse transfer  
_______________________________________________________________________________________  
7
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
GND  
R
LOAD  
C
LOAD  
PGOOD  
GND  
PG  
PGOOD  
LOGIC  
MAX5938  
V
OUT  
+10V  
+5V  
10V REG  
AND  
5V REG  
50µA TEMP  
COMPENSATED  
CURRENT SOURCE  
V
, V , AND  
SC CB  
75% OF V  
COMPARATORS  
CB  
R
2kΩ  
INT  
BANDGAP  
REF  
CB_ADJ  
V
(1.25V)  
BG  
OFF  
ON  
2V AND  
15V  
CLAMP  
ON, OFF,  
AND OV  
LOGIC CONTROL  
OV  
FAULT  
DETECTION  
52µA  
OV  
STEP  
10µA  
GATE  
CONTROL  
GATE  
STEP_MON  
POL_SEL  
SEQUENCER  
CONTROLLER  
TIMER  
V
BG  
PGOOD  
POLARITY  
LOGIC  
LP  
PG  
LOAD-PROBE  
TEST  
V
EE  
V
EE  
Figure 1. Functional Diagram  
capacitance (gate-to-drain) would pull up and turn on  
the MOSFET gate when the MOSFET drain is rapidly  
The MAX5938 conducts a load-probe test after contact  
transients from the hot plug-in have settled. This follows  
the MAX5938 power-up (when the ON, OFF, and OV  
pulled up by the V step during backplane contact.  
IN  
The MAX5938 GATE clamp can overcome the gate-to-  
drain capacitance of large power MOSFETs with added  
conditions have been met for 220ms (t )) and prior to  
LP  
the turn-on of the power MOSFET. This test pulls a user-  
programmable current through the load (1A, max) for up  
to 220ms (t ) and tests for a voltage of 200mV across  
LP  
slew-rate control (C  
) capacitors while eliminating  
SLEW  
the need for additional gate-to-source capacitance.  
The MAX5938 keeps the MOSFET off indefinitely if the  
supply voltage is below the user-set ON and OFF  
thresholds, if the supply voltage is above the user-set  
overvoltage (OV) threshold, or if a short circuit (user-  
defined) is detected in the load connected to the drain  
of the power MOSFET.  
the load at V  
(Figure 3). This current is set by an  
OUT  
external resistor, R (Figure 17) between V  
and LP.  
LP  
OUT  
When the voltage across the load exceeds 200mV, the  
test is truncated and the GATE turn-on sequence is start-  
ed. If at the end of the 200ms (t ) test period the volt-  
LP  
age across the load has not reached 200mV, the load is  
assumed to be shorted and the current to the load from  
8
_______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
C
R
= 100µF  
LOAD  
C
= 100µF  
GND  
IN  
V
EE  
= 75kΩ  
LP  
20V/div  
V
IN  
GND  
20V/div  
V
LP  
20V/div  
GND  
V
GATE  
1V/div  
V
OUT  
200mV/div  
40ms/div  
4ms/div  
Figure 2. GATE Voltage Clamp During Power-Up  
Figure 3. Load-Probe Test During Initial Power-Up  
V
V
IN  
IN  
50V/div  
50V/div  
V
V
GATE  
GATE  
10V/div  
10V/div  
V
V
OUT  
OUT  
50V/div  
50V/div  
V
V
PGOOD  
PGOOD  
50V/div  
50V/div  
I
I
IN  
IN  
2A/div  
2A/div  
40ms/div  
40ms/div  
Figure 5. MAX5938 Startup into Fault Condition (POL_SEL =  
Floating)  
Figure 4. MAX5938 Normal Startup (POL_SEL = Floating)  
LP is shut off. The MAX5938A times out for 16 x t then  
LP  
the GATE Cycles section in Appendix A). In a normal  
retry the load-probe test. The MAX5938L latches the fault  
condition indefinitely until ON and OFF are cycled low for  
1.5ms or the power is recycled. See the Applications  
power-up GATE cycle, the voltage at V  
(referenced  
OUT  
to V ) ramps to below 74% of the programmed circuit-  
EE  
breaker threshold voltage, V . At this time, the remain-  
CB  
Information for recommendations on selecting R to set  
ing GATE voltage is rapidly pulled up to full  
enhancement. PGOOD is asserted 1.26ms after GATE  
LP  
the load-probe current level.  
is fully enhanced (see Figure 4). If the voltage at V  
OUT  
(when  
Upon successful completion of the load-probe test, the  
MAX5938 enters the power-up GATE cycle and begins  
ramping the GATE voltage with a 52µA current source.  
remains above 74% of the programmed V  
CB  
GATE reaches 90% of full enhancement), then a power-  
up-to-fault-management fault has occurred). GATE is  
rapidly pulled to V , turning off the power MOSFET  
EE  
and disconnecting the load. PGOOD remains deassert-  
ed and the MAX5938 enters the fault management  
mode (Figure 5).  
This current source is restricted if V  
begins to ramp  
OUT  
down faster than the default 9V/ms slew rate. The V  
OUT  
slew rate can be reduced to below 9V/ms by adding  
from GATE to V . Charging up GATE  
C
SLEW  
OUT  
enhances the power MOSFET in a controlled manner  
and ramping V at a user-settable rate controls the  
When the power MOSFET is fully enhanced, the  
OUT  
inrush current from the backplane. The MAX5938 con-  
tinues to charge up the GATE until one of two events  
occurs: a normal power-up GATE cycle is completed or  
a power-up-to-fault-management fault is detected (see  
MAX5938 monitors the drain voltage (V  
) for circuit-  
OUT  
breaker and short-circuit faults. The MAX5938 makes  
use of the power MOSFET’s R as the current-  
DS(ON)  
sense resistance to detect excessive current through  
_______________________________________________________________________________________  
9
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
the load. The short-circuit threshold voltage, V , is  
allow the user to set the sensitivity of the step detection  
SC  
twice V  
(V  
= 2 x V ) and is set by adjusting the  
with an external resistor to V . A capacitor is placed  
EE  
CB  
SC  
CB  
resistance between CB_ADJ and V . There is an inter-  
between GND and the STEP_MON input, which in con-  
junction with the resistor, sets the STEP_MON time  
constant.  
EE  
nal 2kΩ precision-trimmed resistor and an internal 50µA  
current source at CB_ADJ, which results in the mini-  
mum or default V  
of 100mV when CB_ADJ is con-  
SC  
When a step is detected by the STEP_MON input rising  
nected to V . The current source is temperature  
EE  
above its threshold (STEP ), the overcurrent fault  
TH  
compensated (increasing with temperature) to track the  
normalized temperature coefficient of R  
power MOSFETs.  
management is blocked and remains blocked as long  
for typical  
DS(ON)  
as STEP  
is exceeded. When STEP  
is exceeded,  
TH  
TH  
the MAX5938 takes no action until V  
rises above  
OUT  
When the load current is increased during full enhance-  
V
or above V  
for the 1.2ms circuit-breaker glitch  
SC  
CB  
ment, this causes V  
to exceed V but remains less  
rejection period. When either of these conditions  
occurs, a step GATE cycle begins and the GATE is  
immediately brought to V , which turns off the power  
EE  
MOSFET to minimize the resulting inrush current surge  
from the backplane. PGOOD remains asserted. GATE  
is held at V for 350µs, and after about 1ms, begins to  
EE  
ramp up, enhancing the power MOSFET in a controlled  
manner as in the power-up GATE cycle. This provides a  
controlled inrush current to charge the load capaci-  
tance to the new supply voltage (see the GATE Cycles  
section in Appendix A).  
OUT  
CB  
than V , and starts the 1.2ms circuit-breaker glitch  
SC  
rejection timer. At the end of the glitch rejection period,  
if V  
still exceeds V , the GATE is immediately  
OUT  
CB  
pulled to V (330ns), PGOOD is deasserted, and the  
EE  
part enters fault management. Alternatively, during full  
enhancement when V  
exceeds V , there is no  
OUT  
SC  
glitch rejection timer. GATE is immediately pulled to  
, PGOOD is deasserted, and the part enters fault  
V
EE  
management.  
The V step immunity provides a means for transitioning  
IN  
through a large step increase in V with minimal back-  
As in the case of the power-up GATE cycle, if V  
OUT  
drops to less than 74% of the programmed V , inde-  
CB  
pendent of the state of STEP_MON, the GATE voltage is  
rapidly pulled to full enhancement. PGOOD remains  
asserted throughout the step (Figure 6). Otherwise, if the  
STEP_MON input has decayed below its threshold but  
IN  
plane inrush current and without shutting down the load.  
Without V step immunity (when the power MOSFET is  
IN  
fully enhanced), a step increase in V will result in a  
IN  
high inrush current and a large step in V  
trip the circuit breaker.  
, which can  
OUT  
V
remains above 74% of the programmed V  
CB  
OUT  
With V step immunity, the STEP_MON input detects  
IN  
(when GATE reaches 90% of full enhancement), a step-  
to-fault-management fault has occurred. GATE is rapidly  
the step before a short circuit is detected at V  
alters the MAX5938 response to V  
due to the step. The 1.25V voltage threshold at  
STEP_MON and a 10µA current source at STEP_MON  
and  
OUT  
exceeding  
OUT  
pulled to V , turning off the power MOSFET and dis-  
EE  
V
SC  
connecting the load; PGOOD is deasserted and the  
MAX5938 enters the fault management mode (Figure 7).  
V
IN  
5V/div  
V
IN  
40V  
20V  
20V/div  
V
GATE  
40V  
10V/div  
V
GATE  
10V/div  
V
OUT  
V
OUT  
20V/div  
50V/div  
V
PGOOD  
20V/div  
V
PGOOD  
50V/div  
I
IN  
1A/div  
C
R
= 100µF  
= 20Ω  
C
R
= 100µF  
= 100Ω  
LOAD  
LOAD  
LOAD  
LOAD  
I
IN  
5A/div  
2ms/div  
4ms/div  
Figure 7. MAX5938 Response to a Step Input Ending in a Fault  
(V > 0.75V  
Figure 6. MAX5938 Response to a Step Input with No Fault  
(V < 0.75V  
)
CB  
)
CB  
OUT  
OUT  
10 ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Fault Management  
Fault management can be triggered by the following  
conditions:  
V = (GND - V )  
IN EE  
GND  
OFF  
ON  
• V  
exceeds 74% of V  
during GATE ramp at  
CB  
OUT  
90% of full enhancement,  
R4  
• V exceeds the V for longer than 1.2ms during  
CB  
OUT  
full enhancement,  
• V exceeds the V during full enhancement,  
SC  
OUT  
R3  
R2  
R1  
MAX5938  
• Load-probe test fails,  
• V exceeds the programmed overvoltage (OV) limit  
IN  
for more than 1.5ms.  
Once in the fault management mode, GATE will always be  
pulled to V , which turns off the external MOSFET and  
EE  
always deasserts PGOOD. If CB_ADJ is left open, short-  
circuit and circuit-breaker faults are ignored. The  
MAX5938A version has automatic retry following a fault  
while the MAX5938L remains latched in the fault condition.  
OV  
V
EE  
Autoretry Fault Management (MAX5938A)  
If the MAX5938A entered fault management due to an  
OV fault, it will start the autoretry timer when the OV  
fault is removed. For circuit-breaker and short-circuit  
faults, the autoretry timer starts immediately. The timer  
times out in 3.5s (typ) after which the sequencer initi-  
ates a load-probe test and if successful, initiates a nor-  
mal power-up GATE cycle.  
Figure 8. Resetting the MAX5938L after a Fault Condition  
Using a Push-Button Switch  
where I  
= 50µA (typ at +25°C), R  
is an internal  
CB_ADJ  
INT  
precision, 0.5%, 2kΩ resistor at CB_ADJ and R  
CB_ADJ  
EE  
is the external resistor between CB_ADJ and V . The  
current source I  
is temperature-compensated  
CB_ADJ  
Latched Fault Management (MAX5938L)  
(increasing with temperature) to track the normalized  
temperature coefficient of typical power MOSFETs.  
When the MAX5938L enters fault management it  
remains in this condition indefinitely until the power is  
recycled or until OFF is brought below 1.25V (no time  
dependence) and ON is brought below 1.125V for  
1.5ms (typ). In addition, if the MAX5938L enters fault  
management due to an overvoltage fault, the overvolt-  
age fault must be removed. When the last of these con-  
ditions has been met, the sequencer initiates a load-  
probe test and if successful, a normal power-up GATE  
cycle begins. A manual reset circuit as in Figure 2 can  
be used to clear the latch.  
The proper circuit-breaker threshold for an application  
depends on the R  
of the external power MOSFET  
DS(ON)  
and the maximum current the load is expected to draw.  
To avoid false fault indication and dropping of the load,  
the designer must take into account the load response to  
voltage ripples and noise from the backplane power sup-  
ply as well as switching currents in the downstream DC-  
DC converter that is loading the circuit. While the  
circuit-breaker threshold has glitch rejection that ignores  
ripples and noise lasting less than 1.2ms, the short-cir-  
cuit detection is designed to respond very quickly (less  
Circuit-Breaker Threshold  
The MAX5938 has a minimum circuit-breaker threshold  
than 330ns) to a short circuit. For this reason, set V  
SC  
voltage of 50mV when CB_ADJ is connected to V . The  
EE  
and V  
with an adequate margin to cover all possible  
CB  
V
CB  
is half V and can be increased by placing a resis-  
tor between CB_ADJ and V according to the following:  
SC  
ripples, noise, and system current transients (see the  
Setting the Circuit-Breaker and Short-Circuit Thresholds  
section in the Applications Information).  
EE  
1
1
V
CB  
(mV) = / x V (mV) = / x I  
(µA)  
CB_ADJ  
2
SC  
2
x [R (kΩ) + R  
(kΩ)]  
CB_ADJ  
INT  
______________________________________________________________________________________ 11  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Disabling Circuit-Breaker and  
Short-Circuit Functions  
In the MAX5938, the circuit-breaker and short-circuit  
functions can be disabled, if desired, although this is  
not recommended. (See Warning note in the PGOOD  
Open-Drain Output section). This can be accomplished  
by leaving CB_ADJ open. In this case, PGOOD asserts  
1.26ms after GATE has ramped to 90% of full enhance-  
V
OFF_REF  
OFF  
ON  
V
ON_REF,R  
ment, after which V  
is ignored, resulting in the cir-  
OUT  
cuit-breaker and short-circuit faults being ignored.  
220ms  
LOAD-PROBE  
DETECTION TEST  
BEGINS  
PGOOD Open-Drain Output  
The power-good output, PGOOD, is open drain and is  
I
LP  
referenced to V  
. It asserts and latches if V  
OUT  
OUT  
ramps below 74% of V , and with the built-in delay,  
CB  
(a)  
this occurs 1.26ms after the external MOSFET becomes  
fully enhanced. PGOOD deasserts any time the part  
enters fault management. PGOOD has a delayed  
response to ON and OFF. The GATE will go to V  
EE  
OFF  
when OFF is brought below 1.25V (no time depen-  
dence) while ON is brought below 1.125V for 1.5ms.  
This turns off the power MOSFET and allows V  
to  
OUT  
V
OFF_REF  
rise depending on the RC time constant of the load.  
PGOOD, in this situation, deasserts when V rises  
OUT  
ON  
1.3ms  
above V  
for more than 1.4ms or above V  
,
SC  
CB  
whichever occurs first (see Figure 9b).  
V
Since PGOOD is open drain, it requires an external  
pullup resistor to GND. Due to this external pullup,  
PGOOD does not follow positive V steps as well as if  
IN  
ON_REF,F  
GATE  
it were driven by an active pullup. As a result, when  
PGOOD is asserted high, an apparent negative glitch  
appears at PGOOD during a positive V step. This  
IN  
negative glitch is a result of the RC time constant of the  
external resistor and the PGOOD pin capacitance lag-  
ging the V step. It is not due to switching of the inter-  
IN  
V
OUT  
nal logic. To minimize this negative transient, it may be  
necessary to increase the pullup current and/or to add  
a small amount of capacitance from PGOOD to GND to  
compensate for the pin capacitance.  
PGOOD  
(b)  
The PGOOD output logic polarity is selected using  
POL_SEL input. For an active-high output, connect  
Figure 9. ON and OFF Timing Diagram  
POL_SEL to V . Leave POL_SEL open for an active-  
EE  
low output.  
WARNING: When disabling the circuit-breaker and  
short-circuit functions (CB_ADJ open), PGOOD asserts  
1.26ms after the power MOSFET is fully enhanced inde-  
cuit-breaker and short-circuit functions are disabled  
and ON and OFF are cycled low, PGOOD is deassert-  
ed. In summary, when CB_ADJ is open (once the MOS-  
pendent of V  
. Once the MOSFET is fully enhanced  
FET is fully enhanced), the MAX5938 ignores V  
and  
OUT  
OUT  
and ON and OFF are pulled below their respective  
deasserts PGOOD only for an overvoltage fault, when  
ON and OFF are cycled low or when the power to the  
MAX5938 is fully recycled.  
thresholds, the GATE will be pulled to V to turn off the  
EE  
power MOSFET and disconnect the load. When the cir-  
1± ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Undervoltage Lockout (OFF and ON) and  
OV Functions  
Output Voltage (V  
)
OUT  
Slew-Rate Control  
The V  
slew rate controls the inrush current required  
OV, ON, and OFF provide an accurate means to set the  
overvoltage, turn-on, and turn-off voltage levels. All three  
are high-impedance inputs and by use of a 4-element  
OUT  
to charge the load capacitor. The MAX5938 has a  
default internal slew rate set for 9V/ms. The internal cir-  
cuit establishing this slew rate accommodates up to  
about 1000pF of reverse transfer capacitance (Miller  
Capacitance) in the external power MOSFET without  
effecting the default slew rate. Using the default slew  
rate, the inrush current required to charge the load  
capacitance is given by:  
resistor-divider from GND to V , the user can set an  
EE  
upper V threshold for triggering an overvoltage fault, a  
EE  
middle threshold for turning the part on, and a lower  
threshold for turning the part off.  
The input voltage threshold at OFF is 1.25V. ON has  
hysteresis with a rising threshold of 1.25V and a falling  
threshold of 1.125V. The logic of the inputs is such that  
both OFF and ON must be above their thresholds to  
latch the part on. Both OFF and ON must be below their  
respective thresholds to latch the part off, otherwise the  
part stays in its current state. There is glitch rejection on  
the ON input going low, which additionally requires that  
ON remain below its falling threshold for 1.5ms to turn  
off the part. A startup delay of 220ms allows contacts  
and voltages to settle prior to initiating the startup  
sequence. This startup delay is from a valid ON condi-  
tion until the start of the load-probe test.  
I
(mA) = C  
(µF) x SR (V/ms)  
INRUSH  
LOAD  
where SR = 9V/ms (default, typ).  
The slew rate can be reduced by adding an external  
slew-rate control capacitor (C ) from V (the  
SLEW  
OUT  
drain of the power MOSFET) to the GATE output of the  
MAX5938 (Figure 19). Values of C < 4700pF have  
SLEW  
little effect on the slew rate because of the default slew-  
rate control circuit. For C > 4700pF, the combina-  
SLEW  
tion of C  
and reverse transfer capacitance of the  
SLEW  
external power MOSFET dominate the slew rate. When  
> 4700pF, SR and C are inversely related  
C
SLEW  
SLEW  
The OV input has hysteresis with a rising threshold of  
1.25V and a falling threshold of 1.125V. The OV input  
also has a rising fault transient delay of 1.5ms. When  
OV rises above its threshold, an OV GATE cycle is  
immediately initiated (see the GATE Cycles section in  
as follows (Figure 18):  
SR (V/ms) = 23 / C  
(nF)  
SLEW  
If the reverse transfer capacitance of the external  
power MOSFET is large compared to the externally  
added C  
equation above.  
, then it should be added to C  
in the  
SLEW  
Appendix A). The GATE output is brought to V with  
SLEW  
EE  
about 300ns of propagation delay. If the OV input drops  
below its falling threshold before the fault transient  
delay of about 1.5ms, the device will not enter fault  
management mode and the GATE output will ramp up  
to fully enhance the external MOSFET (Figure 10).  
Otherwise, an OV fault occurs (Figure 11). See the  
Setting ON, OFF, and OV Voltage Levels section in the  
Applications Information.  
See the Adjusting the V  
Slew Rate section in the  
OUT  
Applications Information and Figure 18, which graphi-  
cally displays the relation between C  
and slew  
SLEW  
rate. This section discusses specific recommendations  
for compensating power MOSFET parasitics that may  
lead to oscillation when an external C  
is added.  
SLEW  
V
IN  
5V/div  
V
IN  
10V/div  
48V  
48V  
V
V
GATE  
GATE  
10V/div  
10V/div  
t
OVREJ  
V
V
OUT  
OUT  
10V/div  
50V/div  
V
V
PGOOD  
PGOOD  
10V/div  
50V/div  
1ms/div  
2ms/div  
Figure 10. Overvoltage Gate Cycle Without a Fault (t < 1.3ms)  
Figure 11. Overvoltage Fault (t > 1.3ms)  
OV  
OV  
______________________________________________________________________________________ 13  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Applications Information  
Setting ON, OFF, and OV Voltage Levels  
V
IN  
= (GND - V )  
EE  
The trip levels for ON, OFF, and OV can readily be set  
with a 4-element resistor-divider. Total resistance is a  
trade off of quiescent current, threshold tolerance due  
to pin input bias current (25nA), and the ability to follow  
very fast supply transients. Both ON and OV have hys-  
teresis on the reference threshold voltage: the rising  
reference threshold is 1.25V and the falling threshold is  
1.125V. The reference threshold voltage for OFF is  
GND  
OFF  
ON  
R4  
R3  
R2  
R1  
MAX5938  
1.25V. In determining a set of resistors, use V  
=
REF  
= 100kΩ in  
1.25V for ON, OFF, and OV and an R  
TOT  
this example. See Figure 12 for nomenclature. For this  
example, use V = 80V, V = 42V, and V = 38V  
OV  
ON  
OFF  
as the desired voltage trip levels.  
OV  
1) R = R  
4
x V  
x V  
x V  
/ V  
/ V  
/ V  
TOT  
TOT  
TOT  
TOT  
REF  
REF  
REF  
OV  
2) R = R  
3
- R  
4
ON  
OFF  
3) R = R  
- R - R  
3 4  
2
V
EE  
4) R = R  
- R - R - R  
2 3 4  
1
The exact result to three decimal places is R1 =  
96.711kΩ, R2 = 313Ω, R3 = 1.414kΩ, and R4 =  
1.563kΩ. When converted to the nearest 1% standard  
resistor, the values become R1 = 97.6kΩ, R2 = 316Ω,  
R3 = 1.40kΩ, and R4 = 1.58kΩ.  
Figure 12. Programming the MAX5938’s ON, OFF, and OV  
Thresholds  
GND  
50µA  
R
INT  
MAX5938  
I
2kΩ  
0.5%  
CB_ADJ  
V
CB_ADJ  
SC  
SC TRIP  
R
R
R
CB_ADJ  
CB TRIP  
t
CB_DLY  
I
LOAD  
C
LOAD  
LOAD  
V
OUT  
V
EE  
R
ON  
Figure 13. MAX5938 Circuit-Breaker Threshold Adjustment  
1. ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Determine the trip voltages these values will actually  
yield for rising and falling voltages. Rising voltages use  
and the maximum load current plus one half the peak-  
to-peak AC response of V to load-switching cur-  
OUT  
the V  
= 1.25V reference threshold, while falling volt-  
rents and the noise and ripple at V :  
REF  
IN  
ages use V = 1.125V reference threshold.  
LO  
1
(mA) + / x VOUT  
LOAD,MAX 2 AC  
R
(Ω) x I  
DS(ON)  
1) R  
2) V  
3) V  
4) V  
5) V  
6) V  
= R + R + R + R  
TOT  
1
2
3
4
< V (mV)  
CB  
= V  
x R  
/ R  
TOT 4  
OV,RISING  
OV,FALLING  
ON,RISING  
ON,FALLING  
REF  
where  
= V x R  
/ R  
4
LO  
TOT  
TOT  
1
V
(mV) = / x I  
(µA) x [R (kΩ)  
CB_ADJ INT  
CB  
2
= V  
x R  
/ (R + R )  
3 4  
+ R  
(kΩ)]  
REF  
CB_ADJ  
= V x R  
/ (R + R )  
3 4  
R
in a power MOSFET has a positive tempera-  
LO  
TOT  
DS(ON)  
ture coefficient and the MAX5938, when placed adja-  
= V  
x R  
/ (R + R + R )  
OFF  
REF  
TOT  
2
3
4
cent to the power MOSFET, tracks and compensates  
for this temperature coefficient. In the MAX5938, V  
is  
The resulting voltage levels are V  
= 79.82V  
=
CB  
OV,RISING  
half of V , which is set by placing an external resis-  
2.5%, V  
= 71.84V 5%, V  
SC  
OV,FALLING  
ON,RISING  
tance between CB_ADJ and V . The minimum  
EE  
42.32V 2.5%, V  
= 38.09V 5%, and V  
OFF  
ON,FALLING  
(default) short-circuit threshold voltage, V , is set by  
SC  
= 38.26V 2.5%. The voltage tolerance does not  
account for the tolerance of the resistors.  
an internal 2kΩ precision-trimmed ( 0.5%) resistor pro-  
viding a minimum series resistance and a temperature-  
compensated 50µA (+25°C) current source. When  
Setting the Circuit-Breaker and  
Short-Circuit Thresholds  
CB_ADJ is connected to V this gives a 50mV circuit-  
EE  
The MAX5938 can operate with a wide range of power  
MOSFETs to meet the requirements of almost any appli-  
cation. MOSFETs mentioned here are done to demon-  
strate certain capabilities and features of the MAX5938.  
They should not be construed as a recommendation or a  
limitation of the interoperability of the MAX5938.  
breaker threshold. When an external resistor, R  
,
CB_ADJ  
is placed between CB_ADJ and V , the new circuit-  
EE  
breaker threshold becomes:  
1
1
2
V
(mV) = / x V (mV) = / x I  
(µA)  
CB  
2
SC  
CB_ADJ  
x (2kΩ + R  
)
CB_ADJ  
and at +25°C, it becomes:  
In the implementation of the circuit-breaker and short-  
circuit functions, the MAX5938 eliminates the need for  
an external current-sense resistor at the source of the  
power MOSFET. As in any other hot-swap controller,  
the proper circuit-breaker threshold for an application  
1
1
V
CB  
(mV) = / V (mV) = / x 50µA  
2 SC  
2
x (2kΩ + R  
)
CB_ADJ  
The short-circuit and circuit-breaker voltages are sensed  
must take into account the DC level of V  
, while at  
OUT  
at V  
DS(ON)  
, which is the drain of the power MOSFET. The  
of the MOSFET is the current-sense resistance  
OUT  
the same time accommodating the AC response of  
R
V
V
to the modulation of V . The AC response from  
IN  
OUT  
OUT  
and so the total current through the load and load  
capacitance is the drain current of the power MOSFET.  
Accordingly, the voltage at V  
MOSFET drain current is:  
to V  
is dependent on the parasitics of the load,  
IN  
especially the load capacitor, in conjunction with the  
of the power MOSFET. It behaves as a highly  
as a function of  
OUT  
R
DS(ON)  
dampened second-order system. As such, this system  
functions as a bandpass filter from V to V . The  
V
OUT  
= I  
x R  
D,MOSFET DS(ON)  
IN  
OUT  
response of V  
to load-switching currents and volt-  
OUT  
The temperature compensation of the MAX5938 is  
designed to track the R of the typical power  
age ripple and noise from the backplane power supply  
must be taken into account. Adequate margin must be  
DS(ON)  
MOSFET. Figure 14 shows the typical normalized temp-  
provided between V , V , and the DC level of V  
,
CB SC  
which depends on the R  
OUT  
co of the circuit-breaker threshold along with the nor-  
of the power MOSFET  
DS(ON)  
malized tempco of R  
for several typical power  
DS(ON)  
(with V  
at 10V) and the maximum current the load is  
GS  
MOSFETS. When determining the circuit-breaker  
threshold in an application go to the power MOSFET  
manufacturer’s data sheet and locate the maximum  
expected to draw. While the circuit-breaker threshold  
has glitch rejection for V excursions lasting less  
OUT  
than 1.4ms, the short-circuit detection is designed to  
respond very quickly (less than 330ns) to a short cir-  
R
at +25°C with a V  
of 10V. Next, find the fig-  
GS  
DS(ON)  
ure presenting the tempco of normalized R  
or  
DS(ON)  
cuit. In the application, select a value for R  
CB_ADJ  
on-resistance vs. temperature. Since this curve is in  
resulting in a V  
that exceeds the product of R  
CB  
DS(ON)  
______________________________________________________________________________________ 15  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
normalized units, typically with a value of 1 at +25°C, it  
is possible to multiply the curve by the drain voltage at  
+25°C and convert the curve to drain voltage. Now  
compare this curve to that of the MAX5938 normalized  
tempco of the circuit-breaker threshold to make a  
determination of the tracking error in mV between the  
conditions, it becomes imperative that the MAX5938 be  
located as close as possible to the power MOSFET. The  
marginal effect of temperature differences on circuit-  
breaker and short-circuit voltages can be estimated  
from a comparative plot such as Figure 14.  
power MOSFET [I  
x R  
] and the  
)] over the  
D,MOSFET  
DS(ON)  
CB_ADJ  
Selecting a Resistor and Capacitor  
for Step Monitor  
MAX5938 [I  
(µA) x (2kΩ + R  
operating temperature range of the application.  
CB_ADJ  
When a positive V step or ramp occurs, the V  
IN  
IN  
If the tempco of the power MOSFET is greater than the  
MAX5938’s, then additional margin in setting the circuit-  
breaker and short-circuit voltages will be required at  
higher temperatures as compared to +25°C (Figure 15).  
When dissipation in the power MOSFET is expected to  
lead to local temperature elevation relative to ambient  
increase results in a voltage rise at both STEP_MON  
and V  
relative to V . When the voltage at  
EE  
OUT  
STEP_MON is above STEP , the MAX5938 blocks  
TH  
short-circuit and circuit-breaker faults. During this  
STEP_MON high condition, if V  
rises above V , the  
SC  
OUT  
MAX5938 will immediately and very rapidly pull GATE to  
. This turns off the power MOSFET to avoid inrush  
V
EE  
current spiking. GATE is held low for 350µs. About 1ms  
after the start of GATE pulldown, the MAX5938 begins to  
ramp GATE up to turn on the MOSFET in a controlled  
NORMALIZED MOSFET ON-RESISTANCE  
vs. TEMPERATURE  
1.6  
manner that results in ramping V  
down to the new  
OUT  
supply level (see the GATE Cycles section in Appendix  
A). This occurs with the least possible disturbance to  
OUT  
1.4  
1.2  
V
, although during the brief period that the MOSFET  
is off, the voltage across the load droops slightly  
depending on the load current and load storage capaci-  
1.0  
0.8  
0.6  
0.4  
MAX5938  
NORMALIZED V  
tance. PGOOD remains asserted throughout the V  
IN  
CB  
step event.  
IRFR3910  
NORMALIZED R  
The objective in selecting the resistor and capacitor for  
the step monitor function is to ensure that the V steps  
IN  
of all anticipated slopes and magnitudes will be proper-  
ly detected and blocked, which otherwise would result  
in a circuit-breaker or short-circuit fault. The following is  
a brief analysis for finding the resistor and capacitor.  
For a more complete analysis, see Appendix B.  
ON  
IRF1310NS  
NORMALIZED R  
ON  
-40  
-15  
10  
35  
60  
85  
TEMPERATURE (°C)  
Figure 14. MAX5938 Normalized Circuit Breaker  
CIRCUIT-BREAKER  
TRIP REGION  
CIRCUIT-BREAKER  
TRIP REGION  
1/2 x I  
x R  
CB_ADJ  
CB_ADJ  
1/2 x I  
x R  
CB_ADJ  
CB_ADJ  
DS(ON)  
∆V  
CB,MIN  
I
x R  
D
I
D
x R  
DS(ON)  
R
HIGH TEMPCO  
R
LOW TEMPCO  
DS(ON)  
DS(ON)  
∆V  
CB,MIN  
TEMPERATURE  
TEMPERATURE  
T = +25°C  
A
T
= +25°C  
A
Figure 15. Circuit-Breaker Voltage Margin For High and Low Tempco Power MOSFETS  
16 ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
GND  
FAULT  
MGT  
MAX5938  
C
STEP_MON  
I
STEP_OS  
STEP_MON  
STEP_DET  
V
STEP_MON  
CYCLE  
GATE  
LOW  
I
STEP  
STEP  
TH  
ESL  
V
STEP  
IN  
V
SC  
R
SC TRIP  
STEP_MON  
C
LOAD  
LOAD  
ESR  
C
t
CB_DLY  
CB TRIP  
V
CB  
V
GATE  
V
OUT  
EE  
R
DS,ON  
NOTE: V , V , V  
, V  
, AND V  
ARE REFERENCED TO V .  
EE  
SC CB STEPTH STEP_MON  
OUT  
Figure 16. MAX5938 Step Immunity Functional Diagram  
Figure 16 is a functional diagram exhibiting the elements  
of the MAX5938 involved in the step immunity function.  
This functional diagram shows the parallel relationship  
with an adequate margin, ∆V  
, to accommodate  
STEP_MON  
the tolerance of both I  
( 8%) and R  
.
STEP_OS  
STEP_MON  
R
is typically set to 100kΩ, which gives a  
STEP_MON  
between V  
and V  
. Each has an I*R compo-  
∆V for a worst-case high of 0.36V.  
OUT  
STEP-MON  
STEP_MON  
nent establishing the DC level prior to a step. While it is  
The margin of V  
, with respect to V and V , was  
SC CB  
OUT  
referred to as a V step, it is the dynamic response to a  
IN  
set when R  
was selected as described in the  
CB_ADJ  
finite voltage ramp that is of interest.  
Setting the Circuit-Breaker and Short-Circuit Thresholds  
section. This margin may be lower at one of the temper-  
ature extremes and if so, that value should be used in  
the following discussion. These margins will be called  
Given a positive V ramp with a ramp rate of dV/dt, the  
IN  
approximate response of V  
to V is:  
OUT  
IN  
V
OUT  
(t) = (dV/dt) x τ x (1-e(-t / τL,eqv) ) + R  
C DS(ON)  
∆V  
and ∆V and they represent the minimum V  
SC OUT  
CB  
I
LOAD  
excursion required to trip the respective fault.  
where τ = C  
x R and τL,eqv is the equiva-  
DS(ON)  
C
LOAD  
To set τ to block all V and V faults for any  
STEP  
CB  
SC  
lent time constant of the load that must be found empir-  
ramp rate, find the ratio of ∆V  
to ∆V  
and  
CB  
STEP_MON  
/ ∆V  
STEP_MON CB  
ically (see Appendix B).  
choose τ  
so:  
STEP  
Similarly, the response of STEP_MON to a V ramp is:  
IN  
τ
= 1.2 x τ x ∆V  
STEP  
C
V
(t) = (dV/dt) x τ  
x (1-e(-t / τSTEP) ) + 10µA  
STEP_MON  
STEP  
And since R  
STEP_MON  
= 100kΩ. This results in  
STEP_MON  
x R  
STEP  
C
= τ  
/ 100kΩ.  
STEP  
where τ  
= R  
x C  
.
STEP_MON  
STEP  
STEP_MON  
After the first-pass component selection, if sufficient  
For proper step detection, V  
must exceed  
STEP_MON  
timing margin exists (see Appendix B), it is possible but  
STEP  
prior to V  
reaching V  
or within 1.4ms of  
TH  
OUT  
CB  
SC  
not necessary to lower R  
below 100kΩ to  
IN  
STEP_MON  
V
OUT  
reaching V (over all V ramp rates anticipated in  
the application). V  
IN  
reduce the sensitivity of STEP_MON to V noise.  
must be set below STEP  
STEP_MON  
TH  
______________________________________________________________________________________ 17  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
GND  
MAX5938  
200mV  
LOAD  
OK  
TIMING  
LOGIC  
V
IN  
Q1  
LP  
I
LOAD  
I
TEST  
V
GATE  
V
OUT  
EE  
R
LP  
C
LOAD  
LOAD  
R
ON  
Figure 17. Load Probe Functional Diagram  
Appendix B gives a more complete analysis and dis-  
cussion of the step monitor function. It provides meth-  
ods for the characterization of the load response to a  
limiting resistor, R . During the test, this switch is  
LP  
pulsed on for up to 220ms (typ). Current is pulled  
through the load, which should charge up the load  
capacitance unless there is a short. If the voltage  
across the load exceeds 200mV, the test is truncated  
and normal power-up is allowed to proceed. If the volt-  
age across the load does not reach 200mV in the  
220ms period that the current is on, the load is  
assumed to be shorted and the current to the load from  
V
ramp and graphical verification of the step monitor  
IN  
timing margins for a set of design parameters.  
Selecting the PGOOD Pullup Resistor  
Due to the open-drain driver, PGOOD requires an exter-  
nal pullup resistor to GND. This resistor should be  
selected to minimize the current load while PGOOD is  
LP is shut off. The MAX5938A will timeout for 16 x t  
LP  
low. The PGOOD output specification for V is 0.4V at  
OL  
then retry the load-probe test. The MAX5938L will latch  
the fault condition indefinitely until ON and OFF are  
cycled low for 1.5ms or the power is recycled.  
1mA. As described in the Detailed Description, the  
external pullup interferes with the ability of PGOOD to  
follow positive V steps as well as if it were driven by an  
IN  
In the application, the current-limiting resistor should be  
selected to minimize the current pulled through the  
load while guaranteeing that it will charge the maximum  
expected load capacitance to 220mV in 90ms. These  
parameters are the maximum load-probe test voltage  
and the minimum load-probe current pulse period,  
respectively. The maximum current possible is 1A,  
which is adequate to test a load capacitance as large  
as 190,000µF over the typical telecom operating  
voltage range.  
active pullup. When PGOOD is asserted high, an appar-  
ent negative glitch appears at PGOOD during a positive  
IN  
necessary to increase the pullup current and/or to add a  
small amount of capacitance from PGOOD to GND to  
compensate for the pin capacitance.  
V
step. To minimize this negative transient it may be  
Setting the Test Current Level for  
Load-Probe Test  
The load-probe test is a current test of the load that  
avoids turning on the power MOSFET. The MAX5938  
has an internal switch (Q1 in Figure 17) that pulls cur-  
rent through the load and through an external current-  
I
(A) = C  
(F) x 220mV / 90ms  
LOAD,MAX  
TEST  
18 ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Since the minimum intended V for the application will  
IN  
result in the lowest I  
during the load-probe test, this  
SLEW RATE vs. C  
TEST  
SLEW  
10  
1
V
should be used to set the R . This voltage will  
IN,MIN  
likely be near V  
LP  
or V  
for the application.  
ON,FALLING  
OFF  
R
(Ω) = V  
/ I  
= V  
x 90ms /  
TEST  
IN,MIN TEST  
IN,MIN  
(C  
x 220mV)  
LOAD(MAX)  
Example: V operating range = 36V to 72V, C  
=
IN  
LOAD  
10,000µF. First, find the R that will guarantee a suc-  
LP  
cessful test of the load.  
0.1  
0.01  
R
= 36V x 90ms / (10,000µF x 220mV) = 1.472Ω ⇒  
1.47kΩ 1%  
LP  
Next, evaluate the R at the maximum operating volt-  
LP  
age to verify that it will not exceed the 1A current limit  
for the load-probe test.  
0.1  
1
10  
100  
1000  
C
(nF)  
SLEW  
I
= V / R = 72V / 1.47kΩ = 49.0mA  
IN,MAX LP  
TEST,MAX  
If the C  
is increased to 190,000µF, the test  
LOAD(MAX)  
Figure 18. MAX5938 Slew Rate vs. C  
SLEW  
current will approach the limit. In this case, R will be  
LP  
a much lower value and must include the internal  
switch resistance. To find the external series resistor  
value that will guarantee a successful test at the lowest  
supply voltage, the maximum value for the load-probe  
switch on-resistance of 11Ω should be used:  
GND  
GND  
C
LOAD  
LOAD  
R
= 36V x 90ms / (190,000µF x 220mV) =  
90Ω = 11Ω + R  
LP,TOT  
MAX5938  
LP  
R
= 77.51Ω - 11Ω = 66.51Ω ⇒ 66.5Ω 1%  
LP  
V
OUT  
Again R must be evaluated at the maximum operat-  
LP  
ing voltage to verify that it will not exceed the 1A cur-  
rent limit for the load-probe test. In this case, the  
minimum value for the load-probe switch on-resistance  
of 6Ω should be used:  
V
GATE  
EE  
C
SLEW  
I
= V  
/ R  
= 72V / (66.5Ω + 6Ω) =  
LP,TOT  
TEST,MAX  
IN,MAX  
993mA  
R
GATE  
Adjusting the V  
Slew Rate  
OUT  
The default slew rate is set internally for 9V/ms. The slew  
rate can be reduced by placing an external capacitor  
from the drain of the power MOSFET to the GATE output  
of the MAX5938. Figure 18 shows a graph of Slew Rate  
-48V  
Figure 19. Adjusting the MAX5938 Slew Rate  
vs. C  
. This graph shows that for C  
< 4700pF  
SLEW  
SLEW  
there is very little effect to the addition of external slew-  
rate control capacitance. This is intended so the GATE  
output can drive large MOSFETs with significant gate  
capacitance and still achieve the default slew rate. To  
select a slew-rate control capacitor, go into the graph  
with the desired slew rate and find the value of the Miller  
From the data sheet of the power MOSFET find the  
reverse transfer capacitance (gate-to-drain capacitance)  
above 10V. If the reverse transfer capacitance of the  
external power MOSFET is 5% or more of C  
, then it  
SLEW  
should be subtracted from C  
in the equation above.  
SLEW  
Capacitance. When C  
> 4700pF, SR and C  
SLEW  
SLEW  
are inversely related. Given the desired slew rate, the  
Figure 19 gives an example of the external circuit for con-  
trolling slew rate. Depending on the parasitics associated  
required C  
is found as follows:  
SLEW  
with the selected power MOSFET, the addition of C  
SLEW  
C
SLEW  
(nF) = 23 / SR (V/ms)  
may lead to oscillation while the MOSFET and GATE con-  
______________________________________________________________________________________ 19  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
trol are in the linear range. If this is an issue, an external  
resistor, R , in series with gate of the MOSFET is rec-  
ommended to prevent possible oscillation. It should be as  
small as possible, e.g., 5Ω to 10Ω, to avoid impacting the  
MOSFET turn-off performance of the MAX5938.  
GATE  
BACKPLANE  
48V  
PLUG-IN CARD  
1kΩ  
Layout Guidelines  
To benefit from the temperature compensation designed  
into the MAX5938, the part should be placed as close as  
possible to the power MOSFET that it is controlling. The  
0.1µF  
100kΩ  
GND  
0.1µF  
OFF  
ON  
1µF  
V
pin of the MAX5938 should be placed close to the  
EE  
PGOOD  
source pin of the power MOSFET and they should share  
a wide trace. A common top layer plane would service  
both the thermal and electrical requirements. The load-  
probe current must be taken into account. If this current  
is high, the layout traces and current-limiting resistor  
must be sized appropriately. Stray inductance must be  
minimized in the traces of the overall layout of the hot-  
swap controller, the power MOSFET and the load capac-  
itor. Starting from the board contacts, all high-current  
traces should be short, wide, and direct. The potentially  
high pulse current pins of the MAX5938 are GATE (when  
OV  
STEP_MON  
V
EE  
Figure 20. Protecting the MAX5938 Input from High-Voltage  
Transients  
Appendix A  
pulling GATE low), load probe, and V . Because of the  
EE  
nature of the hot-swap requirement no decoupling  
capacitor is recommended for the MAX5938. Because  
there is no decoupling capacitor, stray inductance may  
result in excessive ringing at the GND pin during power-  
GATE Cycles  
The power-up GATE cycle, step GATE cycle, and the OV  
GATE cycle are quite similar but have distinct differ-  
ences. Understanding these differences may clarify  
application issues.  
up or during very rapid V steps. This should be exam-  
IN  
ined in every application design since ringing at the  
GND pin may exceed the absolute maximum supply rat-  
ing for the part.  
GATE Cycle During Power-Up  
The power-up GATE cycle occurs during the initial  
power-up of the MAX5938 and the associated power  
MOSFET and load. The power-up GATE cycle can  
result in full enhancement or in a fault (all voltages are  
Input Transient Protection  
During hot plug-in/unplug and fast V steps, stray  
IN  
inductance in the power path may cause voltage ring-  
ing above the normal input DC value, which may  
exceed the absolute maximum supply rating. An input  
transient such as that caused by lightning can also put  
a severe transient peak voltage on the input rail. The  
following techniques are recommended to reduce the  
effect of transients:  
relative to V ).  
EE  
Power-Up-to-Full-Enhancement Fault:  
1) At the beginning of the power-up sequence to the  
start of the power-up GATE cycle, the GATE is held  
at V . Following a successful completion of the  
load-probe test, GATE is held at V for an additional  
EE  
EE  
350µs and then is allowed to float for 650µs. At this  
point, the GATE begins to ramp with 52µA charging  
the gate of the power MOSFET. [GATE turn-on]  
1) Minimize stray inductance in the power path using  
wide traces and minimize loop area including the  
power traces and the return ground path.  
2) When GATE reaches the gate threshold voltage of  
2) Add a high-frequency (ceramic) bypass capacitor  
on the backplane as close as possible to the plug-  
in connector (Figure 20).  
the power MOSFET, V  
begins to ramp down  
OUT  
toward V . [V  
ramp]  
EE  
OUT  
3) When V  
ramps below 74% V , the GATE is  
CB  
OUT  
3) Add a 1kΩ resistor in series with the MAX5938’s  
rapidly pulled to full enhancement and the power-  
up GATE cycle is complete. 1.26ms after GATE is  
pulled to full enhancement, PGOOD asserts. [Full  
enhancement]  
GND pin and a 0.1µF capacitor from GND to V to  
EE  
limit transient current going into this pin.  
±0 ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Power-Up-to-Fault-Management Fault:  
Step-to-Fault-Management Fault:  
1) Same as step 1 above. [GATE turn-on]  
1) Same as step 1 above. [Step detection]  
2) Same as step 2 above. [GATE pulldown]  
2) Same as step 2 above. [V  
ramp]  
OUT  
3) GATE ramps to 90% of full enhancement while  
remains above 74% V , at which point the  
3) Same as step 3 above. [GATE turn-on]  
4) Same as step 4 above. [V ramp]  
V
OUT  
CB  
OUT  
GATE is rapidly pulled to V  
and fault manage-  
EE  
5) If STEP_MON is below STEP  
when GATE ramps  
TH  
ment is initiated. [Fault management]  
to 90% of full enhancement and V  
remains  
OUT  
GATE Cycle During V Step  
IN  
A step GATE cycle occurs only after a successful  
power-up GATE cycle to full enhancement occurs and  
above 74% V  
GATE is rapidly pulled to V  
.
EE  
CB,  
Fault management is initiated and PGOOD is de-  
asserted. If STEP_MON is above STEP when  
TH  
as a result of a positive V step (all voltages are  
IN  
GATE ramps to 90% of full enhancement and V  
OUT  
relative to V ).  
EE  
remains above 74% of V , GATE remains at 90%.  
CB  
It is not pulled to full enhancement nor is it pulled to  
Step-to-Full-Enhancement Fault:  
V
V
. In this condition, if V  
CB  
drops below 74% of  
EE  
OUT  
1) A V step occurs resulting in STEP_MON rising  
IN  
before STEP_MON drops below STEP  
,
TH  
above STEP before V  
detection]  
rises above V . [Step  
SC  
TH  
OUT  
GATE is rapidly pulled to full enhancement and a  
fault is avoided. Conversely, if STEP_MON drops  
below STEP  
2) After a step is detected, V  
rises above V  
OUT  
in  
SC  
OUT  
SC  
first, the GATE is rapidly pulled to  
TH  
, fault management is initiated, and PGOOD is  
EE  
response to the step. When V  
rises above V  
,
V
GATE is immediately pulled to V , rapidly turning  
off the power MOSFET. GATE is held at V  
EE  
deasserted. [Fault management]  
for  
EE  
It should be emphasized that while STEP_MON remains  
350µs to damp any ringing. Once GATE is pulled to  
, the gate cycle has begun and STEP_MON can  
above STEP  
the current fault management is  
TH  
V
EE  
blocked. During this time it is possible for there to be  
multiple events involving V rising above V then  
safely drop below STEP  
and successfully com-  
TH  
OUT  
SC  
plete a step GATE cycle to full enhancement without  
initiating fault management. [GATE pulldown]  
falling below 74% V . In each of these events, when  
CB  
V
rises above V , a full GATE cycle is initiated  
OUT  
SC  
3) Following the 350µs of GATE pulldown, GATE is  
allowed to float for 650µs. At this point, the GATE  
begins to ramp with 52µA charging the gate of the  
power MOSFET. [GATE turn-on]  
where GATE is first pulled low then allowed to ramp up.  
Then finally, when V  
fully enhanced.  
conditions are met, it will be  
OUT  
GATE Cycle During Momentary Overvoltage  
4) When GATE reaches the gate threshold voltage of  
An OV GATE cycle occurs only after a successful  
power-up GATE cycle to full enhancement and as a  
result of a momentary excursion of OV above the OV  
threshold voltage. An OV GATE cycle does not result in  
an OV fault unless OV remains above the threshold for  
the power MOSFET, V  
begins to ramp down  
OUT  
toward the new lower V . In the interval where  
EE  
GATE is below the MOSFET threshold, the MOSFET  
is off and V  
will droop depending on the RC  
OUT  
time constant of the load. [V  
ramp]  
OUT  
more than 1.5ms (all voltages are relative to V ).  
EE  
5) When V  
ramps below 74% V , the GATE pulls  
CB  
OUT  
OV GATE Cꢀcle to Full enhancement:  
rapidly to full enhancement and the step GATE  
cycle is complete. If STEP_MON remains above  
1) When OV rises above the OV threshold voltage,  
STEP  
when GATE has ramped to 90% of full  
TH  
GATE is immediately pulled to V , rapidly turning  
EE  
enhancement and V  
remains above 74% of V  
,
OUT  
CB  
off the power MOSFET. GATE is held at V indefi-  
EE  
GATE remains at 90% and is not pulled to full  
enhancement. In this condition, if V drops below  
nitely while OV is above the OV threshold voltage. It  
is held for an additional 350µs to damp any ringing.  
[GATE pulldown]  
OUT  
74% of V  
before STEP_MON drops below  
STEP , GATE is rapidly pulled to full enhancement  
CB  
TH  
2) Following the GATE pulldown, GATE is allowed to  
float for 650µs. At this point, the GATE begins to  
ramp with 52µA charging the gate of the power  
MOSFET. [GATE turn-on]  
and the step GATE cycle is complete. PGOOD  
remains asserted throughout the step GATE cycle.  
[Full enhancement]  
______________________________________________________________________________________ ±1  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
3) When GATE reaches the gate threshold voltage of  
V
to V  
limiting the ability of V  
to follow the V  
IN  
OUT  
OUT IN  
the power MOSFET, V  
begins to ramp back  
ramp. STEP_MON lags the V ramp with a first-order  
OUT  
IN  
down toward V . In the interval where GATE is  
EE  
below the MOSFET threshold, the MOSFET is off  
RC response, while V  
second-order response.  
lags with an overdamped  
OUT  
and V  
will droop depending on the RC time con-  
OUT  
Given a positive V ramp with a ramp rate of dV/dt, the  
approximate response of V  
IN  
stant of the load. [V  
ramp]  
OUT  
to V is:  
IN  
OUT  
(t) = (dV/dt) x τ x (1-e(-t / τL,eqv)  
)
4) When V  
ramps below 74% V , the GATE is  
CB  
OUT  
V
OUT C  
rapidly pulled to full enhancement and the OV GATE  
cycle is complete. [Full enhancement]  
+ R  
x I  
(Equation 1)  
DS(ON) LOAD  
where τ = C  
x R  
.
C
LOAD  
DS(ON)  
OV GATE Cꢀcle to Fault management:  
1) Same as step 1 above. [GATE pulldown]  
2) Same as step 2 above. [GATE turn-on]  
Equation 1 is a simplification for the overdampened  
second-order response of the load to a ramp input, τ  
C
= C  
x R  
and corresponds to the ability of  
LOAD  
DS(ON)  
the load capacitor to transfer dV/dt current to the fully  
enhanced power MOSFET’s R . The equivalent  
DS(ON)  
3) Same as step 3 above. [V  
ramp]  
OUT  
time constant of the load (τ  
) accounts for the para-  
L,eqv  
4) If GATE ramps to 90% of full enhancement and  
sitic series inductance and resistance of the capacitor  
and board interconnect. To characterize the load  
dynamic response to V ramps, determine τ  
V
remains above 74% V , GATE is rapidly  
CB  
OUT  
pulled to V , fault management is initiated, and  
EE  
IN  
L,eqv  
PGOOD is deasserted. [Fault management]  
empirically with a few tests.  
Similarly, the response of STEP_MON to a V ramp is:  
IN  
GATE Output  
GATE is a complex output structure and its condition at  
any moment is dependent on various timing  
sequences in response to multiple inputs. A diode to  
V
(t) = (dV/dt) x τ  
x (1-e(-t / τSTEP)  
STEP_MON  
)
STEP_MON  
STEP  
+ 10µA x R  
(Equation 2)  
where τ  
= R  
x C  
STEP  
STEP_MON  
STEP_MON.  
V
prevents negative excursions. For positive excur-  
EE  
For proper step detection, V  
STEP prior to V  
must exceed  
STEP_MON  
reaching V or within 1.4ms of  
SC  
sions, the states are:  
TH  
OUT  
1) Power-off with 2V clamp.  
V
reaching V  
(or overall V ramp rates anticipat-  
OUT  
CB IN  
2) 8Ω pulldown to V  
EE.  
ed in the application). It is impossible to give a fixed set  
of design guidelines that rigidly apply over the wide  
array of applications using the MAX5938. There are,  
however, limiting conditions and recommendations that  
should be observed.  
a. Continuous during startup delay and during  
fault conditions.  
b. Pulsed following detected step or OV  
condition.  
One limiting condition that must be observed is to  
3) Floating with 16V clamp [prior to GATE ramp].  
4) 52µA current source with 16V clamp [GATE ramp].  
ensure that the STEP_MON time constant, τ  
, is not  
STEP  
so low that at the lowest ramp rate, the anticipated  
STEP cannot be obtained. The product (dV/dt) x  
TH  
5) Pullup to internal 10V supply with 16V clamp [full  
enhancement].  
τ
= τ  
, is the maximum differential  
STEP_MON,MAX  
STEP  
voltage at STEP_MON if the V ramp were to continue  
IN  
Appendix B  
Step Monitor Component  
Selection Analysis  
indefinitely. A related condition is setting the  
STEP_MON voltage below STEP with adequate mar-  
TH  
gin, ∆V  
, to accommodate the tolerance of  
STEP_MON  
STEP_OS  
both I  
( 8%) and R  
. In determining  
STEP_MON  
As mentioned previously in the Setting the Circuit-  
Breaker and Short-Circuit Thresholds section, the AC  
τ
, use the 9.2µA limit to ensure sufficient mar-  
STEP_MON  
gin with worst-case I  
.
STEP_OS  
response from V to V  
is dependent on the para-  
OUT  
IN  
The margin of V  
(with respect to V  
and V ) is  
SC CB  
OUT  
sitics of the load. This is especially true for the load  
capacitor in conjunction with the power MOSFET’s  
set when R  
is selected as described in the  
CB_ADJ  
Setting the Circuit-Breaker and Short-Circuit Thresholds  
section. This margin may be lower at one of the temper-  
ature extremes and if so, that value should be used in  
the following discussion. These margins will be called  
R
. The load capacitor (with parasitic ESR and  
DS(ON)  
LSR) and the power MOSFET’s R  
can be mod-  
DS(ON)  
eled as a heavily damped second-order system. As  
such, this system functions as a bandpass filter from  
±± ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
∆V  
and ∆V and they represent the minimum V  
SC OUT  
CB  
excursion required to trip the respective fault.  
will typically be set to 100kΩ 1%. This  
V
IN  
V
= GND = V  
EE  
IN  
R
STEP_MON  
gives a ∆V  
of 0.25V, a worst-case low of  
STEP_MON  
0.13V, and a worst-case high of 0.37V. In finding τ  
STEP  
L
EQU  
in the equation below, use ∆V  
= 0.37V to  
STEP_OS  
STEP_MON  
ensure sufficient margin with worst-case I  
.
LOAD CAPACITOR  
WITH PARASITICS  
V
RAMP  
LOAD  
IN  
To set τ  
to block all V  
and V  
faults for any  
SC  
STEP  
CB  
R
EQV  
ramp rate, find the ratio of ∆V  
to ∆V  
and  
CB  
STEP_MON  
/ ∆V  
STEP_MON CB  
choose τ  
so:  
STEP  
C
LOAD  
10V  
τ
= 1.2 x τ x ∆V  
STEP  
C
and since R  
= 100kΩ:  
STEP_MON  
C
= τ  
/ R  
= τ  
/ 100kΩ  
STEP  
STEP_MON  
STEP  
STEP_MON  
R
DS,ON  
After the first-pass component selection, if sufficient  
timing margin exists, it is possible (but not necessary)  
Figure 21. V Ramp Test Of Load  
IN  
to lower R  
below 100kΩ to reduce the sensitivity of  
STEP  
STEP_MON to V noise.  
IN  
V
IN  
Verification of the Step  
Monitor Timing  
dv  
dt  
τ
C
dv  
dt  
It is prudent to verify conclusively that all circuit-breaker  
and short-circuit faults will be blocked for all ramp  
rates. To do this, some form of graphical analysis is  
recommended but first, find the value of τ  
of the  
L,eqv  
load by a series of ramp tests as indicated earlier.  
These tests include evaluating the load with a series of  
V
.F  
OUT  
V
i
OUT  
t1 t2  
RAMP  
t3 t4  
V
ramps of increasing ramp rates and monitoring the  
IN  
0
rate of rise of V  
during the ramp. Each V ramp  
IN  
OUT  
V
IN  
should have a constant slope. The V  
response data  
OUT  
must be taken only during the positive ramp. Data  
Figure 22. General Response of V  
to a V Ramp  
IN  
OUT  
taken after V has leveled off at the new higher value  
IN  
must not be used.  
Figure 21 shows the load in parallel with the load  
V
RESPONSE TO V RAMP OF 300V/ms  
IN  
OUT  
capacitor, C  
, and the parallel connection in series  
2.7  
2.4  
2.1  
1.8  
1.5  
1.2  
0.9  
0.6  
0.3  
0
LOAD  
with the power MOSFET, which is fully enhanced with  
= 10V. The objective is to determine τ from  
d
dt  
VIN  
A
B
V
GS  
the V  
L,eqv  
response.  
OUT  
Figure 22 shows the general response of V  
to a V  
OUT  
IN  
ramp over time t. Equation 1 gives the response of V  
OUT  
C
to a ramp of dV/dt. The product (dV/dt) x τ  
=
∆V  
(max) or the maximum V  
voltage differential if  
OUT  
OUT  
C
D
t
t
STEP  
CB  
the V ramp were to continue indefinitely. The parame-  
IN  
t
SC  
F
E
ter of interest is ∆V  
necessary to subtract the DC shift in V  
due to the ramp dV/dt, thus it is  
OUT  
due to the  
OUT  
load resistance. For some loads, which are relatively  
independent of supply voltage, this may be insignificant.  
0
1
2
3
)
4
5
6
7
8
TIME (µs)  
V
OUT  
(t) = V  
(t) – R x I  
DS(ON) LOAD  
OUT  
A = V (GND - V  
IN  
B = ∆V  
C = ∆V  
D = ∆V  
E = ∆V  
F = ∆V  
EE  
STEP,TH  
CB  
SC  
STEP_MON  
where I  
is a function of the V  
level that should  
LOAD  
OUT  
OUT  
be determined separately with DC tests.  
Figure 23. V  
Response to V Ramp of 300V/ms  
IN  
OUT  
______________________________________________________________________________________ ±3  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
At any time (t) the ∆V  
fraction of ∆V  
(max) is:  
Having τ , τ  
, R  
, and C  
in a graphical  
STEP  
OUT  
OUT  
C
L,eqv  
STEP  
analysis using Equation 1 and Equation 2 can verify the  
step monitor function by displaying the relative timing  
∆V  
(t) / [(dV/dt) x τ ] = (1-e(-t / τL,eqv)  
)
OUT  
C
If V  
(t) is measured at time t, then the equivalent  
OUT  
of t , t  
STEP_MON  
, and t , which are the times when V  
,
CB STEP  
SC  
SC  
CB  
time constant of the load is found from:  
V
, and V voltage thresholds are exceeded.  
τ
= -t / ln(1 – ∆V / [(dV/dt) x τ ])  
A simple Excel spreadsheet for this purpose can be  
supplied by Maxim upon request. Figures 23, 24, and  
25 graphically verify a particular solution over 3  
L,eqv  
OUT  
C
As mentioned earlier, several measurements of ∆V  
at times t1, t2, t3, and t4 should be made during the  
ramp. Each of these may result in slightly different val-  
OUT  
decades of V ramp rates. In addition, Figure 25 veri-  
IN  
fies that this solution will block all circuit-breaker and  
ues of τ  
and all values should then be averaged.  
L,eqv  
short-circuit faults for even the lowest V ramp that will  
IN  
In making the measurements, the V ramp duration  
IN  
cause V  
to exceed V  
.
CB  
OUT  
should be such that ∆V  
reaches 2 or 3 times the  
OUT  
selected ∆V . The ramp tests should include three  
SC  
ramp rates: ∆V / τ , 2 x ∆V / τ , and 4 x ∆V / τ .  
SC  
C
SC  
C
SC  
C
The values of τ  
may vary over the range of slew  
L,eqv  
rates due to measurement error, nonlinear dynamics in  
the load, and due to the fact that Equation 1 is a simpli-  
fication from a higher order dynamic system. The  
resulting range of τ  
date the performance of the final design.  
values should be used to vali-  
L,eqv  
V
RESPONSE TO V RAMP OF 30V/ms  
IN  
OUT  
V
RESPONSE TO V RAMP OF 3V/ms  
IN  
OUT  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
A
A
B
t
STEP  
D
t
STEP  
F
D
C
B
F
t
SC  
t
E
CB  
E
C
0
4
8
12 16 20 24 28 32 36 40  
0
100  
200  
300  
400  
500  
TIME (µs)  
TIME (µs)  
A = V (GND - V  
IN  
)
D = ∆V  
E = ∆V  
F = ∆V  
A = V (GND - V  
IN  
)
D = ∆V  
E = ∆V  
F = ∆V  
EE  
STEP,TH  
CB  
SC  
EE  
STEP,TH  
CB  
SC  
B = ∆V  
B = ∆V  
STEP_MON  
C = ∆V  
STEP_MON  
C = ∆V  
OUT  
OUT  
Figure 25. V  
Response to V Ramp of 3V/ms  
IN  
Figure 24. V  
Response to V Ramp of 30V/ms  
IN  
OUT  
OUT  
±. ______________________________________________________________________________________  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Typical Operating Circuit  
GND  
V+  
(V = GND - V  
IN  
)
EE  
V
IN  
DC-DC  
CONVERTER  
GND  
OFF  
ON  
C
LOAD  
MAX5938  
PGOOD  
ON  
V-  
V
OUT  
LP  
BACKPLANE  
OV  
STEP_MON  
POL_SEL  
*
GATE  
CB_ADJ  
V
EE  
**  
-48V  
*OPTIONAL COMPONENT.  
**OPTIONAL COMPONENT REPLACED BY SHORT.  
Timing Table  
Chip Information  
TRANSISTOR COUNT: 2320  
TYPICAL  
NAME  
Power-Up Delay  
SYMBOL  
TIME (s)  
PROCESS: BiCMOS  
t
220m  
220m  
3.5  
ONDLY  
Load-Probe Test Timeout  
Load-Probe Retry Time  
t
LP  
t
LP_OFF  
PGOOD Assertion  
Delay Time  
t
1.26m  
PGOOD  
Autoretry Delay  
t
3.5  
RETRY  
Circuit-Breaker Glitch Rejection  
ON Glitch Rejection  
t
1.4m  
1.5m  
1.5m  
CB_DLY  
t
REJ  
OV Transient Rejection  
t
OVREJ  
GATE Pulldown Pulse Following  
—
350µ  
1m  
a V Step  
IN  
GATE Low after a V Step,  
IN  
Prior to Ramp  
—
______________________________________________________________________________________ ±5  
-48V Hot-Swap Controller with V Step Immunity,  
IN  
No R  
, and Overvoltage Protection  
SENSE  
Package Information  
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,  
go to www2maxim-ic2comꢁpackages.)  
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH  
1
21-0055  
E
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are  
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.  
±6 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600  
© 2005 Maxim Integrated Products  
Printed USA  
is a registered trademark of Maxim Integrated Products, Inc.  

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