MAX5940 [MAXIM]
IEEE 802.3af PD Interface Controller For Power-Over-Ethernet;
| 型号： | MAX5940 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | IEEE 802.3af PD Interface Controller For Power-Over-Ethernet 光电二极管 |
| 文件： | 总15页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2991; Rev 2; 2/06
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
General Description
Features
♦ Fully Integrated IEEE 802.3af-Compliant PD
The MAX5940A/MAX5940B/MAX5940C/MAX5940D pro-
vide complete interface function for a powered device
(PD) to comply with the IEEE 802.3af standard in a
power-over-ethernet system. MAX5940A/MAX5940B/
MAX5940C/MAX5940D provide the PD with a detection
signature, a classification signature, and an integrated
isolation switch with programmable inrush current control.
These devices also feature power-mode undervoltage
lockout (UVLO) with wide hysteresis and power-
good outputs. The MAX5940A/MAX5940B are available
with an absolute maximum rating of 80V and the
MAX5940C/MAX5940D are rated for an absolute maxi-
mum rating of 90V.
Interface
♦ PD Detection and Programmable Classification
Signatures
♦ Less than 10µA Leakage Current Offset During
Detection
♦ Integrated MOSFET For Isolation and Inrush
Current Limiting
♦ 90V Absolute Maximum Rating
(MAX5940C/MAX5940D)
♦ Gate Output Allows External Control of the
An integrated MOSFET provides PD isolation during
detection and classification. All devices guarantee a leak-
age current offset of less than 10µA during the detection
phase. A programmable current limit prevents high inrush
current during power-on. The device features power-
mode UVLO with wide hysteresis and long deglitch time
to compensate for twisted-pair cable resistive drop and to
assure glitch-free transition between detection, classifica-
tion, and power-on/-off phases.
Internal Isolation MOSFET
♦ Programmable Inrush Current Control
♦ Programmable Undervoltage Lockout
(MAX5940B/MAX5940D Only)
♦ Wide UVLO Hysteresis Accommodates Twisted-
Pair Cable Voltage Drop
♦ PGOOD/PGOOD Outputs to Enable Downstream
DC-DC Converters
The MAX5940A/MAX5940C provide an active-high
(PGOOD) open-drain output and a fixed UVLO threshold.
The MAX5940B/MAX5940D provide both active-high
(PGOOD) and active-low (PGOOD) outputs and have an
adjustable UVLO threshold with the default value compli-
ant to the 802.3af standard. All devices are designed to
work with or without an external diode bridge.
♦ -40°C to +85°C Operating Temperature Range
Ordering Information
PIN-
PACKAGE
PART
TEMP RANGE
UVLO
MAX5940AESA -40°C to +85°C 8 SO
MAX5940BESA -40°C to +85°C 8 SO
MAX5940CESA -40°C to +85°C 8 SO
MAX5940DESA -40°C to +85°C 8 SO
Fixed
The MAX5940A/MAX5940B/MAX5940C/MAX5940D are
available in 8-pin SO packages and are rated over the
extended temperature range of -40°C to +85°C.
Adjustable
Fixed
Adjustable
Applications
IP Phones
Security Cameras
Wireless Access Nodes IEEE 802.3af Power Devices
Computer Telephony
Pin Configurations appear at end of data sheet.
Typical Operating Circuits
D1*
DC-DC CONVERTER
GND
V+
8
V
REG
GND
C
OUT
MAX5014
2
3
4
R
DISC
25.5kΩ
60V
68nF
RCLASS
GATE
GND
LOAD
SS_SHDN
MAX5940A
MAX5940C
6
PGOOD
OUT
R
CL
D2*
5
-48V
V
EE
C
GATE
*OPTIONAL.
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
ABSOLUTE MAXIMUM RATINGS
(All voltages are referenced to V , unless otherwise noted.)
GND, RCLASS to V .....................................................70mA
EE
EE
GND (MAX5940A/MAX5940B) ...............................-0.3V to +80V
GND (MAX5940C/MAX5940D)...............................-0.3V to +90V
OUT, PGOOD ...........................................-0.3V to (GND + 0.3V)
RCLASS, GATE ......................................................-0.3V to +12V
UVLO........................................................................-0.3V to +8V
PGOOD to OUT.........................................-0.3V to (GND + 0.3V)
Maximum Input/Output Current (continuous)
UVLO, PGOOD, PGOOD to V .....................................20mA
EE
GATE to V ....................................................................80mA
EE
Continuous Power Dissipation (T = +70°C)
A
8-Pin SO (derate 5.9mW/°C above +70°C)..................470mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) ................................+300°C
OUT to V ...................................................................500mA
EE
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , T = -40°C to +85°C, unless otherwise noted.
IN
EE
EE
A
Typical values are at T = +25°C. All voltages are referenced to V , unless otherwise noted.) (Note 1)
A
EE
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DETECTION MODE
Input Offset Current (Note 2)
I
V
V
= 1.4V to 10.1V
10
µA
OFFSET
IN
IN
Effective Differential Input
Resistance (Note 3)
= 1.4V up to 10.1V with 1V step,
dR
550
kΩ
OUT = PGOOD = GND
CLASSIFICATION MODE
Classification Current Turn-Off
Threshold (Note 4)
V
V
rising
20.8
21.8
22.5
V
TH,CLSS
IN
Class 0, R = 10kΩ
0
2
CL
Class 1, R = 732Ω
9.17
17.29
26.45
36.6
11.83
19.71
29.55
41.4
CL
V
= 12.6V to
IN
Classification Current (Notes 5, 6)
I
20V, R
25.5kΩ
=
Class 2, R = 392Ω
mA
CLASS
DISC
CL
Class 3, R = 255Ω
CL
Class 4, R = 178Ω
CL
POWER MODE
Operating Supply Voltage
Operating Supply Current
V
V
= (GND - V )
EE
67
1
V
IN
IN
I
Measure at GND, not including R
0.4
mA
IN
DISC
MAX5940A/MAX5940C
34.3
37.4
35.4
36.6
Default Power Turn-On Voltage
V
V
increasing
V
UVLO, ON
IN
MAX5940B/MAX5940D,
38.6
39.9
UVLO = V
EE
V
decreasing, UVLO = V for
IN
EE
Default Power Turn-Off Voltage
V
30
V
V
UVLO, OFF
MAX5940B/MAX5940D
MAX5940A/MAX5940C
4.2
7.4
Default Power Turn-On/Off
Hysteresis
V
HYST,
UVLO
MAX5940B/MAX5940D, UVLO = V
EE
External UVLO Programming
Range
Set UVLO externally (MAX5940B/
MAX5940D only) (Note 7)
V
12
67
V
V
IN,EX
REF, UVLO
HYST
UVLO External Reference Voltage
V
2.400
19.2
-1.5
2.460
20
2.522
20.9
+1.5
UVLO External Reference Voltage
Hysteresis
Ratio to V
%
µA
REF,UVLO
UVLO Bias Current
I
UVLO = 2.460V
UVLO
2
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
ELECTRICAL CHARACTERISTICS (continued)
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V , T = -40°C to +85°C, unless otherwise noted.
IN
EE
EE
A
Typical values are at T = +25°C. All voltages are referenced to V , unless otherwise noted.) (Note 1)
A
EE
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UVLO Input Ground Sense
Threshold (Note 8)
V
50
440
mV
TH,G,UVLO
UVLO Input Ground Sense Glitch
Rejection
UVLO = V
7
µs
EE
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time (Note 9)
t
V
, V falling
IN UVLO
0.32
ms
OFF_DLY
T
= +25°C
A
Output current =
300mA, V = 6V,
0.6
0.8
1.1
1.5
(Note 10)
Isolation Switch N-Channel
MOSFET On-Resistance
GATE
R
ON
Ω
measured between
OUT and V
T
A
= +85°C
EE
Isolation Switch N-Channel
MOSFET Off-Threshold Voltage
OUT = GND, V
< 1µA
- V
EE,
output current
GATE
V
0.5
V
GSTH
Power-off mode, V = 12V,
IN
GATE Pulldown Switch Resistance
R
G
38
80
Ω
UVLO = V for MAX5940B
EE
GATE Charging Current
GATE High Voltage
I
V
= 2V
5
10
15
µA
V
G
GATE
V
I
= 1µA
5.59
5.76
5.93
GATE
GATE
V
V
- V , |V
- V | decreasing,
OUT
EE
OUT EE
1.16
4.62
1.23
1.31
4.91
0.4
V
PGOOD, PGOOD Assertion V
Threshold
OUT
= 5.75V
V
GATE
OUTEN
Hysteresis
70
4.76
80
mV
V
(GATE - V ) increasing, OUT = V
EE
EE
PGOOD, PGOOD Assertion V
Threshold
GATE
V
GSEN
Hysteresis
mV
PGOOD, PGOOD Output Low
Voltage (Note 11)
I
= 2mA; for PGOOD, OUT ≤
SINK
V
V
OLDCDC
(GND - 5V)
PGOOD Leakage Current (Note 11)
GATE = high, GND - V
= 67V
1
1
µA
µA
OUT
PGOOD Leakage Current (Note 11)
GATE = V , PGOOD - V = 67V
EE EE
Note 1: All min/max limits are production tested at +85°C. Limits at +25°C and -40°C are guaranteed by design.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between GND and V without any external
EE
resistance. See Figure 1.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the PD Classification Mode section. R
and R must be 1%, 100ppm or better. I
includes the IC
CLASS
DISC
CL
bias current and the current drawn by R
.
DISC
Note 6: See the Thermal Dissipation section for details.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ ( 1%), the turn-
on threshold set-point for the power mode is defined by the external resistor-divider. Make sure the voltage on the UVLO
pin does not exceed its maximum rating of 8V when V is at the maximum voltage (MAX5940B only).
IN
Note 8: When the UVLO input voltage is below V
the MAX5940B sets the UVLO threshold internally.
TH,G,UVLO,
Note 9: An input voltage or V
glitch below their respective thresholds shorter than or equal to t
does not cause the
UVLO
OFF_DLY
MAX5940A/MAX5940B/MAX5940C/MAX5940D to exit power-on mode (as long as the input voltage remains above an opera-
ble voltage level of 12V).
Note 10: Guaranteed by design.
Note 11: PGOOD references to OUT while PGOOD references to V
.
EE
_______________________________________________________________________________________
3
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
I
IN
(V
(I
- V
)
1V
INi + 1
INi
dR ≅
i
=
- I
)
(I
- I
)
INi + 1 INi
INi + 1 INi
V
INi
I
≅ I
-
OFFSET INi
dR
i
I
INi + 1
dR
i
I
INi
I
OFFSET
V
1V
V
INi + 1
V
IN
INi
Figure1. Effective Differential Input Resistance/Offset Current
Typical Operating Characteristics
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V (MAX5940B), T = -40°C to +85°C. Typical values
IN
EE
EE
A
are at T = +25°C. All voltages are referenced to V , unless otherwise noted.)
A
EE
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT VOLTAGE
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
DETECTION CURRENT vs. INPUT VOLTAGE
0.5
0.4
0.3
0.2
0.1
0
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
R
= 25.5kΩ
DISC
CLASS 4
CLASS 3
40
30
20
10
0
I
+ I
IN RDISC
CLASS 2
CLASS 1
CLASS 0
0
2
4
6
8
10
0
5
10
15
20
25
30
0
2
4
6
8
10
12
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
NORMALIZED UVLO
vs. TEMPERATURE
0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
250
200
150
100
50
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
UVLO = V
EE
0
1
3
5
7
9
11
0
5
10
(mA)
15
20
-40
-15
10
35
60
85
INPUT VOLTAGE (V)
I
TEMPERATURE (°C)
SINK
4
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Typical Operating Characteristics (continued)
(V = (GND - V ) = 48V, GATE = PGOOD = PGOOD = OUT = OPEN, UVLO = V (MAX5940B), T = -40°C to +85°C. Typical values
IN
EE
EE
A
are at T = +25°C. All voltages are referenced to V , unless otherwise noted.)
A
EE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
OUT LEAKAGE CURRENT
vs. TEMPERATURE
INRUSH CURRENT CONTROL (V = 12V)
IN
MAX5940A/B toc09
400
320
240
160
80
20
V
= 67V
OUT
V
GATE
16
12
8
5V/div
I
INRUSH
100mA/div
V
V
OUT TO EE
10V/div
4
PGOOD
10V/div
0
0
1ms/div
0
5
10
(mA)
15
20
-40
-15
10
35
60
85
I
TEMPERATURE (°C)
SINK
INRUSH CURRENT CONTROL (V = 48V)
IN
INRUSH CURRENT CONTROL (V = 67V)
IN
MAX5940A/B toc10
MAX5940A/B toc11
V
V
GATE
GATE
5V/div
5V/div
I
I
INRUSH
INRUSH
100mA/div
100mA/div
V
V
OUT TO EE
V
V
OUT TO EE
50V/div
50V/div
PGOOD
50V/div
PGOOD
50V/div
2ms/div
2ms/div
_______________________________________________________________________________________
5
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Pin Description
PIN
NAME
FUNCTION
MAX5940A/ MAX5940B/
MAX5940C MAX5940D
1, 7
—
N.C.
No Connection. Not internally connected.
Undervoltage Lockout Programming Input for Power Mode. When UVLO is above its
threshold, the device enters power mode. Connect UVLO to V to use the default
EE
undervoltage lockout threshold. Connect UVLO to an external resistor-divider to define a
threshold externally. The series resistance value of the external resistors must add to 25.5kΩ
( 1%) and replaces the detection resistor. To keep the device in undervoltage lockout, pull
—
1
UVLO
UVLO to between V
and V
.
TH,G,UVLO
REF,UVLO
Classification Setting. Add a resistor from RCLASS to V to set a PD class (see Tables 1
EE
and 2).
2
3
2
3
RCLASS
GATE
Gate of Internal N-Channel Power MOSFET. GATE sources 10µA when the device enters
power mode. Connect an external 100V ceramic capacitor (C ) from GATE to OUT to
GATE
program the inrush current. Pull GATE to V to turn off the internal MOSFET. The detection
EE
and classification functions operate normally when GATE is pulled to V
.
EE
Negative Input Power. Source of the integrated isolation N-channel power MOSFET. Connect
to -48V.
4
5
4
5
V
EE
V
EE
OUT
Output Voltage. Drain of the integrated isolation N-channel power MOSFET.
Power-Good Indicator Output, Active-High, Open-Drain. PGOOD is referenced to OUT.
PGOOD goes high impedance when V
is within 1.2V of V and when GATE is 5V above
EE
OUT
6
6
PGOOD
V
. Otherwise, PGOOD is pulled to OUT (given that V
is at least 5V below GND).
OUT
EE
Connect PGOOD to the ON pin of a downstream DC-DC converter.
Power-Good Indicator Output, Active-Low, Open-Drain. PGOOD is referenced to V
.
EE
PGOOD is pulled to V when V
Otherwise, PGOOD goes high impedance. Connect PGOOD to the ON pin of a downstream
DC-DC converter.
is within 1.2V of V and when GATE is 5V above V
.
EE
OUT
EE
EE
—
8
7
8
PGOOD
GND
Ground. GND is the positive input terminal.
(1V step minimum), and then records the current mea-
Detailed Description
Operating Modes
The PD front-end section of the MAX5940_ operates in 3
different modes, PD detection signature, PD classifica-
surements at the two points. The PSE then computes
ΔV/ΔI to ensure the presence of the 25.5kΩ signature
resistor. In this mode, most of the MAX5940_ internal cir-
cuitry is off and the offset current is less than 10µA.
tion, and PD power, depending on its input voltage (V
=
IN
If the voltage applied to the PD is reversed, install pro-
tection diodes on the input terminal to prevent internal
damage to the MAX5940_ (see the Typical Application
Circuits). Since the PSE uses a slope technique (ΔV/ΔI)
to calculate the signature resistance, the DC offset due
to the protection diodes is subtracted and does not
affect the detection process.
GND - V ). All voltage thresholds are designed to oper-
EE
ate with or without the optional diode bridge while still
complying with the IEEE 802.3af standard (see Figure 4).
Detection Mode (1.4V ≤ V ≤ 10.1V)
IN
In detection mode, the power source equipment (PSE)
applies two voltages on V in the range of 1.4V to 10.1V
IN
6
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Table 1. PD Power Classification/R Selection
CL
CLASS
USAGE
Default
R
(Ω)
MAXIMUM POWER USED BY PD (W)
0.44 to 12.95
CL
0
1
2
3
4
10k
732
392
255
178
Optional
Optional
Optional
Not Allowed
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
Reserved*
*Class 4 reserved for future use.
Table 2. Setting Classification Current
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS CURRENT SEEN AT V (mA)
IN
CLASS
R
(Ω)
V * (V)
IN
CL
MIN
0
MAX
2
MIN
0
MAX
4
0
1
2
3
4
10k
732
392
255
178
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
9.17
17.29
26.45
36.6
11.83
19.71
29.55
41.4
9
12
20
30
44
17
26
36
*V is measured across the MAX5940 input pins, which does not include the diode bridge voltage drop.
IN
Classification Mode (12.6V ≤ V ≤ 20V)
(see Figure 2). The MAX5940_ charge the gate of Q1
with a constant current source (10µA, typ). The drain-
to-gate capacitance of Q1 limits the voltage rise rate at
the drain of the MOSFET, thereby limiting the inrush
current. To reduce the inrush current, add external
drain-to-gate capacitance (see the Inrush Current Limit
section). When the drain of Q1 is within 1.2V of its
source voltage and its gate-to-source voltage is above
5V, the MAX5940_ asserts the PGOOD/PGOOD out-
puts. The MAX5940_ have a wide UVLO hysteresis and
turn-off deglitch time to compensate for the high
impedance of the twisted-pair cable.
IN
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distri-
bution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor (R
)
CL
connected from RCLASS to V sets the classification
EE
current.
The PSE determines the class of a PD by applying a volt-
age at the PD input and measures the current sourced
out of the PSE. When the PSE applies a voltage between
12.6V and 20V, the MAX5940_ exhibit a current charac-
teristic with values indicated in Table 2. The PSE uses the
classification current information to classify the power
requirement of the PD. The classification current includes
the current drawn by the 25.5kΩ detection signature
resistor and the supply current of the MAX5940_ so the
total current drawn by the PD is within the IEEE 802.3af
standard figures. The classification current is turned off
whenever the device is in power mode.
Undervoltage Lockout
The MAX5940_ operate up to a 67V supply voltage with a
default UVLO turn-on (V
) set at 35V
UVLO,ON
(MAX5940A/MAX5940C) or 39V (MAX5940B/MAX5940D)
and a UVLO turn-off (V ) set at 30V. The
UVLO,OFF
MAX5940B/MAX5940D have an adjustable UVLO thresh-
old using a resistor-divider connected to UVLO (see
Figure 3). When the input voltage is above the UVLO
threshold, the IC is in power mode and the MOSFET is
on. When the input voltage goes below the UVLO thresh-
Power Mode
During power mode, when V rises above the under-
IN
old for more than t , the MOSFET turns off.
OFF_DLY
voltage lockout threshold (V
), the MAX5940_
gradually turn on the internal N-channel MOSFET Q1
UVLO,ON
_______________________________________________________________________________________
7
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
GND
2.46V
UVLO
REF
6.8V
EN
GND
RCLASS
(PGOOD)
CLASSIFICATION
R1
R2
MAX5940B
MAX5940D
Q4
20%
R3
V
GATE
1.2V, REF
EN
(UVLO)
PGOOD
OUT
5V, REF
Q3
Q2
200mV
GATE
Q1
V
EE
( ) MAX5940B.
Figure 2. Block Diagram
To adjust the UVLO threshold (MAX5940B/MAX5940D
only), connect an external resistor-divider from GND to
V
IN
= 12V TO 67V
UVLO and from UVLO to V . Use the following equations
EE
to calculate R1 and R2 for a desired UVLO threshold:
V
REF,UVLO
GND
R2 = 25.5kΩ x
V
IN,EX
R1
R2
R1 = 25.5kΩ - R2
is the desired UVLO threshold. Since the
MAX5940B
MAX5940D
where V
IN,EX
UVLO
resistor-divider replaces the 25.5kΩ PD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5kΩ
1%. When using the external resistor-divider, the
MAX5940B/MAX5940D has an external reference volt-
age hysteresis of 20% (typ). When UVLO is pro-
grammed externally, the turn-off threshold is 80% (typ)
of the new UVLO threshold.
V
EE
Figure 3. Setting Undervoltage Lockout with an External
Resistor-Divider
8
_______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
(MAX5940B/MAX5940D only)
Inrush Current Limit
The MAX5940_ charge the gate of the internal MOSFET
with a constant current source (10µA, typ). The drain-
to-gate capacitance of the MOSFET limits the voltage
rise rate at the drain, thereby limiting the inrush current.
Add an external capacitor from GATE to OUT to further
reduce the inrush current. Use the following equation to
calculate the inrush current:
PGOOD is an open-drain, active-low logic output.
PGOOD is pulled to V when V
is within 1.2V of V
EE
EE
OUT
and when GATE is 5V above V . Otherwise, PGOOD
EE
goes high impedance. Connect PGOOD to the ON pin of
a downstream DC-DC converter. Connect a 100kΩ
pullup resistor from PGOOD to GND if needed.
Thermal Dissipation
During classification mode, if the PSE applies the maxi-
mum DC voltage, the maximum voltage drop from GND
COUT
IINRUSH = IG
x
CGATE
to V
will be 13V. If the maximum classification cur-
RCLASS
rent of 42mA flows through the MAX5940_, then the maxi-
mum DC power dissipation will be 546mW, which is
slightly higher than the maximum DC power dissipation of
the IC at maximum operating temperature. However,
according to the IEEE 802.3af standard, the duration of
the classification mode is limited to 75ms (max). The
MAX5940_ handle the maximum classification power dis-
sipation for the maximum duration time without sustaining
any internal damage. If the PSE violates the IEEE 802.3af
standard by exceeding the 75ms maximum classification
duration, it may cause internal damage to the IC.
PGOOD/PGOOD Outputs
(MAX5940A/MAX5940C only)
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when V
is within 1.2V
OUT
of V
and when GATE is 5V above V . Otherwise,
EE
EE
PGOOD is pulled to V
(given that V
is at least 5V
OUT
OUT
below GND). Connect PGOOD to the ON pin of a down-
stream DC-DC converter. Connect a 100kΩ pullup resis-
tor from PGOOD to GND if needed.
_______________________________________________________________________________________
9
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Typical Application Circuits
Application Circuit 1
POWER-OVER
SIGNAL PAIRS
V
REG
RX
3
6
1
PHY
2
GND
+
-
+
-
RJ-45
4
5
7
8
TX
-48V
POWER-OVER
SPAIR PAIRS
DC-DC CONVERTER
GND
V+
R
DISC
R1*
25.5kΩ
MAX5014
V
REG
1
2
3
4
8
C
OUT
UVLO
GND
MAX5940B
MAX5940D
60V
68nF
7
RCLASS
GATE
PGOOD
GND
SS_SHDN
LOAD
6
5
PGOOD
OUT
R
CL
R2*
V
EE
-48V
C
GATE
*R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
Figure 4. PD with Power-Over-Ethernet (Power is Provided by Either the Signal Pairs or the Spare Pairs)
10 ______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Typical Application Circuits (continued)
GATE is pulled low to pinch off the power-over-ethernet.
The wall adapter power pollutes the discovery signa-
ture, preventing PSE from detecting this PD.
Application Circuit 2
Diode D1 prevents the power-over-ethernet to back
drive the wall adapter. Whenever the wall adapter
power is greater than (V
+ approximately 2V), the
D3
DC-DC CONVERTER
V+
GND
8
R
1
DISC
UVLO
GND
VREG
25.5kΩ
C
OUT
MAX5014
MAX5940B
MAX5940D
RCLASS
60V
68nF
PGOOD
7
2
PGOOD
GND
SS_SHDN
LOAD
6
5
GATE
3
4
PGOOD
OUT
R
CL
V
EE
-48V
V
EE
C
GATE
WALL
ADAPTER
SUPPLY
GATE
D1
D3
100kΩ
PGOOD
PS2701A-1
GATE
V
EE
CMPT3904
2.0kΩ
CMPT3904
Figure 5. Adding Wall Adapter Input Supply (Wall Adapter Supply Takes Precedence Over Power-Over-Ethernet)
______________________________________________________________________________________ 11
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Typical Application Circuits (continued)
R4 provides the 10mA minimum power maintenance
signature to keep the power-over-ethernet from discon-
necting.
Application Circuit 3
D2 prevents the wall adapter power from polluting the
discovery and classification signatures. The optional
DC-DC CONVERTER
D2
V+
GND
8
R
1
2
DISC
VREG
UVLO
GND
25.5kΩ
MAX5014
R4
4kΩ
2W
C
OUT
MAX5940B
MAX5940D
60V
68nF
7
RCLASS
PGOOD
GND
SS_SHDN
LOAD
6
5
GATE
3
4
PGOOD
OUT
R
CL
V
EE
-48V
C
GATE
D1
WALL
ADAPTER
SUPPLY
Figure 6. Adding Wall Adapter Input Supply (Wall Adapter Supply And Power-Over-Ethernet Co-Exist, the One with Higher Voltage
Provides Power To The Load)
12 ______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Typical Application Circuits (continued)
fication signatures. If the power-over-ethernet comes
up first, it powers the load until taken over by a wall
adapter with higher output voltage.
Application Circuit 4
If the wall adapter supply comes up first, it provides
power to the load and pollute the discovery and classi-
DC-DC CONVERTER
V+
GND
8
R
1
2
DISC
VREG
UVLO
GND
25.5kΩ
C
OUT
MAX5014
MAX5940B
MAX5940D
60V
68nF
7
RCLASS
PGOOD
GND
SS_SHDN
LOAD
6
5
3
4
GATE
PGOOD
OUT
R
CL
V
EE
-48V
C
GATE
D1
WALL
ADAPTER
SUPPLY
Figure 7. Adding Wall Adapter Input Supply (the One with Higher Voltage Provides Power to the Load)
______________________________________________________________________________________ 13
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Typical Operating Circuits (continued)
D1*
DC-DC CONVERTER
V+
GND
R
DISC
R1**
25.5kΩ
V
REG
C
MAX5014
OUT
1
2
8
UVLO
GND
60V
68nF
7
GND
RCLASS
PGOOD
SS_SHDN
LOAD
3
4
MAX5940B
MAX5940D
6
5
GATE
PGOOD
OUT
R
R2**
CL
D2*
-48V
V
EE
C
GATE
*OPTIONAL.
**R1 AND R2 ARE OPTIONAL AND WHEN USED, THEY MUST TOTAL 25.5kΩ AND REPLACE THE 25.5kΩ RESISTOR.
Pin Configurations
Chip Information
TRANSISTOR COUNT: 3,643
TOP VIEW
PROCESS: BiCMOS
N.C.
1
2
3
4
8
7
6
5
GND
RCLASS
GATE
N.C.
MAX5940A
MAX5940C
PGOOD
OUT
V
EE
SO
UVLO
RCLASS
GATE
1
2
3
4
8
7
6
5
GND
PGOOD
PGOOD
OUT
MAX5940B
MAX5940D
V
EE
SO
14 ______________________________________________________________________________________
IEEE 802.3af PD Interface Controller
For Power-Over-Ethernet
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
MAX
MAX
1.75
0.25
0.49
0.25
DIM
A
MIN
MIN
1.35
0.10
0.35
0.19
0.053
0.004
0.014
0.007
0.069
0.010
0.019
0.010
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
MAX
0.197
0.344
0.394
MAX
5.00
DIM
D
MIN
MIN
4.80
8.55
9.80
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0∞-8∞
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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