MAX5953C [MAXIM]
IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs; IEEE 802.3af PD接口和PWM控制器，集成功率MOSFET
| 型号： | MAX5953C |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | IEEE 802.3af PD Interface and PWM Controllers with Integrated Power MOSFETs |
| 文件： | 总27页 (文件大小：500K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3945; Rev 1; 7/06
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
General Description
Features
♦ Powered Device Interface
The MAX5953A/MAX5953B/MAX5953C/MAX5953D
integrate a complete power IC solution for Powered
Devices (PD) in a Power-Over-Ethernet (PoE) system, in
compliance with the IEEE 802.3af standard. The
MAX5953A/MAX5953B/MAX5953C/MAX5953D provide
the PD with a detection signature, a classification sig-
nature, and an integrated isolation switch with program-
mable inrush current control. These devices also
integrate a voltage-mode PWM controller with two
power MOSFETs connected in a two-switch voltage-
clamped DC-DC converter configuration.
Fully Integrated IEEE 802.3af-Compliant PD
Interface
PD Detection and Programmable Classification
Signatures
Less than 10µA Leakage Current Offset During
Detection
Integrated MOSFET for Isolation and Inrush
Current Limiting
Gate Output Allows External Control of the
Internal Isolation MOSFET
Programmable Inrush Current Control
Programmable Undervoltage Lockout
(MAX5953A/MAX5953C)
An integrated MOSFET provides PD isolation during
detection and classification. All devices guarantee a
leakage current offset of less than 10µA during the
detection phase. A programmable current limit pre-
vents high inrush current during power-on. The devices
feature power-mode undervoltage lockout (UVLO) with
wide hysteresis and long deglitch time to compensate
for twisted-pair-cable resistive drop and to assure
glitch-free transition between detection, classification,
and power-on/-off phases. The MAX5953A/MAX5953C
have an adjustable UVLO threshold with the default
value compliant to the 802.3af standard, while the
MAX5953B/MAX5953D have a lower and fixed UVLO
threshold compatible with some legacy pre-802.3af
power-sourcing equipment (PSE) devices.
♦ DC-DC Converter
Clamped, Two-Switch Power IC for High
Efficiency
Integrated High-Voltage 0.4Ω Power MOSFETs
Up to 15W Output Power
Bias Voltage Regulator with Automatic High-
Voltage Supply Turn-Off
11V to 76V Wide Input Voltage Range
Feed-Forward Voltage-Mode Control for Fast
Input Transient Rejection
Programmable Undervoltage Lockout
Overtemperature Shutdown
Indefinite Short-Circuit Protection with
Programmable Fault Integration
Integrated Look-Ahead Signal for Secondary-
Side Synchronous Rectification
> 90% Efficiency with Synchronous
Rectification
The DC-DC converters are operable in either forward or
flyback configurations with a wide input voltage range
from 11V to 76V and up to 15W of output power. The
voltage-clamped power topology enables full recovery
of stored magnetizing and leakage inductive energy for
enhanced efficiency and reliability. When using the
high-side MOSFET, the controller can be configured as
a buck converter. A look-ahead signal for driving sec-
ondary-side synchronous rectifiers can be used to
increase efficiency. A wide array of protection features
include UVLO, over-temperature shutdown, and short-
circuit protection with hiccup current limit for enhanced
performance and reliability. Operation up to 500kHz
allows for smaller external magnetics and capacitors.
Up to 500kHz Switching Frequency
♦ High-Power (2.22W), 7mm x 7mm Thermally
Enhanced Lead-Free Thin QFN Package
Ordering Information
PART
PIN-PACKAGE
48 TQFN
PKG CODE
T4877-6
T4877-6
T4877-6
T4877-6
MAX5953AUTM+
MAX5953BUTM+
MAX5953CUTM+
MAX5953DUTM+
48 TQFN
The MAX5953A/MAX5953B/MAX5953C/MAX5953D are
available in a high-power (2.22W), 7mm x 7mm ther-
mally enhanced thin QFN package.
48 TQFN
48 TQFN
Operating junction temperature range is 0°C to +125°C.
+Denotes lead-free package.
Applications
IEEE 802.3af Powered
Devices
Internet Appliances
Security Cameras
Computer Telephony
IP Phones
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
Wireless Access Nodes
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
ABSOLUTE MAXIMUM RATINGS
V+ to V ................................................................-0.3V to +90V
Maximum Input/Output Current (Continuous)
OUT to V ....................................................................500mA
EE
OUT, PGOOD, PGOOD to V .....................-0.3V to (V+ + 0.3V)
EE
EE
RCLASS, GATE to V ...........................................-0.3V to +12V
V+, RCLASS to V .........................................................70mA
UVLO, PGOOD, PGOOD to V .....................................20mA
EE
EE
EE
UVLO to V ............................................................ -0.3V to +8V
EE
PGOOD to OUT........................................... -0.3V to (V+ + 0.3V)
HVIN, INBIAS, DRNH, XFRMRH,
XFRMRL to GND.................................................-0.3V to +80V
BST to GND........................................................... -0.3V to +95V
BST to XFRMRH .................................................... -0.3V to +12V
PGND to GND .......................................................-0.3V to +0.3V
DCUVLO, RAMP, CSS, OPTO, FLTINT, RCFF,
GATE to V ....................................................................80mA
REGOUT to GND ............................................................50mA
DRNH, XFRMRH, XFRMRL, SRC to GND (Average),
EE
T = +125°C..................................................................0.9A
J
PPWM to GND .............................................................. 20mA
Continuous Power Dissipation* (T = +70°C)
A
48-Pin TQFN 7mm X 7mm
RTCT to GND..................................................... -0.3V to +12V
SRC, CS to GND...................................................... -0.3V to +6V
REGOUT, DRVIN to GND.......................................-0.3V to +12V
REGOUT to HVIN .................................................. -80V to +0.3V
REGOUT to INBIAS ............................................... -80V to +0.3V
(derate 27.8mW/°C above +70°C).............................2222mW
θ
................................................................................36°C/W
JA
Operating Ambient Temperature Range ................0°C to +85°C
Operating Junction Temperature Range..............0°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
PPWM to GND....................................-0.3V to (V
+ 0.3V)
REGOUT
*As per JEDEC 51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = (V+ - V ) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = V , T = 0°C to +125°C, unless
IN
EE
EE
J
otherwise noted. Typical values are at T = +25°C. All voltages are referenced to V , unless otherwise noted.) (Note 1)
J
EE
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWERED DEVICE (PD) INTERFACE
DETECTION MODE
Input Offset Current
I
V
V
= 1.4V to 10.1V (Note 2)
10
µA
OFFSET
IN
IN
Effective Differential Input
Resistance (Note 3)
dR
= 1.4V, up to 10.1V with 1V step
550
kΩ
CLASSIFICATION MODE
Classification Current Turn-Off
Threshold
V
V
V
rising (Note 4)
20.8
21.8
22.5
V
TH,CLASS
IN
IN
Class 0, R
Class 1, R
Class 2, R
Class 3, R
Class 4, R
= 10kΩ
= 732Ω
= 392Ω
= 255Ω
= 178Ω
0
2
RCLASS
RCLASS
RCLASS
RCLASS
RCLASS
= 12.6V
9.17
17.29
26.45
36.6
11.83
19.71
29.55
41.4
to 20V,
R
25.5kΩ
(Notes 5, 6)
Classification Current
I
=
mA
CLASS
DISC
POWER MODE
Operating Supply Voltage
V
V
= (V+ - V )
EE
67
1
V
IN
IN
Measure at V+, not including R
GATE = V , HVIN = GND = OUT
,
DISC
Operating Supply Current
I
0.4
mA
IN
EE
MAX5953A/MAX5953C
MAX5953B/MAX5953D
37.4
34.3
30
38.6
35.4
40.2
36.9
V
IN
Default Power Turn-On Voltage
Default Power Turn-Off Voltage
V
V
V
V
UVLO, ON
increasing
V
decreasing, MAX5953A/MAX5953C
UVLO,OFF
IN
2
_______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
ELECTRICAL CHARACTERISTICS (continued)
(V = (V+ - V ) = 48V, GATE = PGOOD = PGOOD = unconnected, GND = OUT, HVIN = V+, UVLO = V , T = 0°C to +125°C, unless
IN
EE
EE
J
otherwise noted. Typical values are at T = +25°C. All voltages are referenced to V , unless otherwise noted.) (Note 1)
J
EE
PARAMETER
SYMBOL
CONDITIONS
MAX5953A/MAX5953C
MAX5953B/MAX5953D
MIN
7.1
4
TYP
MAX
UNITS
Default Power Turn-On/Off
Hysteresis Voltage
V
V
HYST,UVLO
External UVLO Programming
Range
V
MAX5953A/MAX5953C only (Note 7)
12
67
V
V
IN,EX
UVLO External Reference
Voltage
V
V
increasing
UVLO
2.400
2.460
20
2.522
REF,UVLO
UVLO External Reference
Voltage Hysteresis
V
Ratio to V
19.2
-1.5
50
20.9
+1.5
440
%
µA
mV
HYST,UVLO
REF, UVLO
UVLO Bias Current
I
V
= 2.460V
UVLO
IN,UVLO
UVLO Input Ground-Sense
Threshold
V
(Note 8)
TH,G,UVLO
UVLO Input Ground-Sense Glitch
Rejection
7
µs
Power Turn-Off Voltage,
Undervoltage Lockout Deglitch
Time
t
V
, V falling (Note 9)
IN UVLO
0.32
0.5
ms
OFF_DLY
Isolation Switch n-Channel
MOSFET On-Resistance
Output current = 300mA, V
measured between OUT and V
= 5.6V,
GATE
R
0.6
38
1.5
80
Ω
V
ON,ISO
EE
Isolation Switch n-Channel
MOSFET Off-Threshold Voltage
V
- V , OUT = V+,
GATE EE
V
GSTH
output current < 1µA
GATE Pulldown Switch
Resistance
R
G
Power-off mode, V = +12V
Ω
IN
GATE Charging Current
GATE High Voltage
I
V
= 2V
4.5
10
5.76
1.23
70
16.5
5.93
1.31
µA
V
GATE
GATE
V
I
= 1µA
5.59
1.16
GATE
GATE
V
- V decreasing, V = 5.75V
EE GATE
V
OUT
PGOOD Assertion V
Threshold (Note 10)
OUT
V
OUTEN
Hysteresis
- V increasing
mV
V
V
4.62
4.76
80
4.91
GATE
EE
PGOOD, PGOOD Assertion
Threshold
V
GSEN
V
GATE
Hysteresis
= 2mA, V ≤ (V+ - 5V) (Note 11)
OUT
mV
PGOOD, PGOOD Output Low
Voltage
V
I
0.2
1
V
OL,PGOOD
SINK
PGOOD Leakage Current
GATE = high, V+ - V
= 67V (Note 11)
µA
µA
OUT
GATE = V , PGOOD - V = 67V
(Note 11)
EE
EE
PGOOD Leakage Current
1
_______________________________________________________________________________________
3
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
ELECTRICAL CHARACTERISTICS (DC-DC Controller)
(All voltages referenced to GND, unless otherwise noted. V
= +48V, C
= 1µF, C
= 2.2µF, R
= 25kΩ, C
=
RTCT
HVIN
INBIAS
REGOUT
RTCT
100pF, C
= 0.22µF, V
= V = 0V, V
= V
= 3V, T = 0°C to +125°C, unless otherwise noted. Typical values are at
BST
CSS
CS
RAMP
DCUVLO J
T = +25°C, unless otherwise noted.) (Note 1)
J
PARAMETER
Input Supply Range
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
11
76
V
HVIN
OSCILLATOR (RTCT)
PWM Frequency
f
250
47
1
kHz
%
S
Maximum PWM Duty Cycle
Maximum RTCT Frequency
RTCT Peak Trip Level
RTCT Valley Trip Level
RTCT Input Bias Current
D
MAX
f
(Note 12)
MHz
V
RTCTMAX
V
0.51 x V
REGOUT
TH,RTCT
V
1
V
TL,RTCT
IN,RTCT
I
1
µA
RTCT Discharge MOSFET
R
Sinking 50mA
35
50
85
Ω
DIS,RTCT
R
DS(ON)
RTCT Discharge Pulse Width
ns
LOOK-AHEAD LOGIC (PPWM)
PPWM to Output Propagation
Delay
t
V
rising to V falling
XFRMRL
110
ns
PPWM
PPWM
PPWM Output High
PPWM Output Low
V
Sourcing 2mA
Sinking 2mA
7.0
11.0
0.2
V
V
OH,PPWM
V
OL,PPWM
PWM COMPARATOR (OPTO, RAMP, RCFF)
Common-Mode Input Range
Input Offset Voltage
V
0
5.5
+2
V
CM_PWM
10
mV
µA
Input Bias Current
-2
RAMP to XFRMRL Propagation
Delay
From V
(50mV overdrive) rising to
RAMP
rising
t
100
ns
COMPARATOR
V
XFRMRL
Minimum OPTO Voltage
Minimum RCFF Voltage
REGOUT LDO (REGOUT)
V
= 0V, OPTO sinking 2mA
1.47
2.18
V
V
CSS
RCFF sinking 2mA
INBIAS unconnected,
8.3
9.5
8.75
10.6
9.2
V
= 11V to 76V
REGOUT Voltage Set Point
V
HVIN
V
V
REGOUT
V
= V
= 11V to 76V
HVIN
11.0
0.25
INBIAS
INBIAS unconnected, V
= 15V,
HVIN
I
= 0 to 30mA
REGOUT
REGOUT Load Regulation
REGOUT Dropout Voltage
V
= V
= 0 to 30mA
= 15V,
HVIN
INBIAS
0.25
I
REGOUT
INBIAS unconnected, I
= 30mA
1.25
1.25
REGOUT
V
V
V
V
= V
, I
= 30mA
INBIAS
HVIN REGOUT
REGOUT Undervoltage
Lockout Threshold
REGOUT rising
REGOUT falling
6.6
7.0
0.7
7.4
REGOUT Undervoltage
Lockout Threshold Hysteresis
4
_______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. V
= +48V, C
= 1µF, C
= 2.2µF, R
= 25kΩ, C
=
RTCT
HVIN
INBIAS
REGOUT
RTCT
100pF, C
= 0.22µF, V
= V = 0V, V
= V
= 3V, T = 0°C to +125°C, unless otherwise noted. Typical values are at
BST
CSS
CS
RAMP
DCUVLO J
T = +25°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SOFT-START (CSS)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Soft-Start Current
I
V
V
= 0V
CSS
33
µA
CSS
INTEGRATING FAULT PROTECTION
FLTINT Source Current
FLTINT Trip Point
I
80
2.7
µA
V
FLTINT
rising
FLTINT
FLTINT Hysteresis
0.75
V
INTERNAL POWER FETs
V
V
= V
= 9V,
BST
DRVIN
On-Resistance
R
0.4
15
80
0.8
Ω
ON,POWER
= V
= 0V, I = 50mA
DS
XFRMRH
SRC
Off-State Leakage Current
-5
+10
µA
nC
Total Gate Charge Per Power
FET
HIGH-SIDE DRIVER
Driver delay until FET V reaches 0.9 x
(V
GS
Low to High Latency
t
t
ns
LH-HS
HL-HS
- V
) and is fully on
BST
XFRMRH
Driver delay until FET V reaches 0.1 x
(V
GS
High to Low Latency
40
8
ns
V
- V
) and is fully off
BST
XFRMRH
Output Drive Voltage
V
BST to XFRMRH with high side on
BST
LOW-SIDE DRIVER
Driver delay until FET V reaches 0.9 x
GS
Low to High Latency
High to Low Latency
t
t
80
40
ns
ns
LH-LS
HL-LS
V
and is fully on
DRVIN
Driver delay until FET V reaches 0.1 x
GS
V
and is fully off
DRVIN
CURRENT-LIMIT COMPARATOR (CS)
Current-Limit Threshold
Voltage
V
140
-2
156
160
172
+2
mV
µA
ns
ILIM
BILIM
dILIM
Current-Limit Input Bias
Current
I
t
0 < V < 0.3V
CS
From V rising (10mV overdrive) to
CS
Propagation Delay to XFRMRL
V
rising
XFRMRL
BOOST VOLTAGE CIRCUIT (See Figure 9, QB)
Driver Output Delay
t
200
300
30
ns
ns
Ω
PPWMD
One-Shot Pulse Width
t
PWQB
QB R
Sinking 20mA
60
DSON
THERMAL SHUTDOWN
Shutdown Temperature
Thermal Hysteresis
T
Temperature rising
+160
20
°C
°C
SH
T
H
_______________________________________________________________________________________
5
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. V
= +48V, C
= 1µF, C
= 2.2µF, R
= 25kΩ, C
=
RTCT
HVIN
INBIAS
REGOUT
RTCT
100pF, C
= 0.22µF, V
= V = 0V, V
= V
= 3V, T = 0°C to +125°C, unless otherwise noted. Typical values are at
BST
CSS
CS
RAMP
DCUVLO J
T = +25°C, unless otherwise noted.) (Note 1)
J
PARAMETER
SYMBOL
CONDITIONS
MIN
1.14
-100
TYP
MAX
1.38
UNITS
UNDERVOLTAGE LOCKOUT (DCUVLO)
Threshold Voltage
Hysteresis
V
V
V
V
rising
1.26
140
V
REF,DCUVLO
DCUVLO
DCUVLO
mV
nA
HYS,DCUVLO
Input Bias Current
SUPPLY CURRENT
I
= 3V
+100
IN,DCUVLO
From V
= 11V to 76V,
= 11V
INBIAS
HVIN
0.7
1.5
6.4
V
= 0V, V
CSS
Supply Current
mA
mA
From V
= 11V to 76V,
INBIAS
4.4
7
V
= 0V, V
= 76V
HVIN
CSS
From V
= 76V, V
= 4V
OPIO
HVIN
Standby Supply Current
V
= 0V
1
DCUVLO
Note 1: Limits at 0°C are guaranteed by design, unless otherwise noted.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between V+ and V without any external
EE
resistance.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the Classification Mode section. R
and R
must be 1%, 100ppm or better. I
includes the IC
CLASS
DISC
RCLASS
bias current and the current drawn by R
.
DISC
Note 6: See the Thermal Dissipation section.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ ( 1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on UVLO does
not exceed its maximum rating of 8V when V is at the maximum voltage.
IN
Note 8: When V
is below V
, the MAX5953A/MAX5953C set the turn-on voltage threshold internally (V
).
UVLO
TH,G,UVLO
UVLO,ON
Note 9: An input voltage or V
glitch below their respective thresholds shorter than or equal to t
does not cause the
UVLO
OFF_DLY
MAX5953A/MAX5953B/MAX5953C/MAX5953D to exit power-on mode (as long as the input voltage remains above an
operable voltage level of 12V).
Note 10: Guaranteed by design, not tested in production for MAX5953B/MAX5953D.
Note 11: PGOOD references to OUT while PGOOD references to V
.
EE
1
Note 12: Output switching frequency is / oscillator frequency.
2
I
IN
(V
(I
- V
)
1V
INi + 1
INi
dR ≅
i
=
- I
)
(I
- I
)
INi + 1 INi
INi + 1 INi
V
INi
I
≅ I
-
OFFSET INi
dR
i
I
INi + 1
dR
i
I
INi
I
OFFSET
V
1V
V
INi + 1
V
IN
INi
Figure 1. Effective Differential Input Resistance/Offset Current
6
_______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Typical Operating Characteristics
(V = (V+ - V ) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = V , C
= 1µF,
IN
EE
EE INBIAS
C
= 2.2µF, R
= 25kΩ, C
= 100pF, C = 0.22µF, T = 0°C to +125°C, unless otherwise noted. Typical values are
BST J
REGOUT
RTCT
RTCT
at T = +25°C. All voltages are referenced to V , unless otherwise noted.)
J
EE
CLASSIFICATION CURRENT
vs. INPUT VOLTAGE
EFFECTIVE DIFFERENTIAL INPUT
RESISTANCE vs. INPUT CURRENT
DETECTION CURRENT
vs. INPUT VOLTAGE
50
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
0.4
0.3
0.2
0.1
0
R
= 25.5kΩ
DISC
45
40
35
30
25
20
15
10
5
CLASS 4
CLASS 3
I
+ I
IN RDISC
CLASS 2
CLASS 1
CLASS 0
0
0
5
10
15
20
25
30
0
0
0
2
4
6
8
10
0
2
4
6
8
10
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
PGOOD OUTPUT LOW VOLTAGE
vs. CURRENT
NORMALIZED UVLO
vs. TEMPERATURE
0
250
200
150
100
50
1.010
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
0
0
2
4
6
8
10
5
10
(mA)
15
20
0
25
50
75
100
125
INPUT VOLTAGE (V)
I
TEMPERATURE (°C)
SINK
DCUVLO THRESHOLD
vs. TEMPERATURE
OUT LEAKAGE CURRENT
vs. TEMPERATURE
INRUSH CURRENT CONTROL
(V = 48V)
IN
MAX5953A/B/C/D toc08
1000
100
10
1.2825
1.2800
1.2775
1.2750
1.2725
V
= 48V
DCUVLO RISING
OUT
V
GATE
5V/div
0V
V
TO
OUT
V
EE
0V
50V/div
I
INRUSH
100mA/div
1
0A
0V
PGOOD
50V/div
0.1
0
25
50
75
100
125
4ms/div
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
7
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Typical Operating Characteristics (continued)
(V = (V+ - V ) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = V , C
= 1µF,
IN
EE
EE INBIAS
C
= 2.2µF, R
= 25kΩ, C
= 100pF, C = 0.22µF, T = 0°C to +125°C, unless otherwise noted. Typical values are
BST J
REGOUT
RTCT
RTCT
at T = +25°C. All voltages are referenced to V , unless otherwise noted.)
J
EE
HVIN AND INBIAS INPUT CURRENT
vs. TEMPERATURE
HVIN STANDBY CURRENT
vs. TEMPERATURE
HVIN INPUT CURRENT
vs. TEMPERATURE
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
385
350
315
280
245
210
175
140
105
70
4.8
4.7
4.6
4.5
4.4
4.3
4.2
4.1
4.0
V
= V
= 76V
INBIAS
HVIN
INBIAS FLOATING
= 76V
REGOUT = DRVIN
V
HVIN
f
V
HVIN
DCUVLO
= 0V
I
INBIAS
I
HVIN
35
0
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
REGOUT VOLTAGE
vs. LOAD CURRENT
REGOUT VOLTAGE
vs. INPUT VOLTAGE
REGOUT VOLTAGE
vs. TEMPERATURE
8.85
8.84
8.83
8.82
8.81
8.80
8.79
8.78
8.77
8.76
8.75
8.90
8.88
8.86
8.84
8.82
8.80
8.78
8.76
8.74
8.72
8.70
8.85
8.80
8.75
8.70
8.65
V = 15V
HVIN
INBIAS FLOATING
V
= 48V
HVIN
INBIAS FLOATING
GND = V
GND = V
INBIAS FLOATING
EE
EE
11
24
37
50
(V)
63
76
0
25
50
75
100
125
0
5
10
15
20
25
30
V
TEMPERATURE (°C)
I
(mA)
REGOUT
HIN
REGOUT VOLTAGE
vs. LOAD CURRENT
REGOUT VOLTAGE
vs. INPUT VOLTAGE
REGOUT VOLTAGE
vs. TEMPERATURE
10.75
10.70
10.65
10.60
10.55
10.50
10.70
10.68
10.66
10.64
10.62
10.60
10.75
10.74
10.73
10.72
10.71
10.70
10.69
10.68
10.67
10.66
10.65
V
= V
EE
= 15V
INBIAS
HVIN = INBIAS
V
= V
= 48V
INBIAS
HVIN
HVIN
GND = V
GND = V
EE
0
5
10
15
20
25
30
11
24
37
50
(V)
63
76
0
25
50
75
100
125
I
(mA)
V
TEMPERATURE (°C)
REGOUT
HIN
8
_______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Typical Operating Characteristics (continued)
(V = (V+ - V ) = 48V, GATE = PGOOD = unconnected, GND connected to OUT, HVIN connected to V+, UVLO = V , C
= 1µF,
IN
EE
EE INBIAS
C
= 2.2µF, R
= 25kΩ, C
= 100pF, C = 0.22µF, T = 0°C to +125°C, unless otherwise noted. Typical values are
BST J
REGOUT
RTCT
RTCT
at T = +25°C. All voltages are referenced to V , unless otherwise noted.)
J
EE
SOFT-START CURRENT
vs. TEMPERATURE
OPERATING FREQUENCY
vs. TEMPERATURE
REGOUT UVLO VOLTAGE
vs. TEMPERATURE
34.0
33.5
33.0
32.5
32.0
31.5
31.0
7.4
600
550
500
450
400
350
300
250
200
RISING
R
= 12kΩ
RTCT
7.2
7.0
6.8
6.6
6.4
6.2
6.0
C
= 100pF
RTCT
FALLING
R
= 24.3kΩ
RTCT
C
= 100pF
RTCT
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
PPWM TO XFRMRL SKEW
vs. TEMPERATURE
CURRENT-LIMIT COMPARATOR
THRESHOLD vs. TEMPERATURE
MINIMUM RCFF AND OPTO LEVELS
vs. TEMPERATURE
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
100
99
98
97
96
95
94
93
92
91
90
0.160
0.159
0.158
0.157
0.156
0.155
0.154
0.153
0.152
0.151
0.150
HVIN RISING
RCFF
OPTO
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
FLTINT SHUTDOWN VOLTAGE
vs. TEMPERATURE
FLTINT CURRENT
vs. TEMPERATURE
POWER MOSFETS R
DS(ON)
vs. TEMPERATURE
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85
84
83
82
81
80
79
78
77
76
75
RISING
FALLING
0
25
50
75
100
125
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
9
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Pin Description
PIN
NAME
N.C.
V+
FUNCTION
1, 2, 3, 5, 7, 12, 13, 14, 17,
19, 35, 38, 46, 47, 48
No Connection. Not internally connected. Make no electrical connection to these pins.
4
Positive Input Power. Referenced to V
.
EE
Undervoltage Lockout Programming Input for PD Interface. UVLO is referenced to V
.
EE
When UVLO is above its threshold, the device enters the power mode. Connect UVLO to
to use the default undervoltage lockout threshold. Connect UVLO to the center of an
external resistor-divider between V+ and V to define a threshold externally. The series
EE
V
EE
6
UVLO
(MAX5953A/MAX5953C)
resistance value of the external resistors must add to 25.5kΩ ( 1%) and replaces the
detection resistor. To keep the device in undervoltage lockout, drive UVLO between
V
and V
.
REF,UVLO
TH,G,UVLO
6
N.C.
No Connection. Not internally connected. Make no electrical connection to this pin.
Classification Setting for PD Interface. RCLASS is referenced to V . Add a resistor from
(MAX5953B/MAX5953D)
EE
8
RCLASS
RCLASS to V to set a PD class (see Tables 1 and 2).
EE
Gate of Internal Isolation n-Channel Power MOSFET. GATE is referenced to V . GATE
EE
sources 10µA when the device enters power mode. Connect an external 100V ceramic
9
GATE
capacitor from GATE to OUT to program the inrush current. Drive GATE to V to turn off
EE
the internal MOSFET. The detection and classification functions operate normally when
GATE is driven to V
.
EE
10, 11
15, 16
V
Negative Input Power. Source of the integrated isolation n-channel power MOSFET.
EE
Output Voltage. OUT is referenced to V . OUT is connected to the drain of the integrated
EE
isolation n-channel power MOSFET. Connect OUT to GND.
OUT
Active-High, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD is
referenced to OUT. PGOOD goes high impedance when V
is within 1.2V of V and
EE
OUT
18
PGOOD when V
is 5V above V . Otherwise, PGOOD is internally pulled to OUT (given that
EE
GATE
(MAX5953A/MAX5953B)
V
is at least 5V below V+). PGOOD can be connected directly to CSS or DCUVLO to
OUT
enable/disable the DC-DC converter.
Active-Low, Open-Drain Power-Good Indicator Output for PD Interface. PGOOD is
18
referenced to V . PGOOD is pulled to V when V
is within 1.2V of V and when
EE
PGOOD
EE
EE
OUT
(MAX5953C/MAX5953D)
V
is 5V above V . Otherwise, PGOOD goes high impedance.
EE
GATE
Current-Sense Input for PWM Controller. CS is referenced to PGND. The current-limit
threshold is internally set to 156mV relative to PGND. The device has an internal noise filter.
If necessary, connect an external RC filter from CS to PGND for additional filtering.
20
21
CS
PWM Pulse Output. Referenced to GND. PPWM leads the internal power MOSFET pulse by
approximately 100ns.
PPWM
22
23
GND
Signal Ground of PWM Controller. Connect GND to PGND.
PGND
Power Ground of the DC-DC Converter Power Stage. Connect PGND to GND.
Soft-Start Timing Capacitor Connection for PWM Controller. CSS is referenced to GND.
Connect a 0.01µF or greater ceramic capacitor from CSS to GND. Connect to PGOOD to
automatically enable the PWM controller from the PD interface.
24
CSS
10 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Pin Description (continued)
PIN
NAME
FUNCTION
PWM Comparator Inverting Input. OPTO is referenced to GND. Connect the collector of the
optotransistor to OPTO and a pullup resistor to REGOUT.
25
OPTO
Source Connection of Low-Side Power MOSFET in the Two-Switch Power Stage of the DC-
DC Converter. Connect SRC to PGND with a low-value resistor for current limiting.
26, 27
28, 29
30
SRC
Low-Side Connection for the Isolation Transformer. Drain terminal of low-side power
MOSFET in the two-switch power stage of the DC-DC converter.
XFRMRL
DRVIN
Supply Input for the Gate-Driver of Internal Power MOSFETs. DRVIN is referenced to
PGND. Bypass DRVIN with at least 0.1µF to PGND. Connect DRVIN to REGOUT.
High-Side Connection for the Isolation Transformer. Source connection of high-side power
MOSFET in the two-switch power stage of the DC-DC converter.
31, 32
XFRMRH
Drain Connection of High-Side MOSFET in the Two-Switch Power Stage of the DC-DC
Converter. Connect DRNH to the most positive rail of the input supply. Bypass DRNH
appropriately to handle the heavy switching current through the transformer.
33, 34
36
DRNH
BST
Boost Input for the DC-DC Converter. BST is the boost connection point for the high-side
MOSFET driver. Connect a minimum 0.1µF capacitor from BST to XFRMRH with short and
wide PC board traces.
DC-DC Converter Undervoltage Lockout Input. DCUVLO is referenced to GND. Connect a
resistor-divider from HVIN to DCUVLO to GND to set the UVLO threshold.
37
39
40
DCUVLO
HVIN
DC-DC Converter Positive Input Power Supply. HVIN is referenced to GND. Connect HVIN
to V+.
Input from the Rectified Bias Winding to the DC-DC Converter. INBIAS is referenced to
GND. INBIAS is the input to the internal linear voltage regulator (REGOUT).
INBIAS
Internal Regulator Output. REGOUT is used for the DC-DC converter gate driver. REGOUT
is referenced to GND. V
voltage above the DCUVLO threshold. Bypass REGOUT to GND with a minimum 2.2µF
ceramic capacitor.
is always present as long as HVIN is powered with a
REGOUT
41
42
REGOUT
RTCT
Oscillator Frequency Set Input for the PWM Controller. RTCT is referenced to GND.
Connect a resistor from RTCT to REGOUT and a ceramic capacitor from RTCT to GND to
set the oscillator frequency.
Fault Integration Input for PWM Controller. FLTINT is referenced to GND. During persistent
current-limit faults, a capacitor connected to FLTINT is charged with an internal 80µA
43
FLTINT current source. Switching is terminated when V
reaches 2.7V. An external resistor
FLTINT
connected in parallel discharges the capacitor. Switching resumes when V
to 1.9V.
drops
FLTINT
Feed-Forward Input for PWM Controller. RCFF is referenced to GND. To generate the PWM
ramp, connect a resistor from RCFF to HVIN and a capacitor from RCFF to GND.
44
45
RCFF
RAMP
Ramp Sense Input for PWM Controller. Connect RAMP to RCFF.
Exposed Paddle. EP is internally unconnected and must be connected to V externally.
EE
To improve power dissipation, solder the exposed paddle to a copper pad on the PC
board.
—
EP
______________________________________________________________________________________ 11
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Typical Application Circuit
POWER-OVER
SIGNAL PAIRS
V
REG
Rx
3
6
1
PHY
2
-48V
RTN
RJ-45
SGND
+
-
+
-
Tx
4
5
7
8
-48V
POWER-OVER
SPAIR PAIRS
Figure 2. RJ-45 Connector, PoE Magnetic, and Input Diode Bridges
12 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Figure 3. Typical Application Circuit
______________________________________________________________________________________ 13
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Figure 4. For higher power applications, the MAX5953A/MAX5953B/MAX5953C/MAX5953D can be used in a two-switch forward
converter configuration
14 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Operating Modes
Detailed Description
Depending on the input voltage (V = V - V ), the PD
IN
+
EE
PD Interface
The MAX5953A/MAX5953B/MAX5953C/MAX5953D
include complete interface function for a PD to comply
with the IEEE 802.3af standard in a PoE system. They
provide the PD with a detection signature, a classifica-
tion signature, and an integrated isolation switch with
programmable inrush current control. An integrated
MOSFET provides PD isolation during detection and
classification. All devices guarantee a leakage current
offset of less than 10µA during the detection phase. A
programmable current limit prevents high inrush cur-
rent during power-on. The device features power-mode
UVLO with wide hysteresis and long deglitch time to
compensate for twisted-pair-cable resistive drop and to
assure glitch-free transition between detection, classifi-
cation, and power-on/-off phases. The MAX5953A/
MAX5953C have an adjustable UVLO threshold with
the default value compliant to the 802.3af standard,
while the MAX5953B/MAX5953D have a lower and
fixed UVLO threshold compatible with some legacy
pre-802.3af PSE.
front-end section of the MAX5953A/MAX5953B/
MAX5953C/MAX5953D operate in three different modes:
PD detection signature, PD classification, and PD power.
All voltage thresholds are designed to operate with or
without the optional diode bridge while still complying
with the IEEE 802.3af standard (see Figure 2).
Detection Mode (1.4V ≤ V ≤ 10.1V)
IN
In detection mode, the power source equipment (PSE)
applies two voltages on V in the range of 1.4V to 10.1V
IN
(1V step minimum), and records the corresponding cur-
rent measurements at those two points. The PSE then
computes ∆V/∆I to ensure the presence of the 25.5kΩ
signature resistor. In this mode, most interface circuitry
of the MAX5953A/MAX5953B/MAX5953C/MAX5953D is
off and the offset current is less than 10µA.
Classification Mode (12.6V ≤ V ≤ 20V)
IN
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD.
This allows the PSE to efficiently manage power distrib-
ution. The IEEE 802.3af standard defines five different
classes as shown in Table 1. An external resistor
Table 1. PD Power Classification/
(R
) connected from RCLASS to V
sets the
EE
RCLASS
classification current.
R
Selection
RCLASS
The PSE determines the class of a PD by applying a
voltage at the PD input and measuring the current
sourced out of the PSE. When the PSE applies a volt-
age between 12.6V and 20V, the IC exhibits a current
characteristic with values indicated in Table 2. The PSE
uses the classification current information to classify
the power requirement of the PD. The classification cur-
rent includes the current drawn by the 25.5kΩ detec-
tion signature resistor and the supply current of the IC
so the total current drawn by the PD is within the IEEE
802.3af standard figures. The classification current is
turned off whenever the device is in power mode.
R
MAXIMUM POWER
USED BY PD (W)
RCLASS
(Ω)
CLASS
USAGE
0
1
2
3
Default
Optional
Optional
Optional
10k
732
392
255
0.44 to 12.95
0.44 to 3.84
3.84 to 6.49
6.49 to 12.95
Not
Allowed
4
178
Reserved*
*Class 4 reserved for future use.
Table 2. Setting Classification Current
IEEE 802.3af PD CLASSIFICATION
CURRENT SPECIFICATION (mA)
CLASS CURRENT SEEN AT V (mA)
IN
R
RCLASS
(Ω)
CLASS
V * (V)
IN
MIN
0
MAX
MIN
0
MAX
4
0
1
2
3
4
10k
732
392
255
178
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
12.6 to 20
2.00
9.17
17.29
26.45
36.60
11.83
19.71
29.55
41.40
9
12
20
30
44
17
26
36
*V is measured across the MAX5953A/MAX5953B/MAX5953C/MAX5953D input pins (V+ - V ), which do not include the diode
IN
EE
bridge voltage drop.
______________________________________________________________________________________ 15
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Power Mode
C
During power mode, when V rises above the undervolt-
IN
UVLO,ON
OUT
I
= I ×
G
INRUSH
age lockout threshold (V
), the IC gradually turns
C
GATE
on the internal n-channel MOSFET Q1 (see Figure 8).
The IC charges the gate of Q1 with a constant current
source (10µA, typ). The drain-to-gate capacitance of Q1
limits the voltage rise rate at the drain of the MOSFET,
thereby limiting the inrush current. To further reduce the
inrush current, add external drain-to-gate capacitance
(see the Inrush Current Limit section). When the drain of
Q1 is within 1.2V of its source voltage and its gate-to-
source voltage is above 5V, the MAX5953A/MAX5953B
assert the PGOOD output (MAX5953C/MAX5953D assert
the PGOOD output). The IC has a wide UVLO hysteresis
and turn-off deglitch time to compensate for the high
impedance of the twisted-pair cable.
The recommended typical inrush current for a PoE
application is 100mA.
PGOOD/PGOOD Output
PGOOD is an open-drain, active-high logic output.
PGOOD goes high impedance when V
is within
OUT
1.2V of V
and when GATE is 5V above V
.
EE
EE
Otherwise, PGOOD is pulled to V
(given that V
OUT
OUT
is at least 5V below V+). Connect PGOOD directly to
CSS to enable/disable the DC-DC converter. PGOOD is
an open-drain, active-low logic output. PGOOD is
pulled to V
when V
is within 1.2V of V
EE
and
EE
EE
OUT
when GATE is 5V above V . Otherwise, PGOOD goes
Undervoltage Lockout for PD Interface
high impedance. Connect a 100kΩ pullup resistor from
PGOOD to V+ if needed.
The IC operates up to a 67V supply voltage with a default
UVLO turn-on (V
) set at 38.6V (MAX5953A/
UVLO,ON
Thermal Dissipation
Thermal shutdown limits total power dissipation in the
IC. If the junction temperature exceeds +160°C, ther-
mal shutdown is enabled to turn off the MAX5953A/
MAX5953B/MAX5953C/MAX5953D, allowing the IC to
cool. The IC turns on after the junction temperature
cools by 20°C.
MAX5953C) or 35.4V (MAX5953B/MAX5953D) and a
UVLO turn-off (V ) set at 30V. The MAX5953A/
UVLO,OFF
MAX5953C have an adjustable UVLO threshold using a
resistor-divider connected to UVLO (see Figure 3). When
the input voltage goes below the UVLO threshold for
more than t , the MOSFET turns off.
OFF_DLY
To adjust the UVLO threshold, connect an external
resistor-divider from V+ to UVLO to V . Use the follow-
EE
ing equations to calculate R1 and R2 for a desired
UVLO threshold:
DC-DC Converter
The MAX5953A/MAX5953B/MAX5953C/MAX5953D iso-
lated PWM power ICs feature integrated switching power
MOSFETs connected in a voltage-clamped, two-transis-
tor, power-circuit configuration. These devices can be
used in both forward and flyback configurations with a
wide 11V to 76V input voltage range. The voltage-
clamped power topology enables full recovery of stored
magnetizing and leakage inductive energy for enhanced
efficiency and reliability. A look-ahead signal for driving
secondary-side synchronous rectifiers can be used to
increase efficiency. A wide array of protection features
include UVLO, overtemperature shutdown, and short-cir-
cuit protection with hiccup current-limit for enhanced
performance and reliability. Operation up to 500kHz
allows smaller external magnetics and capacitors.
V
REF,UVLO
R2 = 25.5kΩ ×
V
IN,EX
R1= 25.5kΩ − R2
where V
is the desired UVLO threshold. Since the
IN,EX
resistor-divider replaces the 25.5kΩ PD detection resis-
tor, ensure that the sum of R1 and R2 equals 25.5kΩ
1%. When using the external resistor-divider, MAX5953A/
MAX5953C have an external reference voltage hysteresis
of 20% (typ). In other words, when UVLO is programmed
externally, the turn-off threshold is 80% (typ) of the new
UVLO threshold.
Power Topology
The two-switch forward-converter topology offers out-
standing robustness against faults and transformer sat-
uration while affording efficient use of 0.4Ω power
MOSFETs. Voltage-mode control with feed-forward
compensation allows the rejection of input supply dis-
turbances within a single cycle similar to that of current-
mode controlled topologies.
Inrush Current Limit
The IC charges the gate of the internal MOSFET with a
constant current source (10µA, typ). The drain-to-gate
capacitance of the MOSFET limits the voltage rise rate
at the drain, thereby limiting the inrush current. Add an
external capacitor from GATE to OUT to further reduce
the inrush current. Use the following equation to calcu-
late the inrush current:
16 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
The two-switch power topology recovers energy stored
in both the magnetizing and the parasitic leakage induc-
tances of the transformer. The Typical Application
Circuit, Figure 3, shows the schematic diagram of a -48V
input flyback converter using the MAX5953A. Figure 4
shows the schematic diagram of a -48V input forward
converter and a 5V, 3A output isolated power supply.
external resistive divider (R16 and R17) connected to
DCUVLO (see Figure 3). Use the following equation to
calculate R16 and R17:
R16
R17
⎛
⎞
V
= V
× 1+
⎜
DCUVLO
⎟
⎠
DCUVLOIN
⎝
where V
is the desired input voltage lockout
is the undervoltage lockout thresh-
DCUVLOIN
Voltage-Mode Control and the PWM Ramp
For voltage-mode control, the feed-forward PWM ramp
is generated at RCFF. From RCFF, connect a capacitor
to GND and a resistor to HVIN. The ramp generated is
applied to the noninverting input of the PWM compara-
tor at RAMP and has a minimum voltage of approxi-
mately 2V. The slope of the ramp is determined by the
voltage at HVIN and affects the overall loop gain. The
ramp peak must remain below the 5.5V dynamic range
of RCFF. Assuming the maximum duty cycle approach-
es 50% at a minimum input voltage (PWM UVLO turn-
on threshold), use the following formula to calculate the
minimum value of either the ramp capacitor or resistor:
level and V
DCUVLO
old (1.25V, typ). Select the R17 resistance value
between 100kΩ and 500kΩ.
Optocoupled Feedback
Isolated voltage feedback is achieved by using an
optocoupler as shown in Figure 3. Connect the collec-
tor of the optotransistor to OPTO and a pullup resistor
between OPTO and REGOUT.
Internal Regulators
As soon as power is provided to HVIN, internal power
supplies power the DCUVLO detection circuitry.
REGOUT is used to drive the internal power MOSFETs.
Bypass REGOUT to GND with a minimum 2.2µF ceram-
ic capacitor. The HVIN LDO steps down V
nominal output voltage (V
V
IN,EX
R
×C
≥
RCFF
to a
RCFF
HVIN
2×f × V
S
R(P−P)
) of 8.75V. A second
REGOUT
parallel LDO powers REGOUT from INBIAS. A tertiary
winding connected through a diode to INBIAS powers
up REGOUT once switching commences. This powers
REGOUT to 10.5V (typ) and shuts off the current flow-
ing from HVIN to REGOUT. This results in a lower on-
chip power dissipation and higher efficiency.
where f is the switching frequency, V
is the peak-
RCFF
S
R(P-P)
to-peak ramp voltage (2V, typ). Select R
resistance
value between 200kΩ and 600kΩ.
Maximize the signal-to-noise ratio by setting the ramp
peak as high as possible. Calculate the low-frequency,
small-signal gain of the power stage (the gain from the
inverting input of the PWM comparator to the output)
using the following formula:
G
PS
= N x R
x C
x f
RCFF S
SP
RCFF
where N
is the secondary to primary power trans-
SP
MAX5953A
MAX5953B
MAX5953C
former turns ratio.
Secondary-Side Synchronization
MAX5953D
The MAX5953A/MAX5953B/MAX5953C/MAX5953D
provide convenient synchronization for optional sec-
ondary-side synchronous rectifiers. Figure 5 shows the
connection diagram with a high-speed optocoupler.
Choose an optocoupler with a propagation delay of
less than 80ns. The synchronizing pulse is generated
approximately 110ns ahead of the main pulse that dri-
ves the two power MOSFETs.
+5V
R
PPWM
PGND
C
Undervoltage Lockout for DC-DC Converter
Connect PGOOD to DCUVLO to ensure the PD interface
is ready prior to the DC-DC converter. The DCUVLO
block monitors the input voltage at HVIN through an
Figure 5. Secondary-Side Synchronous Rectifier Driver Using a
High-Speed Optocoupler
______________________________________________________________________________________ 17
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Soft-Start
I
× t
SH
1.4
FLTINT
Program the MAX5953A/MAX5953B/MAX5953C/
C
≅
FLTINT
MAX5953D soft-start with an external capacitor (C
)
CSS
connected between CSS and GND. When the device
turns on, C charges with a constant current of
where I
is typically 80µA, and t
is the desired
SH
FLTIN
CSS
ignore time during which current-limit events from the
33µA, ramping up to 7.3V. During this time, the feed-
back input (OPTO) is clamped to V + 0.6V. This ini-
current-limit comparator are ignored.
CSS
This is an approximate formula; some testing may be
required to fine tune the actual value of the capacitor.
tially holds the duty cycle lower than the value the
regulator imposes, thus preventing voltage overshoot at
the output. When the IC turns off, the soft-start capaci-
tor internally discharges to GND.
Calculate the approximate bleed resistor needed for
the desired recovery time using the following formula:
Oscillator
The oscillator is externally programmable through a
resistor connected from RTCT to REGOUT and a
capacitor connected from RTCT to GND. The PWM fre-
quency is one-half the frequency seen at RTCT with a
50% duty cycle. Use the following formula to calculate
the oscillator components:
t
RT
× 0.3514
R
≅
FLTINT
C
FLTINT
where t is the desired recovery time.
RT
Choose t ≥ 10 x t . Typical values for t can range
from a few hundred microseconds to a few milliseconds.
RT
SH
SH
1
⎛
Shutdown
Shut down the controller section of the IC by driving
DCUVLO to GND using an open-collector or open-drain
transistor connected to GND. The DC-DC converter sec-
tion shuts down if REGOUT is below its DCUVLO level.
R
≅
RTCT
⎞
V
REGOUT
− V
2f C
+ C
In
PCB
⎜
(
)
s
RTCT
⎟
V
⎝
⎠
REGOUT
TH,RTCT
where C
(14pF, typ), V
f is the switching frequency.
S
is the stray capacitance on the PC board
PCB
Current-Sense Comparator
The current-sense (CS) comparator and its associated
logic limit the peak current through the internal MOSFET.
Current is sensed at CS as a voltage across a sense
resistor between the source of the MOSFET and GND.
The power MOSFET switches off when the voltage at
CS reaches 156mV. Select the current-sense resistor,
is the RTCT peak trip level, and
TH,RTCT
Integrating Fault Protection
The integrating fault protection feature allows the IC to
ignore transient overcurrent conditions for a program-
mable amount of time, giving the power-supply time to
behave like a current source to the load. This can hap-
pen, for example, under load-current transients when
the control loop requests maximum current to keep the
output voltage from going out of regulation. The ignore
time is programmed externally by connecting a capaci-
tor from FLTINT to GND. Under sustained overcurrent
faults, the voltage across this capacitor ramps up
toward the FLTINT shutdown threshold (2.7V, typ).
R
, according to the following equation:
SENSE
R
= 0.156V / I
LimPrimary
SENSE
where I
current.
is the maximum peak primary-side
LimPrimary
To reduce switching noise, connect CS to an external
RC lowpass filter for additional filtering (Figure 3).
Applications Information
When V
reaches the shutdown threshold, the
FLTINT
power supply shuts down. A high-value bleed resistor
connected in parallel with the FLTINT capacitor allows
the capacitor to discharge toward the restart threshold
(1.9V, typ). FLTINT drops to the restart threshold allow-
ing for soft-starting the supply again.
Design Example
Design Example 1: PD with three-output flyback DC-
DC converter
Figure 6 shows an isolated three-output flyback DC-DC
converter. It provides output voltages of 10V at 30mA,
5.1V at 1.8A, and 2.55V at 5.4A.
The fault integration circuit works by forcing an 80µA
current into FLTINT for one clock cycle every time the
current-limit comparator ILIM (Figure 9) trips. Use the
following formula to calculate the approximate capaci-
tor needed for the desired shutdown time:
Design Example 2: PD with nonisolated step-down
(buck) converter
Figure 7 shows a buck converter with 12V, 0.75A out-
put. Caution: this converter does not have active cur-
rent limit.
18 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Figure 6. PD with Three-Output Flyback DC-DC Converter
______________________________________________________________________________________ 19
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Figure 7. PD with Nonisolated Step-Down (Buck) Converter
20 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Table 3. Component Suppliers
COMPONENT
SUPPLIERS
International Rectifier
Fairchild
WEBSITE
www.irf.com
Power FETS
www.fairchildsemi.com
www.vishay.com/brands/siliconix/main.html
www.vishay.com/brands/dale/main.html
www.irctt.com/pages/index.cfm
www.onsemi.com
Vishay-Siliconix
Dale-Vishay
Current-Sense Resistors
Diodes
IRC
ON Semi
General Semiconductor
Central Semiconductor
Sanyo
www.gensemi.com
www.centralsemi.com
www.sanyo.com
Capacitors
Magnetics
Taiyo Yuden
AVX
www.t-yuden.com
www.avxcorp.com
Coiltronics
www.cooperet.com
Coilcraft
www.coilcraft.com
Pulse Engineering
www.pulseeng.com
Current loops must be analyzed in any layout pro-
posed, and the internal area kept to a minimum to
reduce radiated EMI. Ground planes must be kept as
intact as possible.
Layout Recommendations
All connections carrying pulsed currents must be very
short, as wide as possible, and have a ground plane as
a return path. The inductance of these connections
must be kept to a minimum due to the high di/dt of the
currents in high-frequency-switching power converters.
______________________________________________________________________________________ 21
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Block Diagrams
V+
2.4V
REF
UVLO
REF
6.8V
EN
V+
RCLASS
CLASSIFICATION
MAX5953A
MAX5953B
MAX5953C
MAX5953D
PGOOD**
2.4V, 0.8
HYST
21.8V
39V
Q4
V
GATE
, 6V
1.2V, REF
EN
UVLO*
PGOOD***
5V, REF
Q3
OUT
Q2
38Ω
200mV
Q1
0.6Ω
GATE
V
EE
*MAX5953A/MAX5953C ONLY.
**MAX5953C/MAX5953D ONLY.
***MAX5953A/MAX5953B ONLY.
Figure 8. Powered Device Interface Block Diagram
22 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Block Diagrams (continued)
INBIAS
REGOK
REGOUT
RCFF
HVIN
REG
DCUVLO
OVT
REF
(1.25V)
REFOK
DCUVLO
DCUVLO
1.25V
5V
PPWM
5V
D
7.5V
IFLT
50Ω
80µA
Q
T
BST
GND
R
DRNH
FLTINT
OVRLD
80ns
DELAY
LEVEL
SHIFT
2.7V/1.9V
R
S
Q
0.4Ω
RAMP
QH
XFRMRH
CPWM
OPTO
LEADING-
EDGE
DELAY
30Ω
5V
ONE
SHOT
QB
DRVIN
33µA
CLK
R
SHDN
OSC
XFRMRL
Q
T-FF
T
CSS
0.4Ω
QL
THERMAL
SHUTDOWN
OVT
SRC
PGND
RTCT
OVT
50Ω
DCUVLO
REFOK
REGOK
OVRLD
GND
CS
GND
MAX5953A
MAX5953B
MAX5953C
MAX5953D
ILIM
10MHz
150mV
PGND
Figure 9. DC-DC Converter Block Diagram (Voltage-Mode PWM Controller and Two-Switch Power Stage)
______________________________________________________________________________________ 23
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Typical Operating Circuit
24 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Pin Configuration
TOP VIEW
35 34 33 32 31 30 29 28 27
36
26
25
CSS
DCUVLO
N.C.
24
23
22
37
38
39
PGND
GND
HVIN
21 PPWM
20 CS
INBIAS 40
REGOUT 41
MAX5953A
MAX5953B
MAX5953C
MAX5953D
RTCT
42
43
19 N.C.
18
**
FLTINT
17 N.C.
16 OUT
RCFF 44
RAMP 45
OUT
14 N.C.
13
N.C.
N.C.
N.C.
15
46
47
48
+
N.C.
2
3
4
5
6
7
8
9
10
1
11
12
THIN QFN
7mm x 7mm
*UVLO FOR MAX5953A/MAX5953C
N.C. FOR MAX5953B/MAX5953D
** PGOOD FOR MAX5953A/MAX5953B
PGOOD FOR MAX5953C/MAX5953D
Selector Guide
Chip Information
PROCESS: BiCMOS
PGOOD or
PGOOD
PART
UVLO
MAX5953A
MAX5953B
MAX5953C
MAX5953D
PGOOD
PGOOD
PGOOD
PGOOD
Adjustable
Fixed
Adjustable
Fixed
______________________________________________________________________________________ 25
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
E
DETAIL A
(NE-1) X
e
E/2
k
e
D/2
C
(ND-1) X
e
D2
D
L
D2/2
b
L
E2/2
C
L
k
DETAIL B
E2
e
C
C
L
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
1
21-0144
E
2
26 ______________________________________________________________________________________
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
2
21-0144
E
2
Revision History
Pages changed at Rev 1: 1, 27
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 27
© 2006 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
M. Quijano
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